Address management method, verification platform, electronic device and computer program product

Abstract

The invention discloses an address management method, a verification platform, electronic equipment and a computer program product, and relates to the technical field of storage, the address management method is applied to an address management module, the address management module comprises an address mapping table, and unused logic addresses in the initial address mapping table do not have physical addresses associated with mapping; the method comprises the following steps: receiving a data write-in operation, and determining write-in logic address information corresponding to the data write-in operation; configuring an idle physical address for the write-in logic address information; and mapping and associating the write-in logic address information with the idle physical address, and recording a mapping association relationship in the address mapping table. According to the method, a strategy of generating the physical address on demand and establishing the mapping is realized, so that records of redundant information in the address mapping table are reduced as much as possible, and the size of the address mapping table can be reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an address management method, a verification platform, an electronic device, and a computer program product. Background Technology

[0002] The memory chip verification platform primarily revolves around performing multifaceted simulation tests on the DUT (Design Under Test). Its core lies in simulating the flash memory controller's mapping and management function from host logical addresses to flash memory physical addresses. One of its simulation tasks is the simulation of the storage space. In relevant address management schemes, to simulate the address space of large-capacity storage, a massive mapping table needs to be maintained, especially for large-capacity memory chips, whose address spaces are enormous (reaching hundreds of GB or even TB levels). Therefore, maintaining this massive mapping table consumes a significant amount of simulation memory and computing resources, negatively impacting simulation speed and becoming a bottleneck for verification efficiency.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide an address management method, verification platform, electronic device and computer program product, which aims to solve the technical problem that maintaining the mapping table in related address management schemes requires a lot of simulation resources, resulting in slow simulation speed.

[0005] To achieve the above objectives, this application proposes an address management method applied to an address management module, wherein the address management module includes an address mapping table, wherein unused logical addresses in the initial address mapping table do not have any associated physical addresses; The address management method includes: Receive a data write operation and determine the write logical address information corresponding to the data write operation; Configure an idle physical address for the written logical address information; The written logical address information is mapped and associated with the free physical address, and the mapping relationship is recorded in the address mapping table.

[0006] Optionally, the step of determining the write logical address information corresponding to the data write operation includes: The write logical address information is constructed based on the write start logical address and write operation length in the data write operation.

[0007] Optionally, the step of associating the written logical address information with the free physical address mapping and recording the mapping association in the address mapping table includes: When the write logical address information includes the write start logical address and the write operation length, the write start logical address and the write operation length are mapped and associated with the physical address information of the free physical address to obtain a first mapping association relationship; Record the first mapping association in the address mapping table, or record the first mapping association with the debugging information related to the data writing operation in the address mapping table.

[0008] Optionally, the step of determining the write logical address information corresponding to the data write operation includes: The write logical address range is determined based on the write start logical address and write operation length in the data write operation; The write logical address range is aligned and expanded based on a preset granularity to obtain each write logical address, wherein each write logical address is used to constitute the write logical address information.

[0009] Optionally, the step of associating the written logical address information with the free physical address mapping and recording the mapping association in the address mapping table includes: When the write logical address information includes each write logical address, the write logical address is mapped and associated with the free physical address to obtain a second mapping association relationship; Record the second mapping association in the address mapping table, or associate the second mapping association with debugging information related to the data write operation and record it in the address mapping table.

[0010] Optionally, the step of configuring a free physical address for the written logical address information includes: From the preset virtual physical address pool, select an idle physical address that matches the length of the written logical address information, wherein the distribution of the idle physical addresses satisfies the implementation conditions of the function supported by the test object corresponding to the data writing operation.

[0011] Optionally, after the step of configuring a free physical address for writing the logical address information, the method includes: A sequence of write commands is generated based on the generation parameters, wherein the generation parameters include at least one of the following: the write operation length in the data write operation, the functions supported by the test object corresponding to the data write operation, and the distribution of the free physical addresses. The write command sequence is sent to the test object.

[0012] Optionally, the address management method further includes: Receive a data read operation and determine the read logic address information corresponding to the data read operation; Based on the read logical address information, a query is performed in the address mapping table to obtain the target physical address corresponding to the read logical address information.

[0013] Optionally, after the step of querying the address mapping table based on the read logical address information, the method includes: Once the target physical address is obtained, a read command sequence for the target physical address is generated, and the read command sequence is sent to the test object corresponding to the data write operation. The actual data read by the test object based on the read command sequence is compared with the expected data corresponding to the data read operation to verify the address mapping result.

[0014] Optionally, the address mapping table is associated with a write logical address sequence, which is determined by the write start logical address of each historical data write operation; The step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes: When the read logical address information includes the read start logical address and the read operation length, a candidate write start logical address that matches the read start logical address is queried in the write logical address sequence; The candidate write start logical address is used as the index key to query the address mapping table and obtain the candidate physical address information corresponding to the candidate write start logical address. The target physical address information is determined based on the offset between the read start logical address and the candidate write start logical address, the read operation length, and the candidate physical address information, wherein the address under the target physical address information is used as the target physical address.

[0015] Optionally, the step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes: When the read logical address information includes each read logical address, each read logical address is used as an index key to perform a lookup in the address mapping table; If the query determines that each of the read logical addresses is mapped to a physical address, then each mapped physical address is used as the target physical address.

[0016] Optionally, the address management method further includes: The address mapping table is modified based on preset conditions. When the preset condition is receiving an erase operation, the modification operation deletes the mapping relationship pointed to by the erase operation in the address mapping table. When the preset condition is triggering storage space fragmentation reclamation, the modification operation updates the mapping relationship of the valid data of storage space fragmentation reclamation in the address mapping table.

[0017] Furthermore, to achieve the above objectives, this application also proposes a verification platform, which includes an address management module, an address mapping table, and further includes: A parsing unit is used to receive a data write operation and determine the write logical address information corresponding to the data write operation. A physical address pool allocation unit is used to configure free physical addresses for the written logical address information; The address mapping unit is used to associate the written logical address information with the free physical address mapping and to record the mapping association in the address mapping table.

[0018] In addition, to achieve the above objectives, this application also proposes an electronic device, which includes: a processor, a memory, and an address management program stored in the memory and executable on the processor, wherein the address management program, when executed, implements the steps of the address management method as described above.

[0019] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the address management method described above.

[0020] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the address management method described above.

[0021] One or more technical solutions proposed in this application have at least the following technical effects: In this embodiment, the address management method is applied to an address management module, which includes an address mapping table. Initially, unused logical addresses in the address mapping table do not have associated physical addresses. During actual Founder testing, a data write operation is received, and the write logical address information corresponding to the data write operation is determined. An idle physical address is configured for the write logical address information. The write logical address information is mapped and associated with the idle physical address, and the mapping relationship is recorded in the address mapping table. It is understood that in this embodiment, the initial address mapping table does not have associated physical addresses for unused logical addresses. However, during actual simulation testing, the write logical address information is determined based on actual testing requirements (such as data write operations), an idle physical address is configured for the write logical address information, and the address mapping table is updated to record the mapping relationship between the write logical address information and the idle physical address. The strategy of "generating physical addresses on demand" and establishing mappings is implemented. This means that physical addresses are dynamically allocated and mapping table entries are created only when a logical address is accessed for the first time. This approach aims to meet testing requirements while minimizing the recording of redundant information in the address mapping table, reducing the size of the address mapping table, thereby reducing the consumption of simulation memory and computing resources, improving simulation speed, and breaking through the bottleneck of verification efficiency. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the first process of an embodiment of the address management method in this application; Figure 2 This is a schematic diagram illustrating the principle of waste recycling in the address management method of this application; Figure 3 This is a schematic diagram of the second process in an embodiment of the address management method of this application; Figure 4 This is a schematic diagram of the framework of the verification platform for this application.

[0025] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0027] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0028] The memory chip verification platform primarily revolves around the Device Under Test (DUT) for multifaceted simulation testing. Its core lies in simulating the flash memory controller's mapping and management function from host logical addresses to flash memory physical addresses. One of its simulation tasks is the simulation of the storage space. In relevant address management schemes, to simulate the address space of large-capacity storage, a massive mapping table needs to be maintained, especially for large-capacity memory chips, whose address spaces are enormous (reaching hundreds of GB or even TB levels). Therefore, maintaining this massive mapping table consumes a significant amount of simulation memory and computing resources, negatively impacting simulation speed and becoming a bottleneck for verification efficiency.

[0029] The main solution of this application embodiment is: applied to the address management module, the address management module includes an address mapping table, wherein, in the initial address mapping table, there is no physical address associated with the unused logical address; receive data write operation, determine the write logical address information corresponding to the data write operation; configure an idle physical address for the write logical address information; map and associate the write logical address information with the idle physical address, and record the mapping association relationship in the address mapping table.

[0030] In this embodiment, unused logical addresses in the initial address mapping table do not have associated physical addresses. However, during actual simulation testing, the logical address information is determined based on actual test requirements (such as data write operations). A free physical address is configured for the logical address information, and the address mapping table is updated to record the mapping relationship between the logical address information and the free physical address. This implements a strategy of "generating" physical addresses and establishing mappings on demand. Essentially, physical addresses are dynamically allocated and mapping table entries are created only when a logical address is accessed for the first time. This satisfies test requirements while minimizing redundant information in the address mapping table, reducing its size, and consequently lowering simulation memory and computational resource consumption, improving simulation speed, and overcoming the bottleneck of verification efficiency.

[0031] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program execution functions, such as a verification platform, storage device, computer, mobile phone, etc., or an electronic device capable of realizing the above functions.

[0032] Reference Figure 1 , Figure 1The illustration shows a first flowchart of the address management method provided in this application embodiment. In this application embodiment, the address management method can be applied to an address management module, which includes an address mapping table. In the initial address mapping table, unused logical addresses do not have a mapped physical address.

[0033] In this embodiment, the address management method described above can be applied to the address management module. The address management module includes an address mapping table, which is used to manage the mapping relationship between logical addresses and physical addresses during simulation testing. It's important to note that in relevant address management schemes, a mapping table is typically set up, and this mapping table is usually a complete table, resulting in a large size. For example, a complete mapping table typically means that logical addresses in the table are mapped to associated logical addresses regardless of whether they are used in the simulation test. Therefore, such mapping tables record a lot of redundant information, leading to high storage space consumption and simulation resource consumption. To address this issue, in this embodiment, the initial address mapping table is optimized in the simulation scenario. That is, unused logical addresses in the initial address mapping table do not have associated physical addresses. In other words, for a completely new address mapping table, the portion of available storage space corresponding to this address mapping table only records logical addresses and does not have mapped physical addresses, thus significantly reducing the size of the address mapping table.

[0034] Furthermore, it should be noted that, since the management functions corresponding to the address management method in this embodiment can be encapsulated into an address management module, and this module provides a unified configuration interface, parameters of the address management module can be configured through this interface for different test or simulation scenarios, such as configuring the address space range, mapping granularity, and granular logical structure attributes. Therefore, the address management module can be called by different test objects, thus decoupling the address management function from the specific simulation test content and objects, greatly improving the reusability of the address management module.

[0035] The address management method includes steps S10~S30: Step S10: Receive a data write operation and determine the write logical address information corresponding to the data write operation; It should be noted that, in practical applications, the aforementioned address management module can be set up within the verification platform. Optionally, the data write operation can be sent by the test object, which can be a front-end verification component, a DUT, or software interaction information, etc.

[0036] For example, a verification platform equipped with an address management module can continuously monitor the test object to receive data write operations initiated by the test object. Upon receiving a data write operation, the corresponding write logical address information can be determined based on the data write operation. The write logical address information is determined by the destination logical address where the data needs to be written. Optionally, the write logical addresses can be determined based on the write start logical address and write length of the write operation to form the write logical address information. Optionally, the write start logical address and write length can also be directly used as the write logical address information.

[0037] In one feasible implementation, the step of determining the write logical address information corresponding to the data write operation includes step S101: Step S101: Construct write logical address information based on the write start logical address and write operation length in the data write operation.

[0038] For example, a data write operation may include a write start logical address and a write operation length. After extracting the write start logical address and write operation length, these can be used as write logical address information. It should be noted that in this embodiment, different mapping strategies can be set for different simulation or verification scenarios. Under different mapping strategies, the content mapped in the address mapping table differs. Correspondingly, the content included in the write logical address information participating in the mapping may differ in different scenarios. In large-scale storage space simulation scenarios (e.g., the first-scale simulation scenario), the above-mentioned method of constructing write logical address information based on the write start logical address and write operation length can be selected. It can be understood that this method, which forms write logical address information including the write start logical address and write operation length, can represent a large range of addresses with less recorded content.

[0039] In one feasible implementation, the step of determining the write logical address information corresponding to the data write operation includes steps S11 to S12: Step S11: Determine the write logical address range based on the write start logical address and write operation length in the data write operation; Step S12: Align and expand the write logical address range based on a preset granularity to obtain each write logical address, wherein each write logical address is used to constitute write logical address information.

[0040] It should be noted that, in addition to large-scale storage space simulation scenarios, there are also small-scale storage space simulation scenarios (such as the second-scale simulation scenario, where the required storage space for simulation is smaller than that of the first-scale simulation scenario mentioned above). In such cases, the write logical address information can include each write logical address.

[0041] For example, the starting logical address and write operation length in a data write operation can be converted into a continuous address range based on the minimum addressing unit, i.e., the aforementioned write logical address interval. For instance, the starting sector of the write logical address interval is: input LBA (i.e., the start logical address of the write operation), and the ending sector of the write logical address interval is: starting sector + (write operation length) - 1.

[0042] For example, the write logical address range is then aligned and expanded based on a preset granularity to obtain each write logical address. Optionally, the preset granularity can be set according to actual application requirements; for example, the preset granularity can be 4KB. For example, the alignment operation can include: start address alignment (rounding down), calculating the logical page number where the start sector is located, and calculating the start sector address of that page; end address alignment (rounding up), calculating the logical page number where the end sector is located, and calculating the end sector address of that page. Expansion refers to generating addresses covering all complete logical pages within this range, i.e., the aforementioned write logical addresses, based on the aligned start and end sectors.

[0043] Step S20: Configure an idle physical address for writing logical address information; For example, after determining the write logical address information, physical resources are allocated to the write logical address information, that is, free physical addresses are configured for the write logical address information. Optionally, an equal number of available physical page addresses can be selected from the free pool according to the size of the write logical address information (such as the number of logical pages contained, or the write length), ensuring that each logical page can correspond to a unique physical destination.

[0044] For example, suppose the written logical address information contains 6 logical pages. Accordingly, 6 free physical page addresses can be selected from the available space. These free physical page addresses can be represented in multi-dimensional coordinates, such as: (Die0, Plane0, Block5, Page10), (Die0, Plane0, Block5, Page11), (Die0, Plane1, Block8, Page10), (Die1, Plane0, Block3, Page10), (Die1, Plane0, Block3, Page11), (Die1, Plane1, Block2, Page10).

[0045] In one feasible implementation, the step of configuring a free physical address for writing logical address information includes step S21: Step S21: Select an idle physical address from the preset virtual physical address pool that matches the length of the written logical address information. The distribution of the idle physical addresses satisfies the implementation conditions of the functions supported by the test object corresponding to the data writing operation.

[0046] It should be noted that the address management module can be configured with a preset virtual physical address pool, which can contain the physical addresses of available, unoccupied physical pages. The structure of the physical address is consistent with that of a real chip, and can include fields such as Die, Plane, Block, and Page.

[0047] For example, a number of free physical addresses matching the length of the written logical address information can be selected from a preset virtual physical address pool. Optionally, the distribution of the selected free physical addresses can also satisfy the implementation conditions of the functions supported by the test object. For example, the features supported by the DUT (such as Multi-Plane Program, Multi-Die Interleaving, Cache Program) can be analyzed, and then physical pages that can satisfy the concurrency conditions of these features can be selectively selected from the address pool. For example, the module may preferentially allocate a set of "empty pages" distributed across multiple dies (chips) and / or multiple planes, but with the same page number (row address). This distribution is a hardware prerequisite for enabling Multi-Plane operations (multiple planes concurrent within the same die) and Multi-Die operations (multiple dies fully concurrent).

[0048] Understandably, by selectively filtering idle physical addresses, the initiative and depth of verification are greatly enhanced. This allows the verification platform to not only passively respond to DUT requests but also proactively construct high-performance, high-concurrency extreme test scenarios, thereby more effectively verifying the performance of the DUT's command optimizer and hardware concurrency capabilities under real workloads.

[0049] Step S30: Associate the written logical address information with the free physical address mapping and record the mapping association in the address mapping table.

[0050] For example, the written logical address information is associated with the determined free physical address mapping, and the address mapping table is updated, that is, the mapping relationship between the written logical address information and the free physical address is recorded in the address mapping table.

[0051] In this embodiment, the address management method is applied to the address management module, which includes an address mapping table. Initially, unused logical addresses in the address mapping table do not have associated physical addresses. During actual Founder testing, a data write operation is received, and the write logical address information corresponding to the data write operation is determined. An idle physical address is configured for the write logical address information. The write logical address information is mapped and associated with the idle physical address, and the mapping relationship is recorded in the address mapping table. It is understood that in this embodiment, the initial address mapping table does not have associated physical addresses for unused logical addresses. However, during actual simulation testing, the write logical address information is determined based on actual testing requirements (such as data write operations), an idle physical address is configured for the write logical address information, and the address mapping table is updated to record the mapping relationship between the write logical address information and the idle physical address. The strategy of "generating physical addresses on demand" and establishing mappings is implemented. This means that physical addresses are dynamically allocated and mapping table entries are created only when a logical address is accessed for the first time. This approach aims to meet testing requirements while minimizing the recording of redundant information in the address mapping table, reducing the size of the address mapping table, thereby reducing the consumption of simulation memory and computing resources, improving simulation speed, and breaking through the bottleneck of verification efficiency.

[0052] In one feasible implementation, the steps of associating the written logical address information with the free physical address mapping and recording the mapping association in the address mapping table include steps S301 to S302: Step S301: When the written logical address information includes the write start logical address and the write operation length, the write start logical address and the write operation length are mapped and associated with the physical address information of the free physical address to obtain the first mapping association relationship. Step S302: Record the first mapping association in the address mapping table, or record the first mapping association and the debugging information related to the data writing operation in the address mapping table.

[0053] For example, when the write logical address information includes the write start logical address and the write operation length, the write start logical address and the write operation length are mapped and associated with the physical address information of the free physical address to form a first mapping association. Optionally, the physical address information of the free physical address can be represented by the write start physical address, by the write start physical address and the address length, by the write start physical address and the write end physical address, or by one or more data blocks corresponding to the free physical address. The first mapping association is then stored in an address mapping table, or the first mapping association is associated with debugging information related to the data write operation and stored in the address mapping table. For example, in the mapping table, the write start physical address, or the write start physical address and the write operation length, can be used as the primary key, and the value corresponding to each key can contain physical address information, or contain physical address information and debugging information. Optionally, the debugging information includes at least one of a timestamp, a system address, and an algorithm configuration. Optionally, the timestamp can be the initiation time of the data write operation. The system address can be a system memory address, that is, the source address of the data corresponding to the write operation in the host system memory. Algorithm configuration can be the strategy used for allocating free physical addresses (such as "forced multi-plane alignment mode", "random allocation mode", "wear leveling simulation mode", etc.).

[0054] Understandably, an address mapping table is constructed by mapping and associating the start logical address and write operation length with the physical address information of an available physical address. This ensures that a single data write operation only creates a mapping record with a granularity of 1 (i.e., one mapping record) in the address mapping table, thereby significantly reducing the amount of information recorded in the address mapping table. Therefore, this mapping method can further reduce the size of the address mapping table, thereby reducing the consumption of simulation memory and computing resources and improving simulation speed.

[0055] In one feasible implementation, the steps of associating the written logical address information with the free physical address mapping and recording the mapping association in the address mapping table include steps S31 to S33: Step S31: When the written logical address information includes each written logical address, map and associate each written logical address with an idle physical address to obtain a second mapping association relationship; Step S32: Record the second mapping association in the address mapping table, or record the second mapping association and debugging information related to the data writing operation in the address mapping table.

[0056] For example, when the written logical address information includes each written logical address, each written logical address is mapped one-to-one with a free physical address to form a second mapping relationship. Optionally, the logical address list (corresponding to each written logical address) and the physical address list (corresponding to a free physical address) are traversed, and the elements at corresponding positions are paired to form a mapping pair list, key-value pair, or dictionary, i.e., the aforementioned second mapping relationship. The second mapping relationship is then stored in an address mapping table, or the second mapping relationship is associated with debugging information related to the data write operation and stored in the address mapping table. For example, the logical address can be used as the primary key, and the value corresponding to each key is a composite structure containing the physical address, or containing the physical address and debugging information. For example, the debugging information related to the aforementioned data write operation is determined, and the debugging information includes at least one of timestamp, system address, and algorithm configuration. It is understood that the address mapping table in this embodiment can not only record the mapping relationship between logical addresses and physical addresses, but also associate and record debugging information related to data write operations, realizing "deep observability" of the verification process. When a test fails, by looking up the table, you can not only find out which logical address mapping is incorrect, but also immediately see when, under what test scenario, and for which part of the host data the mapping was established, so as to meet the actual simulation test requirements.

[0057] In one feasible implementation, after the step of configuring a free physical address for writing logical address information, the method includes steps S01 to S02: Step S01: Generate a sequence of write commands based on the generation parameters, wherein the generation parameters include at least one of the following: the length of the write operation in the data write operation, the functions supported by the test object corresponding to the data write operation, and the distribution of free physical addresses. Step S02: Send the write command sequence to the test object.

[0058] It should be noted that, in this embodiment, in addition to managing the mapping relationship between logical addresses and physical addresses, the address management module can also generate corresponding command sequences to provide incentives in a real host environment.

[0059] For example, multiple maintenance parameters for generating the write command sequence, namely the aforementioned generation parameters, are determined to make the optimal instruction sequence decision. Optionally, the generation parameters may include at least one of the following: the write operation length in the data write operation, the functions supported by the test object corresponding to the data write operation, and the distribution of free physical addresses. The write operation length refers to the number of pages to be written, which determines the basic length of the command sequence. The functions supported by the test object can be read from the DUT's configuration model or feature registers to determine whether it supports advanced commands such as Cache Program, Multi-Plane Program, and Toggle Mode. This is to avoid generating commands that the test object's functions do not support when generating the command sequence. The distribution of free physical addresses may refer to the distribution characteristics of the allocated physical addresses in the Die, Plane, Block, and Page maintenance in the above embodiments.

[0060] For example, the module can adaptively generate optimized and real write command sequences based on the generated parameters, and send the write command sequences to the test object, causing the test object and the write command sequences to execute the write operation. Optionally, based on the write operation length, the distribution of free physical addresses, and the functions supported by the test object (such as CacheProgram, Multi-Plane Program), the module can automatically adapt and generate a series of optimized and real NAND interface command sequences (such as combinations of commands like Multi-plane program, Multi-plane cache program, page program, etc.). This ensures that the stimulus applied to the test object by the verification platform is highly consistent with the behavior in a real host environment.

[0061] Optionally, the adaptive generation strategy for write command sequences may include: if the physical address distribution supports Multi-Plane, the generator will use the Multi-Plane Program command to merge write operations of two Planes into a single command. If the operation length is large and the DUT supports Cache Program, the generator will interleave Cache Program commands and ordinary Program commands to form a pipeline that "programs the previous page while loading the next page of data," thus hiding the long tPROG (programming time). If the address spans multiple dies, the generator will generate independent command streams for different dies and ensure that they overlap in time to simulate multi-die concurrency. Transmission mechanism: The generated command sequence is converted into a series of bus transactions or direct level signals, which are applied to the DUT's NAND interface pins by the verification platform's NAND PHY or Bus Function Model (BFM). Specifically, the generation method or strategy for the write command sequence can be set by technical personnel according to actual needs, and will not be elaborated here.

[0062] In one feasible implementation, the address management method further includes step S100: Step S100: Modify the address mapping table based on preset conditions. When the preset condition is receiving an erase operation, the modification operation is to delete the mapping relationship pointed to by the erase operation in the address mapping table. When the preset condition is triggering storage space fragmentation reclamation, the modification operation is to update the mapping relationship of valid data for storage space fragmentation reclamation in the address mapping table.

[0063] It should be noted that, in this embodiment, the verification platform can modify existing address mapping relationships in the address mapping table based on preset conditions. Optionally, the preset conditions may be receiving an erase operation, wherein receiving an erase operation may include an erase start logical address, or may include an erase start logical address and an erase length. Optionally, the mapping relationship pointed to by the erase operation in the address mapping table may be the mapping relationship between the erase start logical address and the physical address in the address mapping table, or the mapping relationship between logical addresses within the range corresponding to the erase start logical address and the erase length and their physical addresses in the address mapping table. Correspondingly, the modification operation can delete the pointed-to mapping relationship.

[0064] Optionally, the preset condition can also be to trigger storage space fragmentation reclamation, also known as garbage collection. When storage space fragmentation reclamation is triggered, specific valid data will be moved from the old data block to the new data block. Accordingly, the mapping relationship between the logical address and physical address of this valid data needs to be updated. For example, the logical address of the valid data is no longer associated with the physical address of the old data block, but is now associated with the physical address of the new data block. In other words, the change operation in this case is to update the mapping relationship (the mapping relationship between logical address and physical address) of valid data in the address mapping table.

[0065] Additionally, it should be noted that the verification platform where the address management module is located in this embodiment supports garbage collection (GC). Optionally, after one or more write operations, the verification platform can trigger a garbage collection process according to a preset strategy (such as the physical address pool being below a threshold) or configurably. Optionally, the garbage collection process can be as follows: a. Data integration: The GC module selects the data blocks to be reclaimed (e.g., a small number of valid data pages), and reads all the data pages that are still "valid" (their mapping relationship still exists in the address mapping table).

[0066] b. Data migration and table update: After reading these valid data sets, write them centrally into a new, free physical data block. Subsequently, update the address mapping table, replacing the old mapping relationship with the original logical address mapping relationship with the new physical address mapping relationship.

[0067] c. Block erasure and resource reclamation: The GC module simulates the issuance of the BLOCK ERASE command to erase the old data blocks after reclamation, forming new free physical data blocks, and releasing all physical addresses in them back to the physical address pool, i.e., the aforementioned preset virtual physical address pool, thus completing resource reclamation.

[0068] Reference Figure 2 This diagram illustrates the principle of garbage collection in this embodiment. Data block a and data block b represent the currently selected data blocks to be collected (source blocks), where valid and invalid data coexist on their internal pages; data block c represents the target free block (target block) used to receive the migrated data, and the valid data in data blocks a and b are centrally stored in data block c.

[0069] Reference Figure 3 , Figure 3 This illustration shows a second flowchart of the address management method provided in an embodiment of this application. Contents in this embodiment that are the same as or similar to those in the above embodiments can be referred to the above description and will not be repeated hereafter. The address management method further includes steps A10 to A20: Step A10: Receive a data read operation and determine the read logic address information corresponding to the data read operation; It should be noted that, in addition to initiating data write operations, the test object can also initiate data read operations.

[0070] For example, the address management module can receive data read operations sent by the test object. It then determines the corresponding read logical address information based on the data read operation. The processing logic is similar to that of a write operation, involving parsing the start read logical address and the write operation length, performing address alignment and expansion, and finally generating a read logical address. Alternatively, the start read logical address and the write operation length can be directly used as the read logical address information.

[0071] In one feasible implementation, the step of determining the read logical address information corresponding to the data read operation includes steps A11 to A12: Step A11: Determine the read logical address range based on the read start logical address and read operation length in the data read operation; Step A12: Align and expand the read logical address range based on a preset granularity to obtain each read logical address, wherein each read logical address is used to constitute read logical address information.

[0072] It should be noted that steps A11-A12 are implemented similarly to steps S11-S12 above, and this step mainly focuses on the initial address parsing of the read operation. After the address management module receives and parses a data read operation, it can extract the read start logical address (Read LBA) and read operation length (Read 4k_Len). Based on the read start logical address and read operation length, a read logical address range is calculated. This range is then aligned and expanded using a preset granularity to obtain the read logical address information. Similarly, the read logical address range can be aligned and expanded using a preset granularity to obtain the read logical address information. Optional implementation methods can refer to steps S11-S12 above, and will not be repeated here.

[0073] In one feasible implementation, the step of determining the read logical address information corresponding to the data read operation includes step A101: Step A101: Construct read logical address information based on the read start logical address and read operation length in the data read operation.

[0074] It should be noted that step A101 is implemented in a similar way to step S101 described above, and this step mainly focuses on the preliminary address parsing of the read operation. For example, the read start logical address and read operation length can be extracted from the data read operation, and then the extracted read start logical address and read operation length can be used as read logical address information.

[0075] It should be noted that whether the read logical address information includes each read logical address or includes the read start logical address and read operation length depends on the actual storage space simulation scenario in the application. For example, in a large-scale storage space simulation scenario (such as the first-scale simulation scenario mentioned above), the read logical address information may include the read start logical address and read operation length. However, in a small-scale storage space simulation scenario (such as the second-scale simulation scenario mentioned above, where the storage space required for simulation in the first-scale simulation scenario is larger than that in the second-scale simulation scenario), the read logical address information may include the read start logical address and read operation length.

[0076] Step A20: Based on the read logical address information, query the address mapping table to obtain the target physical address corresponding to the read logical address information.

[0077] For example, a lookup is performed in the address mapping table based on the read logical address information. Optionally, each logical address involved in the logical address information can be read as a lookup key in the address mapping table (hash table / associative array). The goal of the lookup is to obtain the "correct" physical page address mapped to each read logical address during writing, i.e., the target physical address corresponding to the read logical address information. It is understood that this embodiment can simplify the address mapping operation to a table entry lookup operation, which can significantly improve the simulation speed.

[0078] In one feasible implementation, after the step of querying the address mapping table based on reading logical address information, the method includes: Step A30: After obtaining the target physical address, generate a read command sequence for the target physical address and send the read command sequence to the test object corresponding to the data write operation; It should be noted that there are two possible results when querying the address mapping table: either the target physical address is found, or the target physical address is not found.

[0079] For example, given the target physical address, a corresponding read command sequence (such as PAGE READ or MULTI-PLANE READ) can be generated based on the target physical address and sent to the test object corresponding to the data write operation through the relevant command component. Optionally, based on the queried target physical address, a corresponding NAND read command sequence (such as 00h - address period - 30h) can be generated using a command sequence generator. Optionally, if the physical address distribution supports Multi-Plane Read, the generator will also optimize the command. For example, for physical addresses (0,0,5,10) and (0,1,5,10), the generator may generate a Multi-Plane Read command sequence to read the data from Page 10 of both planes at once. After receiving the read command sequence, the test object can complete the data read operation according to the read command sequence.

[0080] Step A40: Compare the actual data read by the test object based on the read command sequence with the expected data corresponding to the data read operation to verify the address mapping result.

[0081] For example, the test object can read actual data based on a read command sequence. The actual data is then compared with the expected data corresponding to the data read operation. The address mapping result is verified by the consistency between the actual and expected data. If the actual and expected data are inconsistent, it indicates that there may be errors in the address mapping relationship or other aspects, thus providing a reference for functional testing verification. Optionally, the expected data corresponding to the data read operation can be obtained from the address mapping table. For example, during the data writing phase, when updating the address mapping table, the debugging information associated with the mapping relationship can include the original data to be written. Optionally, a dedicated "expected data pool" can also be maintained for read verification. The data initially written to these logical addresses is retrieved from the "expected data pool" maintained by the verification platform. The expected data pool is updated according to the system memory address and data content each time a write operation is successful.

[0082] Understandably, in this embodiment, comparison and verification can provide the ultimate and objective criterion for the correctness of the entire data path and address mapping function. If the comparison is consistent, it proves that the complete chain from logical address mapping, physical address allocation, data programming, to address query and data reading is completely correct. If they are inconsistent, it clearly indicates that there is a defect in a certain link (e.g., it may be mapping management or data processing of the test object), thus meeting specific simulation test requirements.

[0083] In one feasible implementation, the step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes steps A21 to A22: Step A21: If the read logical address information includes each read logical address, use each read logical address in the read logical address information as an index key to perform a lookup in the address mapping table; Step A22: If the query determines that each read logical address is mapped to a physical address, then each mapped physical address is used as the target physical address.

[0084] For example, when the read logical address information includes each read logical address, for any read logical address in the read logical address information, the address mapping table data structure can be accessed and retrieval can be performed using that read logical address as the index key. This process can be repeated to traverse each read logical address in the read logical address information.

[0085] For example, if it is determined through querying that each read logical address is mapped to a physical address in the address mapping table, then the table lookup is successful. Accordingly, the physical address mapped to each read logical address obtained through the query can be used as the target physical address.

[0086] For example, if a query determines that a logical address is not mapped to a physical address in the address mapping table, this means the test object is attempting to read an address that has never been written to, i.e., the table lookup failed. Accordingly, an error message can be output, i.e., an error or assertion failure can be reported, and detailed debugging information can be recorded. Understandably, this embodiment effectively captures issues such as unauthorized access to test objects, inconsistent mapping tables, or state machine errors. It enhances the robustness of the verification platform and its ability to verify exception handling logic, ensuring that any unexpected behavior can be detected and located promptly, preventing errors from being masked and propagated to subsequent testing phases.

[0087] In one feasible implementation, the address mapping table is associated with a sequence of write logical addresses, which is determined by the write start logical address of each historical data write operation; the step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes steps A201~A203: Step A201: When the read logical address information includes the read start logical address and the read operation length, query the write logical address sequence for a candidate write start logical address that matches the read start logical address; Step A202: Use the candidate write start logical address as the index key to query the address mapping table and obtain the candidate physical address information corresponding to the candidate write start logical address; Step A203: Based on the offset between the read start logical address and the candidate write start logical address, and the read operation length, determine the target physical address information from the candidate physical address information, wherein the address under the target physical address information is used as the target physical address.

[0088] It should be noted that, in this embodiment, in order to adapt to the address mapping table formed by mapping and associating the write start logical address and the write operation length with the physical address information of the free physical address, a corresponding write logical address sequence will also be configured for the address mapping table. The write logical address sequence is determined by the write start logical address of each historical data write operation. Optionally, each time a data write operation is received and the write start logical address is extracted from the data write operation, the write start logical address can be inserted into the write logical address sequence in address order.

[0089] For example, when the read logical address information includes the read start logical address and the read operation length, a query can be performed in the write logical address sequence based on the read start logical address to obtain candidate write start logical addresses that match the read start logical address. Optionally, a write start logical address in the write logical address sequence that is the same as the read start logical address can be used as a candidate write start logical address. Optionally, a write start logical address in the write logical address sequence that is closest to the read start logical address (or within a preset range) and smaller than the read start logical address can be used as a candidate write start logical address.

[0090] For example, the candidate write start logical address is used as the index key to look up the address mapping table. Since there is a correspondence between the address mapping table and the write logical address sequence, the address mapping table usually contains a record corresponding to the candidate write start logical address. The physical address information in this record is the candidate physical address information corresponding to the candidate write start logical address. Then, based on the offset between the read start logical address and the candidate write start logical address, and the length of the read operation mentioned above, the target physical address information is determined from the candidate physical address information. For example, offsetting the starting position of the candidate physical address information by this offset (where the offset can be zero) yields the starting address of the target physical address information. Then, using the read operation length as the length of the target physical address information, the target physical address information is formed. Finally, the address under the target physical address information is the target physical address.

[0091] It is understandable that the above process is an address mapping table lookup method proposed to adapt to a specific mapping table (an address mapping table formed by mapping and associating the write start logical address and write operation length with the physical address information of the free physical address), which ensures the simulation of normal read and write operations while reducing the size of the address mapping table.

[0092] This application also provides a verification platform, such as Figure 4 As shown, the verification platform includes an address management module 10, which includes an address mapping table. The address management module 10 also includes: The parsing unit 11 is used to receive data write operations and determine the write logical address information corresponding to the data write operation; The physical address pool allocation unit 12 is used to configure free physical addresses for writing logical address information; Address mapping unit 13 is used to associate written logical address information with free physical address mapping and to record the mapping association in the address mapping table.

[0093] It should be noted that the verification platform provided in this application can solve the technical problem in related address management schemes where maintaining the mapping table requires a large amount of simulation resources, resulting in slow simulation speed. Compared with related technologies, the implementation method and beneficial effects of the verification platform provided in this application are consistent with the implementation method and beneficial effects of the address management method provided above, and will not be repeated here.

[0094] This application provides an electronic device, which includes a processor, a memory, and an address management method program stored in the memory and executable on the processor. When the address management method program is executed, it implements the steps of the address management method as described in the above embodiments.

[0095] The electronic device provided in this application can be a programmable logic chip, or other devices including a programmable logic chip. Furthermore, this electronic device can solve the technical problem in related address management schemes where maintaining the mapping table requires a large amount of simulation resources, resulting in slow simulation speed. Compared with related technologies, the beneficial effects of the electronic device provided in this application are the same as those of the address management method provided in the above embodiments, and will not be repeated here.

[0096] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the address management method in the above embodiments.

[0097] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0098] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0099] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to: Receive a data write operation, determine the write logical address information corresponding to the data write operation; configure an idle physical address for the write logical address information; map and associate the write logical address information with the idle physical address, and record the mapping relationship in the address mapping table.

[0100] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0101] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0102] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0103] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described address management method. This solves the technical problem in related address management schemes where maintaining the mapping table requires significant simulation resources, resulting in slow simulation speed. Compared with related technologies, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the address management method provided in the above embodiments, and will not be elaborated upon here.

[0104] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the address management method described above.

[0105] The computer program product provided in this application can solve the technical problem in related address management schemes where maintaining the mapping table requires a large amount of simulation resources, resulting in slow simulation speed. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as those of the address management method provided in the above embodiments, and will not be repeated here.

[0106] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. An address management method, characterized in that, It is applied to the address management module, which includes an address mapping table, wherein unused logical addresses in the initial address mapping table do not have any associated physical addresses; The address management method includes: Receive a data write operation and determine the write logical address information corresponding to the data write operation; Configure an idle physical address for the written logical address information; The written logical address information is mapped and associated with the free physical address, and the mapping relationship is recorded in the address mapping table.

2. The address management method as described in claim 1, characterized in that, The step of determining the write logical address information corresponding to the data write operation includes: The write logical address information is constructed based on the write start logical address and write operation length in the data write operation.

3. The address management method as described in claim 1, characterized in that, The step of mapping and associating the written logical address information with the free physical address and recording the mapping association in the address mapping table includes: When the write logical address information includes the write start logical address and the write operation length, the write start logical address and the write operation length are mapped and associated with the physical address information of the free physical address to obtain a first mapping association relationship; Record the first mapping association in the address mapping table, or record the first mapping association with the debugging information related to the data writing operation in the address mapping table.

4. The address management method as described in claim 1, characterized in that, The step of determining the write logical address information corresponding to the data write operation includes: The write logical address range is determined based on the write start logical address and write operation length in the data write operation; The write logical address range is aligned and expanded based on a preset granularity to obtain each write logical address, wherein each write logical address is used to constitute the write logical address information.

5. The address management method as described in claim 1, characterized in that, The step of mapping and associating the written logical address information with the free physical address and recording the mapping association in the address mapping table includes: When the write logical address information includes each write logical address, the write logical address is mapped and associated with the free physical address to obtain a second mapping association relationship; Record the second mapping association in the address mapping table, or associate the second mapping association with debugging information related to the data write operation and record it in the address mapping table.

6. The address management method as described in claim 1, characterized in that, The step of configuring a free physical address for the written logical address information includes: From the preset virtual physical address pool, select an idle physical address that matches the length of the written logical address information, wherein the distribution of the idle physical addresses satisfies the implementation conditions of the function supported by the test object corresponding to the data writing operation.

7. The address management method as described in claim 1, characterized in that, After the step of configuring a free physical address for writing the logical address information, the method includes: A sequence of write commands is generated based on the generation parameters, wherein the generation parameters include at least one of the following: the write operation length in the data write operation, the functions supported by the test object corresponding to the data write operation, and the distribution of the free physical addresses. The write command sequence is sent to the test object.

8. The address management method as described in claim 1, characterized in that, The address management method further includes: Receive a data read operation and determine the read logic address information corresponding to the data read operation; Based on the read logical address information, a query is performed in the address mapping table to obtain the target physical address corresponding to the read logical address information.

9. The address management method as described in claim 8, characterized in that, After the step of querying the address mapping table based on the read logical address information, the method includes: Once the target physical address is obtained, a read command sequence for the target physical address is generated, and the read command sequence is sent to the test object corresponding to the data write operation. The actual data read by the test object based on the read command sequence is compared with the expected data corresponding to the data read operation to verify the address mapping result.

10. The address management method as described in claim 8, characterized in that, The address mapping table is associated with a sequence of write logical addresses, which is determined by the write start logical address of each historical data write operation. The step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes: When the read logical address information includes the read start logical address and the read operation length, a candidate write start logical address that matches the read start logical address is queried in the write logical address sequence; The candidate write start logical address is used as the index key to query the address mapping table and obtain the candidate physical address information corresponding to the candidate write start logical address. The target physical address information is determined based on the offset between the read start logical address and the candidate write start logical address, the read operation length, and the candidate physical address information, wherein the address under the target physical address information is used as the target physical address.

11. The address management method as described in claim 8, characterized in that, The step of querying the address mapping table based on the read logical address information to obtain the target physical address corresponding to the read logical address information includes: When the read logical address information includes each read logical address, each read logical address is used as an index key to perform a lookup in the address mapping table; If the query determines that each of the read logical addresses is mapped to a physical address, then each mapped physical address is used as the target physical address.

12. The address management method as described in claim 1, characterized in that, The address management method further includes: The address mapping table is modified based on preset conditions. When the preset condition is receiving an erase operation, the modification operation deletes the mapping relationship pointed to by the erase operation in the address mapping table. When the preset condition is triggering storage space fragmentation reclamation, the modification operation updates the mapping relationship of the valid data of storage space fragmentation reclamation in the address mapping table.

13. A verification platform, characterized in that, The verification platform includes an address management module, which includes an address mapping table. The address management module also includes: A parsing unit is used to receive a data write operation and determine the write logical address information corresponding to the data write operation. A physical address pool allocation unit is used to configure free physical addresses for the written logical address information; The address mapping unit is used to associate the written logical address information with the free physical address mapping and to record the mapping association in the address mapping table.

14. An electronic device, characterized in that, The electronic device includes: a processor, a memory, and an address management method program stored in the memory and executable on the processor, wherein the address management method program, when executed, implements the steps of the address management method as described in any one of claims 1-12.

15. A computer program product, characterized in that, The computer program product includes an address management method program, which, when executed by a processor, implements the steps of the address management method as described in any one of claims 1-12.

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