Address conversion method and data processing equipment

Abstract

The invention provides an address conversion method and data processing equipment, the data processing equipment comprises an address conversion module, a multi-stage query controller, a hierarchical extension decision unit and a shadow buffer, and the method comprises the following steps: the address conversion module determines a target query key in response to an address conversion request; the multi-stage query controller queries an initial translation lookaside buffer TLB structure stage by stage based on the target query key to obtain a query result, and the query result comprises a target page table item which is not queried or a target page table item matched with the address translation request; the hierarchical extension decision unit responds to the situation that the target page table item is not queried, each page table item in the initial TLB structure is migrated to a shadow buffer area, and the shadow buffer area which works stably is determined as an extended target TLB structure; the target TLB structure is used for next address translation.

Description

Technical Field

[0001] This application relates to, but is not limited to, data processing technology, and in particular to an address translation method and a data processing device. Background Technology

[0002] Memory management is a key technology for improving the performance and stability of data processing devices. A paged memory management mechanism is typically used, which achieves efficient memory management through the mapping of virtual addresses to physical addresses. However, this mechanism relies on a multi-level page table structure to record address mapping relationships, resulting in high access latency due to the need for multiple accesses to physical memory to complete address translation. Related technologies often use a Translation Lookahead (TLB) to cache frequently used page table entries to reduce the number of accesses to the physical page table. However, due to limitations in TLB capacity and structural design, when frequently accessed addresses are not found, a fallback to the physical page table is still required, impacting performance. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one address translation method and a data processing device.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides an address translation method applied to a data processing device. The data processing device includes an address translation module, a multi-level query controller, and a hierarchical expansion decision unit. The method includes: the address translation module determining a target query key in response to an address translation request; the multi-level query controller querying the initial translation back buffer (TLB) structure level by level based on the target query key to obtain query results, wherein the query results include: no target page table entry found, or a target page table entry matching the address translation request; the hierarchical expansion decision unit migrating each page table entry in the initial TLB structure to a shadow buffer in response to no target page table entry found, and determining the shadow buffer after stable operation as the expanded target TLB structure; the target TLB structure is used for the next address translation.

[0005] This application provides a data processing device, including an address translation module, a multi-level query controller, and a hierarchical expansion decision unit. The address translation module is used to determine a target query key in response to an address translation request. The multi-level query controller is used to query the initial translation back buffer (TLB) structure level by level based on the target query key to obtain query results, wherein the query results include: no target page table entry found, or a target page table entry matching the address translation request. The hierarchical expansion decision unit is used to migrate each page table entry in the initial TLB structure to a shadow buffer in response to no target page table entry found, and to determine the stabilized shadow buffer as the expanded target TLB structure. The target TLB structure is used for the next address translation.

[0006] In this embodiment, the address translation module generates a target query key in response to an address translation request; the multi-level query controller queries the initial TLB structure level by level based on the target query key to obtain query results; the hierarchical expansion decision unit, in response to the query result not finding the target page table entry, migrates each page table entry in the initial TLB structure to the shadow buffer, and determines the shadow buffer after it has stabilized as the expanded target TLB structure; the target TLB structure is used for the next address translation. In this way, the shadow buffer enables parallel operation of the old and new levels, achieving a smooth transition between the old and new structures and avoiding resource allocation conflicts and increased address translation latency. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0008] Figure 1 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 1 ; Figure 2 A schematic diagram illustrating the implementation flow of an address translation method provided in an embodiment of this application; Figure 3 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 2 ; Figure 4 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 3 ; Figure 5 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 4 ; Figure 6 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 5 ; Figure 7 A schematic diagram illustrating the implementation process of a RISC-V address translation method based on a multi-level scalable TLB provided in this application embodiment; Figure 8 This is a schematic diagram of a dynamic hierarchical expansion stage state machine provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0010] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0011] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0012] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to be limiting of this application.

[0013] This application provides a data processing device. Figure 1 A schematic diagram of the composition structure of a data processing device provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the data processing device 100 includes an address translation module 101, a multi-level query controller 102, a hierarchical expansion decision unit 103, and a shadow buffer 104, wherein: Data processing device 100 is a hardware device used for handling large-scale data computation and multi-task concurrency. The data processing device can be a high-performance server based on the RISC-V instruction set architecture.

[0014] Address translation module 101 is a hardware module in data processing device 100 used to receive and respond to address translation requests.

[0015] The multi-level query controller 102 is a hardware component in the data processing device 100 used to query the TLB structure and efficiently locate target page entries. The core functions of the multi-level query controller include hash calculation, group index generation, and hit determination.

[0016] The hierarchical expansion decision unit 103 is a hardware component in the data processing device 100 used to monitor the query results of the multi-level query controller on the TLB structure and control the dynamic hierarchical expansion of the TLB structure based on the query results.

[0017] The shadow buffer 104 is used to cache frequently accessed page table entries in the initial TLB structure during dynamic expansion of the TLB level, so as to maintain a high hit rate and reduce access latency during the switch between old and new levels. After the migration is completed, the shadow buffer becomes the expanded target TLB structure.

[0018] In some implementations, the shadow buffer 104 includes multiple hierarchical buffers, wherein the first and second hierarchical buffers have the same structure as the first and second level TLBs of the initial TLB structure. The third hierarchical buffer is a newly added TLB level compared to the initial TLB structure.

[0019] This application provides an address translation method applied to the aforementioned data processing device 100. Figure 2 This is a schematic diagram illustrating the implementation flow of an address translation method provided in an embodiment of this application, as shown below. Figure 2 As shown, the method includes the following steps S201 to S203: Step S201: The address translation module responds to the address translation request and determines the target query key; Here, an address translation request is a process request initiated by a processor or device in a data processing apparatus to translate a virtual address into a physical address. In some implementations, the processor may be a processor based on an open-source instruction set architecture based on Reduced Instruction Set Computing (RISC) principles.

[0020] The target lookup key is a multi-field combination structure used to uniquely identify and efficiently match page table entries in the TLB structure. In some implementations, the target lookup key may include a Virtual Page Number (VPN), an Address Space Identifier (ASID), and a Virtual Machine Identifier (VMID). The VPN is a number used to identify a specific page in the virtual address space; the ASID is an identifier used to distinguish the address spaces of different processes or virtual machines; and the VMID is an identifier used to uniquely identify a virtual machine (VM).

[0021] In some implementations, when a device in the data processing equipment has an address translation requirement, it sends an address translation request to the address translation module. The address translation module responds to the address translation request and determines the target query key corresponding to the address translation request.

[0022] In some implementations, the address translation module responds to an address translation request by obtaining the address space identifier, virtual machine identifier, and virtual address to be translated from the sending device of the address translation request, extracting the virtual page number from the virtual address, and finally generating a target query key that includes the address space identifier, virtual machine identifier, and virtual page number. In one example, the address space identifier is 0x1234, the virtual machine identifier is 0x5678, the virtual address is 0xABCDEF00, the virtual page number extracted from the virtual address is 0xABCD, and the final generated target query key can be {0xABCD, 0x1234, 0x5678}.

[0023] Step S202: The multi-level query controller queries the initial translation back buffer (TLB) structure level by level based on the target query key to obtain the query results, which include: no target page table entry found, or a target page table entry that matches the address translation request; Here, the initial Translation Lookaside Buffer (TLB) structure is used to cache frequently used page table entries to reduce the number of accesses to the physical page table.

[0024] In some implementations, the TLB structure leverages the principles of temporal and spatial locality of reference to cache frequently used page table entries. When address translation is required, the corresponding physical address is first searched in the TLB structure. If found in the TLB, the physical address can be used directly to access memory, eliminating the need to access the page table in memory, thus significantly reducing memory access frequency and improving memory access efficiency. For example, when a program frequently accesses a specific memory region, the page table entry corresponding to that region is cached in the TLB structure. Subsequent accesses to that region can quickly retrieve the physical address from the TLB structure, greatly improving access speed.

[0025] In some implementations, the initial TLB structure can be a scalable TLB structure established by the processor through the memory management control unit in the data processing device during startup. The first-level TLB of the initial TLB structure uses a fully associative structure for storing frequently accessed page table entries; the second-level TLB uses a set-associative structure for storing medium-frequency accessed page table entries. The associativity parameter is a key indicator describing the internal organization of the TLB, i.e., the storage and lookup method of each page table entry in the TLB structure. Higher associativity results in a lower probability of conflict, but also higher hardware overhead. During dynamic expansion, the associativity parameter needs to be adjusted using atomic configuration update instructions. A fully associative structure means that page table entries can be stored in any location without fixed grouping. Fully associative structures offer the fastest query speed but have higher hardware costs and are typically used for the first-level TLB. A set-associative structure means that page table entries are divided into groups, with each group containing several entries. During a query, the target group is first determined, and then all entries within the group are compared to find a match. The set-associative structure strikes a balance between hit rate and hardware complexity.

[0026] In some implementations, when establishing the initial TLB structure, a dynamic extension flag is configured for each TLB level of the initial TLB structure for subsequent TLB structure level expansion.

[0027] In some implementations, a multi-level query controller is a hardware component used to perform step-by-step queries on the TLB structure according to a preset priority order. The multi-level query controller queries the TLB structure step-by-step according to the preset priority order and generates target group indexes to efficiently locate target page table entries. Its core functions include hash calculation, group index generation, and hit determination.

[0028] When the multi-level query controller queries the initial TLB structure level by level, it first queries the first-level TLB based on the target query key. If the target page table entry is found in the first-level TLB, the query result is determined to be a target page table entry found, as well as a target page table entry that matches the address translation request. The initial TLB structure determines the corresponding physical address based on the target page table entry and sends the physical address to the sender of the address translation request. If the target page table entry is not found in the first-level TLB, the multi-level query controller continues to query the second-level TLB.

[0029] In some implementations, the multi-level query controller directly queries the second-level TLB based on the target query key.

[0030] In some implementations, when querying the second-level TLB, the multi-level query controller employs a dynamic group selection algorithm based on access frequency. This algorithm weights the hash value of the target query key with the most recently accessed group index to generate a target group index, which is then used to query the second-level TLB. For example, assuming the hash value of the target query key... See the following formula (1): (1); in, For address space identifiers, For virtual machine identifier, This is a virtual page number.

[0031] Extract the index of the most recently successfully accessed group from the group access history table corresponding to the second-level TLB. This index reflects the spatial or temporal locality trend of the current access sequence. Final target group index. The result is obtained through weighted fusion calculation, see formula (2): (2); in, and These are the hash weight coefficient and the locality weight coefficient for the current time period, respectively. The initial value is set to 0.7. The initial value is set to 0.3, indicating that in the initial stage, it tends to rely on the hash distribution of the keys to achieve broad coverage and adapt to the global randomness of the address space. N represents the number of groups in the current level TLB, provided by the status register.

[0032] In some implementations, the target group indexing mechanism adaptively generates target access groups based on both address distribution and historical access patterns, thereby reducing conflict rates and increasing the cache hit probability of mid-frequency page table entries. To further enhance the algorithm's adaptability, a periodic evaluation window is set. At the end of each window period, the current level's usage of existing... and The hit rate fluctuation under certain parameters is analyzed, and the weight parameters are fine-tuned based on the gain trend. If the local hit effect is enhanced, the accuracy is increased. Value, otherwise enhance This improves key-value dispersion. The adjustment process is synchronized by the expansion phase flag in the hierarchical status register and only performs weight modifications during non-expansion periods to avoid group index conflicts or query path inconsistencies during hierarchical structure changes, thereby ensuring the computational security and access consistency of the dynamic group selection logic in the expansion environment.

[0033] In some implementations, if a target page table entry is found in the second-level TLB, the query result is determined to be a found target page table entry and a target page table entry matching the address translation request. The initial TLB determines the corresponding physical address based on the target page table entry and sends the physical address to the sender of the address translation request. If the target page table entry is not found in the second-level TLB, the query result is determined to be no found target page table entry. The multi-level query controller sends the query result to the page table traversal unit, so that the page table traversal unit obtains the target page table entry by traversing the multi-level page tables, determines the corresponding physical address based on the target page table entry, and sends the physical address to the sender of the address translation request.

[0034] In some implementations, after determining the query result, the multi-level query controller sends the query result to the hierarchical expansion decision unit, so that the hierarchical expansion decision unit can determine whether to trigger dynamic hierarchical expansion of the initial TLB structure based on the query result. The query result may include: no target page table entry found, or a target page table entry matching the address translation request.

[0035] Step S203: In response to the failure to find the target page table entry, the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, and determines the shadow buffer after it has stabilized as the expanded target TLB structure; the target TLB structure is used for the next address translation.

[0036] Here, the shadow buffer is used to cache frequently accessed page table entries in the initial TLB structure during dynamic expansion of the TLB level, in order to maintain a high hit rate and reduce access latency during the switch between old and new levels. After the migration is complete, the shadow buffer becomes the expanded target TLB structure.

[0037] In some implementations, the shadow buffer includes multiple hierarchical buffers, wherein the first and second level buffers have the same structure as the first and second level TLBs of the initial TLB structure. The third level buffer is a newly added TLB level compared to the initial TLB structure.

[0038] In some implementations, after migrating each page table entry in the initial TLB structure to the shadow buffer, the initial TLB structure and the shadow buffer work simultaneously. After verifying the query results of the shadow buffer for multiple cycles, the shadow buffer becomes stable and is determined as the target TLB structure.

[0039] In some implementations, the third-level buffer in the shadow buffer can employ a block-associative structure. The third-level buffer is divided into multiple fixed-size sub-regions (e.g., each block contains 16 groups). Each block uses an N-way set-associative mapping, allowing storage blocks to be freely located in any of the N locations within any group of the block. Different blocks are directly mapped to fixed locations via the high-order bits of the address, avoiding cross-block conflicts.

[0040] In some implementations, the newly added third-level buffer reserves space for four logically contiguous bigpage entries per entry, thereby reducing the number of accesses and lookup latency during bigpage mapping. Each entry is equipped with an independent bigpage replacement counter to record the independent access frequency of the four subpage entries. The counter uses a weighted update mechanism to prioritize the retention of high-frequency subpages.

[0041] In some implementations, the hierarchical expansion decision unit receives query results from the multi-level query controller and determines whether to trigger dynamic hierarchical expansion of the TLB structure based on the query results. If the query result indicates that the target page table entry has been found, it is determined that dynamic hierarchical expansion of the TLB structure will not be triggered; if the query result indicates that the target page table entry has not been found, it is determined that dynamic hierarchical expansion of the TLB structure will be triggered.

[0042] In some implementations, when performing dynamic hierarchical expansion of the TLB structure, the hierarchical expansion decision unit activates the shadow buffer and migrates page table entries with high access frequency in the initial TLB hierarchy to the shadow buffer. The shadow buffer works simultaneously with the initial TLB hierarchy. After the shadow buffer stabilizes, the shadow buffer is determined as the target TLB structure.

[0043] In some implementations, when the page table entries in the initial TLB structure begin to migrate, the hierarchical status register automatically switches from the preparation state to the switching state. After the shadow buffer structure stabilizes, the migration ends, and after the consistency check between the shadow buffer and the initial TLB structure is completed, it enters the completion state. The hierarchical status register is written with the completion code. At this time, the flag of the initial TLB structure is set to the frozen state, and the resource reclamation mechanism is triggered.

[0044] In this embodiment, the address translation module generates a target query key in response to an address translation request; the multi-level query controller queries the initial TLB structure level by level based on the target query key to obtain query results; the hierarchical expansion decision unit, in response to the query result not finding the target page table entry, migrates each page table entry in the initial TLB structure to the shadow buffer, and determines the shadow buffer after it has stabilized as the expanded target TLB structure; the target TLB structure is used for the next address translation. In this way, the shadow buffer enables parallel operation of the old and new levels, achieving a smooth transition between the old and new structures and avoiding resource allocation conflicts and increased address translation latency.

[0045] In some embodiments, the data processing device includes a page table traversal module, and the above method further includes the following steps S211 to S212: Step S211: If the multi-level query controller does not find the target page table item in the query result, it sends the query result to the page table traversal module. Here, the page table traversal module is used to query multi-level page tables step by step. Starting from the root page table (such as the first-level page table), it accesses the next level page table in sequence according to the indexes of the virtual address, until the final level page table entry.

[0046] In some implementations, if the multi-level query controller does not find the target page table entry in the initial TLB structure, it sends the query result to the page table traversal module to obtain the target page table entry.

[0047] Step S212: If the target page table entry is not found, the page table traversal module obtains the target page table entry by traversing multiple levels of page tables.

[0048] Here, multi-level page tables are a hierarchical data structure for managing virtual memory. By splitting a single-level page table into multiple levels (such as level 2, level 3, and level 4), efficient space utilization and flexible address translation are achieved. Multi-level page tables store multiple mappings between virtual and physical addresses. Page table entries may be distributed across multiple levels of page tables. For example, in the RISC-V architecture, the page table structure in sv48 mode includes four levels. The page table traversal module needs to traverse these four levels of page table structure in a specific order until the required page table entry is found.

[0049] In some implementations, physical memory is divided into fixed-size pages to achieve efficient management of physical memory. A page table data structure is used to record the mapping relationship between virtual addresses and physical addresses. Page tables typically have a multi-level structure (i.e., multi-level page tables), and each instruction fetch and memory access operation may require multiple accesses to physical memory. For example, in a three-level page table structure, a memory access may require first accessing the three-level page table and then accessing physical memory.

[0050] In some implementations, after the page table traversal module obtains the target page table entry, it determines the corresponding physical address based on the target page table entry and sends the physical address to the sender of the address translation request.

[0051] In this embodiment, when the target page table entry is not found, the page table traversal module obtains the target page table entry by traversing multiple levels of page tables. This allows for the accurate acquisition of the target page table entry even if the initial TLB structure is not hit, thus improving the stability and reliability of address translation.

[0052] In some embodiments, the shadow buffer includes multiple hierarchical buffers; the above method may further include the following step S221: Step S221: In response to the multi-level query controller failing to find the target page table entry more than the first time threshold, the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the corresponding hierarchical buffer in the shadow buffer based on the access frequency and access time corresponding to each page table entry in the initial TLB structure.

[0053] In some implementations, the hierarchical expansion decision unit receives query results from the multi-level query controller. If, based on the query results, it is determined that the multi-level query controller has repeatedly failed to find the target page table entry in the initial TLB (i.e., consecutive misses), and the number of misses exceeds a set first threshold, the hierarchical expansion decision unit initiates a migration mechanism. At this time, the hierarchical expansion decision unit evaluates the importance of each page table entry based on its access frequency and access time in the initial TLB structure, and selects frequently used and recently accessed page table entries for migration. These frequently used and recently accessed page table entries are copied to the corresponding hierarchical buffer in the shadow buffer to enable parallel operation of the initial TLB structure and the dynamically expanded TLB structure.

[0054] In some implementations, when the hierarchical expansion decision unit determines that the multi-level query controller has repeatedly failed to find the same page table size in multiple consecutive queries, it initiates dynamic hierarchical expansion of the TLB.

[0055] In some implementations, page table entries with a high hit probability in the initial TLB structure can be migrated to the shadow buffer. In some implementations, large page table entries that have been recently accessed in the initial TLB structure can also be migrated to the shadow buffer.

[0056] In this embodiment, a migration operation is triggered when the number of misses meets a set threshold. The migration target is dynamically selected based on the access frequency and access time of the missed page table entries. This allows for the priority migration of frequently used and recently used page table entries, thereby improving the hit rate of subsequent queries.

[0057] In some embodiments, the data processing device includes a resource scheduling module, and the above method may further include the following step S231: Step S231: During the process of determining the target TLB structure, the resource scheduling module determines the resource scheduling priority of each level buffer in the shadow buffer based on the hit rate and the access latency reduction ratio of the corresponding level buffer; based on the resource scheduling priority of the level buffer, resource space is allocated to each level buffer; the access latency reduction ratio is determined based on the hit latency of the level buffer and the hit latency of the TLB level corresponding to the level buffer in the initial TLB structure.

[0058] Here, the hit rate refers to the proportion of successful hits among query requests for page table entries in the hierarchical buffer within a certain period. It is an important metric for measuring TLB cache efficiency and reflects the actual contribution of different buffer levels to the address translation process.

[0059] In some implementations, a high hit rate in a hierarchical buffer means that the page table entries stored in that buffer are frequently accessed, and therefore that the hierarchical buffer should be given higher priority during resource allocation.

[0060] In some implementations, the hit rate of a hierarchical buffer is calculated by the resource scheduling module using the ratio of the number of hits for each hierarchical buffer to the total number of queries, based on real-time statistics. For example, if a hierarchical buffer receives a total of 100 query requests within a sampling period, and 85 of them are successful, it indicates that the hit rate of that hierarchical buffer is 85%.

[0061] Hit latency refers to the time consumed from initiating a TLB query operation to returning a result. Hit latency is typically affected by the TLB's structural design (such as set associativity and full associativity), access path complexity, and hardware implementation. Lower hit latency means faster address translation, reducing the waiting time for the sender of the address translation request and improving instruction execution efficiency. For example, if the average hit latency of one level of buffer is 3 clock cycles, while the average hit latency of another level of buffer is 5 clock cycles, then the level of buffer with an average hit latency of 3 clock cycles is superior in response speed.

[0062] In some implementations, the resource scheduling module determines the percentage reduction in access latency corresponding to the hierarchical buffer by comparing the difference in average TLB hit latency before and after the expansion.

[0063] In some implementations, the resource scheduling module determines the resource scheduling priority of a hierarchical buffer by comprehensively considering the hit rate and the access latency reduction ratio of the hierarchical buffer, and allocates resource space to the hierarchical buffer based on the resource scheduling priority of the hierarchical buffer.

[0064] Resource scheduling priority is a quantitative indicator calculated based on the hit rate and hit latency of each buffer level. It guides the dynamic allocation of on-chip memory resources. A higher priority value means more storage space and cache resources should be allocated to that buffer level. For example, if a buffer level has a high hit rate and low hit latency, its resource scheduling priority will increase accordingly, allowing it to receive more sets or cache entries.

[0065] In some implementations, the resource scheduling priority of each level of buffer is... The calculation can be found in formula (3): (3); in, Hierarchical buffer Hit rate within the current sampling period, Hierarchical buffer The corresponding percentage decrease in access latency.

[0066] In some implementations, to improve the adaptability and efficiency of the shadow buffer at each level, a dynamic scheduling mechanism based on resource weight factors is used to adjust the on-chip memory resources in real time. The scheduling mechanism continuously monitors the operating status of each level of buffer and calculates the resource scheduling priority based on the hit rate and the proportion of decrease in access latency, as shown in formula (4): (4); in, This is the weighting coefficient, with a default value of 0.6, used to bias resource allocation towards hit rate control in actual operation.

[0067] In some implementations, the resource scheduling module dynamically adjusts the available on-chip buffer space and number of groups at each level based on the normalized result of the resource scheduling priority corresponding to each level of buffer. Among them, the level buffer with higher weight will be given priority to obtain cache space expansion permission, thereby maximizing data access efficiency and suppressing the miss propagation effect.

[0068] In some implementations, the goal of resource space allocation is to achieve optimal TLB resource configuration, ensuring that frequently accessed page table entries are adequately cached while avoiding resource waste. By dynamically adjusting resource allocation strategies based on resource scheduling priorities at each buffer level, optimal cache performance can be maintained under different load conditions. Furthermore, resource space allocation can facilitate the proper operation of cross-level data migration and eviction mechanisms, ensuring that frequently accessed page table entries remain in the cache while infrequently accessed entries are promptly replaced, thereby maintaining the overall TLB hit rate and access efficiency.

[0069] In this embodiment, for each level of the shadow buffer, the resource scheduling module calculates the resource scheduling priority based on the hit rate and hit latency indicators corresponding to the level buffer, and then dynamically allocates resource space. In this way, by dynamically adjusting the resource allocation strategy based on the resource scheduling priority of each level buffer, storage resources are rationally allocated between different levels, maintaining optimal cache performance under different load conditions, improving resource utilization, and achieving efficient utilization of TLB resources.

[0070] In some embodiments, the initial TLB structure includes a first-level TLB and a second-level TLB, and the above method may further include the following step S232: Step S232: Before migrating page table entries in the initial TLB structure to the shadow buffer, the hierarchical expansion decision unit uses atomic update instructions to adjust the associativity parameters of the first-level TLB and the second-level TLB, providing resource space for the newly added third-level buffer in the shadow buffer.

[0071] Here, an atomic update instruction refers to an instruction that guarantees that the configuration operation cannot be interrupted during execution.

[0072] In some implementations, atomic update instructions are typically hardware-supported, with the hardware performing synchronous modifications to multiple registers or configuration bits within a single clock cycle. The hardware ensures that all processor cores see a consistent configuration state in a multi-core or multi-threaded environment. For example, in the RISC-V architecture, the AMO (Atomic Memory Operation) instruction can be used to ensure that configuration operations are uninterrupted during execution. Atomic update instructions allow for the safe modification of TLB structural parameters, such as the number of groups and associativity, without triggering race conditions.

[0073] In some implementations, the use of atomic update instructions can ensure that no data inconsistencies or race conditions occur when adjusting TLB structure parameters, thereby improving the stability and reliability of parameter modifications.

[0074] In some implementations, during dynamic expansion, it is essential to ensure sufficient resource space to accommodate the new level and its associated functional modules; otherwise, address translation performance may degrade or expansion may fail. By adjusting the associativity parameters of the first-level TLB and the second-level TLB, some resources are released to support the initialization of the newly added third-level buffer. In some implementations, the resource space of the third-level buffer may also include reserved resource space. The resources in the third-level buffer's resource space include, but are not limited to, storage units, control logic, hash calculation modules, etc.

[0075] In some implementations, to achieve resource rebalancing, the hierarchical expansion decision unit adjusts the associativity parameters of the first-level TLB and the second-level TLB, releasing some TLB resources to support the initialization of the new level (third-level buffer). For example, the associativity of the first-level TLB decreases by 10% to 15% during the expansion startup cycle; the number of groups in the first-level TLB increases by 20% to 30% to buffer access jitter caused by increased intermediate frequency access pressure. All associativity parameter adjustments are completed by atomic configuration update instructions, which insert an operation window between two rising clock edges, lock the configuration register, and complete multi-parameter synchronous updates to ensure consistent configuration status in a multi-core environment.

[0076] In this embodiment, the associativity parameters of the first-level TLB and the second-level TLB are modified by atomic update instructions to ensure sufficient resources for adding a third-level buffer. Furthermore, the atomic update instructions ensure the consistency and synchronization of configuration updates, thereby addressing the configuration inconsistency problem in a multi-core environment and improving the stability and reliability of parameter modification.

[0077] In some embodiments, the data processing device includes a page table traversal module, and the above method may further include the following step S241: Step S241: After the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, the page table traversal module traverses the multi-level page tables and caches the large page table entries, including the large page mark, and the adjacent page table entries of the large page table entries in the multi-level page tables to the shadow buffer.

[0078] Here, the page table traversal module is a hardware module used to perform multi-level page table traversal operations. The main function of the page table traversal module is to find the complete physical address mapping path during the virtual address translation process.

[0079] In some implementations, the page table traversal module has a prefetch capability. When a page table entry with a large page mark or other local characteristics is found, the page table entry that may be accessed is preloaded into the shadow buffer to reduce the subsequent TLB miss rate and improve the overall address translation efficiency.

[0080] In some implementations, since the region corresponding to a large page table entry including a large page mark may be accessed frequently, a prefetching strategy based on physical memory attributes is adopted. When a large page table entry including a large page mark is traversed, the adjacent page table entries of the large page table entry are prefetched into the shadow buffer simultaneously, and the priority of the prefetched page table entries is increased by 20%-40% to reduce subsequent TLB misses and improve address translation efficiency.

[0081] In some implementations, the page table traversal module can monitor the access frequency of each page table entry in real time while traversing multi-level page tables. When the access frequency of a certain page table entry is detected to exceed a first frequency threshold, based on the principle of spatial locality of reference, that is, if a page table entry is frequently accessed, then page table entries adjacent to that page table entry are also very likely to be accessed in the near future, the page table traversal module will actively search for adjacent page table entries of that page table entry in the multi-level page tables and cache these adjacent page table entries together in the shadow buffer. This can effectively reduce the probability of misses in subsequent address translation processes, thereby reducing the number of accesses to main memory and improving the overall address translation performance.

[0082] In this embodiment of the application, by pre-caching the large page table entries including the large page mark and the adjacent page table entries of the large page table entries in the multi-level page table to the shadow buffer, potential address translation requests can be predicted and satisfied in advance, thereby reducing the frequency of TLB misses and significantly improving address translation efficiency and response speed.

[0083] In some embodiments, the above method may further include the following step S242: Step S242: For each page table entry in the initial TLB structure that is being migrated to the shadow buffer, the hierarchical expansion decision unit sets a locking flag for the page table entry; the locking flag is used to prevent the page table entry from being removed.

[0084] Here, the lock flag is a boolean status flag used to indicate whether a page table entry is locked.

[0085] In some implementations, when a page table entry is set to a locked state, the replacement policy will no longer treat the page table entry as an object to be evicted. The lock will only be released and normal replacement logic will be allowed to intervene after the page table entry migration is completed, thereby avoiding data loss or inconsistency before the migration is completed.

[0086] In some implementations, page table entries undergoing migration are temporarily locked when they are migrated into the target level buffer of the shadow buffer. This locking flag prevents the replacement strategy from prematurely evicting critical page table entries that are not yet migrated, ensuring data consistency and stability. In some implementations, a replacement strategy is triggered when the capacity utilization of any level buffer exceeds 85%. The replacement logic replaces the page table entries with higher eviction priority in that level with new page table entries.

[0087] In some implementations, during cross-level page table entry migration, to ensure data consistency and access stability, a locking flag is set in the page table entry's metadata. Once activated, the locking flag prevents the replacement logic from selecting that entry as a replacement target and blocks the eviction path. The locking duration is guaranteed by the clock control module to be no less than two full clock cycles. During this period, both the source and target levels maintain a copy state of the entry. A release condition is triggered by comparing the access counter with the status register. After completing the state consistency check, the locking bit is automatically cleared, the target level entry is marked as the primary copy, the source level copy is released, and replacement permissions are restored, achieving secure migration and stable expansion under high concurrency conditions.

[0088] In this embodiment, a locking flag is set to prevent page table entries from being replaced or deleted during migration. This ensures the integrity of the migration process, avoids the loss of critical page table entries, and achieves data integrity and consistency during the migration process.

[0089] In some embodiments, the target query key includes a version tag, and the above method further includes the following steps S251 to S253: Step S251: When the version tag is the first tag, the multi-level query controller queries the initial TLB structure level by level based on the target query key to obtain the first query result; Step S252: When the version tag is the second tag, the multi-level query controller queries the shadow buffer level by level based on the target query key to obtain the second query result; Step S253: When the first query result and the second query result are consistent over multiple periods, the hierarchical expansion decision unit determines that the shadow buffer is working stably and identifies the shadow buffer as the target TLB structure.

[0090] Here, a version tag is an identifier appended to the target query key to indicate the type of TLB structure the current query operation should access. A version tag can contain multiple different values ​​(e.g., the first tag (V1) represents the initial TLB structure, and the second tag (V2) represents the shadow buffer). Version tags can also be called extended epoch tags.

[0091] In some implementations, to prevent index offsets or false hits in query results during TLB level expansion, an extended epoch marker mechanism is used for version-aware control. Each query request, when generating a composite query key, is appended with an extended epoch marker, a version number that automatically increments with the hierarchical structure, used to identify the configuration state of the hierarchy upon which the current query depends. The status register of each TLB level synchronously advances its corresponding epoch value after parameter updates. All query operations must read the current epoch value from the status register and append it to the query key, thus ensuring consistency between the query and the hierarchical parameters.

[0092] In some implementations, a two-step verification mechanism is used to ensure result reliability. The first step, pre-query, uses the old hierarchical parameters (parameters corresponding to the initial TLB structure) to perform a hash index and access the target group. For example, if the initial TLB has eight groups, the input key is mapped to the fifth group for entry matching. If a match is found, the result is temporarily stored. The second step, verification, recalculates the hash index position based on the new hierarchical parameters (parameters corresponding to the shadow buffer). The number of groups in the shadow buffer may be adjusted to sixteen, at which point the same query key may be mapped to a new thirteenth group, where the matching operation is performed again. If the pre-query and verification results are consistent, the query is confirmed as a valid match; otherwise, the page table fallback path is initiated to re-initiate the conversion request.

[0093] In some implementations, a parameter version mapping table is maintained within the hash calculation unit of the data processing device. This table records the hash calculation parameters corresponding to each epoch value, including the number of groups, associativity, and hash function version. This ensures that different query requests use the parameter set matching their epoch marker for index generation when traversing the calculation path. For example, in a query where an expansion operation increases the number of groups in the second-level TLB from eight to sixteen, the new version's group number and calculation factor are registered in the parameter mapping table. If the query finds that the request carries an old epoch marker, the hash calculation unit automatically backtracks to use the old version's calculation path; otherwise, it switches to the new version's calculation path. This ensures that during periods of frequent dynamic events such as hierarchical expansion, resource migration, or replacement strategy updates, all query behaviors are completed in a version-isolated environment, avoiding false hits or missed queries due to parameter inconsistencies. This fundamentally improves the access stability and data consistency of the multi-level scalable TLB structure.

[0094] In some implementations, version tags can be used to determine the specific execution target of a query path. For example, during dynamic expansion, the initial TLB structure and the shadow buffer are queried according to the version tags respectively. After verifying the consistency of the query results, the shadow buffer is determined as the target TLB structure.

[0095] In some implementations, version tagging enables the query process to have version awareness, that is, version tagging automatically selects the appropriate cache structure for address translation.

[0096] In some implementations, a consistency check mechanism is used to determine the shadow buffer as the target TLB structure. That is, if the results of the first and second queries are consistent over multiple periods, the data in the shadow buffer is consistent with the query results of the initial TLB structure, and no data deviation or inconsistency occurs. Once the shadow buffer is deemed to be operating stably, it is determined as the target TLB structure.

[0097] In this embodiment, when the version tag is the first tag, the multi-level query controller queries the initial TLB structure level by level based on the target query key to obtain the first query result; when the version tag is the second tag, it queries the shadow buffer level by level based on the target query key to obtain the second query result; if the first query result and the second query result are consistent over multiple periods, the hierarchical expansion decision unit determines that the shadow buffer is stable and identifies the shadow buffer as the target TLB structure. Thus, by distinguishing query paths through version tags and confirming the stability of the shadow buffer through consistency verification, the reliability and usability of the new structure after the migration process can be ensured, avoiding the impact of unstable structures on the correctness of address translation.

[0098] In some embodiments, the data processing device includes an update unit, and the above method further includes the following step S261: Step S261: The update unit updates each page table entry based on the access frequency and the last access time corresponding to each page table entry in the target TLB structure.

[0099] Here, the update unit refers to the hardware module used to perform page table entry update operations.

[0100] In some implementations, update operations may include adding page table entries, removing page table entries, and modifying the buffer at the level where the page table entry resides.

[0101] In some implementations, the update unit can update each page table entry in each TLB level of the target TLB structure after each address translation request is completed, based on the access frequency and page attributes of the page table entries. For example, large page table entries are written to the first TLB level first. Page attributes refer to a set of flags describing page behavior and permissions, such as whether it is readable, writable, executable, or includes large page markers (e.g., 4KB, 2MB, 1GB).

[0102] In some implementations, the update unit synchronously updates the most recent access time and access counter for each TLB level.

[0103] In some implementations, the update unit can adaptively adjust the TLB level of each page table entry based on the access time and the last access time corresponding to each page table entry.

[0104] In some implementations, during the update process, if the access frequency of a page table entry exceeds the migration threshold of the upper-level TLB, a cross-level migration strategy is implemented to migrate the page table entry to the upper-level cache level. For example, if the access frequency of page table entry A located in the second-level TLB increases, the update unit can migrate page table entry A to the first-level TLB to improve access efficiency. The migration process does not immediately clear the original level replica; instead, the two migrated replicas are kept in a dual-replica state for two clock cycles. During this period, replica entries are temporarily locked to prevent them from being selected by replacement logic. The dual-replica mechanism is uniformly managed by the state synchronization unit, ensuring that any replica update is synchronized to the status register and access counter of the other replica. When the access pattern is detected to be stable or the risk of replica inconsistency has been eliminated, the lower-level replica lock is automatically released, allowing normal eviction logic to intervene. In this way, while ensuring consistency during the migration of critical data, the hit probability of high-frequency page table entries is increased, access latency is avoided from sudden increases, and stable evolution and fast response of multi-level scalable TLBs are achieved under high load environments.

[0105] In this embodiment, the updating unit updates each page table entry according to the access frequency and the last access time corresponding to each page table entry in the target TLB structure, and optimizes each page table entry in the target TLB structure in real time, so that each page table entry in the target TLB structure always maintains optimal allocation, thereby improving the address translation message.

[0106] In some embodiments, step S261 above may include the following step S271: Step S271: In response to the existence of a TLB level in the target TLB structure with a capacity utilization rate greater than a preset capacity threshold, the update unit selects and removes page table entries in the target TLB structure whose replacement priority value is greater than the first replacement threshold based on the replacement priority value of each page table entry; the replacement priority value is determined based on the access frequency of the page table entry and the last access time.

[0107] Here, capacity utilization rate refers to the ratio of the space occupied by page table entries cached in the hierarchical cache in the shadow cache to the total space of the hierarchical buffer. For example, capacity utilization rate can be 85%.

[0108] Replacement priority is an indicator used to determine whether a page table entry is removed from the shadow buffer. In some implementations, a larger replacement priority value indicates that the corresponding page table entry is removed more frequently; a smaller replacement priority value indicates that the corresponding page table entry is less likely to be removed.

[0109] The first replacement threshold is a threshold used to measure whether a page table entry has been removed. The update unit removes page table entries with a replacement priority value greater than the first replacement threshold and retains page table entries with a replacement priority value less than or equal to the first replacement threshold.

[0110] In some implementations, replacement priority is determined based on the access frequency and the last access time of a page table entry. This approach considers both access frequency and temporal locality, making the page table entries selected for removal based on replacement priority more reasonable. Access frequency refers to the number of times a page table entry is accessed per unit of time, reflecting its activity level. Page table entries with high access frequency typically have higher retention value because they represent the critical path of the current program execution. The last access time refers to the time when a page table entry was most recently accessed before the current access; the last access time is used to calculate the access interval.

[0111] In some implementations, a timestamp reversal value can be calculated based on the last access time of the page table entry. A larger timestamp reversal value indicates that the page table entry has not been used for a longer period, and therefore, it is more likely to be evicted. A weighted calculation is performed on the access frequency and timestamp reversal value corresponding to the page table entry to determine its replacement priority value. The calculation method can be found in formula (5): (5); in, Access frequency, This is the reverse of the timestamp corresponding to the last access time. This is the weighting coefficient corresponding to the current replacement strategy, initially set to 0.8 to indicate a greater emphasis on frequency.

[0112] In some implementations, if a decrease in hit rate is detected when using the above replacement strategy, dynamic adjustments are made. The value tends to 0.5, which allows the replacement strategy to incorporate time locality judgments more evenly, thus completing the online switching of the replacement strategy.

[0113] In some implementations, if the update unit determines that the capacity utilization rate of any TLB level in the target TLB level is greater than a preset capacity threshold, it triggers a replacement strategy. The update unit determines the replacement priority value for each page table entry and removes page table entries in the target TLB level whose replacement priority value is greater than a first replacement threshold, thereby reducing the capacity utilization rate of the shadow buffer. For example, the capacity utilization rate can be 85%.

[0114] In some implementations, after the page table entries are removed, the TLB level in which each page table entry in the target TLB level resides can be adaptively adjusted.

[0115] In this embodiment, when there are TLB levels in the target TLB level where the capacity utilization rate is greater than a preset capacity threshold, the update unit determines the replacement priority value corresponding to each page table entry to filter low-frequency page table entries for elimination, thereby optimizing the page table entry distribution of the target TLB level. This maintains a high hit rate while freeing up space for more active page table entries.

[0116] In some embodiments, step S271 may include step S281 as follows: Step S281: For each TLB level in the target TLB structure, based on the access frequency and last access time of each page table entry in the TLB level, and the maximum access frequency of each page table entry in the TLB level, determine the replacement priority value corresponding to each page table entry, and remove page table entries in the target TLB structure whose replacement priority value is greater than the first replacement threshold.

[0117] Here, the maximum access frequency is a statistical value, which refers to the maximum access frequency among all page table entries in a certain TLB level.

[0118] In some implementations, the update unit determines the replacement priority value corresponding to each page table entry based on the access frequency and last access time of each page table entry in the TLB hierarchy, as well as the maximum access frequency among each page table entry in the TLB hierarchy; page table entries with a replacement priority value greater than a first replacement threshold are removed, while page table entries with a replacement priority value less than or equal to the first replacement threshold are retained.

[0119] In some implementations, for page table entries containing execution permission flags, a write protection priority retention mechanism is introduced in the update strategy. For example, the page table entries corresponding to critical code pages with executable permissions are replaced with a lower priority value to reduce the frequency of interrupt reloads and page table re-checks.

[0120] In some implementations, the replacement priority value corresponding to the page table entry containing the execution permission flag is multiplied by a correction factor (such as 0.5), thereby reducing the probability of being replaced, ensuring that critical code pages with executable permissions are retained in the target TLB structure as much as possible, reducing the frequency of interrupt reloading and page table re-checking, and improving the stability of instruction access in the critical path.

[0121] In some implementations, the update unit determines the replacement priority value corresponding to each page table entry based on the access frequency and last access time of each page table entry in the TLB hierarchy, the maximum access frequency of each page table entry in the TLB hierarchy, and the current time. The determination of the replacement priority value corresponding to the page table entry can be found in formula (6): (6); in, Let be the replacement priority value for the i-th page table entry. This refers to the access frequency corresponding to the table entry on this page. This represents the maximum access frequency in the current TLB hierarchy. It is the timestamp of the last access to the table entry. γ is the current time, and γ is the weighting coefficient of frequency and time, with a default value of 0.6, indicating that the contribution of access frequency is given more weight in the eviction decision. Based on the replacement priority value calculated by the above formula (6), each page table entry is replaced so that low-frequency entries that have not been accessed for a long time are removed first, thereby freeing up space for more active page table entries.

[0122] In this embodiment, for each TLB level in the target TLB structure, the update unit determines the replacement priority value corresponding to each page table entry based on the access frequency and last access time of each page table entry in the TLB level, as well as the maximum access frequency of each page table entry in the TLB level. Page table entries with replacement priority values ​​greater than the first replacement threshold in the target TLB structure are removed, further optimizing the replacement priority value corresponding to each page table entry and improving the accuracy of removing each page table entry.

[0123] In some embodiments, the initial TLB structure includes a first-level TLB and a second-level TLB, and step S202 above includes the following steps S291 to S293: Step S291: The multi-level query controller queries the first-level TLB based on the target query key; In some implementations, when the multi-level query controller queries the initial TLB structure level by level, it first queries the first-level TLB based on the target query key. If the target page table entry is found in the first-level TLB, the query result is determined to be a target page table entry found, as well as a target page table entry that matches the address translation request. The initial TLB structure determines the corresponding physical address based on the target page table entry and sends the physical address to the sender of the address translation request. If the target page table entry is not found in the first-level TLB, the multi-level query controller continues to query the second-level TLB.

[0124] Step S292: If the target page table entry is not found in the first-level TLB, the multi-level query controller performs a weighted calculation on the hash value of the target query key and the group index that was successfully hit in the initial TLB structure to obtain the target group index, and queries the second-level TLB based on the target group index. In some implementations, when querying the second-level TLB, the multi-level query controller uses a dynamic group selection algorithm based on access frequency to calculate the hash value of the target query key with the most recently accessed group index, generate a target group index, and then query the second-level TLB through the target group index.

[0125] In some implementations, if a target page table entry is found in the second-level TLB, the query result is determined to be a found target page table entry and a target page table entry matching the address translation request. The initial TLB determines the corresponding physical address based on the target page table entry and sends the physical address to the sender of the address translation request. If the target page table entry is not found in the second-level TLB, the query result is determined to be no found target page table entry. The multi-level query controller sends the query result to the page table traversal unit, so that the page table traversal unit obtains the target page table entry by traversing the multi-level page tables, determines the corresponding physical address based on the target page table entry, and sends the physical address to the sender of the address translation request.

[0126] Step S293: If the multi-level query controller does not find the target page table entry in the second-level TLB, it determines that the query result is that the target page table entry was not found.

[0127] In some implementations, after determining the query structure, the multi-level query controller sends the query results to the hierarchical expansion decision unit, enabling the hierarchical expansion decision unit to determine whether to trigger dynamic hierarchical expansion of the initial TLB structure based on the query results. The query results may include: no target page table entry found, or a target page table entry matching the address translation request.

[0128] This application provides a data processing device, such as... Figure 1 As shown, the data processing device 100 includes an address translation module 101, a multi-level query controller 102, a hierarchical expansion decision unit 103, and a shadow buffer 104. Specifically: the address translation module 101 determines the target query key in response to an address translation request; the multi-level query controller 102 queries the initial translation back buffer (TLB) structure level by level based on the target query key to obtain query results, including: no target page table entry found, or a target page table entry matching the address translation request; the hierarchical expansion decision unit 103 migrates each page table entry in the initial TLB structure to the shadow buffer 104 in response to no target page table entry found, and determines the stabilized shadow buffer 104 as the expanded target TLB structure; the target TLB structure is used for the next address translation.

[0129] In some embodiments, such as Figure 3 As shown, the data processing device 100 includes a page table traversal module 105, wherein: a multi-level query controller 102 is used to send the query result to the page table traversal module 105 when the query result is that no target page table item is found; the page table traversal module 105 is used to obtain the target page table item by traversing the multi-level page table in response to the situation where no target page table item is found.

[0130] In some embodiments, such as Figure 4 As shown, the shadow buffer 104 includes multiple hierarchical buffers 141; the hierarchical expansion decision unit 103 is used to migrate each page table entry in the initial TLB structure to the corresponding hierarchical buffer 141 in the shadow buffer 104 based on the access frequency and access time corresponding to each page table entry in the initial TLB structure when the number of times the multi-level query controller 102 fails to find the target page table entry is greater than the first number threshold.

[0131] In some embodiments, such as Figure 5 As shown, the data processing device 100 includes a resource scheduling module 106, which is used to: in the process of determining the target TLB structure, for each level buffer 141 in the shadow buffer 104, determine the resource scheduling priority corresponding to the level buffer 141 based on the hit rate and the access latency reduction ratio corresponding to the level buffer 141; allocate resource space to each level buffer 141 based on the resource scheduling priority corresponding to the level buffer 141; the access latency reduction ratio is determined based on the hit latency corresponding to the level buffer and the hit latency corresponding to the TLB level corresponding to the level buffer 141 in the initial TLB structure.

[0132] In some embodiments, the initial TLB structure includes a first-level TLB and a second-level TLB. The hierarchical expansion decision unit is further configured to: before migrating page table entries in the initial TLB structure to the shadow buffer, use atomic update instructions to adjust the associativity parameters of the first-level TLB and the second-level TLB to provide resource space for the newly added third-level buffer in the shadow buffer.

[0133] In some embodiments, the data processing device 100 includes a page table traversal module 105, which is configured to: after the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, traverse the multi-level page tables and cache the large page table entries including large page tags and the adjacent page table entries of the large page table entries in the multi-level page tables to the shadow buffer.

[0134] In some embodiments, the hierarchical expansion decision unit is further configured to set a locking flag for each page table entry that is being migrated to the shadow buffer in the initial TLB structure; the locking flag is used to prevent the page table entry from being removed.

[0135] In some embodiments, the target query key includes a version tag, and the multi-level query controller is further configured to: if the version tag is a first tag, query the initial TLB structure level by level based on the target query key to obtain a first query result; if the version tag is a second tag, query the shadow buffer level by level based on the target query key to obtain a second query result; the hierarchical extension decision unit is further configured to determine that the shadow buffer is stable and determine the shadow buffer as the target TLB structure if the first query result and the second query result are consistent over multiple periods.

[0136] In some embodiments, such as Figure 6 As shown, the data processing device 100 includes an update unit 107, which is used to update each page table entry based on the access frequency and the last access time corresponding to each page table entry in the target TLB structure.

[0137] In some embodiments, the update unit 107 is further configured to: in response to the existence of a TLB hierarchy in the target TLB structure with a capacity utilization rate greater than a preset capacity threshold, select and remove page table entries in the target TLB structure whose replacement priority value is greater than a first replacement threshold based on the replacement priority value of each page table entry; the replacement priority value is determined based on the access frequency of the page table entry and the last access time.

[0138] In some embodiments, the updating unit is further configured to, for each TLB level in the target TLB structure, determine the replacement priority value corresponding to each page table entry based on the access frequency and last access time corresponding to each page table entry in the TLB level, and the maximum access frequency in each page table entry in the TLB level, and remove page table entries in the target TLB structure whose replacement priority value is greater than a first replacement threshold.

[0139] In some embodiments, the multi-level query controller is further configured to query the first-level TLB based on the target query key; if the target page table entry is not found in the first-level TLB, the hash value of the target query key and the group index of the last successful hit in the initial TLB structure are weighted and calculated to obtain the target group index, and the second-level TLB is queried based on the target group index; if the target page table entry is not found in the second-level TLB, the query result is determined to be that no target page table entry was found.

[0140] The following describes the application of the embodiments of this application in a real-world scenario.

[0141] In computer systems (corresponding to the data processing device in the aforementioned embodiments), memory management is a crucial element, and its efficiency directly impacts the overall performance, stability, and security of the computer system. As a key area in a computer used to store data and temporary information required for program execution, efficient memory management can optimize memory usage and significantly improve computational response speed. For example, in multitasking scenarios, reasonable memory allocation ensures that multiple programs run simultaneously without interference, effectively improving data processing efficiency. Simultaneously, good memory management can prevent memory leaks and memory conflicts, enhancing the stability and reliability of data processing.

[0142] In related technologies, processors with memory management capabilities all implement a paged memory management mechanism. This mechanism achieves efficient management of physical memory by dividing memory into fixed-size pages. The paged management mechanism uses a page table data structure to record the mapping relationship between virtual addresses and physical addresses. However, since page tables typically have a multi-level structure, each instruction fetch and memory access operation may require multiple accesses to physical memory, which greatly reduces the efficiency of memory access. For example, in a typical three-level page table structure, a memory access may require first accessing the three-level page table and then accessing physical memory, which significantly increases the latency of memory access.

[0143] To address the issue of multiple memory accesses caused by page tables, related technologies typically employ a Memory Management Unit (MMU) and a Translation Lookahead (TLB) to accelerate the mapping process from virtual to physical addresses. The TLB leverages the principles of temporal and spatial locality of reference to cache frequently used page table entries. When the CPU needs to perform address translation, it first looks up the corresponding physical address in the TLB. If found in the TLB, the physical address can be used directly to access memory, eliminating the need to access the page table in memory again. This significantly reduces the number of memory accesses and improves memory access efficiency. For example, when a program frequently accesses a specific region of memory, the page table entry corresponding to that region is cached in the TLB. Subsequent accesses to that region can quickly retrieve the physical address from the TLB, greatly improving access speed.

[0144] In the RISC-V architecture, memory management employs a page-based mechanism. For example, under the Supervisor privilege level, RV32 supports bare and sv32 modes, while RV64 supports multiple page table modes such as bare, sv39, and sv48. However, the RISC-V specifications in related technologies do not explicitly define the TLB structure. This results in a lack of unified standards and specifications for TLB implementations across different RISC-V processors, making it difficult to meet the demands of computing scenarios with varying performance requirements. For instance, in some embedded systems with extremely high real-time requirements, TLB implementations in related technologies may fail to respond quickly to address translation requests, leading to performance degradation. Conversely, in high-performance computing scenarios, the TLB structure in related technologies may not be able to effectively handle a large number of address translation tasks, limiting computational capabilities.

[0145] In related technologies, the general process of address translation methods is as follows: Step S1: During the initialization phase, the processor establishes a scalable TLB structure consisting of at least two levels through the memory management control unit. The first-level TLB uses a fully associative structure to store page table entries that are accessed frequently, and the second-level TLB uses a set-associative structure to store page table entries that are accessed at medium frequency. Dynamic extension flag bits are configured for each TLB level. Step S2: When the address translation module receives a virtual address translation request, it obtains the address space identifier (ASID) and virtual machine identifier (VMID) of the current process and generates a composite query key containing the virtual page number, ASID, and VMID. Step S3: The multi-level query controller queries the scalable TLB structure level by level according to the preset priority order. When querying the second level and subsequent TLBs, a dynamic group selection algorithm based on access frequency is used to calculate the hash value of the composite query key with the most recently accessed group index in a weighted manner to generate the target group index. Step S4: When a TLB miss occurs, the hierarchical expansion decision unit monitors the miss patterns of the most recent N queries in real time. If K consecutive misses of the same page table size are detected, dynamic hierarchical expansion is triggered. An expansion level with different associativity is added to the existing TLB structure, and the address range information of the new expansion level is written to the TLB configuration register. Step S5: When the page table traversal engine (corresponding to the page table traversal module in the aforementioned embodiment) starts multi-level page table traversal, it adopts a prefetch strategy based on physical memory attributes. When traversing a page table entry containing a big page tag, it synchronously prefetches adjacent page table entries into the prefetch buffer and raises the priority of the prefetched page table entries. Step S6: After the address translation is completed, the update unit selects the target TLB level for update based on the access frequency of the page table entries and the page attributes. Large page table entries are written to the first-level TLB first, and the recent access timestamp and access counter of each level are updated at the same time.

[0146] Existing methods have significant drawbacks during dynamic hierarchical expansion. Adding a new expansion level (such as a third-level TLB) and adjusting the associativity of adjacent levels can lead to multi-level TLB resource allocation conflicts. Firstly, the physical resource allocation of the new level competes with ongoing address translation requests. For example, in scenarios with high miss rates, the clock-cycle-level synchronization required for hardware resource reallocation can cause resource allocation delays, blocking normal queries and significantly reducing address translation efficiency. Secondly, dynamic adjustment of hierarchical parameters can cause some TLB entries to temporarily become invalid. For instance, improper adjustment of associativity parameters (such as the number of groups N) can lead to incorrect index calculations of existing TLB entries, preventing these entries from being accessed correctly and affecting the accuracy of address translation. Furthermore, inconsistencies in query paths exist during the transition between old and new hierarchical levels. During hierarchical expansion, the calculation method for composite query keys may change due to hierarchical configuration changes. If query paths are not adjusted and verified in a timely manner, query errors may occur, further reducing data processing performance.

[0147] Based on the above description, embodiments of this application provide a RISC-V address translation method based on a multi-level scalable TLB, such as... Figure 7 As shown, the method may include the following steps S701 to S706: Step S701: During the initialization phase, the processor establishes a scalable TLB structure consisting of at least two levels through the memory management control unit. The first-level TLB uses a fully associative structure to store page table entries that are accessed frequently, and the second-level TLB uses a set-associative structure to store page table entries that are accessed at medium frequency. Dynamic extension flag bits are configured for each TLB level. Step S702: When the address translation module receives a virtual address translation request, it obtains the address space identifier (ASID) and virtual machine identifier (VMID) of the current process and generates a composite query key containing the virtual page number, ASID and VMID (corresponding to the target query key in the previous embodiment). Step S703: The multi-level query controller queries the scalable TLB structure level by level according to the preset priority order. When querying the second level and subsequent TLBs, a dynamic group selection algorithm based on access frequency is used to calculate the hash value of the composite query key with the most recently accessed group index in a weighted manner to generate the target group index. In the dynamic group selection algorithm, considering the access locality characteristics of multi-level TLB query paths, a weighted group index calculation method is used to improve the hit efficiency of mid-frequency access page table entries. Upon receiving a virtual address translation request, the address translation module first constructs a composite query key based on the request's address space identifier, virtual machine identifier, and virtual page number, and calculates its hash value (see formula (1)). This hash value reflects the distribution characteristics of the current address translation request in the address space dimension. Subsequently, the group index of the most recently successfully hit is extracted from the group access history table. This set of indices reflects the spatial or temporal locality trend of the current access sequence. The final target group index is calculated through weighted fusion, see formula (2). In formula (2)... The initial value is set to 0.7. The initial value is set to 0.3, indicating that in the initial stage, it tends to rely on the hash distribution of the keys to achieve broad coverage and adapt to the global randomness of the address space. N represents the number of groups in the current level TLB, provided by the status register.

[0148] The aforementioned target group index calculation method adaptively generates target access groups based on both address distribution and historical access patterns, thereby reducing conflict rates and increasing the cache hit probability of mid-frequency page table entries. To further enhance the algorithm's adaptability, a periodic evaluation window is set. At the end of each window period, the current level's usage of existing... and The hit rate fluctuation under certain parameters is analyzed, and the weight parameters are fine-tuned based on the gain trend. If the local hit effect is enhanced, the accuracy is increased. Value, otherwise enhance This improves key-value dispersion. The adjustment process is synchronized by the expansion phase flag in the hierarchical status register and only performs weight modifications during non-expansion periods to avoid group index conflicts or query path inconsistencies during hierarchical structure changes, thereby ensuring the computational security and access consistency of the dynamic group selection logic in the expansion environment.

[0149] Step S704: When a TLB miss occurs, the hierarchical expansion decision unit monitors the miss patterns of the most recent N queries in real time. If K consecutive misses of the same page table size are detected (K≥3), dynamic hierarchical expansion of the TLB is triggered. In the address translation method of multi-level scalable TLBs, when a series of consecutive misses of the same page table size are detected, the hierarchical expansion decision unit determines to trigger the dynamic hierarchical expansion mechanism. At this time, a shadow buffer needs to be configured for the newly added expansion level to enable the old and new levels to work in parallel during the expansion. The shadow buffer is responsible for temporarily storing page table entries with high hit probability in the original level, ensuring a high hit rate and reducing access latency during the expansion translation process. The writing to the shadow buffer follows the access time order, prioritizing the retention of recent high-frequency entries. To achieve seamless migration, the modification of the associativity parameter must be performed through atomic configuration update instructions to avoid inconsistencies in state during multi-core access. At the start of the migration, the hierarchical status register automatically switches from the preparation state to the switching state. During this stage, the old and new levels jointly respond to query operations. The new level uses the shadow buffer to assist the matching process, while the old level continues to provide query services (the old level continues to provide query services to work in parallel with the new level during dynamic hierarchical expansion, ensuring uninterrupted address translation and maintaining a high hit rate while reducing access latency). After at least two clock cycles, when the structure of the new level (the third-level buffer corresponding to the shadow buffer) is stable, the shadow buffer migration is completed, and the consistency verification between the test query results of the new extended level and the old level is completed, it enters the completion state, the status register is written with the completion code, the old level is marked as frozen, and the resource reclamation mechanism is then started. In the process of expanding a multi-level scalable TLB, in order to achieve efficient management and allocation of on-chip memory resources, the resource scheduling priority of each level is calculated in real time, as shown in formula (3).

[0150] On-chip memory resources are dynamically allocated based on resource scheduling priority. When the resource scheduling priority of a certain level is higher than the preset threshold, more group cache and table space will be allocated to that level first. At the same time, page table entries in the migration process are temporarily locked when they are migrated into the target level buffer. This flag prevents the replacement strategy from prematurely evicting critical page table entries that have not yet been migrated, thus ensuring data consistency and stability.

[0151] In the process of dynamic resource allocation, in order to improve the adaptability and efficiency of the multi-level TLB structure, a dynamic scheduling mechanism based on resource weight factors (resource scheduling priority) is adopted to adjust the on-chip memory resources in real time. The scheduling mechanism continuously monitors the operating status of each level and calculates the resource allocation priority based on the hit rate and the decrease in access latency. The calculation formula for resource scheduling priority is shown in formula (4).

[0152] The resource scheduling module dynamically adjusts the available on-chip buffer space and number of groups at each level based on the normalized result of the resource scheduling priority corresponding to each level of buffer. Among them, the level buffer with higher weight will be given priority to obtain cache space expansion permission, thereby maximizing data access efficiency and suppressing the miss propagation effect.

[0153] To ensure data consistency and access stability, a temporary lock flag is set in the metadata of the target page entry. Once activated, the flag prevents the replacement logic from selecting that entry as a replacement target and blocks the eviction path. The lock duration is guaranteed by the clock control module to be no less than two full clock cycles. During this period, both the source and target levels maintain a copy of the entry. The synchronization mechanism triggers the release condition by comparing the access counter with the status register. After completing the state consistency check, the lock bit is automatically cleared, the target level entry is marked as the primary copy, the source level copy is released, and replacement permissions are restored, achieving secure migration and stable expansion under high concurrency conditions.

[0154] To ensure the correctness of address translation queries during hierarchical expansion, an extended epoch marker is appended to each composite query key. This marker indicates the TLB hierarchy version number corresponding to the query request (new and old versions refer to different configuration states before and after the TLB hierarchy adjustment, distinguished by the extended epoch marker, and the corresponding version parameter is used during the query). The query process adopts a two-stage verification mechanism, in which the first stage, Phase 1, uses the old version parameter for pre-querying, and the second stage, Phase 2, uses the new version parameter to perform consistency verification. To support this mechanism, the hash calculation unit enables parameter version control, and the specific calculation method is shown in formula (7): (7); in, This represents the target group index obtained from the hash calculation. It is a composite lookup key that includes the virtual page number, ASID, and VMID. It is the parameter version number currently used at the i-th level. This represents the total number of groups in this hierarchy. By performing an XOR operation on the key and the version number to calculate the hash value, version isolation of the query path can be maintained during hierarchical structure changes, avoiding false hits or information conflicts caused by version confusion, thereby ensuring the stability and consistency of query behavior during the expansion process.

[0155] In the query path consistency protection mechanism, during TLB level expansion, to prevent index offsets or false hits in query results during the switching between old and new level parameters, an extended epoch marker mechanism is used to implement version-aware control. Each query request, when generating a composite query key, is appended with an extended epoch marker. This marker is a version number that automatically increments with the hierarchical structure adjustment, used to identify the configuration state of the level the current query depends on. The status register of each TLB level synchronously advances the corresponding epoch value after completing parameter updates. All query operations must read the epoch value of the current status register and append it to the query key, thereby binding the consistency between the query and the hierarchical parameters.

[0156] During the query process, a two-step verification mechanism is employed to ensure result reliability. The first step, pre-query, uses the old hierarchical parameters to execute the hash index and access the target group. For example, if the old number of groups was eight, the input key is mapped to the fifth group for table entry matching. If a match is found, the result is temporarily stored. The second step, verification, recalculates the hash index position based on the new hierarchical parameters. The new number of groups may be adjusted to sixteen, at which point the same query key may be mapped to the new thirteenth group, where the matching operation is performed again. If the pre-query and verification results are consistent, the query is confirmed as a valid match; otherwise, a page table fallback path is initiated to re-initiate the conversion request.

[0157] The hash calculation unit maintains a parameter version mapping table internally, recording the hash calculation parameters corresponding to each epoch value, including the number of groups, associativity, and hash function version. This ensures that different query requests use the parameter set matching their epoch marker for index generation when traversing the calculation path. For example, in a query where an expansion operation increases the number of groups in the second-level TLB from eight to sixteen, the new version's group number and calculation factor are registered in the parameter mapping table. If the query finds that the request carries an old epoch marker, the hash calculation unit automatically backtracks to the calculation path using the old version parameters; otherwise, it switches to the new version parameters. This mechanism ensures that during frequent dynamic events such as hierarchical expansion, resource migration, or replacement strategy updates, all query behaviors are completed in a version-isolated environment, avoiding false hits or missed queries due to parameter inconsistencies, fundamentally improving the access stability and data consistency of the multi-level scalable TLB structure.

[0158] During dynamic hierarchical expansion, when a 2MB large page table entry is missed more than a set threshold consecutively, a large page optimization mechanism is triggered, initiating a dedicated third-level TLB creation process. This level employs a block-associative structure design, reserving space for four logically contiguous large page table entries for each entry, thereby reducing the number of accesses and lookup latency during large page mapping. Each entry is equipped with an independent large page replacement counter to record the independent access frequency of the four subpage entries. The counter uses a weighted update mechanism to prioritize the retention of high-frequency subpages. When creating the third-level TLB, a shadow buffer is first activated to cache recently accessed large page table entries from the original level, enabling parallel collaboration between the old and new levels and ensuring uninterrupted queries. Simultaneously, to achieve resource rebalancing, the structural parameters of the first and second-level TLBs are adjusted synchronously. The associativity of the first-level TLB decreases by 10% to 15% during the expansion startup cycle, releasing some TLB resources to support the initialization of the new level; the number of groups in the second-level TLB is increased by 20% to 30% to buffer access jitter caused by increased mid-frequency access pressure. All parameter adjustments are performed by a dedicated atomic configuration update instruction. This instruction inserts an operation window between two rising clock edges, locks the configuration register, and completes multi-parameter synchronous updates to ensure consistent configuration status in a multi-core environment. The replacement strategy for the new extension level is initially set to access frequency priority mode, and the strategy function can be found in formula (5).

[0159] If the hit rate decreases after running the above replacement strategy for a period of time, dynamically adjust... The value tends to 0.5, allowing the replacement strategy to incorporate time locality judgments more evenly and completing the online switching of the replacement strategy. The entire expansion process is monitored by a hierarchical status register, which contains a 2-bit status code, marked as the preparation period, switching period, and completion period, respectively. This provides expansion phase signal feedback to the scheduling module, enabling fine-grained control and status awareness of the expansion behavior.

[0160] Step S705: When the page table traversal engine starts multi-level page table traversal, it adopts a prefetch strategy based on physical memory attributes. When traversing to a page table entry containing a large page tag, it synchronously prefetches adjacent page table entries into the prefetch buffer (i.e., the buffer) and increases the priority of the prefetched page table entries by 20%-40%. Step S706: After the address translation is completed, the update unit selects the target TLB level for update based on the access frequency of the page table entries and the page attributes. Large page table entries are written to the first-level TLB first, and the recent access timestamp and access counter of each level are updated at the same time.

[0161] In the update strategy, to maintain the efficient operation and stable access of the multi-level TLB hierarchy, a dual-threshold eviction mechanism and a tiered update migration mechanism are introduced. When the capacity utilization rate of any level TLB exceeds the set upper limit threshold of 85%, a strict eviction process is immediately activated. The weighted eviction priority of all entries in the current level is calculated, and the specific calculation is shown in formula (6). Based on the replacement priority value calculated by the above formula (6), each page entry is replaced so that infrequent and long-term inaccessible entries are removed first, thereby freeing up space for more active page entries.

[0162] The update strategy introduces a write-protected priority retention mechanism. The priority of a page in the eviction queue is multiplied by a correction factor of 0.5, significantly reducing the probability of replacement. This ensures that critical code pages with executable permissions are retained in the TLB as much as possible, reducing the frequency of interrupt reloading and page table lookups, and improving the stability of instruction access on critical paths. During the update process (after address translation, the update unit triggers the update based on the access frequency of page table entries and page attributes), a cross-level migration strategy is implemented. If the access frequency of a certain entry exceeds the migration threshold of the upper-level TLB, the entry will be migrated to the upper-level cache level, for example, from the second-level TLB to the first-level TLB. The migration process does not immediately clear the original level copy; instead, the two migrated copies are kept in a dual-copy state for two clock cycles. During this period, the copy entries are temporarily locked to prevent selection by replacement logic. The dual-copy mechanism is managed uniformly by the state synchronization unit, ensuring that any copy update is synchronized to the status register and access counter of the other copy. When the access pattern is detected to be stable or the risk of copy inconsistency is eliminated, the lower-level copy lock is automatically released, allowing normal eviction logic to intervene. This strategy ensures consistency during critical data migration while increasing the hit probability of high-frequency page table entries, avoiding sudden increases in access latency, and enabling stable evolution and rapid response of multi-level scalable TLBs under high load environments.

[0163] In this embodiment of the application, the state changes of the above-mentioned TLB dynamic hierarchical expansion can be as follows: Figure 8 As shown, if multiple consecutive misses are detected, the system enters the preparation phase 801 and activates the shadow buffer. At this time, the old and new layers work in parallel. Then, the system enters the switching phase 802. After the migration is completed and the consistency check is passed, the system enters the completion phase, freezes the old layer, and reclaims resources.

[0164] In this embodiment, a high-performance server based on the RISC-V instruction set architecture is used as an example. This server is mainly used for handling large-scale data computation and multi-task concurrent processing. In actual operation, the server needs to run multiple virtual machines simultaneously, and each virtual machine contains multiple processes. These processes frequently perform memory access operations, requiring extremely high efficiency and stability in address translation.

[0165] The specific process is as follows: During the initialization phase, when the server starts, the processor establishes a scalable TLB structure through the memory management control unit. The first-level TLB uses a fully associative structure with a storage capacity of 128 page table entries, enabling fast storage of frequently accessed page table entries. The second-level TLB uses a set-associative structure, divided into 16 sets, each containing 8 page table entries, used to store medium-frequency accessed page table entries. Simultaneously, dynamic expansion flags are configured for both levels of TLB to prepare for possible future dynamic expansions.

[0166] During the address translation request processing phase, when a process on the server initiates a virtual address translation request, the address translation module quickly obtains the ASID of the current process and the VMID of the virtual machine it resides in. Assuming the ASID is 0x1234, the VMID is 0x5678, and the virtual address is 0xABCDEF00, the virtual page number 0xABCD is extracted. This information is then combined to generate a composite lookup key: {0xABCD, 0x1234, 0x5678}.

[0167] During the multi-level query phase, the multi-level query controller queries the first-level TLB according to a preset priority order. If no match is found, the second-level TLB is queried. When querying the second-level TLB, a dynamic group selection algorithm based on access frequency is used. The hash value of the composite query key is calculated using formula (1), yielding a hash value of 0x123456. The most recently accessed group index is then retrieved. Let's assume it's 0x78. Using formula (2), we calculate the final group index as 5. Then, we search for the corresponding page table entry in the 5th group of the second-level TLB.

[0168] During the dynamic hierarchical expansion phase, if the hierarchical expansion decision unit detects four consecutive 2MB large page misses in the last 10 queries during server operation, dynamic hierarchical expansion is triggered. A shadow buffer is configured for the newly added third-level TLB, allowing the shadow buffer to work in parallel with the old level for three clock cycles. An atomic configuration update instruction is used to modify the relevant associativity parameters, such as setting the number of groups in the third-level TLB to 32. The expansion process phase is marked by the hierarchical status register. During the preparation phase, resource allocation and initialization operations are performed; during the switching phase, address translation requests are gradually switched from the old level to the new level; during the completion phase, the success of the expansion is confirmed. At the same time, a hierarchical resource weight factor is introduced. See formula (3) to calculate the resource weight factor of each TLB level in real time, and on-chip memory resources are dynamically allocated according to the weight. A temporary lock flag is set for the entries being migrated, prohibiting them from being replaced before the migration is completed. The lock state is maintained for three clock cycles until the migration is completed and the dual replica states are synchronized. During hierarchical expansion, an extended epoch marker is added to the composite query key; assuming the current extended epoch marker is 0x01. A two-step verification is performed during the query: first, a hash value is calculated using the old hierarchical parameters and pre-queried; then, the hash value is recalculated using the new hierarchical parameters, and the consistency of the result is verified. The hash calculation unit maintains a parameter version mapping table to ensure that each query request generates an index using the parameter version that matches the current hierarchical status register.

[0169] During the page table traversal phase, when the page table traversal engine starts multi-level page table traversal, when it traverses a page table entry containing a large page tag, it assumes that the memory area corresponding to the page table entry is a frequently accessed large data storage area, synchronously prefetches adjacent page table entries into the prefetch buffer, and increases the priority of the prefetched page table entries by 30%.

[0170] In the update phase after address translation, the update unit selects the target TLB level for update based on the access frequency and page attributes of the page table entries. It is assumed that large page table entries, due to their high access frequency, are preferentially written to the first-level TLB. Simultaneously, the most recent access timestamp and access counter for each level are updated. A dual-threshold eviction mechanism is implemented; when the level's capacity utilization exceeds 85%, strict eviction is initiated, using a weighted eviction algorithm based on access frequency and timestamp. For page table entries containing execution permissions, a write-protected priority retention strategy is implemented, reducing their eviction priority by 50%. Cross-level migration is performed during the update process; when migrating frequently accessed entries to higher levels, a copy of the original level is retained, and a dual-copy state is maintained for 3 clock cycles after migration. The copy state is managed collaboratively by a temporary locking flag.

[0171] In this embodiment, by configuring a shadow buffer for the newly added level, parallel operation of the old and new levels is achieved, effectively avoiding the competition between the allocation of physical resources for the new level and the ongoing address translation requests. Atomic configuration update instructions are used to modify the associativity parameters, ensuring the accuracy and stability of level parameter adjustments and preventing the temporary invalidation of some TLB entries. Marking the expansion process stages with level status registers ensures orderly dynamic level expansion, improving the controllability of the expansion process. Introducing level resource weight factors and dynamically allocating on-chip memory resources based on real-time weights optimizes the resource allocation strategy and improves resource utilization. Setting temporary lock flags for migrating entries ensures the integrity and accuracy of the migration process, avoiding inconsistencies in entry states during cross-level migration. Adding an extension epoch marker and employing a two-step verification mechanism, along with parameter versioning control for hash calculation units, ensures the consistency of the query path and improves query accuracy.

[0172] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0173] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0174] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0175] The above are merely embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An address translation method, characterized in that, Applied to a data processing device, the data processing device including an address translation module, a multi-level query controller, a hierarchical extended decision unit, and a shadow buffer, the method includes: The address translation module responds to the address translation request and determines the target query key; The multi-level query controller queries the initial translation back buffer (TLB) structure level by level based on the target query key to obtain query results, wherein the query results include: no target page table entry found, or a target page table entry that matches the address translation request; In response to the absence of the target page table entry, the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, and determines the shadow buffer, after it has stabilized, as the expanded target TLB structure; the target TLB structure is used for the next address translation.

2. The method according to claim 1, characterized in that, The data processing device includes a page table traversal module, and the method further includes: If the query result is that the target page table item is not found, the multi-level query controller sends the query result to the page table traversal module. When the target page table traversal module does not find the target page table entry, it retrieves the target page table entry by traversing multiple levels of page tables.

3. The method according to claim 1, characterized in that, The shadow buffer includes multiple hierarchical buffers; In response to the failure to find the target page table entry, the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, including: In response to the multi-level query controller failing to find the target page table entry more than the first time threshold, the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the corresponding hierarchical buffer in the shadow buffer based on the access frequency and access time corresponding to each page table entry in the initial TLB structure.

4. The method according to claim 3, characterized in that, The data processing device includes a resource scheduling module, and the method further includes: In determining the target TLB structure, the resource scheduling module, for each level buffer in the shadow buffer, determines the resource scheduling priority corresponding to the level buffer based on the hit rate and the access latency reduction ratio of the level buffer; based on the resource scheduling priority of the level buffer, resource space is allocated to each level buffer; the access latency reduction ratio is determined based on the hit latency of the level buffer and the hit latency of the TLB level corresponding to the level buffer in the initial TLB structure.

5. The method according to claim 3, characterized in that, The initial TLB structure includes a first-level TLB and a second-level TLB, and the method further includes: Before migrating page table entries in the initial TLB structure to the shadow buffer, the hierarchical expansion decision unit uses atomic update instructions to adjust the associativity parameters of the first-level TLB and the second-level TLB, providing resource space for the newly added third-level buffer in the shadow buffer.

6. The method according to any one of claims 1 to 5, characterized in that, The data processing device includes a page table traversal module, and the method further includes: After the hierarchical expansion decision unit migrates each page table entry in the initial TLB structure to the shadow buffer, the page table traversal module traverses the multi-level page tables and caches the large page table entries including large page tags and the adjacent page table entries of the large page table entries in the multi-level page tables to the shadow buffer.

7. The method according to any one of claims 1 to 5, characterized in that, The method further includes: For each page table entry in the initial TLB structure that is being migrated to the shadow buffer, the hierarchical expansion decision unit sets a locking flag for the page table entry; the locking flag is used to prevent the page table entry from being removed.

8. The method according to any one of claims 1 to 5, characterized in that, The target query key includes a version marker, and the method further includes: When the version is marked as the first mark, the multi-level query controller queries the initial TLB structure level by level based on the target query key to obtain the first query result; When the version is marked as the second mark, the multi-level query controller queries the shadow buffer level by level based on the target query key to obtain the second query result. If the first query result and the second query result are consistent over multiple periods, the hierarchical expansion decision unit determines that the shadow buffer is working stably and identifies the shadow buffer as the target TLB structure.

9. The method according to any one of claims 1 to 5, characterized in that, The data processing device includes an update unit, and the method further includes: The update unit updates each page table entry based on the access frequency and the last access time corresponding to each page table entry in the target TLB structure.

10. The method according to claim 9, characterized in that, The update unit updates each page table entry based on the access frequency and the last access time corresponding to each page table entry in the target TLB structure, including: In response to the existence of a TLB level in the target TLB structure with a capacity utilization rate greater than a preset capacity threshold, the update unit selects and removes page table entries in the target TLB structure whose replacement priority value is greater than a first replacement threshold, based on the replacement priority value of each page table entry; the replacement priority value is determined based on the access frequency and the last access time of the page table entry.

11. The method according to claim 10, characterized in that, The step of selecting and removing page table entries in the target TLB structure whose replacement priority value is greater than a first replacement threshold based on the replacement priority value of each page table entry includes: For each TLB level in the target TLB structure, based on the access frequency and last access time of each page table entry in the TLB level, and the maximum access frequency of each page table entry in the TLB level, a replacement priority value is determined for each page table entry, and page table entries in the target TLB structure with a replacement priority value greater than a first replacement threshold are removed.

12. The method according to any one of claims 1 to 5, characterized in that, The multi-level query controller queries the initial translation backup buffer (TLB) structure level by level based on the target query key to obtain the query results, including: The multi-level query controller queries the first-level TLB based on the target query key; If the target page table entry is not found in the first-level TLB, the multi-level query controller performs a weighted calculation on the hash value of the target query key and the group index of the last successful hit in the initial TLB structure to obtain the target group index, and queries the second-level TLB based on the target group index. If the target page table entry is not found in the second-level TLB, the multi-level query controller determines that the query result is that the target page table entry was not found.

13. A data processing device, characterized in that, It includes an address translation module, a multi-level query controller, a hierarchical extended decision unit, and a shadow buffer, wherein: The address translation module is used to determine the target query key in response to an address translation request; The multi-level query controller is used to query the initial translation back buffer (TLB) structure level by level based on the target query key to obtain query results, wherein the query results include: no target page table entry found, or a target page table entry that matches the address translation request; The hierarchical expansion decision unit is used to migrate each page table entry in the initial TLB structure to the shadow buffer in response to the failure to find the target page table entry, and to determine the shadow buffer after it has stabilized as the expanded target TLB structure; the target TLB structure is used for the next address translation.

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