Video memory migration method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to a video memory migration method and device, electronic equipment and a storage medium, and the method comprises the steps that migration information and vGPU video memory data of a source-end host machine are received from the source-end host machine, the migration information comprises address space description information of a source-end vGPU and a base address of a GPU page table, and the vGPU video memory data of the source-end host machine are stored in the source-end host machine; the vGPU video memory data comprises a GPU page table; calculating a physical address of a destination end corresponding to the GPU page table based on the migration information and address space description information of a destination end vGPU; and using the calculated physical address to update the received physical address corresponding to the GPU page table. According to the embodiment of the invention, the flexibility and the application range of vGPU migration can be effectively improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method and apparatus for video memory migration, electronic devices, and storage media. Background Technology

[0002] In virtualization technology, virtual machine migration requires copying the complete state, including GPU memory data, from the source host to the destination host. GPU memory contains crucial page tables that record the mapping between GPU virtual addresses and physical addresses.

[0003] After memory migration, the physical addresses allocated to the GPU at the destination are often different from those at the source. This can cause the page tables copied from the source to become unusable due to invalid physical addresses. To avoid this problem, related technologies typically require that the physical addresses at the destination and source be identical. This necessitates maintaining complete hardware consistency between the physical memory at the destination and source, relying on specific hardware to keep the addresses unchanged, which severely limits the flexibility and versatility of memory migration. Summary of the Invention

[0004] In view of this, this disclosure proposes a memory migration technology solution.

[0005] According to one aspect of this disclosure, a video memory migration method is provided, applied to a target host machine for video memory migration, the method comprising:

[0006] The source host receives migration information and vGPU memory data of the source host. The migration information includes address space description information of the source vGPU and base address of the GPU page table. The vGPU memory data includes the GPU page table.

[0007] Based on the migration information and the address space description information of the destination vGPU, calculate the physical address of the destination corresponding to the GPU page table;

[0008] Use the calculated physical address to update the physical address corresponding to the received GPU page table.

[0009] In one possible implementation, the physical address corresponding to the GPU page table includes: the physical address in the GPU page table entry and / or the base address of the GPU page table itself;

[0010] The calculation of the destination physical address corresponding to the GPU page table includes:

[0011] The base address of the GPU page table itself is translated to obtain the base address of the destination page table;

[0012] The physical address recorded in the page table entry of the GPU page table is translated to obtain the physical address recorded in the page table entry of the destination GPU page table.

[0013] In one possible implementation, calculating the physical address of the destination end corresponding to the GPU page table includes:

[0014] Based on the address space description information of the source vGPU, the physical address corresponding to the page table of the source GPU is converted into a CPU physical address that remains unchanged before and after the migration.

[0015] Based on the address space description information of the destination vGPU, the CPU physical address is converted into the GPU physical address corresponding to the page table of the destination GPU.

[0016] In one possible implementation, the step of converting the physical address corresponding to the source GPU page table into a CPU physical address that remains unchanged before and after the migration, based on the address space description information of the source GPU, includes:

[0017] Based on the address space description information of the source vGPU, determine the source memory segment to which the physical address of the source GPU belongs, and obtain the source segment base address of the memory segment.

[0018] Calculate the offset of the source GPU physical address relative to the source segment base address;

[0019] Based on the first mapping relationship, determine the CPU physical address segment base address corresponding to the source memory segment;

[0020] The CPU physical address is obtained by adding the segment base address of the CPU physical address to the offset.

[0021] In one possible implementation, the step of converting the CPU physical address to the GPU physical address corresponding to the GPU page table on the destination GPU based on the address space description information of the destination vGPU includes:

[0022] Based on the address space description information and the second mapping relationship of the destination vGPU, the base address of the destination video memory segment corresponding to the CPU physical address is determined.

[0023] The base address of the target memory segment is added to the offset to obtain the target GPU physical address.

[0024] In one possible implementation, the address space description information includes the base address and size information of one or more video memory segments, wherein the addresses within a video memory segment are contiguous.

[0025] In one possible implementation, the base address of the GPU page table is recorded by the source host machine during the virtual machine's operation by tracking the creation and destruction operations of the GPU page table by the virtual machine.

[0026] In one possible implementation, the source host maintains a list of page table base addresses; when the source host detects that the virtual machine is creating a new GPU page table, it adds the base address of the new page table to the list; when the source host detects that the virtual machine is destroying an existing GPU page table, it removes the base address of the destroyed page table from the list.

[0027] According to another aspect of this disclosure, a video memory migration apparatus is provided, applied to a target host machine for video memory migration, the apparatus comprising:

[0028] A receiving module is used to receive migration information and vGPU memory data of the source host machine from the source host machine. The migration information includes address space description information of the source vGPU and the base address of the GPU page table. The vGPU memory data includes the GPU page table.

[0029] The calculation module is used to calculate the physical address of the destination end corresponding to the GPU page table based on the migration information and the address space description information of the destination vGPU;

[0030] The update module is used to update the physical address corresponding to the received GPU page table using the calculated physical address.

[0031] In one possible implementation, the physical address corresponding to the GPU page table includes: the physical address in the GPU page table entry and / or the base address of the GPU page table itself;

[0032] The computing module is used for:

[0033] The base address of the GPU page table itself is translated to obtain the base address of the destination page table;

[0034] The physical address recorded in the page table entry of the GPU page table is translated to obtain the physical address recorded in the page table entry of the destination GPU page table.

[0035] In one possible implementation, the computing module is used for:

[0036] Based on the address space description information of the source vGPU, the physical address corresponding to the page table of the source GPU is converted into a CPU physical address that remains unchanged before and after the migration.

[0037] Based on the address space description information of the destination vGPU, the CPU physical address is converted into the GPU physical address corresponding to the page table of the destination GPU.

[0038] In one possible implementation, the computing module is used for:

[0039] Based on the address space description information of the source vGPU, determine the source memory segment to which the physical address of the source GPU belongs, and obtain the source segment base address of the memory segment.

[0040] Calculate the offset of the source GPU physical address relative to the source segment base address;

[0041] Based on the first mapping relationship, determine the CPU physical address segment base address corresponding to the source memory segment;

[0042] The CPU physical address is obtained by adding the segment base address of the CPU physical address to the offset.

[0043] In one possible implementation, the computing module is used for:

[0044] Based on the address space description information and the second mapping relationship of the destination vGPU, the base address of the destination video memory segment corresponding to the CPU physical address is determined.

[0045] The base address of the target memory segment is added to the offset to obtain the target GPU physical address.

[0046] In one possible implementation, the address space description information includes the base address and size information of one or more video memory segments, wherein the addresses within a video memory segment are contiguous.

[0047] In one possible implementation, the base address of the GPU page table is recorded by the source host machine during the virtual machine's operation by tracking the creation and destruction operations of the GPU page table by the virtual machine.

[0048] In one possible implementation, the source host maintains a list of page table base addresses; when the source host detects that the virtual machine is creating a new GPU page table, it adds the base address of the new page table to the list; when the source host detects that the virtual machine is destroying an existing GPU page table, it removes the base address of the destroyed page table from the list.

[0049] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0050] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0051] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0052] In this embodiment, the destination host receives migration information from the source host, including the address space description information of the source vGPU and the base address of the GPU page table. Then, it receives vGPU memory data from the source host, which contains the GPU page table. Based on the migration information and the address space description information of the destination vGPU, it calculates the physical address of the destination corresponding to the GPU page table. Finally, it uses the calculated physical address to update the physical address corresponding to the received GPU page table. Thus, by executing a series of software operations on the destination host, all physical addresses corresponding to the migrated GPU page table are dynamically recalculated and updated, ensuring they correctly correspond to the new physical address space of the destination. This method does not rely on specific hardware and does not impose any restrictions on the physical address configuration of the destination. The destination only needs to provide the local vGPU address layout structure. Based on the migration information and the address space description information of the destination vGPU, the physical address of the destination corresponding to the GPU page table can be calculated. Finally, the physical address corresponding to the received GPU page table is updated using the calculated physical address, so that the migrated GPU page table is re-aligned with the physical address space of the destination, thereby significantly improving the flexibility and applicability of vGPU migration.

[0053] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0054] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0055] Figure 1 A flowchart illustrating a memory migration method according to an embodiment of the present disclosure is shown.

[0056] Figure 2 A block diagram of a memory migration apparatus according to an embodiment of the present disclosure is shown.

[0057] Figure 3 This is a block diagram illustrating a video memory migration device according to an exemplary embodiment. Detailed Implementation

[0058] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0059] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0060] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0061] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0062] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0063] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0064] In a virtualization environment, video memory migration is the process of transferring the video memory data of a virtual machine's GPU (vGPU) from the source host machine to the destination host machine.

[0065] The architecture involved in the video memory migration process mainly includes a source host and a destination host, as well as virtual machines (guests) running on these hosts. The source host is the physical host where the virtual machines reside at the start of the migration; it is responsible for running the virtual machines and managing their resources, including vGPU memory data. The destination host is the physical host where the virtual machines will run after the migration; it needs to receive and correctly configure the migrated virtual machines and their resources to ensure the virtual machines can continue running seamlessly.

[0066] A virtual machine (guest) is a virtualized instance running on a host machine. It contains an operating system and applications and uses vGPUs to handle graphics tasks. During the migration process, the virtual machine on the source host is paused, its video memory data and state information are migrated to the destination host, and then it resumes operation on the destination host.

[0067] The vGPU memory data contains not only the application's graphics data, but also the GPU page table. This page table maintains the mapping relationship between GPU virtual addresses and physical addresses, which is the basis for the GPU to access video memory normally based on virtual addresses.

[0068] However, during memory migration, the physical memory address range allocated to the vGPU on the destination end often differs from that on the source end. This causes the physical addresses recorded in the GPU page tables copied from the source end to become invalid on the destination end. If these outdated page tables are used directly, the GPU will be unable to access memory correctly on the destination end, resulting in virtual machine service interruption. To circumvent this problem, related technologies typically employ two strategies: one is to strictly limit the destination end to have a completely identical physical address layout to the source end, which severely restricts the flexibility of migration; the other is to rely on specific hardware mechanisms to ensure address invariance, which increases costs and limits the versatility of the solution.

[0069] Therefore, this disclosure proposes a software-based method for GPU memory migration, aiming to fundamentally solve the aforementioned problems. In this method, a series of software operations are executed on the destination host machine to dynamically recalculate and update all physical addresses corresponding to the migrated GPU page tables, ensuring they correctly correspond to the new physical address space of the destination. This method does not rely on specific hardware and does not impose any restrictions on the physical address configuration of the destination. The destination only needs to provide the local vGPU address layout structure. Based on the migration information and the address space description information of the destination vGPU, the physical addresses corresponding to the GPU page tables on the destination can be calculated. Finally, the calculated physical addresses are used to update the physical addresses corresponding to the received GPU page tables, realigning the migrated GPU page tables with the destination physical address space, thereby significantly improving the flexibility and applicability of vGPU migration.

[0070] The following will, in conjunction with the accompanying drawings, elaborate on the implementation details, workflow, and technical effects of this method through specific embodiments.

[0071] Figure 1 A flowchart illustrating a video memory migration method according to an embodiment of the present disclosure is shown. The method is applied to the target host machine for video memory migration, such as… Figure 1 As shown, the method includes:

[0072] In step S11, migration information and vGPU memory data of the source host are received from the source host. The migration information includes the address space description information of the source vGPU and the base address of the GPU page table. The vGPU memory data includes the GPU page table.

[0073] During the memory migration process, the source host machine sends migration information and vGPU memory data to the destination host machine. The migration information and vGPU memory data can be sent independently by the source host machine, for example, logically in chronological order, or sent and received separately through independent data packets; in addition, the migration information and vGPU memory data can also be sent simultaneously, or sent and received through the same transmission link, and this disclosure does not limit this.

[0074] Migration information is essential for describing vGPU memory data migration, including address space description information and the base address of the GPU page table.

[0075] Address space description information is used to describe the layout structure of the source vGPU memory in the physical address space. Specifically, it describes that the vGPU memory consists of one or more address segments and records the starting position (base address) and length of each address segment. In other words, there are multiple discrete intervals in the physical memory, and the address space description information enables precise management and positioning of the memory.

[0076] For example, the video memory of a vGPU may consist of two address spaces: the first segment starts at address 1G and has a length of 1G; the second segment starts at address 3G and has a length of 1G. The address space description information records the base address (1G and 3G) and the size (1G each) of these two segments.

[0077] The base address of a GPU page table is a specific physical address value that indicates the location of the GPU page table structure in video memory. A GPU page table is a hierarchical table structure used to maintain the mapping relationship between GPU virtual addresses and GPU physical addresses. For example, at the source of the migration, a GPU page table might be stored in video memory starting at physical address 0x40000000; this address 0x40000000 is the base address of that page table.

[0078] In one possible implementation, the base address of the GPU page table is recorded by the source host machine during the virtual machine's operation by tracking the creation and destruction operations of the GPU page table by the virtual machine.

[0079] The source host machine can monitor the creation and destruction of GPU page tables by the virtual machine in real time through its device drivers or other related mechanisms. This ensures that the recorded page table base addresses can dynamically and accurately reflect the state of the GPU page tables within the virtual machine.

[0080] In one possible implementation, the source host maintains a list of page table base addresses; when the source host detects that the virtual machine is creating a new GPU page table, it adds the base address of the new page table to the list; when the source host detects that the virtual machine is destroying an existing GPU page table, it removes the base address of the destroyed page table from the list.

[0081] Specifically, the source-side host driver performs this task by maintaining a dedicated list structure. When it detects that a new GPU page table is being created within the virtual machine, it captures the starting address of the new page table, i.e., the base address, and adds it to the page table base address list. Conversely, when it detects that the virtual machine is destroying an existing GPU page table, it removes the base address entry corresponding to the destroyed page table from the page table base address list.

[0082] For example, suppose a virtual machine needs to create a set of GPU page tables for a new rendering task when running a graphics rendering application. The source host driver detects this creation event, obtains the base address of the newly allocated page table (e.g., 0x40000000), and adds it to the list. When the rendering task is completed and the virtual machine releases these page table resources, the driver will also detect the destruction event and remove the base address 0x40000000 from the list.

[0083] In this embodiment of the disclosure, the source host machine can build and maintain a complete and accurate list of active GPU page table base addresses through this tracking mechanism. At the start of the migration, this list is sent to the destination as a key component of the migration information. This allows the destination to clearly understand which page table structures need to be processed, thereby ensuring the integrity and correctness of the migrated GPU memory mapping.

[0084] During the video memory migration process, the destination host machine performs the operation of receiving vGPU video memory data. The vGPU video memory data is a complete copy of all video memory content owned by the source vGPU at the time of migration, ensuring that it can be seamlessly resumed and executed on the destination side after migration.

[0085] vGPU memory data consists of two main parts: one part is the business data directly generated and used by the application, such as the geometry models, textures, shader programs, and images in the framebuffer used for rendering; the other part is the GPU page table. The GPU page table is a specific data structure stored in video memory that maintains the mapping relationship between GPU virtual addresses and GPU physical addresses, enabling the GPU Memory Management Unit (MMU) to correctly access all data in video memory.

[0086] When the migration manager on the source host (such as QEMU) determines that there are sufficiently few dirty pages, it can pause the virtual machine, and the virtual machine enters the pre-copy state. At this time, the virtual machine's vCPUs are paused, meaning that no new computing tasks are initiated. Since GPU tasks are usually driven and scheduled by the CPU (e.g., the CPU issues instructions to the GPU to render), the pause of vCPUs directly causes the GPU to stop receiving new tasks, thereby stopping the creation of new GPU page tables and the modification of existing page table contents.

[0087] During this window of time when business operations are stabilizing and memory status is relatively stable, the source host begins sending the complete vGPU memory data to the destination host. The destination host then receives this vGPU memory data. Since the GPU page table itself also resides in video memory, it is transmitted to the destination host as part of the video memory data.

[0088] For example, assuming that at the source end, a GPU page table structure is stored in the video memory region starting from the base address 0x40000000, then the video memory content corresponding to the page table size starting from that address will be sent from the source host to the destination host as a fragment of vGPU video memory data.

[0089] In this implementation, the destination receives full memory data from the source when virtual machine services are paused and GPU page table updates are paused. This ensures that the GPU page table obtained by the destination is a consistent snapshot of the source at the moment of migration, laying an accurate and reliable data foundation for subsequent updates of these page table entries on the destination based on the new physical address environment.

[0090] In step S12, based on the migration information and the address space description information of the destination vGPU, the physical address of the destination corresponding to the GPU page table is calculated;

[0091] The computation process performed by the destination host machine updates the physical addresses in the GPU page table to ensure that the physical addresses in the GPU page table are correctly mapped to the physical video memory space of the destination host machine. This process is based on two parts of information: migration information received from the source host machine and address space description information of the destination vGPU.

[0092] The migration information includes the address space description of the source vGPU and the base address of the GPU page table. This information allows the destination host to clearly understand the layout of the source video memory. The address space description of the destination vGPU provides the layout of the destination video memory, enabling the destination host to correctly map the physical addresses of the source to the physical address space of the destination.

[0093] During computation, CPU physical addresses that remain unchanged before and after virtual machine migration can be used as an intermediary. First, based on the address space description information of the source vGPU, the source GPU physical address to be converted is mapped to its corresponding CPU physical address; then, based on the address space description information of the destination vGPU, the aforementioned CPU physical address is remapped to the destination GPU physical address space. For specific implementation details, please refer to the possible implementations provided in this disclosure, which will not be elaborated here.

[0094] Of course, the specific implementation of calculating the physical address of the destination end corresponding to the GPU page table is not limited to this. For example, the destination end can maintain a segment table, which defines the correspondence between different blocks or segments of the source and destination memory. During calculation, the block to which the source address belongs is first determined based on the source address. Then, the corresponding destination block is found based on the segment table. Finally, the final physical address is calculated within the destination block using the same offset within the same block.

[0095] In step S13, the physical address corresponding to the received GPU page table is updated using the calculated physical address.

[0096] After calculating the valid physical address of the destination, this physical address can be written to the corresponding location in the GPU page table structure received from the source. The updated physical addresses fall into two categories: the physical addresses recorded in each page table entry; and the base address of the GPU page table itself. This address information to be updated can be contained in the GPU page table data structure received from the source and recovered at the destination.

[0097] The update process can proceed sequentially. The destination driver can traverse each GPU page table that needs updating. For each page table entry, the original source GPU physical address is replaced with the destination GPU physical address calculated for that entry. After updating all page table entries, the base address of the page table itself is also updated using the newly calculated base address.

[0098] For example, for a specific GPU page table, the new base address calculated at the destination end could be 0xB0000000. The destination driver can write this new address into the hardware register or software data structure responsible for locating the page table. Simultaneously, for the page table entry with a source physical address of 0x1G + 0.5G in the original record, after calculating its corresponding destination physical address as 0xB0000000 + 0.5G, this new physical address can be written into the corresponding field of the page table entry.

[0099] In this embodiment, the destination host receives migration information from the source host, including the address space description information of the source vGPU and the base address of the GPU page table. Then, it receives vGPU memory data from the source host, which contains the GPU page table. Based on the migration information and the address space description information of the destination vGPU, it calculates the physical address of the destination corresponding to the GPU page table. Finally, it uses the calculated physical address to update the physical address corresponding to the received GPU page table. Thus, by executing a series of software operations on the destination host, all physical addresses corresponding to the migrated GPU page table are dynamically recalculated and updated, ensuring they correctly correspond to the new physical address space of the destination. This method does not rely on specific hardware and does not impose any restrictions on the physical address configuration of the destination. The destination only needs to provide the local vGPU address layout structure. Based on the migration information and the address space description information of the destination vGPU, the physical address of the destination corresponding to the GPU page table can be calculated. Finally, the physical address corresponding to the received GPU page table is updated using the calculated physical address, so that the migrated GPU page table is re-aligned with the physical address space of the destination, thereby significantly improving the flexibility and applicability of vGPU migration.

[0100] In one possible implementation, the physical address corresponding to the GPU page table includes: the physical address in the GPU page table entry and the base address of the GPU page table itself; calculating the physical address of the destination end corresponding to the GPU page table includes: performing address translation on the base address of the GPU page table itself to obtain the base address of the destination page table; and performing address translation on the physical address recorded in the page table entry of the GPU page table to obtain the physical address recorded in the page table entry of the destination GPU page table.

[0101] The physical address corresponding to the GPU page table may include: the physical address recorded in the GPU page table entry, and the base address of the GPU page table itself. The physical address recorded in the GPU page table entry is used to point to the video memory location storing specific graphics data or other page table structures; while the base address of the GPU page table itself is used to locate the starting position of the page table structure in video memory.

[0102] The page table itself, as the accessed data object, needs to be relocated at the destination; similarly, the data addresses mapped to page table entries also need to adapt to the new physical address space. By performing address translation on these two types of addresses, the entire GPU page table system can maintain inherent consistency after migration. When the GPU starts working at the destination, it can not only find the starting position of the page table through the updated page table base address, but also ensure that the physical address corresponding to each page table entry correctly points to the corresponding data in the destination's video memory during address translation.

[0103] When calculating the destination physical address, the destination host machine can perform address translation operations on both levels separately. For the base address of the GPU page table itself, the destination driver can perform one address translation to obtain the new base address of the page table in the destination video memory space. For the physical addresses recorded in each page table entry in the GPU page table, the destination driver can traverse the page table and perform address translation on the address recorded in each entry to obtain the valid physical address in the destination address space.

[0104] For example, assuming a GPU page table has a base address of 0x40000000 at the source, the destination driver can calculate that the page table should be located at 0xB0000000 at the destination through address translation. Simultaneously, a page table entry at the source records a physical address of 0x40001000 pointing to graphics data; using the same translation mechanism, this address can be translated to 0xB0001000 at the destination.

[0105] In this embodiment, after receiving the migrated GPU page table from the source, the destination host machine performs corresponding translations on the page table base address and the physical addresses in the page table entries to obtain a GPU page table adapted to the destination. This process does not rely on specific hardware support, nor does it require the source and destination hardware configurations to be completely identical, significantly improving the flexibility and versatility of memory migration. It allows the destination host machine to dynamically adjust physical addresses based on its own address space layout, so vGPU memory migration is no longer limited by hardware configuration, lowering the migration threshold and improving migration efficiency. Simultaneously, this method is implemented in software, avoiding hardware dependence, reducing the risk of migration failure due to hardware differences, and enhancing the reliability of vGPU migration.

[0106] In one possible implementation, the address space description information includes the base address and size information of one or more video memory segments, wherein the addresses within a video memory segment are contiguous.

[0107] Address space description information is used to characterize the organization of video memory in detail. Specifically, address space description information includes the base address and size information of one or more video memory segments. A video memory segment is a contiguous address region into which the video memory is divided, and each segment corresponds to a base address and a size. The base address is the starting address of the segment, and the size information indicates the length of the segment. The addresses within a video memory segment are continuous; that is, within the segment, the addresses increase sequentially without interruption.

[0108] The purpose of address space description information is to provide necessary mapping information for memory migration. By maintaining address space description information, the source host machine can record the detailed layout of the source vGPU memory. This information is sent to the destination host machine during the migration process, enabling the destination host machine to understand the structure of the source memory and perform corresponding address translations. For example, the source host machine's memory may be divided into multiple segments, each with its own base address and size. The base address and size information of these segments constitute part of the address space description information, used to characterize the specific organization of the source memory.

[0109] After receiving this information, the destination host machine translates the addresses of each segment according to its own video memory layout. For example, if the base address of a video memory segment on the source side is 1GB and its size is 1GB, the destination host machine can map this segment to the corresponding location on the destination side based on its own video memory layout. If the starting address of the video memory on the destination side is 100GB, the destination host machine can map the 1GB base address on the source side to 100GB, thus obtaining the video memory segment on the destination side.

[0110] Address space description information is the foundation for subsequent address calculations. It enables the destination host machine to dynamically adjust the mapping of memory segments based on its own hardware configuration, without relying on specific hardware support. This not only improves the flexibility of memory migration but also reduces the risk of migration failure due to hardware configuration differences. After receiving the migrated memory data from the source, the address space description information allows the destination host machine to convert the memory segments accordingly based on its own address space layout, thereby obtaining a memory layout adapted to the destination. This is done without relying on specific hardware support or requiring the source and destination hardware configurations to be completely identical, significantly improving the flexibility and versatility of memory migration.

[0111] In one possible implementation, calculating the physical address of the destination GPU corresponding to the GPU page table includes: converting the physical address of the source GPU page table into a CPU physical address that remains unchanged before and after migration, based on the address space description information of the source vGPU; and converting the CPU physical address into the GPU physical address of the destination GPU page table, based on the address space description information of the destination vGPU.

[0112] During memory migration, GPU physical addresses can be translated based on CPU physical addresses, which serve as an intermediate reference that remains unchanged throughout the migration process. In a virtualization environment, the CPU physical address space required by the virtual machine operating system is abstracted and managed by the hypervisor, and it remains stable before and after memory migration. Therefore, the CPU physical address can serve as an intermediary connecting the source and destination GPU physical address spaces.

[0113] During memory migration, the calculation of GPU physical addresses on the destination side can be performed in stages. In the first stage of the conversion process, the destination driver can map the source GPU physical addresses to be converted to the corresponding CPU physical addresses based on the address space description information of the source vGPU. In the specific mapping process, the segmented layout of the source GPU memory can be considered, and the calculation can be completed by combining the base address and the offset.

[0114] In the second stage, the destination driver can map the CPU physical address obtained above to the GPU physical address space of the destination based on the address space description information of the destination vGPU. This process can use the same conversion method, but uses the base address parameter of the destination.

[0115] For example, assume the source GPU physical address is 0x1G+0.5G. According to the source address space description information, this address can be located within the memory segment with a base address of 0x1G, and its offset relative to this segment is 0.5G. By querying the address mapping relationship, the base address of the CPU physical address segment corresponding to this source segment can be 0x1940000000 (i.e., 101G). Adding the CPU base address to the offset, we get the CPU physical address 0x1944000000 (i.e., 101.5G). On the destination side, this CPU physical address corresponds to the destination memory segment with a base address of 0x2C0000000 (i.e., 11G). Adding the destination memory segment base address to the same offset of 0.5G, we finally get the destination GPU physical address 0x2C4000000 (i.e., 11.5G).

[0116] In this embodiment of the disclosure, the physical address of the source GPU is converted into the physical address of the CPU according to the address space description information of the source vGPU, and then the physical address of the CPU is converted into the physical address of the destination vGPU according to the address space description information of the destination vGPU. Thus, the memory migration process relies on a hardware-independent address translation method. This translation method does not depend on specific hardware characteristics and can adapt to different physical address layouts, thereby improving the applicability and deployment flexibility of the vGPU migration solution in different hardware environments.

[0117] In one possible implementation, the step of converting the physical address corresponding to the source GPU page table into a CPU physical address that remains unchanged before and after migration, based on the address space description information of the source GPU, includes: determining the source memory segment to which the source GPU physical address belongs based on the address space description information of the source GPU, and obtaining the source segment base address of the memory segment; calculating the offset of the source GPU physical address relative to the source segment base address; determining the CPU physical address segment base address corresponding to the source memory segment according to a first mapping relationship; and adding the CPU physical address segment base address to the offset to obtain the CPU physical address.

[0118] This conversion process utilizes the segmented structure defined in the address space description information to establish a cross-address space correspondence through the calculation of relative offsets and the mapping of base addresses.

[0119] A source-side video memory segment is a contiguous address range defined in the source-side vGPU address space description information. Each segment can be defined by its starting position and length, with the starting position determined by the segment's base address. The offset refers to the displacement of a specific address relative to its segment's base address; this value remains constant within the segment. The CPU physical address segment base address refers to the starting position when the base address of this video memory segment is mapped to the CPU physical address space; this mapping relationship can be established during system initialization.

[0120] For ease of description, the mapping relationship between the source-end video memory segment base address and the CPU physical address segment base address is called the first mapping relationship, and the mapping relationship between the destination-end video memory segment base address and the CPU physical address segment base address is called the second mapping relationship.

[0121] The first mapping relationship is the address correspondence rule established and maintained during system operation. This mapping relationship records the base address correspondence between each source vGPU memory segment and its corresponding CPU physical address segment. This correspondence can be established during vGPU initialization or memory allocation, configured by the system software according to the address space layout at that time.

[0122] For example, in a virtualization environment, the hypervisor can allocate a corresponding address range in the CPU physical address space for each vGPU memory segment and record the base address correspondence between the two. This mapping relationship can be stored in the host machine's memory data structure for querying during the migration process.

[0123] For example, suppose a source vGPU has two memory segments: the first segment has a GPU base address of 0x1G, corresponding to a CPU physical address segment base address of 0x1940000000 (101G); the second segment has a GPU base address of 0x3G, corresponding to a CPU physical address segment base address of 0x1944000000 (101.25G). These correspondences can constitute the contents of a predefined mapping table.

[0124] In other words, the mapping relationship is based on the unified management of the address space by the system software. By establishing and maintaining the correspondence between GPU memory segments and CPU address segments during the system initialization phase, a reliable lookup basis can be provided for subsequent address translation. This allows the address translation process to be completed at the software level, without relying on specific hardware characteristics.

[0125] During the conversion process, the destination driver first determines the specific video memory segment to which the physical address of the source GPU to be converted belongs, based on the address space description information of the source vGPU. By comparing the source GPU physical address with the address range of each segment, the segment containing that address can be found. Subsequently, the offset of that address relative to the base address of its segment is calculated; this offset represents the relative position of the address within the segment.

[0126] After determining the source memory segment to which it belongs, the base address of the corresponding CPU physical address segment is obtained by querying the first mapping relationship. For example, for the GPU physical address 0x1G+0.5G belonging to the first segment, the corresponding CPU physical address segment base address can be obtained by querying the mapping relationship table as 0x1940000000.

[0127] Finally, the base address of the CPU physical address segment is added to the calculated offset to obtain the corresponding CPU physical address.

[0128] For example, assume the source GPU physical address to be converted is 0x1G + 0.5G. By querying the source address space description information, it can be determined that this address belongs to the video memory segment with a base address of 0x1G. The calculated offset is 0.5G. According to the first mapping relationship, the base address of the CPU physical address segment corresponding to this source segment is 0x1940000000 (i.e., 101G). Adding the two together, we get the CPU physical address 0x1944000000 (i.e., 101.5G).

[0129] In this embodiment, the memory segment to which the physical address of the source GPU belongs is determined based on the address space description information of the source vGPU, and the base address of the source segment is obtained. Then, the offset of the source GPU physical address relative to the source segment base address is calculated. The corresponding CPU physical address segment base address is determined according to the first mapping relationship. Finally, the CPU physical address segment base address is added to the offset to obtain the CPU physical address. This makes the complex address space mapping manageable and predictable, providing accurate input for subsequent destination address translation, thereby supporting the maintenance of address consistency during vGPU migration.

[0130] In one possible implementation, the step of converting the CPU physical address into the GPU physical address corresponding to the destination GPU page table based on the address space description information of the destination vGPU includes: determining the base address of the destination video memory segment corresponding to the CPU physical address based on the address space description information of the destination vGPU and the second mapping relationship; and adding the base address of the destination video memory segment to the offset to obtain the destination GPU physical address.

[0131] As mentioned earlier, the second mapping relationship is the correspondence between the CPU physical address and the base address of the destination video memory segment. This mapping relationship can be established during the initialization phase of the destination vGPU, recording the correspondence rules between the CPU physical address range and the base address of the destination video memory segment. The destination host machine's driver can maintain and use this mapping relationship to complete address translation.

[0132] During the conversion process, the destination driver first determines the destination memory segment base address corresponding to the CPU physical address to be converted, based on the address space description information and second mapping relationship of the destination vGPU. This process can be accomplished by querying the mapping table, taking the CPU physical address as input and obtaining the corresponding destination memory segment base address as output. Subsequently, the obtained destination memory segment base address is added to the offset calculated in the source conversion stage to obtain the final destination GPU physical address.

[0133] For example, assume the CPU physical address to be converted is 0x1944000000 (i.e., 101.5G). By consulting the second mapping table, the destination memory segment base address corresponding to this CPU physical address can be determined to be 0x2C0000000 (i.e., 11G). The offset calculated in the source-side conversion is 0.5G. Adding the destination memory segment base address 0x2C0000000 to this offset 0.5G yields the destination GPU physical address 0x2C4000000 (i.e., 11.5G).

[0134] In this embodiment of the disclosure, the base address of the target memory segment corresponding to the CPU physical address is determined by the address space description information and the second mapping relationship of the target vGPU. Then, the base address of the target memory segment is added to the offset to obtain the physical address of the target GPU. Thus, the entire migration process can adapt to different hardware address layouts, which helps to improve the adaptability and deployment flexibility of the vGPU migration solution in heterogeneous environments.

[0135] The following describes an application scenario of an embodiment of this disclosure. In this scenario, during the operation of a virtual machine, the virtual machine operating system (Guest) performs GPU page table creation and destruction operations according to its graphics processing requirements. The source host's driver monitors these operations and records the base addresses of all active GPU page tables. The source host maintains a list of page table base addresses to dynamically track changes in these base addresses.

[0136] When virtual machine migration begins, the source host driver sends the vGPU address space description information and the recorded GPU page table base address as migration information to the destination host.

[0137] During the migration process, when the migration manager (such as QEMU) determines that the number of dirty pages has reached a predetermined condition, it will put the virtual machine into a pre-copy state. In this state, the virtual machine's vCPUs are paused, no new GPU tasks are generated, and the GPU page table content remains stable. The source host driver then sends the vGPU's memory data, which contains the complete GPU page table content, to the destination host. The destination host driver receives this memory data and writes it into the destination's video memory.

[0138] After the video memory data synchronization is complete, the destination host driver begins address translation, traversing the page table structure corresponding to all GPU page table base addresses obtained from the source, and recalculating the physical addresses within them. The calculation process is based on the address space description information of the source vGPU and the destination vGPU, and adopts a staged translation method: first, the source GPU physical address is translated into an intermediate CPU physical address according to the source description information, and then the CPU physical address is translated into the destination GPU physical address according to the destination description information.

[0139] During the translation process, the GPU physical address can be calculated by adding an offset within the address segment to the base address of the current address segment. The offset remains constant during address translation; the address space mapping is achieved by replacing the base address.

[0140] After updating the addresses of all GPU page table entries, the migration process ends. The virtual machine resumes operation on the destination machine, and its GPU page table now contains valid physical addresses in the destination address space, ensuring that the GPU can continue to access video memory data normally. The entire process is implemented in software and does not rely on specific hardware support, enabling vGPU migration to adapt to different physical address configuration environments.

[0141] Figure 2 A block diagram of a memory migration apparatus according to an embodiment of the present disclosure is shown, such as Figure 2 As shown, the video memory migration device 20 includes:

[0142] The receiving module 21 is used to receive migration information and vGPU memory data of the source host from the source host. The migration information includes address space description information of the source vGPU and the base address of the GPU page table. The vGPU memory data includes the GPU page table.

[0143] The calculation module 22 is used to calculate the physical address of the destination end corresponding to the GPU page table based on the migration information and the address space description information of the destination vGPU.

[0144] The update module 23 is used to update the physical address corresponding to the received GPU page table using the calculated physical address.

[0145] In one possible implementation, the physical address corresponding to the GPU page table includes: the physical address in the GPU page table entry and / or the base address of the GPU page table itself;

[0146] The computing module is used for:

[0147] The base address of the GPU page table itself is translated to obtain the base address of the destination page table;

[0148] The physical address recorded in the page table entry of the GPU page table is translated to obtain the physical address recorded in the page table entry of the destination GPU page table.

[0149] In one possible implementation, the computing module is used for:

[0150] Based on the address space description information of the source vGPU, the physical address corresponding to the page table of the source GPU is converted into a CPU physical address that remains unchanged before and after the migration.

[0151] Based on the address space description information of the destination vGPU, the CPU physical address is converted into the GPU physical address corresponding to the page table of the destination GPU.

[0152] In one possible implementation, the computing module is used for:

[0153] Based on the address space description information of the source vGPU, determine the source memory segment to which the physical address of the source GPU belongs, and obtain the source segment base address of the memory segment.

[0154] Calculate the offset of the source GPU physical address relative to the source segment base address;

[0155] Based on the first mapping relationship, determine the CPU physical address segment base address corresponding to the source memory segment;

[0156] The CPU physical address is obtained by adding the segment base address of the CPU physical address to the offset.

[0157] In one possible implementation, the computing module is used for:

[0158] Based on the address space description information and the second mapping relationship of the destination vGPU, the base address of the destination video memory segment corresponding to the CPU physical address is determined.

[0159] The base address of the target memory segment is added to the offset to obtain the target GPU physical address.

[0160] In one possible implementation, the address space description information includes the base address and size information of one or more video memory segments, wherein the addresses within a video memory segment are contiguous.

[0161] In one possible implementation, the base address of the GPU page table is recorded by the source host machine during the virtual machine's operation by tracking the creation and destruction operations of the GPU page table by the virtual machine.

[0162] In one possible implementation, the source host maintains a list of page table base addresses; when the source host detects that the virtual machine is creating a new GPU page table, it adds the base address of the new page table to the list; when the source host detects that the virtual machine is destroying an existing GPU page table, it removes the base address of the destroyed page table from the list.

[0163] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0164] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0165] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0166] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0167] Figure 3 This is a block diagram illustrating a video memory migration device according to an exemplary embodiment. For example, device 1900 may be provided as a server or terminal device. (Refer to...) Figure 3 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0168] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0169] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0170] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0171] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0172] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0173] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0174] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0175] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0176] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0177] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory migration method, characterized in that, The method, applied to the target host machine for video memory migration, includes: The source host receives migration information and vGPU memory data of the source host. The migration information includes address space description information of the source vGPU and base address of the GPU page table. The vGPU memory data includes the GPU page table. Based on the migration information and the address space description information of the destination vGPU, calculate the physical address of the destination corresponding to the GPU page table; Use the calculated physical address to update the physical address corresponding to the received GPU page table.

2. The method according to claim 1, characterized in that, The physical address corresponding to the GPU page table includes: the physical address in the GPU page table entry and / or the base address of the GPU page table itself; The calculation of the destination physical address corresponding to the GPU page table includes: The base address of the GPU page table itself is translated to obtain the base address of the destination page table; The physical address recorded in the page table entry of the GPU page table is translated to obtain the physical address recorded in the page table entry of the destination GPU page table.

3. The method according to claim 1, characterized in that, The calculation of the destination physical address corresponding to the GPU page table includes: Based on the address space description information of the source vGPU, the physical address corresponding to the page table of the source GPU is converted into a CPU physical address that remains unchanged before and after the migration. Based on the address space description information of the destination vGPU, the CPU physical address is converted into the GPU physical address corresponding to the page table of the destination GPU.

4. The method according to claim 3, characterized in that, The step of converting the physical address corresponding to the source GPU page table into a CPU physical address that remains unchanged before and after the migration, based on the address space description information of the source GPU, includes: Based on the address space description information of the source vGPU, determine the source memory segment to which the physical address of the source GPU belongs, and obtain the source segment base address of the memory segment. Calculate the offset of the source GPU physical address relative to the source segment base address; Based on the first mapping relationship, determine the CPU physical address segment base address corresponding to the source memory segment; The CPU physical address is obtained by adding the segment base address of the CPU physical address to the offset.

5. The method according to claim 3, characterized in that, The step of converting the CPU physical address into the GPU physical address corresponding to the GPU page table on the destination GPU based on the address space description information of the destination vGPU includes: Based on the address space description information and the second mapping relationship of the destination vGPU, the base address of the destination video memory segment corresponding to the CPU physical address is determined. The base address of the target memory segment is added to the offset to obtain the target GPU physical address.

6. The method according to claim 1, characterized in that, The address space description information includes the base address and size information of one or more video memory segments, and the addresses within a video memory segment are contiguous.

7. The method according to claim 1, characterized in that, The base address of the GPU page table is recorded by the source host machine during the virtual machine's operation by tracking the creation and destruction operations of the GPU page table by the virtual machine.

8. The method according to claim 7, characterized in that, The source host maintains a list of page table base addresses; when the source host detects that the virtual machine is creating a new GPU page table, it adds the base address of the new page table to the list; when the source host detects that the virtual machine is destroying an existing GPU page table, it removes the base address of the destroyed page table from the list.

9. A video memory migration device, applied to a target host machine for video memory migration, characterized in that, The device includes: A receiving module is used to receive migration information and vGPU memory data of the source host machine from the source host machine. The migration information includes address space description information of the source vGPU and the base address of the GPU page table. The vGPU memory data includes the GPU page table. The calculation module is used to calculate the physical address of the destination end corresponding to the GPU page table based on the migration information and the address space description information of the destination vGPU; The update module is used to update the physical address corresponding to the received GPU page table using the calculated physical address.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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