SPI (Serial Peripheral Interface) data acquisition method and device

Abstract

The invention relates to an SPI (Serial Peripheral Interface) data acquisition method and device. The method is applied to a system-on-chip integrated with a multi-core CPU (Central Processing Unit), and comprises the following steps of: binding a high-precision timer and an SPI (Serial Peripheral Interface) data acquisition task to a special CPU core; the high-precision timer is configured into an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to a trigger period is higher than a target sampling frequency; the special CPU core is configured to exclusively run the high-precision timer, process interruption generated by the high-precision timer and execute an SPI data acquisition task; in response to the interruption generated by the high-precision timer, starting SPI data acquisition by utilizing an interruption processing function, and storing the acquired data into an annular buffer area; and reading the data stored in the annular buffer area, and correcting the read data to obtain SPI data meeting the sampling requirement. By adopting the method, the problem of sampling time sequence jitter caused by Linux kernel scheduling in a high-frequency and high-precision scene of the existing SPI data acquisition method can be solved.

Description

Technical Field

[0001] This application relates to the field of embedded communication technology, and in particular to an SPI data acquisition method and apparatus. Background Technology

[0002] With the rapid development of industrial IoT and edge computing technologies, the performance requirements for data acquisition systems are increasing, especially in fields such as structural health monitoring and industrial equipment diagnosis. It is necessary to achieve high-frequency continuous acquisition of vibration, acoustic and other signals at a frequency of no less than 48kHz, while ensuring high sampling time accuracy to ensure the accuracy of sampling points.

[0003] Traditional data acquisition systems often use a microcontroller unit (MCU) as the main controller for sensors. Data is read from the sensors via an SPI (Serial Peripheral Interface) bus, and then the MCU performs preliminary processing or forwards the data to a high-performance main control system via serial ports, I2C, CAN, or other buses. This approach has two drawbacks. First, the MCU's processing power and resources are limited, making it unsuitable for tasks such as audio / video processing and complex edge computing. Second, in product designs that prioritize high integration and small size, a separate MCU module increases the complexity of the circuit design and the area required for the printed circuit board (PCB), hindering product miniaturization and cost control.

[0004] Because the SoC+Linux system architecture possesses powerful multitasking and high concurrency capabilities, it can integrate data acquisition with complex upper-layer applications. Therefore, a more integrated SoC+Linux system architecture for data acquisition was proposed. However, as a general-purpose time-sharing operating system, the standard Linux system's kernel is not designed for hard real-time tasks, and it has inherent defects when handling SPI data acquisition tasks with high real-time requirements. Specifically, the scheduling delay of the system kernel, untimely interrupt response, and resource preemption between multiple tasks can cause unpredictable timing jitter in SPI data transmission. Especially in the acquisition of high-frequency, high-precision vibration signals, this jitter can lead to the loss of sampling points or severe timestamp distortion, making the acquired data unable to truly reflect the continuous changes in the physical world, greatly limiting the application of this architecture in high-end industrial scenarios.

[0005] To improve the performance of SPI acquisition in high-frequency, high-precision scenarios under the SoC+Linux system architecture, existing technologies have attempted to optimize real-time performance using methods such as RT-Linux (Real-Time Linux) kernel patches. However, actual tests have shown that in SPI data acquisition scenarios at frequencies of 48kHz and above, the optimization effect of such general real-time patches is limited, and the problem of sampling timing jitter caused by Linux kernel scheduling still exists.

[0006] For existing SPI data acquisition methods, in high-frequency, high-precision scenarios, there is a problem of sampling timing jitter caused by Linux kernel scheduling, and no effective solution has been proposed yet. Summary of the Invention

[0007] Therefore, it is necessary to provide an SPI data acquisition method and apparatus to address the aforementioned technical problems.

[0008] Firstly, this application provides an SPI data acquisition method. Applied to a system-on-a-chip integrating a multi-core CPU, the method includes:

[0009] A pre-built high-precision timer and SPI data acquisition task are bound to a dedicated CPU core in the multi-core CPU. The high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle. The high-precision timer is configured to use an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency. The target sampling frequency is the sampling frequency corresponding to the sampling requirements. The dedicated CPU core is configured to exclusively run the high-precision timer, process the interrupts generated by the high-precision timer, and execute the SPI data acquisition task.

[0010] In response to the interrupt generated by the high-precision timer, the interrupt handling function is used to start SPI data acquisition and the acquired data is stored in a circular buffer;

[0011] The data stored in the circular buffer is read and corrected to obtain SPI data that meets the sampling requirements.

[0012] In one embodiment, before binding the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core, the process includes:

[0013] The dedicated CPU core is isolated from the multi-core CPU integrated in the system-on-a-chip through the CPU isolation mechanism of the Linux kernel.

[0014] In one embodiment, before binding the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core, the process includes:

[0015] Based on the sampling requirements, the trigger period of the high-precision timer is determined;

[0016] Based on the trigger period of the high-precision timer, the hardware timer in the system-on-a-chip is configured to obtain the high-precision timer.

[0017] In one embodiment, binding the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core includes:

[0018] During initialization, it is detected whether the process of the high-precision timer is running on the dedicated CPU core. If the process of the high-precision timer is not running on the dedicated CPU core, the process of the high-precision timer is migrated to the dedicated CPU core and locked to the dedicated CPU core.

[0019] In one embodiment, before initiating SPI data acquisition using an interrupt handler function in response to an interrupt generated by the high-precision timer, and storing the acquired data into a circular buffer, the process includes:

[0020] Within the Linux kernel space, a physically contiguous circular buffer is dynamically allocated; the circular buffer has a fixed size and is a circular queue data structure.

[0021] In one embodiment, the step of responding to an interrupt generated by the high-precision timer, initiating SPI data acquisition using an interrupt handling function, and storing the acquired data into a circular buffer includes:

[0022] In response to the interrupt generated by the high-precision timer, the Linux kernel standard SPI message queue is bypassed, and the transfer_one_message function is directly called in the interrupt handler to start SPI transmission, perform SPI data acquisition, and store the acquired data into the circular buffer.

[0023] In one embodiment, reading the data stored in the circular buffer and correcting the read data to obtain SPI data that meets the sampling requirements includes:

[0024] Read the data stored in the circular buffer;

[0025] The read data is corrected to meet the sampling requirements and the target correction is performed to obtain SPI data. The target correction includes oversampling correction and outlier correction.

[0026] In one embodiment, the step of performing target correction on the read data to obtain SPI data that meets the sampling requirements includes:

[0027] The read data is downsampled to obtain an initial sequence with a frequency consistent with the target sampling frequency;

[0028] If the difference between adjacent points in the initial sequence is greater than or equal to a preset difference threshold, then the point located in the next position among the adjacent points is identified as an abnormal point.

[0029] Based on the normal points in the initial sequence, the correction values ​​of the abnormal points are calculated using a curve fitting algorithm, and the abnormal points are replaced with the correction values ​​to obtain SPI data that meets the sampling requirements.

[0030] In one embodiment, the step of calculating correction values ​​for outlier points based on normal points in the initial sequence using a curve fitting algorithm, and replacing the outlier points with the correction values ​​to obtain SPI data that meets the sampling requirements, includes:

[0031] If an outlier is found to be on the boundary of the initial sequence, the fitting interval of the curve fitting algorithm is dynamically adjusted. Based on the normal points in the initial sequence, the correction value of the outlier is calculated by the curve fitting algorithm, and the outlier is replaced with the correction value to obtain SPI data that meets the sampling requirements.

[0032] Secondly, this application also provides an SPI data acquisition device. Applied to a system-on-a-chip integrating a multi-core CPU, the device includes:

[0033] A task binding module is used to bind a pre-built high-precision timer and an SPI data acquisition task to a dedicated CPU core in the multi-core CPU. The high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle. The high-precision timer is configured to use an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency. The target sampling frequency is the sampling frequency corresponding to the sampling requirements. The dedicated CPU core is configured to exclusively run the high-precision timer, process the interrupts generated by the high-precision timer, and execute the SPI data acquisition task.

[0034] The data acquisition module is used to respond to the interrupt generated by the high-precision timer, start SPI data acquisition using the interrupt handling function, and store the acquired data into a circular buffer.

[0035] And a correction module, used to read the data stored in the circular buffer and correct the read data to obtain SPI data that meets the sampling requirements.

[0036] The aforementioned SPI data acquisition method and apparatus bind a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core. Within this dedicated CPU core, the high-precision timer runs, interrupts generated by the timer are handled, and the SPI data acquisition task is executed. SPI data is acquired according to a pre-configured trigger cycle, stored in a circular memory area, and read from the circular buffer. The read data is then corrected to obtain SPI data that meets the sampling requirements. By binding the high-precision timer and SPI data acquisition task to a dedicated CPU core and ensuring that the dedicated CPU core only runs the high-precision timer, handles interrupts generated by the timer, and executes critical real-time tasks such as SPI data acquisition, the SPI acquisition task is transformed into an actively executed task running in a dedicated, clean, and non-preemptive hardware environment. This fundamentally eliminates jitter caused by task scheduling and resource contention. It solves the problem of sampling timing jitter caused by Linux kernel scheduling in existing SPI data acquisition methods under high-frequency, high-precision scenarios.

[0037] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 A hardware structure block diagram of a terminal for an SPI data acquisition method provided in an embodiment of this application;

[0040] Figure 2 A flowchart illustrating an embodiment of the SPI data acquisition method provided in this application;

[0041] Figure 3 A flowchart of an SPI data acquisition method provided in a preferred embodiment of this application;

[0042] Figure 4 This is a structural block diagram of an SPI data acquisition device provided in an embodiment of this application. Detailed Implementation

[0043] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0044] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0045] The method embodiments provided in this example can be executed on a terminal, computer, or similar computing device. For example, it can run on a terminal. Figure 1 This is a hardware structure block diagram of the terminal for the SPI data acquisition method in this embodiment. For example... Figure 1 As shown, a terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 and a memory 104 for storing data are also included. The processor 102 may be, but is not limited to, a microprocessor (MCU) or a programmable logic device (FPGA). The terminal may also include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that… Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the terminal described above. For example, the terminal may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown are illustrated.

[0046] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the SPI data acquisition method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. This network includes a wireless network provided by the terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 can be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0048] This embodiment provides an SPI data acquisition method, applied to a system-on-a-chip integrating a multi-core CPU. Figure 2 This is a flowchart of the SPI data acquisition method in this embodiment, as follows: Figure 2 As shown, the process includes the following steps:

[0049] Step S210: Bind the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core in the multi-core CPU; the high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle; the high-precision timer is configured as an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency; the target sampling frequency is the sampling frequency corresponding to the sampling requirements; the dedicated CPU core is configured to exclusively run the high-precision timer, handle the interrupts generated by the high-precision timer, and execute the SPI data acquisition task.

[0050] The number of CPUs in the above system-on-a-chip varies depending on the specific hardware platform SoC model. It should be noted that the system-on-a-chip in this embodiment includes at least two CPU cores, of which at least one core is a dedicated CPU core.

[0051] The aforementioned binding of a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core in a multi-core CPU can utilize a CPU affinity mechanism to fix both the pre-built high-precision timer and SPI data acquisition task to the dedicated CPU core. This fixed binding of the pre-built high-precision timer to the dedicated CPU core means that the high-precision timer's interrupt task is also bound to the dedicated CPU core. Specifically, after determining the dedicated CPU core in the multi-core CPU, the Linux kernel's `cpuset` function can be used to configure the dedicated CPU core to handle only high-priority tasks and not participate in the scheduling of other tasks. These high-priority tasks can include running the high-precision timer, handling interrupts generated by the high-precision timer, and executing real-time tasks such as SPI data acquisition. The `cpuset` function is a Linux kernel function used to manage CPU affinity. Through the `cpuset` function, a dedicated CPU core can be partitioned from the system-on-a-chip of a multi-core CPU, and target processes, threads, or interrupts can be bound to the dedicated CPU core, achieving CPU resource isolation. The target process, thread, or interrupt can be the process, thread, or interrupt corresponding to the high-priority task.

[0052] In this step, binding the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core in a multi-core CPU can be achieved by checking whether the high-precision timer process is running on a dedicated CPU core during initialization. If the high-precision timer process is not running on a dedicated CPU core, it is migrated to the dedicated CPU core and locked there. Simultaneously, during initialization, it is also checked whether the SPI data acquisition task process is running on a dedicated CPU core. If the SPI data acquisition task process is not running on a dedicated CPU core, it is migrated to the dedicated CPU core and locked there. Additionally, it can also check whether there are non-high-priority tasks (non-real-time tasks) on the dedicated CPU core. If non-high-priority tasks exist on the dedicated CPU core, they are migrated to a CPU core other than the dedicated CPU core. The aforementioned non-high-priority tasks can be network interruptions (e.g., eth0), storage I / O interruptions (e.g., SATA (Serial Advanced Technology Attachment) or USB (Universal Serial Bus)), system service interruptions, etc.

[0053] This step ensures the real-time performance of SPI acquisition tasks and high-precision ADC (Analog-to-Digital Converter) data acquisition by dividing the CPU into dedicated CPU cores and setting them to handle only high-priority tasks, thus avoiding multi-task preemption interference. The CPU isolation mechanism also prevents task scheduling and interrupt preemption from interfering with the sampling accuracy of the timed sampling task, thereby ensuring the real-time performance of SPI acquisition tasks and high-precision ADC (Analog-to-Digital Converter) data acquisition.

[0054] In step S220, in response to the interrupt generated by the high-precision timer, the interrupt handling function is used to start SPI data acquisition and the acquired data is stored in the circular buffer.

[0055] After the high-precision timer is bound to the dedicated CPU core, the high-precision timer will generate an interrupt based on the hardware clock trigger point (the time point of each trigger) set by absolute time. That is, when the time reaches the hardware clock trigger point, the APIC (Advanced Programmable Interrupt Controller) generates a hardware interrupt (Interrupt Request, IRQ) and sends it to the dedicated CPU core. The dedicated CPU core responds to the interrupt generated by the high-precision timer, uses the interrupt handling function to start SPI data acquisition, and stores the acquired data into a circular buffer.

[0056] The dedicated CPU core responds to interrupts generated by a high-precision timer, initiating SPI data acquisition using an interrupt handler function and storing the acquired data in a circular buffer. Alternatively, the dedicated CPU core may respond to an interrupt generated by a high-precision timer, interrupting the current task (or remaining idle if there is no task), bypassing the Linux kernel's standard SPI message queue, and directly jumping to a preset interrupt handler function (Interrupt Service Routine, ISR). This interrupt handler function then initiates SPI data acquisition and stores the acquired data in the circular buffer. By using a high-resolution timer (high-precision timer) to directly initiate data acquisition at precise time points, it eliminates the need for intermediate message queues or scheduling mechanisms, reducing system scheduling latency and improving the real-time performance of critical tasks, thereby reducing data transmission latency and jitter. By directly triggering transmission in this step, the scheduling latency is reduced from the μs level to the ns level, ensuring the stability of the target sampling period. The aforementioned target sampling period corresponds to the period of the actual sampling frequency.

[0057] Step S230: Read the data stored in the circular buffer and correct the read data to obtain SPI data that meets the sampling requirements.

[0058] The aforementioned corrections can be at least one of oversampling correction and outlier correction.

[0059] This embodiment isolates a dedicated CPU core, providing a clean environment for high-precision timer-triggered interrupts and SPI data acquisition. It uses high-precision timer-triggered interrupts for accurate sampling and corrects the sampled data to ensure the reliability of the data source. These three processes form a closed-loop optimization chain, jointly solving the problem of high-precision data acquisition that cannot be solved by single-point optimization.

[0060] Steps S210 to S230 above bind a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core. Within this dedicated CPU core, the high-precision timer runs, interrupts generated by the timer are handled, and the SPI data acquisition task is executed. SPI data is acquired according to a pre-configured trigger cycle, stored in a circular memory area, and read from the circular buffer. The read data is then corrected to obtain SPI data that meets the sampling requirements. By binding the high-precision timer and SPI data acquisition task to a dedicated CPU core and ensuring that the dedicated CPU core only runs the high-precision timer, handles interrupts generated by the timer, and executes critical real-time tasks such as SPI data acquisition, the SPI acquisition task is transformed into an actively executed task running in a dedicated, clean, and non-preemptive hardware environment. This fundamentally eliminates jitter caused by task scheduling and resource contention. This solves the problem of sampling timing jitter caused by Linux kernel scheduling in existing SPI data acquisition methods under high-frequency, high-precision scenarios.

[0061] In one embodiment, prior to step S210, the following steps are included:

[0062] Step S202: Through the CPU isolation mechanism of the Linux kernel, a dedicated CPU core is isolated from the multi-core CPU integrated in the system-on-a-chip.

[0063] The above-mentioned CPU isolation mechanism in the Linux kernel isolates a dedicated CPU core from the multi-core CPU integrated in the system-on-a-chip. This can be achieved by modifying kernel boot parameters, using the isolcpus instruction to exclude the target CPU core (dedicated CPU core) from the general scheduler, enabling a completely tick-free mode with nohz_full to eliminate clock interrupt interference, and using rcu_nocbs to offload the kernel synchronization mechanism callback task to other cores. Then, a dedicated cpuset partition is created and the target CPU core is assigned to it. At the same time, the default cpuset is configured to restrict ordinary processes to run on non-dedicated CPU cores. Finally, the real-time task process is bound to the isolated partition (dedicated CPU core).

[0064] This step uses the cpuset mechanism to build a resource isolation barrier at the scheduler level, isolating a dedicated CPU core from the multi-core CPU integrated in the system-on-a-chip. Then, the pre-built high-precision timer and SPI data acquisition tasks are fixedly bound to the dedicated CPU core in the multi-core CPU, providing a clean execution environment for the high-precision timer and SPI data acquisition tasks, providing a stable hardware foundation, and fundamentally eliminating the timing jitter problem caused by system scheduling and interrupt interference.

[0065] Specifically, in one embodiment, prior to step S210, the following is included:

[0066] Step S204: Determine the trigger period of the high-precision timer based on the sampling requirements.

[0067] The above sampling requirements can be considered as those for SPI data acquisition. Specifically, these may include the target sampling frequency, maximum jitter tolerance, oversampling factor, and dropout tolerance for SPI data acquisition. Based on these sampling requirements, the calculation process for determining the trigger period T of the high-precision timer is as follows:

[0068]

[0069] The above N is the oversampling factor for SPI data acquisition, and f is the target sampling frequency for SPI data acquisition.

[0070] For example, if the target sampling frequency for SPI data acquisition is 48kHz and the oversampling factor for SPI data acquisition is 2, then the actual sampling frequency is 96kHz, and the trigger period T of the high-precision timer is approximately 10.417µs.

[0071] Step S206: Based on the trigger period of the high-precision timer, configure the hardware timer in the system-on-a-chip to obtain the high-precision timer.

[0072] The aforementioned high-precision timer, based on its trigger period, is obtained by configuring the hardware timer within the system-on-a-chip. This can be achieved using a hardware clock source (e.g., a CPU timestamp counter (TSC)) and setting the trigger point based on absolute time (wall-clock time). This high-precision timer directly binds to the hardware clock using an absolute time mechanism, ensuring the hardware clock is independent of system scheduling. Furthermore, CPU isolation reduces scheduling interference, and the stable sampling interval guarantees consistent SPI data sampling rates, eliminating data point unevenness caused by system time drift.

[0073] Steps S204 to S206 above determine the trigger period of the high-precision timer based on sampling requirements. Then, based on the trigger period of the high-precision timer, the hardware timer in the system-on-a-chip is configured to obtain the high-precision timer. Through the design of the high-precision timer, the consistency of SPI data sampling frequency is ensured, and the problem of uneven data points caused by system time drift is eliminated.

[0074] In another embodiment, step S210 above, which binds the pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core, includes:

[0075] Step S212: During the initialization process, it is detected whether the process of the high-precision timer is running on the dedicated CPU core. If the process of the high-precision timer is not running on the dedicated CPU core, the process of the high-precision timer is migrated to the dedicated CPU core and locked on the dedicated CPU core.

[0076] Normally, high-precision timer processes are randomly assigned to CPU cores when created by the kernel. If this process is assigned to a non-isolated core (non-dedicated CPU core), it needs to migrate along with the high-precision timer process to avoid cross-core scheduling latency, ensuring the high-precision timer task permanently resides on a dedicated CPU core. The above-mentioned detection of whether the high-precision timer process is running on a dedicated CPU core can be achieved using the `smp_processor_id()` function. If the high-precision timer process is not running on a dedicated CPU core, migrating it to a dedicated CPU core can be done by calling the `smp_call_function_single()` function to force the migration to an isolated core (dedicated CPU core). Finally, locking the high-precision timer process to a dedicated CPU core can be achieved using the `set_cpus_allowed_ptr()` function. The determination of whether the high-precision timer process is running on a dedicated CPU core can be achieved by judging whether the kernel thread or driver process managing the high-resolution timer (such as the khrtimer thread in Linux) is on a dedicated CPU core. If the kernel thread or driver process managing the high-resolution timer is on a dedicated CPU core, then the high-precision timer process is determined to be running on a dedicated CPU core. If the kernel thread or driver process managing the high-resolution timer is not on a dedicated CPU core, then the high-precision timer process is determined to be running on a dedicated CPU core.

[0077] In this step, during initialization, it checks whether the high-precision timer process is running on a dedicated CPU core. If the high-precision timer process is not running on a dedicated CPU core, it migrates the high-precision timer process to the dedicated CPU core and locks it there. This prevents the operating system scheduler from migrating high-priority task processes to other cores (non-dedicated CPU cores), preventing high-priority task processes from jumping between cores due to load balancing algorithms, which could cause timing jitter. It ensures that the high-precision timer interrupt is always handled by the same core, avoiding the context switching overhead caused by migrating the high-precision timer interrupt between different cores, while maintaining the stability and predictability of interrupt response time. The dedicated CPU core provides a clean execution environment for the high-precision timer, free from interference from other tasks, ensuring strict consistency of sampling intervals, eliminating time drift, providing accurate isochronous intervals for data acquisition, guaranteeing signal integrity, reducing the difficulty of troubleshooting occasional performance problems caused by core migration, and preventing critical processes from being accidentally interfered with by system management tasks or user processes.

[0078] In one embodiment, prior to step S220, the following is included:

[0079] Step S218: In the Linux kernel space, dynamically allocate a physically contiguous circular buffer; the circular buffer has a fixed size and is a circular queue data structure.

[0080] The aforementioned size is fixed and can be the number of sampling points with a preset length. This preset number can be set based on specific needs, and this embodiment does not impose a specific limitation. The aforementioned circular buffer is represented in memory as a circular region with its ends connected. Data access is managed through two pointers (read pointer and write pointer). When the pointer reaches the end of the buffer, it automatically wraps back to the beginning, ensuring that the memory space is reused cyclically and avoiding frequent memory allocation and deallocation.

[0081] Specifically, the first-in-first-out (FIFO) operation using read and write pointers works as follows: when the buffer is full, new data overwrites the oldest data; when the buffer is empty, read operations wait for new data. Furthermore, the circular buffer described above supports efficient memory management (lock-free read / write operations or the use of lightweight synchronization mechanisms such as spinlocks), reducing CPU overhead.

[0082] This step, through the setting of a circular buffer, can efficiently store high-frequency sampled data, enabling the digital-to-analog converter to write sampled data into the buffer at a preset sampling frequency, avoiding data loss, and also decoupling producers and consumers.

[0083] In another embodiment, step S220, in response to an interrupt generated by a high-precision timer, initiates SPI data acquisition using an interrupt handling function and stores the acquired data into a circular buffer, including:

[0084] In step S222, in response to the interrupt generated by the high-precision timer, the Linux kernel standard SPI message queue is bypassed, and the transfer_one_message function is directly called in the interrupt handler to start SPI transmission, perform SPI data acquisition, and store the acquired data into a circular buffer.

[0085] The aforementioned Linux kernel standard SPI message queue can be considered an asynchronous transmission mechanism within the SPI subsystem, used to manage and schedule multiple SPI data transmission requests. Essentially, this Linux kernel standard SPI message queue is a request queue structure maintained by the kernel, responsible for sorting, buffering, and scheduling the execution of SPI transmission messages.

[0086] In response to an interrupt generated by a high-precision timer, the system bypasses the standard Linux kernel SPI message queue and directly calls the `transfer_one_message` function within the interrupt handler to initiate SPI transmission, acquire SPI data, and store the acquired data in a circular buffer. This means that when a high-precision timer generates an interrupt on a dedicated CPU core, the system does not follow the standard Linux data transmission path but instead directly performs the following operations within the interrupt handler: bypassing the standard kernel SPI message queue, directly calling the underlying driver function `transfer_one_message`, instructing the SoC's SPI controller to communicate with the external ADC sensor, read the sampled data, perform SPI transmission, and write the raw sampled data obtained from the SPI transmission into the circular buffer.

[0087] The aforementioned interrupt handler function, as a built-in interface provided by the Linux SPI subsystem (a native function of the open-source kernel), is defined in the kernel source code. Its core function is to initiate a single SPI transmission. This function itself is pre-compiled kernel core code, and interrupt signals only trigger its execution.

[0088] This step is completed in the interrupt context of a dedicated CPU core. The process can be as follows: when an interrupt is triggered, the CPU hardware mechanism will automatically switch the execution state to kernel mode and directly call the corresponding registered interrupt service routine. In this context, the SPI transmission startup and data processing are completed synchronously.

[0089] Further, in one embodiment, step S230 above, which involves reading data stored in the circular buffer and correcting the read data to obtain SPI data that meets the sampling requirements, includes:

[0090] Step S232: Read the data stored in the circular buffer.

[0091] Step S234: Perform target correction on the read data to obtain SPI data that meets the sampling requirements; target correction includes oversampling correction and outlier correction.

[0092] Steps S232 to S234 above involve reading the data stored in the circular buffer and performing oversampling correction and outlier correction on the read data to obtain SPI data that meets the sampling requirements. By correcting the read data, the collected data is corrected to be accurate data of the target sampling frequency.

[0093] In one embodiment, step S234, which involves target correction of the read data to obtain SPI data that meets the sampling requirements, includes:

[0094] Step S2342: Downsample the read data to obtain an initial sequence with the same frequency as the target sampling frequency.

[0095] The aforementioned downsampling of the read data to obtain an initial sequence with the same frequency as the target sampling frequency can be based on the oversampling factor of SPI data acquisition. Specifically, it can be based on the oversampling factor of SPI data acquisition to determine the target sampling frequency for downsampling the read data, and then using that target sampling frequency to sample the read data to obtain an initial sequence with the same frequency as the target sampling frequency.

[0096] For example, if the oversampling factor of SPI data acquisition is 2 and the actual sampling frequency is 96kHz, then the read data needs to be sampled at intervals (only one of every two points is kept, and one point is selected every other point) to obtain an initial sequence with a sampling frequency of 48kHz.

[0097] Step S2344: If the difference between adjacent points in the initial sequence is greater than or equal to a preset difference threshold, then the point located in the next position among the adjacent points is identified as an abnormal point.

[0098] The preset difference threshold can be determined based on the system noise level or experimental experience. This embodiment does not impose specific limitations, as long as the preset difference threshold can be used to determine outliers. In this embodiment, before performing step S2344, it is necessary to calculate the difference between adjacent points in the initial sequence. This calculation can be done by traversing each point in the initial sequence and calculating the absolute deviation between the next point and the previous point (i.e., the absolute value of the sampled value of the next point minus the sampled value of the previous point).

[0099] Step S2346: Based on the normal points in the initial sequence, calculate the correction value of the abnormal points using a curve fitting algorithm, and replace the abnormal points with the correction values ​​to obtain SPI data that meets the sampling requirements.

[0100] In this step, the above-mentioned calculation of the correction value of the outlier based on the normal points in the initial sequence using a curve fitting algorithm can be achieved by selecting a preset number of normal points before and after the outlier to be corrected, centered on the outlier. The correction value of the outlier is then calculated using a curve fitting algorithm based on these preset numbers of normal points. The preset number of normal points can be specifically set based on specific needs or circumstances; this embodiment does not impose a specific limitation. It should be noted that the preset number is sufficient to calculate the correction value of the outlier based on the selected normal points using a curve fitting algorithm. Alternatively, the calculation of the correction value of the outlier based on the preset number of normal points before and after the outlier can be achieved by using a least-squares optimization algorithm to determine the distribution trend approximating the outlier to be corrected, and then calculating the optimal estimate of the outlier's position through a curve fitting process. This optimal estimate is then determined as the correction value of the outlier.

[0101] Furthermore, when multiple consecutive outliers occur (e.g., three consecutive outliers), a cascaded correction strategy is employed to ensure reliability. This cascaded correction strategy may include the following steps: sequentially processing outliers from beginning to end; calculating correction values ​​for outliers based on normal points in the initial sequence using a curve fitting algorithm; and replacing the outliers with their correction values.

[0102] For example, consider consecutive outliers: point A, point B, and point C. Correction begins with the earliest outlier (marked as point A). When correcting point A: only the four closest normal points before and after point A are used (skipping intermediate outliers). Based on these eight normal points, a curve fitting algorithm is used to calculate the correction value for outlier A, and this correction value is then used to correct point A. After correction, the sequence state of point A is updated, and it is marked as a "normal point." If point A is a normal point after correction, the same correction method is used to correct points B and C sequentially.

[0103] In one embodiment, step S2346, based on the normal points in the initial sequence, calculates the correction value of the outlier points using a curve fitting algorithm, and replaces the outlier points with the correction values ​​to obtain SPI data that meets the sampling requirements, including:

[0104] Step S2: If the outlier is located at the boundary of the initial sequence, dynamically adjust the fitting interval of the curve fitting algorithm. Based on the normal points in the initial sequence, calculate the correction value of the outlier using the curve fitting algorithm, and replace the outlier with the correction value to obtain SPI data that meets the sampling requirements.

[0105] The fitting interval of the curve fitting algorithm described above can be used to estimate the number of normal points before the outlier to be corrected. If the outlier is located at the boundary of the initial sequence, the number of points preceding the outlier may be less than the preset number of normal points. In this case, fewer than the preset number of normal points can be selected. If there are no points preceding the outlier, only the nearest normal point following the outlier can be used for correction. The preset number can also be adjusted based on requirements. (The last two sentences are a repetition of the previous two and can be omitted.)

[0106] This step dynamically corrects outliers, eliminating sampling point errors caused by jitter and improving the signal-to-noise ratio of data acquisition.

[0107] The present embodiment will now be described and illustrated through preferred embodiments.

[0108] Figure 3 This is a flowchart of an SPI data acquisition method provided in a preferred embodiment of this application. Figure 3 As shown, the SPI data acquisition method includes the following steps:

[0109] Step S301: Through the CPU isolation mechanism of the Linux kernel, a dedicated CPU core is isolated from the multi-core CPU integrated in the system-on-a-chip. The dedicated CPU core is configured to exclusively run a high-precision timer, handle interrupts generated by the high-precision timer, and execute SPI data acquisition tasks.

[0110] Step S302: Based on the sampling requirements, determine the trigger period of the high-precision timer;

[0111] Step S303: Based on the trigger cycle of the high-precision timer, configure the hardware timer in the system-on-a-chip to obtain the high-precision timer; the high-precision timer is used to periodically generate interrupts in the dedicated CPU core according to the pre-configured trigger cycle; the high-precision timer is configured to absolute time trigger mode based on the hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency; the target sampling frequency is the sampling frequency corresponding to the sampling requirements;

[0112] Step S304: Bind the pre-built high-precision timer and SPI data acquisition task to the dedicated CPU core;

[0113] Step S305: In response to the interrupt generated by the high-precision timer, the interrupt handling function is used to start SPI data acquisition and the acquired data is stored in the circular buffer.

[0114] Step S306: Read the data stored in the circular buffer;

[0115] Step S307: Perform target correction on the read data to obtain SPI data that meets the sampling requirements; target correction includes oversampling correction and outlier correction.

[0116] Steps S301 to S307 above bind a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core. Within this dedicated CPU core, the high-precision timer runs, interrupts generated by the timer are handled, and the SPI data acquisition task is executed. SPI data is acquired according to a pre-configured trigger cycle, stored in a circular memory area, and read from the circular buffer. The read data is then corrected to obtain SPI data that meets the sampling requirements. By binding the high-precision timer and SPI data acquisition task to a dedicated CPU core and ensuring that the dedicated CPU core only runs the high-precision timer, handles interrupts generated by the timer, and executes critical real-time tasks such as SPI data acquisition, the SPI acquisition task is transformed into an actively executed task running in a dedicated, clean, and non-preemptive hardware environment. This fundamentally eliminates jitter caused by task scheduling and resource contention. This solves the problem of sampling timing jitter caused by Linux kernel scheduling in existing SPI data acquisition methods under high-frequency, high-precision scenarios.

[0117] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0118] Based on the same inventive concept, this embodiment also provides an SPI data acquisition device for implementing the above embodiments and preferred embodiments, which will not be repeated as already described. The terms "module," "unit," "subunit," etc., used below can refer to combinations of software and / or hardware that implement a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0119] In one embodiment, Figure 4 This is a structural block diagram of an SPI data acquisition device provided in an embodiment of this application, as shown below. Figure 4 As shown, this SPI data acquisition device is applied to a system-on-a-chip (SoC) integrating a multi-core CPU, and includes:

[0120] The task binding module 42 is used to bind a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core in a multi-core CPU. The high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle. The high-precision timer is configured to use an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency. The target sampling frequency is the sampling frequency corresponding to the sampling requirements. The dedicated CPU core is configured to exclusively run the high-precision timer, handle the interrupts generated by the high-precision timer, and execute the SPI data acquisition task.

[0121] The data acquisition module 44 is used to respond to the interrupt generated by the high-precision timer, start SPI data acquisition using the interrupt handling function, and store the acquired data into a circular buffer.

[0122] And a correction module 46, used to read the data stored in the circular buffer and correct the read data to obtain SPI data that meets the sampling requirements.

[0123] The aforementioned SPI data acquisition device binds a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core. Within this dedicated CPU core, the high-precision timer runs, interrupts generated by the timer are handled, and the SPI data acquisition task is executed. SPI data is acquired according to a pre-configured trigger cycle, stored in a circular memory area, and read from the circular buffer. The read data is then corrected to obtain SPI data that meets the sampling requirements. By binding the high-precision timer and SPI data acquisition task to a dedicated CPU core and ensuring that the dedicated CPU core only runs the high-precision timer, handles interrupts generated by the timer, and executes critical real-time tasks such as SPI data acquisition, the SPI acquisition task is transformed into an actively executed task running in a dedicated, clean, and non-preemptive hardware environment. This fundamentally eliminates jitter caused by task scheduling and resource contention. It solves the problem of sampling timing jitter caused by Linux kernel scheduling in existing SPI data acquisition methods under high-frequency, high-precision scenarios.

[0124] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.

[0125] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An SPI data acquisition method, applied to a system-on-a-chip integrating a multi-core CPU, characterized in that, The method includes: A pre-built high-precision timer and SPI data acquisition task are bound to a dedicated CPU core in the multi-core CPU. The high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle. The high-precision timer is configured to use an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency. The target sampling frequency is the sampling frequency corresponding to the sampling requirements. The dedicated CPU core is configured to exclusively run the high-precision timer, process the interrupts generated by the high-precision timer, and execute the SPI data acquisition task. In response to the interrupt generated by the high-precision timer, the interrupt handling function is used to start SPI data acquisition and the acquired data is stored in a circular buffer; The data stored in the circular buffer is read and corrected to obtain SPI data that meets the sampling requirements.

2. The SPI data acquisition method according to claim 1, characterized in that, Before binding the pre-built high-precision timer and SPI data acquisition tasks to a dedicated CPU core, the following steps are included: The dedicated CPU core is isolated from the multi-core CPU integrated in the system-on-a-chip through the CPU isolation mechanism of the Linux kernel.

3. The SPI data acquisition method according to claim 1, characterized in that, Before binding the pre-built high-precision timer and SPI data acquisition tasks to a dedicated CPU core, the following steps are included: Based on the sampling requirements, the trigger period of the high-precision timer is determined; Based on the trigger period of the high-precision timer, the hardware timer in the system-on-a-chip is configured to obtain the high-precision timer.

4. The SPI data acquisition method according to claim 1, characterized in that, The step of binding a pre-built high-precision timer and SPI data acquisition task to a dedicated CPU core includes: During initialization, it is detected whether the process of the high-precision timer is running on the dedicated CPU core. If the process of the high-precision timer is not running on the dedicated CPU core, the process of the high-precision timer is migrated to the dedicated CPU core and locked to the dedicated CPU core.

5. The SPI data acquisition method according to claim 1, characterized in that, Before initiating SPI data acquisition using the interrupt handler function in response to an interrupt generated by the high-precision timer, and storing the acquired data into the circular buffer, the process includes: Within the Linux kernel space, a physically contiguous circular buffer is dynamically allocated; the circular buffer has a fixed size and is a circular queue data structure.

6. The SPI data acquisition method according to claim 1, characterized in that, In response to an interrupt generated by the high-precision timer, the interrupt handler function is used to initiate SPI data acquisition, and the acquired data is stored in a circular buffer, including: In response to the interrupt generated by the high-precision timer, the Linux kernel standard SPI message queue is bypassed, and the transfer_one_message function is directly called in the interrupt handler to start SPI transmission, perform SPI data acquisition, and store the acquired data into the circular buffer.

7. The SPI data acquisition method according to claim 1, characterized in that, The step of reading data stored in the circular buffer and correcting the read data to obtain SPI data that meets the sampling requirements includes: Read the data stored in the circular buffer; The read data is corrected to meet the sampling requirements and the target correction is performed to obtain SPI data. The target correction includes oversampling correction and outlier correction.

8. The SPI data acquisition method according to claim 7, characterized in that, The step of performing target correction on the read data to obtain SPI data that meets the sampling requirements includes: The read data is downsampled to obtain an initial sequence with a frequency consistent with the target sampling frequency; If the difference between adjacent points in the initial sequence is greater than or equal to a preset difference threshold, then the point located in the next position among the adjacent points is identified as an abnormal point. Based on the normal points in the initial sequence, the correction values ​​of the abnormal points are calculated using a curve fitting algorithm, and the abnormal points are replaced with the correction values ​​to obtain SPI data that meets the sampling requirements.

9. The SPI data acquisition method according to claim 8, characterized in that, The process of calculating correction values ​​for outlier points based on normal points in the initial sequence using a curve fitting algorithm, and replacing the outlier points with these correction values ​​to obtain SPI data that meets the sampling requirements, includes: If an outlier is found to be on the boundary of the initial sequence, the fitting interval of the curve fitting algorithm is dynamically adjusted. Based on the normal points in the initial sequence, the correction value of the outlier is calculated by the curve fitting algorithm, and the outlier is replaced with the correction value to obtain SPI data that meets the sampling requirements.

10. An SPI data acquisition device, applied to a system-on-a-chip integrating a multi-core CPU, characterized in that, The device includes: A task binding module is used to bind a pre-built high-precision timer and an SPI data acquisition task to a dedicated CPU core in the multi-core CPU. The high-precision timer is used to periodically generate interrupts within the dedicated CPU core according to a pre-configured trigger cycle. The high-precision timer is configured to use an absolute time trigger mode based on a hardware clock source, and the frequency corresponding to the trigger cycle of the high-precision timer is higher than the target sampling frequency. The target sampling frequency is the sampling frequency corresponding to the sampling requirements. The dedicated CPU core is configured to exclusively run the high-precision timer, process the interrupts generated by the high-precision timer, and execute the SPI data acquisition task. The data acquisition module is used to respond to the interrupt generated by the high-precision timer, start SPI data acquisition using the interrupt handling function, and store the acquired data into a circular buffer. And a correction module, used to read the data stored in the circular buffer and correct the read data to obtain SPI data that meets the sampling requirements.

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