Discharging circuit, microcontroller system, vehicle-mounted controller and vehicle

Abstract

The invention provides a discharging circuit, a microcontroller system, a vehicle-mounted controller and a vehicle, the discharging circuit is connected with a power supply chip, and the discharging circuit comprises a chip state detection module and a discharging module; the detection end of the chip state detection module is connected with the enabling end of the power supply chip, the output end of the chip state detection module is connected with the control end of the discharge module, and the discharge module is connected between the voltage output end of the power supply chip and the ground. The chip state detection module is used for detecting the enabling state of the power supply chip, so that when the power supply chip is reset, the discharging module is used for discharging the output end of the power supply chip, so that related devices of the power supply chip are completely powered off, the correct power-on time sequence of the follow-up power supply chip is ensured, and meanwhile, in the non-reset state, the power supply chip is not powered off. If yes, discharging of the discharging module is not triggered, so that standby power consumption improvement caused by the discharging module is avoided.

Description

Technical Field

[0001] This invention relates to the field of controllers, and more particularly to a discharge circuit, a microcontroller system, an on-board controller, and a vehicle. Background Technology

[0002] In vehicle controllers, chips such as MCUs (Microcontroller Units) have strict power-on timing requirements. When the system control MCU is reset, the MCU performs a complete power-down and power-on restart. However, some components within the MCU may not be completely powered down during the power-down process, which causes changes in the power-on timing during the power-on process and leads to startup failure. To avoid this problem, existing technologies usually set up a discharge circuit to discharge the MCU during reset to ensure complete discharge. However, the setting of the discharge circuit increases the standby power consumption of the controller. Summary of the Invention

[0003] The main objective of this invention is to provide a discharge circuit, a microcontroller system, an on-board controller, and a vehicle, aiming to solve the problem of increased standby power consumption in existing discharge circuit designs.

[0004] To achieve the above objectives, the present invention provides a discharge circuit connected to a power supply chip. The discharge circuit includes a chip state detection module and a discharge module. The detection terminal of the chip state detection module is connected to the enable terminal of the power supply chip, and the output terminal of the chip state detection module is connected to the control terminal of the discharge module. The discharge module is connected between the voltage output terminal of the power supply chip and ground. Wherein: The chip status detection module is used to detect the enable signal of the power chip, and when the enable signal indicates a reset state, send a discharge signal to the discharge module, and when the enable signal indicates a non-reset state, stop sending the discharge signal to the discharge module. The discharge module is used to perform a discharge operation when the discharge signal is received, so as to connect the voltage output terminal of the power chip to ground.

[0005] Optionally, the chip status detection module includes a transistor, a first resistor, and a second resistor; wherein: The base of the transistor is connected to the enable terminal of the power chip through the first resistor. The base of the transistor is also grounded through the second resistor. The emitter of the transistor is grounded. The collector of the transistor is connected to the control terminal of the discharge module as the output terminal of the chip status detection module.

[0006] Optionally, the discharge module includes a discharge control unit and a discharge unit; the control terminal of the discharge control unit serves as the control terminal of the discharge module and is connected to the output terminal of the chip status detection module; the output terminal of the discharge control unit is connected to the control terminal of the discharge unit; and the discharge unit is connected between the voltage output terminal of the power chip and ground; wherein: The discharge control unit is used to control the discharge unit to perform a discharge operation when the discharge signal is received.

[0007] Optionally, the discharge control unit includes a diode, a third resistor, a fourth resistor, a fifth resistor, and a first capacitor; wherein: The positive terminal of the diode is connected to the output terminal of the chip status detection module as the control terminal of the discharge control unit. The positive terminal of the diode is also connected to the voltage output terminal of the power chip through the third resistor. The negative terminal of the diode is grounded through the fourth resistor and the first capacitor. The negative terminal of the diode is connected to the first end of the fifth resistor. The second end of the fifth resistor is connected to the control terminal of the discharge unit as the output terminal of the discharge control unit.

[0008] Optionally, the time it takes for the first capacitor to drop from its maximum voltage value to the conduction threshold of the discharge unit is greater than the target discharge time of the power chip; the target discharge time is twice the discharge time constant of the output terminal of the power chip.

[0009] Optionally, the discharge control unit includes a sixth resistor and a seventh resistor, wherein: The first end of the sixth resistor is connected to the output end of the chip status detection module as the control end of the discharge control unit. The first end of the sixth resistor is connected to the power supply through the seventh resistor. The second end of the sixth resistor is connected to the control end of the discharge unit as the output end of the discharge control unit.

[0010] Optionally, the discharge unit includes a switching transistor and an eighth resistor; wherein: The gate of the switching transistor is connected to the output terminal of the discharge control unit as the control terminal of the discharge unit. The source of the switching transistor is grounded, and the drain of the switching transistor is connected to the control terminal of the discharge unit through the eighth resistor.

[0011] In addition, to achieve the above objectives, the present invention also provides a microcontroller system, the microcontroller system including a power supply chip and a discharge circuit as described above.

[0012] In addition, to achieve the above objectives, the present invention also provides an in-vehicle controller, which includes the microcontroller system described above.

[0013] In addition, to achieve the above objectives, the present invention also provides a vehicle, the vehicle including the vehicle controller described above.

[0014] This invention proposes a discharge circuit, a microcontroller system, an on-board controller, and a vehicle. The discharge circuit is connected to a power supply chip and includes a chip status detection module and a discharge module. The detection terminal of the chip status detection module is connected to the enable terminal of the power supply chip, and the output terminal of the chip status detection module is connected to the control terminal of the discharge module. The discharge module is connected between the voltage output terminal of the power supply chip and ground. Specifically, the chip status detection module detects the enable signal of the power supply chip and sends a discharge signal to the discharge module when the enable signal indicates a reset state, and stops sending the discharge signal to the discharge module when the enable signal indicates a non-reset state. The discharge module performs a discharge operation upon receiving the discharge signal to connect the voltage output terminal of the power supply chip to ground. The enable status of the power chip is detected by the chip status detection module. When the power chip is reset, the discharge module discharges the output terminal of the power chip to completely de-energize the related components of the power chip, thereby ensuring the correct power-on sequence of the power chip in the future. At the same time, the discharge module is not triggered when the power chip is not reset, so as to avoid the increase in standby power consumption caused by the discharge module. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a functional block diagram of an embodiment of the discharge circuit of the present invention; Figure 2 This is a circuit structure diagram of an embodiment of the discharge circuit of the present invention; Figure 3 This is a circuit diagram of another embodiment of the discharge circuit of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0018] Explanation of icon numbers: Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0022] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0023] This invention provides a discharge circuit applied in a microcontroller system. Please refer to [link / reference]. Figure 1 , Figure 1 This is a functional block diagram of an embodiment of the discharge circuit of the present invention. In this embodiment, the discharge circuit is connected to the power chip U1, and the discharge circuit includes a chip status detection module 100 and a discharge module 200; the detection terminal of the chip status detection module 100 is connected to the enable terminal of the power chip U1, the output terminal of the chip status detection module 100 is connected to the control terminal of the discharge module 200, and the discharge module 200 is connected between the voltage output terminal of the power chip U1 and ground; wherein: The chip status detection module 100 is used to detect the enable signal of the power chip U1, and when the enable signal indicates a reset state, it sends a discharge signal to the discharge module 200, and when the enable signal indicates a non-reset state, it stops sending the discharge signal to the discharge module 200. The discharge module 200 is used to perform a discharge operation when the discharge signal is received, so as to connect the voltage output terminal of the power chip U1 to ground.

[0024] Power chip U1 is a chip within the MCU (Microcontroller Unit) system used to output a stable voltage VCC. Power chip U1 is powered by a power supply and outputs the voltage required by subsequent loads, such as providing power to the MCU's RTC (Real-Time Clock) domain. The power supply can be configured according to actual needs; for example, the power supply can be a linear regulator from the vehicle's infotainment system, and the voltage provided by the power supply is VDD.

[0025] The enable pin of power chip U1 is used to control the operating state of power chip U1. The enable pin of power chip U1 is connected to the reset chip. When power chip U1 is powered normally, the enable pin of power chip U1 receives a high-level signal to enable power chip U1. When it is necessary to control the power chip U1 to be reset, the reset chip outputs a low-level enable signal to the enable pin of power chip U1 to reset power chip U1. After a preset reset time, it resumes outputting a high-level enable signal to the enable pin of power chip U1 to complete the reset operation. The specific length of the preset reset time can be set according to actual needs, such as 10~20ms.

[0026] The chip status detection module 100 detects the enable signal at the enable terminal of the power chip U1. Since the enable terminal of the power chip U1 receives different enable signals from the reset chip in different states, the chip status detection module 100 can determine the reset state of the power chip U1 based on the enable signal. Specifically, when the chip status detection module 100 detects that the enable signal is high, it determines that the power chip U1 is operating normally, and when it detects that the enable signal is low, it determines that the power chip U1 is performing a reset.

[0027] When the power chip U1 is reset, in order to ensure that the power chip U1 can be completely powered down within the reset cycle, such as when the residual voltage is less than 10% VCC, the chip status detection module 100 sends a discharge signal to the discharge module 200. When the discharge module 200 receives the discharge signal, it turns on the voltage output terminal of the power chip U1 to ground to achieve the discharge of the voltage output terminal of the power chip U1. It can be understood that there are actively set capacitors and parasitic capacitors on the voltage output terminal of the power chip U1. When the voltage output terminal of the power chip U1 is grounded, the output capacitors discharge to ground, thereby avoiding incomplete discharge caused by residual charge in the output capacitors.

[0028] When the power chip U1 is in a non-reset state, there is no need to discharge the voltage output terminal of the power chip U1 through the discharge module 200. At this time, in order to avoid the increase in power consumption caused by the discharge module 200, the discharge module 200 will disconnect the voltage output terminal of the power chip U1 from the ground. The non-reset state refers to the other states of the power chip U1 besides the reset state, such as normal operation state, standby state, etc.

[0029] The implementation process of the discharge circuit is explained below; When the power chip U1 is running normally, the chip status detection module 100 detects that the enable terminal of the power chip U1 is at a high level. The chip status detection module 100 does not send a discharge signal to the discharge module 200. The discharge module 200 disconnects the voltage output terminal of the power chip U1 from the ground and does not generate power consumption. When the power chip U1 is triggered to reset and lose power, the chip status detection module 100 detects that the enable terminal of the power chip U1 is at a low level. The chip status detection module 100 sends a discharge signal to the discharge module 200. The discharge module 200 connects the voltage output terminal of the power chip U1 to ground, and the voltage output terminal of the power chip U1 is connected to ground to complete the discharge. After the power chip U1 is reset and restarted, the chip status detection module 100 detects that the enable terminal of the power chip U1 is at a high level. The chip status detection module 100 does not send a discharge signal to the discharge module 200. The discharge module 200 disconnects the voltage output terminal of the power chip U1 from the ground and does not generate power consumption.

[0030] In this embodiment, the enable state of the power chip U1 is detected by the chip state detection module 100. This allows the power chip U1 to be discharged by the discharge module 200 when it is reset, so that the related devices of the power chip U1 are completely powered off, thereby ensuring the correct power-on sequence of the power chip U1. At the same time, in the non-reset state, the discharge module 200 is not triggered to avoid the increase in standby power consumption caused by the discharge module 200.

[0031] Furthermore, the chip status detection module 100 includes a transistor Q1, a first resistor R1, and a second resistor R2; wherein: The base of transistor Q1 is connected to the enable terminal of power chip U1 through the first resistor R1. The base of transistor Q1 is also grounded through the second resistor R2. The emitter of transistor Q1 is grounded. The collector of transistor Q1 is connected to the control terminal of discharge module 200 as the output terminal of chip status detection module 100.

[0032] Transistor Q1 is an NPN type transistor.

[0033] The second resistor R2 is a pull-down resistor, used to clamp the base of transistor Q1 to a low level when there is no high-level signal at the base of transistor Q1.

[0034] When the enable pin of the power chip U1 is high, the transistor Q1 is turned on, and the collector of the transistor Q1 is grounded through the transistor Q1, so the collector of the transistor Q1 is at a low level. When the enable pin of power chip U1 is low, transistor Q1 is turned off, and the collector of transistor Q1 is not grounded through transistor Q1, so the collector of transistor Q1 appears to be high.

[0035] Therefore, the collector of transistor Q1 can follow the level change of the enable terminal of power chip U1. Thus, transistor Q1 can output a corresponding signal to discharge module 200 based on whether power chip U1 is reset, so as to control discharge module 200 to perform discharge operation based on the operating state of power chip U1.

[0036] When the power chip U1 is running normally, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, the collector of the transistor Q1 shows a low level, indicating that the discharge module 200 does not discharge. When the power chip U1 is triggered to reset and power off, the low level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1. The transistor Q1 is turned off, and the collector of the transistor Q1 is not grounded through the transistor Q1. The collector of the transistor Q1 is high, indicating that the discharge module 200 is discharging. After the power chip U1 is reset and restarted, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, the collector of the transistor Q1 is low level, indicating that the discharge module 200 does not discharge.

[0037] In this embodiment, by setting the transistor Q1, the discharge operation of the discharge module 200 can be accurately controlled based on the operating state of the power chip U1.

[0038] Further, the discharge module 200 includes a discharge control unit and a discharge unit; the control terminal of the discharge control unit serves as the control terminal of the discharge module 200 and is connected to the output terminal of the chip status detection module 100; the output terminal of the discharge control unit is connected to the control terminal of the discharge unit; and the discharge unit is connected between the voltage output terminal of the power chip U1 and ground; wherein: The discharge control unit is used to control the discharge unit to perform a discharge operation when the discharge signal is received.

[0039] The discharge control unit specifically controls the discharge status of the discharge unit; the discharge unit, based on the control of the discharge control unit, specifically controls the connection between the output terminal of the power chip U1 and ground.

[0040] It is understandable that the discharge operation of the discharge unit needs to ensure that the output terminal charge of the power chip U1 is completely discharged. Therefore, in this embodiment, a discharge control unit is specifically set to control the discharge unit so as to execute the discharge conditions that meet the complete discharge.

[0041] Furthermore, the discharge control unit includes a diode D1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first capacitor C1; wherein: The positive terminal of diode D1 is connected to the output terminal of the chip status detection module 100 as the control terminal of the discharge control unit. The positive terminal of diode D1 is also connected to the voltage output terminal of the power chip U1 through the third resistor R3. The negative terminal of diode D1 is grounded through the fourth resistor R4 and the first capacitor C1. The negative terminal of diode D1 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the control terminal of the discharge unit as the output terminal of the discharge control unit.

[0042] If the chip status detection module 100 outputs a low level, then the positive terminal of diode D1 is at a low level, the voltage across diode D1 is less than the forward voltage of diode D1, diode D1 is cut off, the voltage across the first capacitor C1 is 0, and the voltage output to the control terminal of the discharge unit is 0. If the chip status detection module 100 switches to a high output level, the positive terminal of diode D1 is connected to the voltage output terminal of power chip U1 through the third resistor R3. The voltage at the positive terminal of diode D1 is the discharge voltage of the output capacitor of power chip U1. Since the negative terminal of diode D1 is at 0 potential, the voltage across diode D1 reaches the forward voltage of diode D1, diode D1 conducts, and the first capacitor C1 begins to charge. When the voltage of the first capacitor C1 is charged to the output capacitor voltage minus the voltage drop of diode D1, diode D1 is reverse-biased and cut off, and the first capacitor C1 stops charging. Then the first capacitor C1 begins to discharge through the fourth resistor R4. The voltage across the first capacitor C1 is the control signal output to the discharge unit.

[0043] Diode D1 is used to prevent the discharge circuit of the first capacitor C1 from being interfered with by other circuits after reverse cutoff.

[0044] Furthermore, the discharge unit includes a switching transistor T1 and an eighth resistor R8; wherein: The gate of the switching transistor T1 is connected to the output terminal of the discharge control unit as the control terminal of the discharge unit. The source of the switching transistor T1 is grounded, and the drain of the switching transistor T1 is connected to the control terminal of the discharge unit through the eighth resistor R8.

[0045] The specific type of the switch T1 can be set according to actual needs. In this embodiment, the switch T1 is an NMOS transistor for example.

[0046] When the gate voltage of switch T1 reaches the threshold voltage, switch T1 is turned on, connecting the output terminal of power chip U1 to ground; when the gate voltage of switch T1 is less than the threshold voltage, switch T1 is turned off, disconnecting the output terminal of power chip U1 from ground.

[0047] During the charging process of the first capacitor C1, when the voltage of the first capacitor C1 is charged to the threshold voltage of the switching transistor T1, the gate voltage of the switching transistor T1 reaches the threshold voltage, the switching transistor T1 is turned on, and the first capacitor C1 continues to charge. When the voltage of the first capacitor C1 is charged to V2 = output capacitor voltage V1 - diode D1 voltage drop VF, the first capacitor C1 stops charging and begins to discharge through the fourth resistor R4. When the voltage of the first capacitor C1 is discharged to a level lower than the threshold voltage of the switching transistor T1, the switching transistor T1 is turned off. That is, the switching transistor T1 is continuously turned on during the period from when the voltage of the first capacitor C1 is charged to the threshold voltage to when it is discharged to a level lower than the threshold voltage, so that the output terminal of the power chip U1 discharges to ground.

[0048] Furthermore, the time it takes for the first capacitor C1 to drop from its maximum voltage value to the conduction threshold of the discharge unit is greater than the target discharge time of the power chip U1; the target discharge time is twice the discharge time constant of the output terminal of the power chip U1.

[0049] It is understandable that the output terminal of power chip U1 needs to discharge for a certain period of time to achieve complete discharge. Specifically, the discharge must be at least twice the discharge time constant to ensure complete discharge. The discharge time constant τ = C4 × R8, where C4 is the output capacitance of power chip U1, and R8 is the equivalent resistance between the output terminal of power chip U1 and ground. The specific value of R8 can be set according to actual needs, such as between 5 and 15KΩ. When VCC is 3.3V, the discharge current of the output terminal of power chip U1 is VCC / Rz≈0.22~0.66mA.

[0050] Therefore, in order to ensure that the power chip U1 is fully discharged, the conduction time of the switch T1 needs to be at least twice the discharge time constant; and the conduction time of the switch T1 is determined by the voltage across the first capacitor C1; as mentioned above, the switch T1 is continuously turned on during the period from when the voltage of the first capacitor C1 is charged to reach the threshold voltage to when it is discharged to below the threshold voltage. Therefore, during the charging-discharging process, the time for the voltage of the first capacitor C1 to reach the threshold voltage needs to be at least twice the discharge time constant.

[0051] The discharge time constant of the first capacitor C1 is determined by the capacitance of the first capacitor C1 itself and the resistance of the fourth resistor R4. At the same time, based on the discharge constant of the first capacitor C1, the time from the threshold voltage of the switch T1 to V2 is calculated plus the time from V2 to the threshold voltage of the switch T1. This gives the duration for which the first capacitor C1 can turn on the switch T1 under the action of the fourth resistor R4. Thus, we can reverse the process after determining that the conduction time of the switch T1 needs to be at least twice the discharge time constant, and then determine the values ​​of the first capacitor C1 and the fourth resistor R4.

[0052] The overall process of this embodiment is described below: When the power chip U1 is operating normally, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, and the collector of the transistor Q1 outputs a low level; at this time, the anode of the diode D1 is at a low level, the voltage across the diode D1 is less than the forward voltage of the diode D1, the diode D1 is turned off, the voltage across the first capacitor C1 is 0, the gate voltage of the switching transistor T1 is 0, the switching transistor T1 is turned off, and the output terminal of the power chip U1 is not grounded; When power chip U1 is triggered and reset, the low level at the enable terminal of power chip U1 is transmitted to the base of transistor Q1 through the first resistor R1, turning off transistor Q1. The collector of transistor Q1 is not grounded through transistor Q1. The anode of diode D1 is connected to the voltage output terminal of power chip U1 through the third resistor R3. The voltage at the anode of diode D1 is the discharge voltage of the output capacitor of power chip U1. Since the cathode of diode D1 is at 0 potential, the voltage across diode D1 reaches the forward voltage of diode D1, turning it on and starting to charge the first capacitor C1. The voltage of the first capacitor C1 is charged to... When the threshold voltage of switch T1 is reached, the gate voltage of switch T1 reaches the threshold voltage, switch T1 is turned on, and the output terminal of power chip U1 is grounded for discharge. When the voltage of the first capacitor C1 is charged to the output capacitor voltage minus the voltage drop of diode D1, diode D1 is reverse-biased and cut off, and the first capacitor C1 stops charging. Then the first capacitor C1 starts discharging through the fourth resistor R4. After the power chip U1 is fully discharged, when the voltage of the first capacitor C1 is discharged to a level lower than the threshold voltage of switch T1, switch T1 is turned off, the output terminal of power chip U1 is not grounded, and the discharge stops. The first capacitor C1 continues to discharge until the first capacitor C1 is fully discharged.

[0053] After the power chip U1 is reset and powered on, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, and the collector of the transistor Q1 outputs a low level; at this time, the anode of the diode D1 is at a low level, the voltage across the diode D1 is less than the forward voltage of the diode D1, the diode D1 is turned off, the voltage across the first capacitor C1 is 0, the gate voltage of the switching transistor T1 is 0, the switching transistor T1 is turned off, and the output terminal of the power chip U1 is not grounded.

[0054] Furthermore, the discharge control unit includes a sixth resistor R6 and a seventh resistor R7, wherein: The first end of the sixth resistor R6 is connected to the output end of the chip status detection module 100 as the control end of the discharge control unit. The first end of the sixth resistor R6 is connected to the power supply through the seventh resistor R7. The second end of the sixth resistor R6 is connected to the control end of the discharge unit as the output end of the discharge control unit.

[0055] In this embodiment, another configuration of the discharge control unit is provided.

[0056] The seventh resistor, R7, serves as a pull-up resistor.

[0057] It should be noted that in this embodiment, the voltage provided to the discharge control unit is supplied by a power supply; while in the previous embodiment, the voltage provided to the discharge control unit was supplied by the output terminal of the power chip U1. Since the previous embodiment included a charging and discharging circuit composed of the first capacitor C1, the residual charge at the output terminal of the power chip U1 was sufficient to provide the charging voltage when the first capacitor C1 was charging. Even after the voltage at the output terminal of the power chip U1 decreased due to discharge, the first capacitor C1, having completed charging, could still maintain the conduction of the switch T1. In this embodiment, however, the voltage is directly supplied to the discharge unit through the sixth resistor R6, thus requiring a stable power supply voltage to maintain the conduction of the switch T1. Obviously, the output terminal of the power chip U1 cannot provide a stable power supply voltage. Therefore, to realize the function of the discharge control unit, a power supply needs to be connected to provide a stable power supply voltage. This embodiment requires a power supply connection compared to the previous embodiment, thus limiting its application scenarios. In contrast, the previous embodiment was constructed based on the output terminal of the power chip U1, thus enabling its application in scenarios where the power chip U1 is present, expanding its application scope.

[0058] If the chip status detection module 100 outputs a low level, then the first end of the sixth resistor R6 is grounded, and the voltage output by the sixth resistor R6 to the control terminal of the discharge unit is 0. If the chip status detection module 100 outputs a high level, the first end of the sixth resistor R6 is connected to the power supply through the seventh resistor R7. The power supply voltage is transmitted to the discharge unit through the seventh resistor R7 and the sixth resistor R6, making the discharge unit conduct.

[0059] The overall process of this embodiment is described below: When the power chip U1 is operating normally, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, and the collector of the transistor Q1 outputs a low level; at this time, the first end of the sixth resistor R6 is grounded, the gate voltage of the switch T1 is 0, the switch T1 is turned off, and the output terminal of the power chip U1 is not grounded; When the power chip U1 is triggered to reset and power off, the low level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned off, the collector of the transistor Q1 is not grounded through the transistor Q1, the first end of the sixth resistor R6 is connected to the power supply through the third resistor R3, the power supply voltage is transmitted to the gate of the switching transistor T1 through the seventh resistor R7 and the sixth resistor R6, the switching transistor T1 is turned on, and the output terminal of the power chip U1 is grounded for discharge; After the power chip U1 is reset and restarted, the high level of the enable terminal of the power chip U1 is transmitted to the base of the transistor Q1 through the first resistor R1, the transistor Q1 is turned on, the collector of the transistor Q1 is grounded through the transistor Q1, and the collector of the transistor Q1 outputs a low level; at this time, the first end of the sixth resistor R6 is grounded, the gate voltage of the switching transistor T1 is 0, the switching transistor T1 is turned off, and the output terminal of the power chip U1 is not grounded.

[0060] The overall principle of this application is explained below: The power chip U1 outputs voltage VCC to the RTC domain of the subsequent MCU. When the MCU is reset, the external reset chip pulls the MCU reset interface MCU_RST low. The MCU Power Control, which controls the reset signal output of the power chip U1, is set to low by default. After the reset, MCU_RST is pulled high, and the MCU Power Control outputs a high level after a delay inside the reset chip, controlling the power supply of all external MCUs to be turned on. During the reset period, the external power supply voltage of the MCU must drop to the threshold range in the datasheet to ensure the power-on sequence of the MCU to start normally.

[0061] The charging and discharging time constant of a capacitor is τ = RC.

[0062] For a capacitor C powered by a power source Vu, and a resistor R connected in parallel with the capacitor C, the power source Vu charges the capacitor C through the resistor R. V0 is the initial voltage value across the capacitor, Vu is the voltage value of the capacitor after it is fully charged, and Vt is the voltage value across the capacitor at any time t. Then, the following calculation formula can be obtained:

[0063] If the initial voltage across the capacitor is 0, the formula can be simplified to:

[0064] As can be seen from the above formula, since the exponent value can only approach 0 infinitely, but will never equal 0, it takes an infinite amount of time for the capacitor to be fully charged.

[0065] When fully filled, Vt approaches E, and time is infinite; When t=τ, the capacitor voltage is 0.63E; When t=2τ, the capacitor voltage is 0.86E; When t=3τ, the capacitor voltage is 0.95E; When t=4τ, the capacitor voltage is 0.98E; When t=5τ, the capacitor voltage is 0.99E; It is evident that the charging process is essentially complete after 5 t.

[0066] When the capacitor is fully charged, and the power supply Vu is short-circuited, the capacitor C will discharge through R. Therefore, at any time t, the voltage across the capacitor is:

[0067] The voltage across the capacitor is 0.63 times the power supply voltage. During discharge, after a time constant τ, the voltage across the capacitor drops to 0.37 times the power supply voltage.

[0068] When t=τ, the capacitor voltage is 0.37E; When t=2τ, the capacitor voltage is 0.14E; When t=3τ, the capacitor voltage is 0.05E; When t=4τ, the capacitor voltage is 0.02E; When t=5τ, the capacitor voltage is 0.01E; It is evident that the discharge process essentially ends after 5 days.

[0069] See Figure 2 In one embodiment, VDD is the power supply, such as the linear regulator in the vehicle's infotainment system that provides a constant voltage to power the power chip U1. SYS_EN is the enable terminal of the power chip U1. When SYS_EN is high, the output terminal of the power chip U1 outputs the voltage VCC. Conversely, when SYS_EN is low, the VCC output is turned off.

[0070] 1. MCU system normal operation / sleep state - MCU_RST set high; Power supply circuit status analysis: VDD is the constant supply voltage, SYS_EN is the enable signal output by the MCUPowerControl of the reset chip, which is currently at a high level. Therefore, the power chip U1 normally outputs VCC=3.3V; the eleventh resistor R11 is the detection resistor of the detection pin of the power chip U1; the third capacitor C3 is the input capacitor of VDD; the ninth resistor R9 is the input resistor of the enable signal; the tenth resistor R10 and the second capacitor C2 constitute the enable signal RC circuit; the eighth resistor R8 is the equivalent resistance of the VCC discharge circuit.

[0071] Discharge circuit state analysis: SYS_EN is in a high level state, so NPN transistor Q1 is in a saturated conduction state. The third resistor R3 is connected to ground through transistor Q1. At this time, V1 is 0V. The resistance of the third resistor R3 is usually set between 5K and 15KΩ. V1 and V2 are both 0V at this time. Switch T1 is in the off state at this time, so VCC does not discharge to ground and there is no additional static current consumption.

[0072] 2. MCU System Reset - At this time, MCU_RST is set low. The MCU reset time is controlled by an external reset chip, and is usually around 10-20ms. Power circuit status analysis: VDD is the constant voltage provided. SYS_EN is at a low level at this time. The power chip U1 stops outputting voltage VCC. However, due to the influence of the downstream energy storage device capacitor, i.e., the output capacitor C4, the VCC voltage will not immediately drop to 0V.

[0073] Discharge circuit status analysis: 1. Analysis of the state of the first capacitor C1: During the charging phase of the first capacitor C1, when SYS_EN is low, the power chip U1 stops outputting voltage, and the VCC voltage is the discharge voltage of the charge stored in the fourth capacitor C4. When SYS_EN is low, the transistor Q1 is cut off, and VCC charges the first capacitor C1 through the third resistor R3 and the diode D1; During the discharge phase of the first capacitor C1, when the voltage across the first capacitor C1 is V2 = V1 - VF, charging stops. At this time, diode D1 is reverse-biased and cut off. Then, the fourth resistor R4 is connected in series with the first capacitor C1 to discharge.

[0074] 2. Analysis of the state of switch T1: When the first capacitor C1 is charged to the conduction threshold VGSth of switch T1, switch T1 is turned on, and VCC releases the residual charge of the fourth capacitor C4 to ground. When the discharge voltage of the first capacitor C1 is lower than the threshold VGSth, switch T1 is turned off, and the discharge path of VCC to ground is closed.

[0075] 3. Design Considerations: The capacitance value of the fourth capacitor C4 on the VCC power domain needs to be fully calculated. The VCC discharge time constant τ1 = C4 × R8. The VCC discharge time t1 must at least satisfy t1 > 2τ to ensure complete discharge. Therefore, the conduction time of the switching transistor T1 must be greater than the VCC discharge time t1. Note that the selection requirement for the switching transistor T1 is that the threshold voltage of VGSth should be 1 / 3 VCC. When V2 reaches the threshold of VGSth, VCC discharges to ground. The on-time t2 of switch T1: The time for V2 to rise from VGSth to Vmax = V1 - VF + the time for Vmax to fall back to VGSth; The time it takes for V2 to rise from VGSth to Vmax is the same as the time it takes for the first capacitor C1 to charge from VGSth to Vmax. This can be calculated by applying the charging and discharging time constants in combination with the values ​​of the first capacitor C1 and the fourth resistor R4. Similarly, the time it takes for Vmax to fall from VGSth is calculated.

[0076] Based on the first capacitor C1 and the fourth resistor R4, it is necessary to control the conduction time of the switch T1 in order to determine the parameter τ2=R4×C4; The function of diode D1 is to reverse cut off when V2 = V1 - VF, ensuring that the discharge circuit of the first capacitor C1 and the fourth resistor R4 is not interfered with by other circuits.

[0077] 3. MCU System Reset - At this time, MCU_RST is set low for a delay of approximately 10-20ms before being pulled high. Power circuit status analysis: VDD is constantly powered, SYS_EN outputs a high level after a delay of about 10-20ms, and the power chip U1 outputs VCC normally.

[0078] Discharge circuit state analysis: Transistor Q1 is in saturation conduction state at this time, and switch T1 is in cutoff state at this time, so VCC does not discharge to ground and there is no additional static current consumption.

[0079] The above analysis shows that when VCC is fully discharged and the residual voltage is <10%VCC, the normal power-on timing of the MCU can be met.

[0080] See Figure 3 The implementation principle of another embodiment: 1. MCU system normal operation / sleep state - MCU_RST set high; Power circuit status analysis: SYS_EN is the enable signal output by the MCUPowerControl of the reset chip. At this time, it is in a high level state, so the power chip U1 normally outputs VCC=3.3V.

[0081] Discharge circuit state analysis: This embodiment eliminates the charging and discharging design of the fourth resistor R4 and the first capacitor C1, and uses constant voltage VDD as the pull-up power supply for the switch T1. This allows for real-time control of the switch T1. When SYS_EN is high, transistor Q1 is turned on, and switch T1 is turned off. There is no additional static current consumption.

[0082] 2. MCU system reset - At this time, MCU_RST is set low for about 10-20ms; Power circuit status analysis: VDD is constantly powered, SYS_EN is at a low level, and power chip U1 stops outputting VCC.

[0083] Discharge circuit status analysis: When SYS_EN is low, transistor Q1 is cut off, switch T1 is turned on, and VCC discharges rapidly through switch T1.

[0084] The limitation of this embodiment is that the switching transistor T1 must use a constantly powered pull-up power supply, which restricts the application scenarios.

[0085] This invention also protects a microcontroller system, which includes a power supply chip U1 and a discharge circuit. The structure of the discharge circuit can be referred to in the above embodiment, and will not be repeated here. Accordingly, since the microcontroller system of this embodiment adopts the above-described discharge circuit technical solution, the microcontroller system has all the beneficial effects of the above-described discharge circuit.

[0086] This invention also protects an in-vehicle controller, which includes a microcontroller system. The structure of the microcontroller system can be referred to in the above embodiments, and will not be repeated here. Accordingly, since the in-vehicle controller of this embodiment adopts the technical solution of the above-described microcontroller system, it possesses all the beneficial effects of the aforementioned microcontroller system.

[0087] This invention also protects a vehicle including an on-board controller. The structure of the discharge circuit can be referred to in the above embodiments, and will not be repeated here. Accordingly, since the vehicle of this embodiment adopts the above-described on-board controller technical solution, the vehicle has all the beneficial effects of the above-described on-board controller.

[0088] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0089] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A discharge circuit, characterized in that, The discharge circuit is connected to the power supply chip, and includes a chip status detection module and a discharge module; the detection terminal of the chip status detection module is connected to the enable terminal of the power supply chip, the output terminal of the chip status detection module is connected to the control terminal of the discharge module, and the discharge module is connected between the voltage output terminal of the power supply chip and ground; wherein: The chip status detection module is used to detect the enable signal of the power chip, and when the enable signal indicates a reset state, send a discharge signal to the discharge module, and when the enable signal indicates a non-reset state, stop sending the discharge signal to the discharge module. The discharge module is used to perform a discharge operation when the discharge signal is received, so as to connect the voltage output terminal of the power chip to ground.

2. The discharge circuit as described in claim 1, characterized in that, The chip status detection module includes a transistor, a first resistor, and a second resistor; wherein: The base of the transistor is connected to the enable terminal of the power chip through the first resistor. The base of the transistor is also grounded through the second resistor. The emitter of the transistor is grounded. The collector of the transistor is connected to the control terminal of the discharge module as the output terminal of the chip status detection module.

3. The discharge circuit as described in claim 1, characterized in that, The discharge module includes a discharge control unit and a discharge unit; the control terminal of the discharge control unit is connected to the output terminal of the chip status detection module, serving as the control terminal of the discharge module; the output terminal of the discharge control unit is connected to the control terminal of the discharge unit; and the discharge unit is connected between the voltage output terminal of the power chip and ground. The discharge control unit is used to control the discharge unit to perform a discharge operation when the discharge signal is received.

4. The discharge circuit as described in claim 3, characterized in that, The discharge control unit includes a diode, a third resistor, a fourth resistor, a fifth resistor, and a first capacitor; wherein: The positive terminal of the diode is connected to the output terminal of the chip status detection module as the control terminal of the discharge control unit. The positive terminal of the diode is also connected to the voltage output terminal of the power chip through the third resistor. The negative terminal of the diode is grounded through the fourth resistor and the first capacitor. The negative terminal of the diode is connected to the first end of the fifth resistor. The second end of the fifth resistor is connected to the control terminal of the discharge unit as the output terminal of the discharge control unit.

5. The discharge circuit as described in claim 4, characterized in that, The time it takes for the first capacitor to drop from its maximum voltage value to the conduction threshold of the discharge unit is greater than the target discharge time of the power chip; the target discharge time is twice the discharge time constant of the output terminal of the power chip.

6. The discharge circuit as described in claim 3, characterized in that, The discharge control unit includes a sixth resistor and a seventh resistor, wherein: The first end of the sixth resistor is connected to the output end of the chip status detection module as the control end of the discharge control unit. The first end of the sixth resistor is connected to the power supply through the seventh resistor. The second end of the sixth resistor is connected to the control end of the discharge unit as the output end of the discharge control unit.

7. The discharge circuit as described in claim 3, characterized in that, The discharge unit includes a switching transistor and an eighth resistor; wherein: The gate of the switching transistor is connected to the output terminal of the discharge control unit as the control terminal of the discharge unit. The source of the switching transistor is grounded, and the drain of the switching transistor is connected to the control terminal of the discharge unit through the eighth resistor.

8. A microcontroller system, characterized in that, The microcontroller system includes a power supply chip and a discharge circuit as described in any one of claims 1 to 7.

9. A vehicle-mounted controller, characterized in that, The vehicle controller includes the microcontroller system as described in claim 8.

10. A vehicle, characterized in that, The vehicle includes the on-board controller as described in claim 9.

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