Hybrid semiconductor wafer and method of forming same

Abstract

A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and dividing the poly-SiC ingot into a plurality of poly-SiC wafer substrates. The method further includes, for a respective poly-SiC wafer substrate, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer substrate to define a mixed Si / poly-SiC stack structure; and performing a singulation process to remove a portion of a thickness of the Si wafer structure from the mixed Si / poly-SiC stack structure to provide a mixed Si / poly-SiC wafer, the mixed Si / poly-SiC wafer including a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer substrate.

Description

Related patent applications

[0001] This patent application claims priority to jointly owned U.S. Provisional Patent Application No. 63 / 542,179, filed October 3, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to integrated circuit (IC) devices, and more particularly to hybrid semiconductor wafers for IC devices and methods for forming hybrid semiconductor wafers. Background Technology

[0003] Semiconductor wafers used in IC devices are typically formed from single-crystal silicon (Si) (i.e., silicon wafers grown from a single silicon crystal), gallium arsenide (GaAs), gallium nitride (GaN), single-crystal silicon carbide (SiC), or sapphire. Different wafer materials have inherent advantages and disadvantages. For example, SiC is known as a semiconductor with a particularly wide bandgap and can be used in high-voltage devices such as high-voltage power MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated-gate bipolar transistors). However, single-crystal SiC is very difficult and expensive to manufacture, typically requiring specialized processing tools, such as specialized high-temperature doping / implantation equipment. Furthermore, single-crystal SiC wafers generally have higher defect levels compared to silicon, which limits yield.

[0004] Improved semiconductor wafers are needed for use in IC devices, such as for high-voltage applications. Summary of the Invention

[0005] This disclosure provides hybrid semiconductor wafers for use in IC devices and methods for forming such hybrid wafers. As used herein, a hybrid semiconductor wafer refers to a semiconductor wafer comprising multiple components comprising different materials bonded together. Some examples provide a hybrid semiconductor wafer comprising (a) a polycrystalline SiC (poly-SiC) wafer substrate and (b) a device layer comprising a silicon (Si) or III-V semiconductor material (e.g., GaN) bonded to the poly-SiC wafer substrate.

[0006] One aspect provides a method comprising performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and dividing the poly-SiC ingot into a plurality of poly-SiC wafer substrates. The method further comprises, for each of the plurality of poly-SiC wafer substrates, bonding a silicon (Si) wafer structure to a respective poly-SiC wafer substrate to define a hybrid Si / poly-SiC stacked structure; and performing a dicing process to remove a portion of the thickness of the Si wafer structure from the hybrid Si / poly-SiC stacked structure to provide a hybrid Si / poly-SiC wafer including the remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer substrate.

[0007] In some examples, the method includes performing a further pressing operation on the hybrid Si / poly-SiC wafer to further bond the remaining portion of the Si wafer structure to the corresponding poly-SiC wafer substrate.

[0008] In some examples, the method includes at least one of pressing the volume of SiC powder using a hot press and further pressing the mixed Si / poly-SiC wafer.

[0009] In some examples, the method includes forming a plurality of hybrid Si / poly-SiC wafers, wherein each hybrid Si / poly-SiC wafer includes a respective poly-SiC wafer substrate in a plurality of poly-SiC wafer substrates, and wherein a further pressing operation includes loading the plurality of hybrid Si / poly-SiC wafers in a stacked arrangement into a press, and operating the press to compress the plurality of hybrid Si / poly-SiC wafers.

[0010] In some examples, loading multiple hybrid Si / poly-SiC wafers into a press in a stacked arrangement includes arranging spacer elements between adjacent hybrid Si / poly-SiC wafers.

[0011] In some examples, the spacer element has a lattice mismatch of at least 5% relative to both the Si wafer structure and the corresponding poly-SiC wafer substrate. In some examples, the spacer element comprises ceramic. In some examples, the spacer element comprises boron nitride (BN), beryllium oxide (BeO), gallium oxide (GaO), or yttrium oxide (Y2O3).

[0012] In some examples, the method includes loading a plurality of SiC powder layers into a hot press to form a multilayer powder stack, wherein different SiC powder layers in the multilayer powder stack have different dopant properties, and wherein a corresponding poly-SiC wafer substrate includes at least two of the plurality of SiC powder layers, wherein the at least two SiC powder layers have different dopant properties.

[0013] One aspect provides a hybrid semiconductor wafer comprising a poly-SiC wafer substrate and a silicon layer bonded to a first side of the poly-SiC wafer substrate.

[0014] In some examples, the method includes a poly-SiC wafer substrate comprising multiple poly-SiC sublayers with different dopant properties.

[0015] One aspect provides a method comprising forming or providing a donor wafer structure including a donor wafer substrate and a GaN layer formed on the donor wafer substrate; bonding the GaN layer of the donor wafer structure to a poly-SiC wafer substrate; and performing a dicing process to remove at least a portion of the thickness of the donor wafer substrate and the GaN layer to provide a hybrid GaN / poly-SiC wafer including the remaining portion of the GaN layer bonded to the poly-SiC wafer substrate.

[0016] In some examples, the method includes performing a pressing operation to further bond the remaining portion of the GaN layer to a poly-SiC wafer substrate.

[0017] In some examples, the method includes forming a plurality of hybrid GaN / poly-SiC wafers, wherein a respective hybrid GaN / poly-SiC wafer among the plurality of hybrid GaN / poly-SiC wafers includes a respective remaining portion of a respective GaN layer bonded to a respective poly-SiC wafer substrate, and wherein the pressing operation includes loading the plurality of hybrid GaN / poly-SiC wafers in a stacked arrangement into a press, and operating the press to compress the plurality of hybrid GaN / poly-SiC wafers.

[0018] In some examples, multiple hybrid GaN / poly-SiC wafers are loaded into a press in a stacked arrangement, including the arrangement of spacer elements between adjacent hybrid GaN / poly-SiC wafers.

[0019] In some examples, the spacer element has at least 5% lattice mismatch relative to both the GaN layer and the poly-SiC wafer substrate.

[0020] In some examples, the donor wafer substrate includes silicon (Si), silicon carbide (SiC), sapphire, aluminum nitride (AlN), or GaN.

[0021] One aspect provides a hybrid semiconductor wafer comprising a poly-SiC wafer substrate and a GaN layer bonded to a first side of the poly-SiC wafer substrate.

[0022] In some examples, the poly-SiC wafer substrate comprises multiple poly-SiC sublayers with different dopant properties.

[0023] One aspect provides a method comprising forming or providing a hybrid semiconductor wafer structure including a wafer substrate and a GaN layer formed on the wafer substrate; and performing at least one iteration of a dopant region formation process. A corresponding iteration of the dopant region formation process includes arranging a template including an opening pattern on a first side of the hybrid semiconductor wafer structure; performing a doping process through the opening pattern in the template to form dopant regions in the GaN layer; and depositing additional GaN over the dopant regions in the GaN layer, the additional GaN deposition increasing the thickness of the GaN layer.

[0024] In some examples, the wafer substrate includes polycrystalline SiC.

[0025] In some examples, the method includes performing multiple iterations of a dopant region formation process, wherein the respective dopant regions formed by the corresponding iterations of the dopant region formation process are separated from each other to define discrete dopant islands.

[0026] In some examples, the doping process includes silane plasma doping to form silicon dopant regions in the GaN layer.

[0027] In some examples, the doping process involves doping with an organic magnesium compound to form magnesium dopant regions in the GaN layer.

[0028] In some examples, the method includes forming a barrier layer over the GaN layer after at least one iteration of performing the dopant region formation process. In some examples, forming a barrier layer over the GaN layer includes forming an aluminum gallium nitride (AlGaN) layer. Attached Figure Description

[0029] Example aspects of this disclosure are described below with reference to the accompanying drawings, in which:

[0030] Figure 1 An example hybrid semiconductor wafer, namely a hybrid Si / poly-SiC wafer, is shown, which includes a silicon layer bonded to a poly-SiC wafer substrate;

[0031] Figures 2A to 2F It shows the method for forming Figure 1 The example process shown is an example of multiple instances of hybrid Si / poly-SiC wafers;

[0032] Figure 3 An example hybrid semiconductor wafer is shown, namely a hybrid GaN / poly-SiC wafer, which includes a GaN layer 304 bonded on a poly-SiC wafer substrate;

[0033] Figures 4A to 4D It shows the method for forming Figure 3 The example process shown is an example of hybrid GaN / poly-SiC wafer fabrication; and

[0034] Figures 5A to 5G An example process for forming an example hybrid wafer structure including a GaN layer comprising floating dopant regions, i.e., dopant islands, is shown.

[0035] It should be understood that reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any illustrated element mentioned or discussed herein in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0036] Figure 1 An example hybrid semiconductor wafer 100 is shown, comprising a polycrystalline SiC (poly-SiC) wafer substrate 102 and a silicon (Si) layer 104 bonded to a first side (top side in the illustrated orientation) of the poly-SiC wafer substrate 102. The first side may also be referred to as the first face. The example hybrid semiconductor wafer 100 is also referred to herein as a hybrid Si / poly-SiC wafer 100. In some examples, the Si layer 104 comprises monocrystalline silicon, i.e., silicon grown from a single crystal.

[0037] In some examples, the poly-SiC wafer substrate 102 may include multiple poly-SiC sublayers of poly-SiC material with different dopant properties, for example, for MOSFET fabrication. In the illustrated example, the poly-SiC wafer substrate 102 includes three poly-SiC sublayers 106 with different corresponding dopant properties. Although three poly-SiC sublayers 106 are shown in the illustrated example, the poly-SiC wafer substrate may include any number of poly-SiC sublayers 106 with different dopant properties.

[0038] Multiple poly-SiC sublayers 106 can be formed during the formation of the poly-SiC wafer substrate 102. For example, see the following reference. Figure 2Aand Figure 2B The poly-SiC wafer substrate 102 discussed herein can be formed by a process comprising: (a) loading multilayer SiC powder with different dopant properties into a press to form a multilayer powder stack in the press; (b) operating the press to compress the multilayer powder stack into a solid ingot having a plurality of poly-SiC sublayers 106 corresponding to the multilayer SiC powder; and (c) slicing the ingot into a plurality of instances of the poly-SiC wafer substrate 102, wherein each instance of the poly-SiC wafer substrate 102 comprises at least two poly-SiC sublayers 106 corresponding to at least two of the plurality of SiC powder layers.

[0039] As used herein, poly-SiC sublayers with “different dopant properties” may include, for example, different dopant concentrations or other properties. In some examples, the poly-SiC wafer substrate 102 may include multiple poly-SiC sublayers with different dopant properties for use in MOSFET fabrication. For example, for certain MOSFET structures, the poly-SiC wafer substrate 102 may include (a) a first poly-SiC sublayer highly doped with nitrogen (e.g., N++++) and (b) a second poly-SiC sublayer doped with nitrogen to a much lower level (e.g., N-) (having a much greater thickness than the first SiC powder layer).

[0040] In other examples, the poly-SiC wafer substrate 102 may have uniform dopant properties over its entire thickness, rather than having multiple poly-SiC sublayers 106.

[0041] Hybrid Si / poly-SiC wafers 100 can offer various benefits or advantages. For example, devices formed from hybrid Si / poly-SiC wafers 100 can realize the functional benefits of SiC, such as large voltage drop and low RV. DS-ON (Drain-source resistance when the device is on) and good heat dissipation, while also benefiting from the ease of processing silicon (e.g., using standard tools), and in some instances avoiding the need for high-temperature processing equipment. Additionally, in some examples, hybrid Si / poly-SiC wafers 100 can be formed into large wafer sizes, such as 300mm (or 12-inch) wafers.

[0042] Figures 2A to 2F It shows the method for forming Figure 1 Example processes for several instances of the hybrid Si / poly-SiC wafer 100 (i.e., hybrid semiconductor wafer 100) shown.

[0043] like Figure 2AAs shown, a certain volume of SiC powder 200 is pressed to form a poly-SiC ingot 202. In some examples, the SiC powder 200 can be loaded into a press 204, such as a hot press (e.g., a hot press conventionally used for forming sputtering targets), which can be operated to compress the SiC powder 200 to form the poly-SiC ingot 202. In some examples, the press 204 includes a hot press that can be operated to compress the SiC powder 200 at an operating temperature between 800°C and 1400°C and at an operating pressure between 5 MPa and 25 MPa for a duration between 5 minutes and 1 hour.

[0044] In some examples, the SiC powder 200 may comprise pure SiC powder or lightly doped SiC powder. In some examples, the SiC powder 200 to be loaded into the press 204 may comprise discrete volumes with different dopant properties. Discrete volumes with different dopant properties may be loaded into the press 204 in a defined order to form a multilayer powder stack 210 in the press chamber 205 of the press 204, wherein the multilayer powder stack 210 comprises different layers 212 of SiC powder 200 with different corresponding dopant properties.

[0045] The poly-SiC ingot 202 formed from such a multilayer powder stack 210 may include a plurality of poly-SiC sublayers 106 with different dopant properties, wherein the respective poly-SiC sublayers 106 correspond to the respective SiC powder layers 212 deposited in the press 204. For example, in order to form a hybrid Si / poly-SiC wafer 100 used in some MOSFET structures, the multilayer powder stack 210 may include (a) a respective first SiC powder layer highly doped with nitrogen (e.g., N++++), which alternates with (b) a respective second SiC powder layer doped with nitrogen to a much lower level (e.g., N-) (having a much larger thickness than the respective first SiC powder layer), wherein after pressing the multilayer powder stack 210 in the press 204, the resulting poly-SiC ingot 202 includes a respective first poly-SiC sublayer 106 (e.g., having N- doping) alternating with the respective second poly-SiC sublayer 106 (e.g., having N- doping). When this poly-SiC ingot 202 is divided into multiple poly-SiC wafer substrates 102 as discussed below (refer to...) Figure 2B The corresponding poly-SiC wafer substrate 102 may include a corresponding first poly-SiC sublayer 106 (e.g., having N-doped) adjacent to the corresponding (thicker) second poly-SiC sublayer 106 (e.g., having N-doped).

[0046] In other examples, SiC5G powder 200 with uniform dopant properties is used to form a uniform powder stack in a press 104, which is compressed to form a poly-SiC ingot 202 with uniform dopant properties over the entire thickness of the ingot 202, rather than multiple poly-SiC sublayers 106 with different dopant properties.

[0047] like Figure 2B As shown, the poly-SiC ingot 202 can be horizontally divided into multiple poly-SiC wafer substrates 102 (i.e., Figure 1 (Multiple examples of the poly-SiC wafer substrate 102 shown). For example, the poly-SiC ingot 202 can be cut or sliced ​​into multiple poly-SiC wafer substrates 102 using a wire saw or other cutting tools. In one example, the poly-SiC ingot 202 may have a thickness of about 0.25 inches and can be sliced ​​into about 12 poly-SiC wafer substrates 102 with corresponding thicknesses in the range of 500µm-750µm. In examples where the poly-SiC ingot 202 includes multiple poly-SiC sublayers 106, the corresponding examples of the poly-SiC wafer substrate 102 may include a stacked arrangement of two or more identical poly-SiC sublayers 106 with different dopant properties.

[0048] In some examples, the corresponding poly-SiC wafer substrate 102 may optionally be ground, milled, polished and / or otherwise treated before further processing.

[0049] like Figure 2C and Figure 2D As shown, the silicon (Si) wafer structure 220 can be bonded to the corresponding poly-SiC wafer substrate 102, for example, by direct contact bonding, to define a hybrid Si / poly-SiC stacked structure 222. In some examples, the Si wafer structure 220 comprises monocrystalline silicon, i.e., silicon grown from a single crystal.

[0050] like Figure 2E As shown, a dicing process is performed to remove a portion 220a of the Si wafer structure 220 from the hybrid Si / poly-SiC stacked structure 222 (the removed portion 220a includes a portion of the thickness of the Si wafer structure 220) to provide Figure 1 The hybrid Si / poly-SiC wafer 100 shown includes a remaining portion 220b of a Si wafer structure 220 bonded to a corresponding poly-SiC wafer substrate 102 (the remaining portion 220b includes the remaining thickness of the Si wafer structure 220). The remaining portion 220b of the Si wafer structure 220 is connected to... Figure 1Corresponding to the Si layer 104 shown, and therefore for simplicity, the remaining portion 220b of the Si wafer structure 220 is referred to below as Si layer 104.

[0051] Depend on Figure 2E The dicing process indicated by the dashed lines can include any suitable sawing or dicing process. In some examples, the exposed diced surfaces 226 of the Si layer 104 can be polished and / or otherwise treated. The removed portions 220a of the Si wafer structure 220 can be reused, for example, as substrates for corresponding integrated circuit devices.

[0052] In some examples, it is possible to perform actions such as Figure 2F The optional pressing process shown further bonds the Si layer 104 (i.e., the remaining portion 220b of the Si wafer structure 220) to the poly-SiC wafer substrate 102, where "further bonding" refers to improving or strengthening the bonding between the Si layer 104 and the poly-SiC wafer substrate 102. Figure 2F As shown, several examples of hybrid Si / poly-SiC wafer 100 (e.g., according to...) Figures 2C to 2E The operation shown can be loaded in a stacked arrangement in the press chamber 205 of the press 204 (or in a different press in another example), wherein corresponding spacer elements 240 are arranged between adjacent hybrid Si / poly-SiC wafers 100 to define a wafer / spacer stack 242 in the press chamber 205.

[0053] The press 204 can be operated to compress the wafer / spacer stack 242, thereby further bonding the respective Si layer 104 to the respective poly-SiC wafer substrate 102 of the respective hybrid Si / poly-SiC wafer 100. In some examples, the press 204 may include a tool for... Figure 2A The suppression operation shown and Figure 2F The optional pressing operation shown is performed on both hot presses. In the example where the same hot press is used for both operations, the hot press can be operated according to the example operating parameters discussed above (i.e., operating temperature between 800°C and 1400°C and operating pressure between 5 MPa and 25 MPa, with a duration between 5 minutes and 1 hour) for use in the pressing operation. Figure 2A The pressing operation shown, and (b) operation according to more aggressive operating parameters (e.g., operating temperature between 1200°C and 1800°C and operating pressure between 30 MPa and 90 MPa, for durations between 10 hours and 100 hours) are used for Figure 2F The suppression operation is shown.

[0054] Spacer element 240 can facilitate separation of adjacent hybrid Si / poly-SiC wafers 100 after a pressing operation, for example, by preventing adjacent hybrid Si / poly-SiC wafers 100 from bonding to each other. In some examples, spacer element 240 may have a lattice mismatch of at least 5%, at least 15%, or at least 25% relative to both Si layer 104 and poly-SiC wafer substrate 102. In some examples, spacer element 240 may have a melting point above 2500°C and a thickness greater than 1000 µm (in... Figure 2F (In the y-direction shown). In some examples, the spacer element 240 may comprise amorphous ceramic or other ceramic materials, such as, but not limited to, boron nitride (BN), beryllium oxide (BeO), gallium oxide (GaO), or yttrium oxide (Y₂O₃). Figure 2F As shown, the spacer element 240 may have a lateral width extending beyond the lateral width of the corresponding hybrid Si / poly-SiC wafer 100 (in Figure 2F (in the x direction shown), for example, as illustrated, to facilitate the separation (e.g., stripping) of the corresponding spacer element 240 from the adjacent hybrid Si / poly-SiC wafer 100.

[0055] In other examples, Figure 2F The suppression operation shown can be performed in Figure 2E The splitting operation shown is performed before (not after). In other words, Figure 2D Multiple instances of the hybrid Si / poly-SiC stacked structure 222 shown can be loaded in a stacked arrangement in the press chamber 205 of press 204 (or in another example, in a different press), wherein corresponding spacer elements 240 are arranged between adjacent hybrid Si / poly-SiC stacked structures 222 to define wafer / spacer stacks 242 within press chamber 205. Press 204 can be operated to compress the wafer / spacer stacks 242, thereby further bonding the corresponding Si wafer structures 220 to the corresponding poly-SiC wafer substrate 102 of the respective hybrid Si / poly-SiC stacked structure 222. The spacer elements 240 can then be removed, and the respective hybrid Si / poly-SiC stacked structure 222 can be subjected to… Figure 2E The segmentation operation shown above (discussed above).

[0056] Figure 3 An example hybrid semiconductor wafer 300 is shown, comprising a poly-SiC wafer substrate 302 and a gallium nitride (GaN) layer 304 bonded to a first side (top side in the illustrated orientation) of the poly-SiC wafer substrate 302. The first side may also be referred to as the first face. The example hybrid semiconductor wafer 300 is also referred to herein as a hybrid GaN / poly-SiC wafer 300.

[0057] In some examples, the poly-SiC wafer substrate 302 can correspond to the poly-SiC wafer substrate 102 of the hybrid semiconductor wafer 100 discussed above. Therefore, the poly-SiC wafer substrate 302 can be configured according to the above-discussed... Figure 2A and Figure 2B The process shown forms, and may optionally include, multiple poly-SiC sublayers 306 with different corresponding dopant properties, for example, as discussed above with respect to the poly-SiC wafer substrate 102, poly-SiC sublayer 106.

[0058] In other examples, GaN layer 304 may alternatively comprise another III-V semiconductor material, such as, but not limited to, indium phosphate (InP), indium arsenide (InAs), gallium arsenide (GaAs), or indium antimonide (InSb). In such examples, within the scope of this disclosure, GaN layer 404 discussed below may be replaced by a layer of other III-V semiconductor material.

[0059] Figures 4A to 4D It shows the method for forming Figure 3 The example process shown is an example of a hybrid GaN / poly-SiC wafer 300 (i.e., a hybrid semiconductor wafer 300).

[0060] like Figure 4A As shown, a donor wafer structure 400 is formed or provided, wherein the donor wafer structure 400 includes a donor wafer substrate 402 and a GaN layer 404 formed (directly or indirectly) on the donor wafer substrate 402. The donor wafer substrate 402 may include silicon (e.g., single-crystal silicon), SiC (e.g., single-crystal SiC), sapphire, aluminum nitride (AlN), GaN, or one or more other suitable materials.

[0061] In some examples, the GaN layer 404 can be formed directly on the donor wafer substrate 404. For example, the GaN layer 404 can be grown on the donor wafer substrate 404 or deposited via a metal-organic chemical vapor deposition (MOCVD) process. In other examples, the GaN layer 404 can be formed indirectly on the donor wafer substrate 404. For example, in an example where the donor wafer substrate 404 is formed of single-crystal silicon, an optional buffer layer 406 (e.g., comprising aluminum nitride (AlN) or other suitable materials) is formed on the donor wafer substrate 404, and the GaN layer 404 can be grown or deposited (e.g., via MOCVD) on the buffer layer 406. In such examples, the buffer layer 406 can facilitate improved bonding between the GaN layer 404 and the single-crystal Si donor wafer substrate 404.

[0062] like Figure 4BAs shown, the GaN layer 404 of the donor wafer structure 400 can be bonded to the corresponding poly-SiC wafer substrate 302, for example, by direct contact bonding, to define the donor wafer / poly-SiC stack structure 410. As discussed above, in some examples, the poly-SiC wafer substrate 302 can be configured according to the methods discussed above. Figure 2A and Figure 2B The process shown forms, and may optionally include multiple poly-SiC sublayers 306 with different dopant properties.

[0063] like Figure 4C As shown, a partitioning process is performed to remove the donor wafer substrate 402, optional buffer layer 406 (if present), and a portion 404a of the GaN layer 404 (the removed portion 404a includes a portion of the thickness of the GaN layer 404) from the donor wafer / poly-SiC stack structure 410, leaving Figure 3 The hybrid GaN / poly-SiC wafer 300 shown includes a remaining portion 404b of a GaN layer 404 bonded to a poly-SiC wafer substrate 302 (the remaining portion 404b includes the remaining thickness of the GaN layer 404). The remaining portion 404b of the GaN layer 404 corresponds to... Figure 3 The GaN layer 304 shown is referred to below as GaN layer 304 for simplicity.

[0064] Depend on Figure 4C The slitting process indicated by the dashed lines can include any suitable sawing or cutting process. In some examples, the exposed cut surface 426 of the GaN layer 304 may be polished and / or otherwise treated.

[0065] In some examples, it is possible to perform actions such as Figure 4D The optional pressing process shown further bonds the GaN layer 304 (i.e., the remaining portion 404b of the GaN layer 404) to the poly-SiC wafer substrate 302, where "further bonding" refers to improving or strengthening the bonding between the GaN layer 304 and the poly-SiC wafer substrate 302. Figure 4D As shown, several examples of hybrid GaN / poly-SiC wafer 300 (e.g., according to...) Figures 4A to 4C The operation shown can be loaded in a stacked arrangement. Figure 2AIn the press chamber 205 (or other press) of the press 204 shown, corresponding spacer elements 440 are arranged between adjacent hybrid GaN / poly-SiC wafers 300 to define a wafer / spacer stack 442 within the press chamber 205. The press 204 can be operated to compress the wafer / spacer stack 442, thereby further bonding the corresponding GaN layer 304 to the corresponding poly-SiC wafer substrate 302 of the corresponding hybrid GaN / poly-SiC wafer 300.

[0066] Spacer element 440 can facilitate separation of adjacent mixed GaN / poly-SiC wafers 300 after a pressing operation, for example, by preventing adjacent mixed GaN / poly-SiC wafers 300 from bonding to each other. In some examples, spacer element 440 may have a lattice mismatch of at least 5%, at least 15%, or at least 25% relative to both GaN layer 304 and poly-SiC wafer substrate 302. In some examples, spacer element 440 may have a melting point above 2500°C and a thickness greater than 1000 µm (in... Figure 4D (In the y-direction shown). In some examples, the spacer element 440 may comprise amorphous ceramic or other ceramic materials, such as, but not limited to, boron nitride (BN), beryllium oxide (BeO), gallium oxide (GaO), or yttrium oxide (Y₂O₃). Figure 4D As shown, the spacer element 440 can have a lateral width extending beyond the lateral width of the corresponding hybrid GaN / poly-SiC wafer 300 (in Figure 4D (in the x direction shown), for example, as illustrated, to facilitate the separation (e.g., stripping) of the corresponding spacer element 440 from the adjacent hybrid GaN / poly-SiC wafer 300.

[0067] In other examples, Figure 4D The suppression operation shown can be performed before (not after) the segmentation operation shown in Figure 4E. In other words, Figure 4B Multiple instances of the donor wafer / poly-SiC stacked structure 410 shown can be loaded in a stacked arrangement in a press chamber 205, wherein corresponding spacer elements 440 are arranged between adjacent donor wafer / poly-SiC stacked structures 410. The press 204 can be operated to further bond corresponding GaN layers 404 to the corresponding poly-SiC wafer substrate 302 of the corresponding donor wafer / poly-SiC stacked structure 410. The spacer elements 440 can then be removed, and the corresponding donor wafer / poly-SiC stacked structure 410 can be subjected to… Figure 4C The segmentation operation shown above (discussed above).

[0068] Figures 5A to 5GAn example process for forming an example wafer structure (e.g., a MOSFET structure) including a GaN layer comprising floating dopant regions or dopant “islands” in the GaN layer is shown.

[0069] like Figure 5A As shown, a hybrid semiconductor wafer structure 500 is formed or provided, which includes a wafer substrate 502 and a GaN layer 504 formed on the wafer substrate 502. In some examples, the wafer substrate 502 may include poly-SiC. In such examples, the hybrid semiconductor wafer structure 500 may correspond to the example hybrid semiconductor wafer 300, i.e., the hybrid GaN / poly-SiC wafer 300. Therefore, the wafer substrate 502 may include, according to Figure 2A and Figure 2B The process shown forms a poly-SiC wafer substrate, and may optionally include multiple poly-SiC sublayers 506 with different dopant properties, for example, as discussed above regarding the poly-SiC sublayer 106 of the poly-SiC wafer substrate 102. In other examples, the wafer substrate 502 may include, but is not limited to, indium phosphate (InP), indium arsenide (InAs), gallium arsenide (GaAs), or indium antimonide (InSb).

[0070] like Figure 5B As shown, an additional GaN layer 508 can be formed on the hybrid semiconductor wafer structure 500. In some examples, an n-type doped GaN layer can be deposited on the GaN layer 504 (e.g., by MOCVD) to define the n-type GaN layer 508. In other examples, a p-type doped GaN layer can be deposited on the GaN layer 504 (e.g., by MOCVD) to define the p-type GaN layer 508.

[0071] The method can be continued by performing at least one iteration of the dopant region formation process to increase the thickness of the GaN layer 508 and form floating dopant regions (i.e., dopant islands) in the GaN layer 508, thereby defining the transistor drift region 526.

[0072] Figures 5C to 5E The first iteration of the dopant region formation process is shown in the figure. For example... Figure 5C As shown, a template 510, including a pattern of opening 512, is disposed on a GaN layer 508, wherein selected areas of the GaN layer 508 are exposed through opening 512. Figure 5DAs shown, a doping process is performed through the pattern of openings 512 in template 510 to form a plurality of first dopant regions 514a in GaN layer 508. In some examples, the doping process may include (a) plasma doping with silane (i.e., SiH4) (e.g., for n-type GaN layer 508) to form silicon dopant regions 514a in GaN layer 508, (b) doping with an organomagnesium compound (for p-type GaN layer 508) to form magnesium dopant regions 514a in GaN layer 508, or (c) doping with another suitable dopant.

[0073] like Figure 5E As shown, an additional GaN 518 can be deposited on the GaN layer 508 (e.g., by MOCVD) and cover the first dopant region 514a. The additionally deposited GaN 518 increases the thickness of the GaN layer 508. The additional GaN 518 can have the same doping (n-type or p-type) as the previously deposited GaN of the GaN layer 508.

[0074] Can be repeated Figures 5C to 5E The dopant region formation process shown is used to further increase the thickness of the GaN layer 508 and to form additional floating dopant regions (i.e., dopant islands) within the GaN layer 508. For example, Figure 5F It shows in Figures 5C to 5E The result shown is after the second iteration of the dopant region formation process, in which multiple second dopant regions 514b are formed in the GaN layer 508, and additional GaN 524 is deposited on top of the second dopant regions 514b (e.g., by MOCVD), the additionally deposited GaN 524 increasing the thickness of the GaN layer 508. Figure 5F As shown, the corresponding first dopant region 514a and second dopant region 514b are spaced apart from other first dopant regions 514a and second dopant regions 514b, such that the corresponding first dopant regions 514a and second dopant regions 514b define floating dopant regions or dopant islands in the GaN layer 508. The corresponding dopant regions 514a and 514b are vertically spaced apart, while the corresponding dopant regions 514a and 514b are horizontally spaced apart from other dopant regions 514a and 514b. Figures 5C to 5E The dopant region formation process shown can be repeated one or more times to further increase the GaN layer 508 to the desired thickness and form additional floating dopant regions (dopant islands). In some examples, the same template 510 can be used to form each set of dopant regions (e.g., first dopant region 514a, second dopant region 514b, etc.), thereby creating a vertical path through the GaN layer 508 that alternates between doped GaN and undoped (or differently doped) GaN, for example, for vertical MOSFET devices.

[0075] like Figure 5G As shown, in some examples, after a repeated dopant region formation process to increase the GaN layer 508 to a desired thickness, a barrier layer 530 can be formed over the GaN layer 508. For example, the barrier layer 530 may comprise an aluminum gallium nitride (AlGaN) layer. The resulting structure can define a GaN MOSFET structure, including a GaN layer 508 with doped islands (e.g., doped islands 514a and 514b) defining a MOSFET drift region that can exhibit a breakdown voltage, for example, greater than 2400V.

[0076] Although example implementations have been described above, other variations and implementations may be made by this disclosure without departing from the substance and scope of these implementations.

Claims

1. A method, the method comprising: A pressing operation is performed on a certain volume of silicon carbide (SiC) powder to form a polycrystalline SiC ingot; The poly-SiC ingot is divided into multiple poly-SiC wafer substrates; For the corresponding poly-SiC wafer substrates among the plurality of poly-SiC wafer substrates: Silicon (Si) wafer structures are bonded to the corresponding poly-SiC wafer substrate to define a hybrid Si / poly-SiC stacked structure; as well as A dicing process is performed to remove a portion of the thickness of the Si wafer structure from the hybrid Si / poly-SiC stacked structure to provide a hybrid Si / poly-SiC wafer, the hybrid Si / poly-SiC wafer including the remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer substrate.

2. The method of claim 1, wherein the method comprises performing a further pressing operation on the hybrid Si / poly-SiC wafer to further bond the remaining portion of the Si wafer structure to the corresponding poly-SiC wafer substrate.

3. The method of claim 2, wherein the method comprises at least one of the pressing operation of the volume of SiC powder using a hot press and the further pressing operation of the mixed Si / poly-SiC wafer.

4. The method according to any one of claims 2 to 3, wherein the method comprises: Multiple hybrid Si / poly-SiC wafers are formed, wherein a corresponding hybrid Si / poly-SiC wafer among the multiple hybrid Si / poly-SiC wafers includes a corresponding poly-SiC wafer substrate among the multiple poly-SiC wafer substrates; and The further pressing operation mentioned above includes: The plurality of hybrid Si / poly-SiC wafers are loaded into a press in a stacked arrangement; as well as The press is operated to compress the plurality of hybrid Si / poly-SiC wafers.

5. The method of claim 4, wherein loading the plurality of hybrid Si / poly-SiC wafers into the press in the stacked arrangement includes arranging spacer elements between adjacent hybrid Si / poly-SiC wafers.

6. The method of claim 5, wherein the spacer element has at least 5% lattice mismatch with respect to both the Si wafer structure and the corresponding poly-SiC wafer substrate.

7. The method of claim 5, wherein the spacer element comprises ceramic.

8. The method of claim 5, wherein the spacer element comprises boron nitride (BN), beryllium oxide (BeO), gallium oxide (GaO), or yttrium oxide (Y2O3).

9. The method according to any one of claims 1 to 8, the method comprising: Multiple SiC powder layers are loaded into a hot press to form a multilayer powder stack, wherein the different SiC powder layers in the multilayer powder stack have different dopant properties; and The corresponding poly-SiC wafer substrate includes at least two SiC powder layers from the plurality of SiC powder layers, wherein the at least two SiC powder layers have different dopant properties.

10. A hybrid semiconductor wafer, the hybrid semiconductor wafer comprising: Polycrystalline SiC (poly-SiC) wafer substrate; and A silicon (Si) layer is bonded to a first side of the poly-SiC wafer substrate.

11. The hybrid semiconductor wafer of claim 10, wherein the poly-SiC wafer substrate comprises a plurality of poly-SiC sublayers with different dopant properties.

12. A method, the method comprising: Forming or providing a donor wafer structure, the donor wafer structure including a donor wafer substrate and a gallium nitride (GaN) layer formed on the donor wafer substrate; The GaN layer of the donor wafer structure is bonded to a polycrystalline SiC wafer substrate; as well as A dicing process is performed to remove at least a portion of the thickness of the donor wafer substrate and the GaN layer to provide a hybrid GaN / poly-SiC wafer, the hybrid GaN / poly-SiC wafer including the remaining portion of the GaN layer bonded to the poly-SiC wafer substrate.

13. The method of claim 12, the method comprising performing a pressing operation to further bond the remaining portion of the GaN layer to the poly-SiC wafer substrate.

14. The method according to claim 13, wherein the method comprises: Multiple hybrid GaN / poly-SiC wafers are formed, wherein a respective hybrid GaN / poly-SiC wafer in the plurality of hybrid GaN / poly-SiC wafers includes a respective remaining portion of a respective GaN layer bonded to a respective poly-SiC wafer substrate; and The pressing operation includes: The plurality of hybrid GaN / poly-SiC wafers are stacked and loaded into a press; as well as The press is operated to compress the plurality of hybrid GaN / poly-SiC wafers.

15. The method of claim 13, wherein loading the plurality of hybrid GaN / poly-SiC wafers in the press in the stacked arrangement includes arranging spacer elements between adjacent hybrid GaN / poly-SiC wafers.

16. The method of claim 15, wherein the spacer element has at least 5% lattice mismatch with respect to both the GaN layer and the poly-SiC wafer substrate.

17. The method of claim 12, wherein the donor wafer substrate comprises silicon (Si), silicon carbide (SiC), sapphire, aluminum nitride (AlN), or GaN.

18. A hybrid semiconductor wafer, the hybrid semiconductor wafer comprising: Polycrystalline SiC (poly-SiC) wafer substrate; and A gallium nitride (GaN) layer is bonded to a first side of the poly-SiC wafer substrate.

19. The hybrid semiconductor wafer of claim 18, wherein the poly-SiC wafer substrate comprises a plurality of poly-SiC sublayers with different dopant properties.

20. A method, the method comprising: Forming or providing a semiconductor wafer structure, the semiconductor wafer structure including a wafer substrate and a gallium nitride (GaN) layer formed on the wafer substrate; Perform at least one iteration of the dopant region formation process, wherein the corresponding iteration of the dopant region formation process includes: A template is arranged on a first side of the semiconductor wafer structure, the template including a pattern of openings; A doping process is performed using the opening pattern in the template to form doped regions in the GaN layer; and Additional GaN is deposited over the dopant region in the GaN layer, and the deposited GaN increases the thickness of the GaN layer.

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