Machining method for reducing edge polishing broken pieces

Abstract

The invention relates to the technical field of semiconductor silicon wafer manufacturing, in particular to a processing method for reducing edge polishing fragmentation, which comprises the following steps: carrying out gradient polishing on the edge of a wafer in three stages: in a rough polishing stage, the rotating speed of a polishing wheel is 100-150 rpm, the feeding speed is 0.3-1 mm / s, and the flow of a polishing solution is 0.8-1.5 L / min; in the medium polishing stage, the rotating speed of a polishing wheel ranges from 150 rpm to 240 rpm, the feeding speed ranges from 0.3 mm / s to 1 mm / s, and the flow of polishing liquid ranges from 1.5 L / min to 2.1 L / min; in the fine polishing stage, the rotating speed of a polishing wheel is 240-300 rpm, the feeding speed is 0.2-0.5 mm / s, and the flow of the polishing solution is 2.2-2.8 L / min; in each stage, a polishing module with multiple angles relative to the horizontal plane is adopted, and an inclination angle of 30 degrees is formed in the polishing module; the polishing solution is a nano-composite polishing solution, and the polishing solution contains 50nm SiO particles to fill the microcracks of the wafer.

Description

A processing method to reduce edge polishing chipping Technical Field

[0001] This invention relates to the field of semiconductor silicon wafer manufacturing technology, and in particular to a processing method for reducing edge polishing breakage of wafers. Background Technology

[0002] During the edge polishing process of 12-inch wafers, wafer breakage often occurs, directly leading to product scrap. The broken particles may contaminate the polishing equipment, causing downtime to increase by 12-18 minutes per hour, affecting product quality and production capacity.

[0003] In the current 12-inch wafer edge polishing process, the breakage rate is generally 2.1%-3.5%, mainly due to the following reasons: Mechanical stress concentration: traditional diamond wheel single-point cutting leads to the propagation of edge microcracks; Thermal stress imbalance: when the temperature difference of the polishing fluid exceeds 5℃, the risk of lattice distortion increases by 30%; Material fragility: the mechanical properties of the silicon wafer (100) surface and the edge (110) surface are significantly different. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a processing method that reduces edge polishing breakage.

[0005] The technical objective of this invention is achieved as follows: a processing method for reducing edge polishing breakage of wafers, comprising: gradient polishing of wafer edges in three stages, wherein: a rough polishing stage: polishing wheel speed 100~150 rpm, feed speed 0.3~1 mm / s, polishing slurry flow rate 0.8~1.5 L / min; a medium polishing stage: polishing wheel speed 150~240 rpm, feed speed 0.3~1 mm / s, polishing slurry flow rate 1.5~2.1 L / min; a fine polishing stage: polishing wheel speed 240~300 rpm, feed speed 0.2~0.5 mm / s, polishing slurry flow rate 2.2~2.8 L / min; in each stage, a polishing module with multiple angles relative to the horizontal plane is used, and the polishing module has a 30° tilt angle; the polishing slurry is a nano-composite polishing slurry, which contains 50nm SiO2 particles to fill the microcracks of the wafer, and the solid content reaches 15%~40%.

[0006] In a further proposed approach, after polishing, the wafer is subjected to ultrasonic cleaning.

[0007] The beneficial effects of this invention are: by designing an asymmetric polishing wheel, this invention disperses the axial cutting force and reduces the possibility of edge microcrack propagation; at the same time, by filling the microcracks in the wafer with 50nm SiO2 particles, it improves the roughness and increases the yield of qualified products.

[0008] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below.

[0010] This embodiment provides a processing method to reduce edge polishing breakage of wafers. The method employs a three-stage gradient polishing process to polish the wafer edge sequentially: Coarse polishing stage: polishing wheel speed 100~150 rpm, feed rate 0.3~1 mm / s, polishing slurry flow rate 1.5~2.1 L / min; its main function is to remove 90% of the polishing residue; Intermediate polishing stage: polishing wheel speed 150~240 rpm, feed rate 0.3~1 mm / s, polishing slurry flow rate 1.5~2.1 L / min; its main function is to prepare a stress transition layer; Fine polishing stage: polishing wheel speed 240~300 rpm, feed rate 0.2~0.5 mm / s, polishing slurry flow rate 1.5~2.1 L / min; its main function is to perform nanoscale surface finishing.

[0011] In each stage, polishing modules with multiple angles relative to the horizontal plane are used. The polishing modules with a 30° tilt angle disperse the axial cutting force, which can fully process the edge of the silicon wafer and release stress relatively evenly to a certain extent, thus improving the problem of mechanical stress concentration. The polishing slurry can use the existing mainstream silicon wafer polishing slurry, which contains 50nm SiO2 particles to fill the microcracks in the wafer, with a solid content of 15%~40%. After polishing, residual polishing slurry can be completely removed by ultrasonic cleaning.

[0012] The comparison between this invention and the traditional process is as follows: Performance Indicators Traditional Process Invention Improvement Average Fragmentation Rate 2.1% 0.11% 94.8% ↓ Edge Roughness Ra 0.8μm 0.3μm 62.5% ↓ Output per Hour 120 pieces 126 pieces +5% ↑ The above description is merely a preferred embodiment of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A processing method for reducing edge polishing chipping, characterized in that, include: The wafer edges are subjected to gradient polishing in three stages: coarse polishing stage: polishing wheel speed 100~150 rpm, feed rate 0.3~1 mm / s, polishing slurry flow rate 0.8~1.5 L / min; medium polishing stage: polishing wheel speed 150~240 rpm, feed rate 0.3~1 mm / s, polishing slurry flow rate 1.5~2.1 L / min; fine polishing stage: polishing wheel speed 240~300 rpm, feed rate 0.2~0.5 mm / s, polishing slurry flow rate 2.2~2.8 L / min. In each stage, polishing modules with multiple angles relative to the horizontal plane are used. The polishing modules have a 30° tilt angle to disperse the axial cutting force. The polishing slurry contains 50nm SiO2 particles to fill the microcracks in the wafer.

2. The processing method for reducing edge polishing chipping according to claim 1, characterized in that, After polishing, the wafer is ultrasonically cleaned.

3. The processing method for reducing edge polishing chipping according to claim 1, characterized in that, The polishing slurry contains 15% to 40% solids.