Storage block processing method and device, electronic equipment and storage medium
By disassembling and binding bad logic blocks in flash memory chips, the problem of small usable capacity of flash memory chips is solved, and the utilization of non-adjacent good blocks is realized, thereby improving the capacity utilization rate of flash memory chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SLICONGO MICROELECTRONICS INC
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-01
AI Technical Summary
Bad blocks in flash memory chips result in limited usable capacity. Existing technologies can only bind adjacent good blocks and cannot fully utilize non-adjacent good blocks.
The logic blocks containing bad blocks in the flash memory chip are disassembled to obtain good blocks, and the good blocks are bound to non-adjacent logic blocks. The logic block addresses are configured and a mapping table is established to enable access.
It increases the available capacity of flash memory chips, enhances the flexibility of good block binding, and maximizes the utilization of good blocks in logical blocks containing bad blocks.
Smart Images
Figure CN121957484A_ABST
Abstract
Description
Storage block processing methods, apparatuses, electronic devices and storage media Technical Field
[0001] This application relates to the field of storage technology, and in particular to a storage block processing method, apparatus, electronic device and storage medium. Background Technology
[0002] Flash memory chips contain wafer dies, which are divided into multiple independent physical storage regions. Each physical storage region contains multiple storage blocks, and these storage blocks can be used to construct logical blocks for computation, operation, or to reserve space.
[0003] Flash memory chips may contain damaged blocks before leaving the factory or during use; these damaged blocks are called bad blocks, while the blocks that can be used normally are called good blocks. When bad blocks exist in a logical block, all the good blocks in that logical block will be discarded, resulting in a significant loss of the usable capacity of the flash memory chip.
[0004] In an exemplary technique, good blocks are separated from a logic block containing bad blocks, and new logic blocks are obtained by binding the separated good blocks. However, the above method of binding good blocks can only bind adjacent good blocks; non-adjacent good blocks cannot be bound together, resulting in some good blocks being unused, which means that the usable capacity of the flash memory chip is relatively small. Summary of the Invention
[0005] This application provides a storage block processing method, apparatus, electronic device, and storage medium to address the problem of limited usable capacity in flash memory chips.
[0006] In a first aspect, embodiments of this application provide a storage block processing method, comprising: disassembling a first logical block containing good blocks and bad blocks in a flash memory chip to obtain a first good block; disassembling a second logical block in the flash memory chip to obtain a second good block, wherein the second logical block is a logical block that does not contain bad blocks; binding the first good block and the second good block to obtain a third logical block, and configuring the logical block address of the third logical block; establishing a mapping relationship table between the logical block address and the address of the storage block in the third logical block, and storing the mapping relationship table, wherein the mapping relationship table is used to access the storage block in the third logical block.
[0007] In one embodiment, before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining a target logic block in the flash memory chip as the second logic block, wherein the distance between the target logic block and at least two first good blocks is less than a distance threshold; and binding the first good block and the second good block to obtain the third logic block includes: binding the first good block to the second good block disassembled from the second logic block corresponding to the first good block to obtain the third logic block, wherein the distance between the first good block and the bound second good block is less than a distance threshold.
[0008] In one embodiment, before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining a first number of the first good block and a second number of storage blocks in the first logic block; and determining a third number of second logic blocks in the flash memory chip based on the first number and the second number, wherein the sum of the number of second good blocks obtained by disassembling the third number of second logic blocks and the first number is an integer multiple of the second number.
[0009] In one embodiment, before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining, in the flash memory chip, a logic block adjacent to the first good block as the second logic block.
[0010] In one embodiment, binding the first good block and the second good block to obtain a third logical block includes: determining the target number of storage blocks in the second logical block; combining the first good block and the second good block to obtain multiple sets, wherein the sum of the number of the first good block and the number of the second good block in each set is the target number; binding the first good block and the second good block in each set to obtain a third logical block corresponding to each set.
[0011] In one embodiment, the step of disassembling the second logic block in the flash memory chip to obtain the second good block includes: determining a first number of the first good block and a second number of storage blocks in the first logic block; and disassembling the second logic block in the flash memory chip to obtain the second good block when the first number is an integer multiple of the second number.
[0012] In one embodiment, disassembling the first logic block containing good blocks and bad blocks in the flash memory chip includes: obtaining the total number of bad blocks in the flash memory chip; and disassembling the first logic block containing good blocks and bad blocks in the flash memory chip if the total number is greater than a number threshold.
[0013] Secondly, this application provides a storage block processing apparatus, comprising: a first processing module for disassembling a first logical block containing good blocks and bad blocks in a flash memory chip to obtain a first good block; a second processing module for disassembling a second logical block in the flash memory chip to obtain a second good block, wherein the second logical block is a logical block that does not contain bad blocks; a binding module for binding the first good block and the second good block to obtain a third logical block, and configuring the logical block address of the third logical block; and an establishment module for establishing a mapping relationship table between the logical block address and the address of the storage block in the third logical block, and storing the mapping relationship table, wherein the mapping relationship table is used to access the storage block in the third logical block.
[0014] Thirdly, embodiments of this application provide an electronic device, including: one or more processors; and a memory storing one or more programs thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the memory block processing method as described in the first aspect.
[0015] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the storage block processing method described in the first aspect.
[0016] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the storage block processing method described in the first aspect.
[0017] In this embodiment, a first logical block containing both good and bad blocks in a flash memory chip is disassembled to obtain a first good block. A second logical block in the flash memory chip is disassembled to obtain a second good block. The first and second good blocks are then bound together to obtain a third logical block. The logical block address of the third logical block is configured, and a mapping table between the logical block address and the addresses of the storage blocks in the third logical block is established and stored. This mapping table is used to access the storage blocks in the third logical block. In this application, by disassembling a logical block containing both good and bad blocks, and also disassembling a logical block consisting entirely of good blocks, the good blocks obtained from both disassembly methods are bound together. Furthermore, the good blocks derived from a logical block containing bad blocks do not need to be adjacent; they can be bound using good blocks from a logical block without bad blocks. This improves the binding flexibility of good blocks from logical blocks containing bad blocks. By utilizing good blocks from logical blocks without bad blocks, the binding of good blocks from logical blocks containing bad blocks is maximized, thereby increasing the usable capacity of the flash memory chip. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0019] Figure 1 is a flowchart of one embodiment of the storage block processing method provided in this application.
[0020] Figure 2 is a second schematic flowchart of an embodiment of the storage block processing method provided in this application.
[0021] Figure 3 is a flowchart of an embodiment of the storage block processing method provided in this application.
[0022] Figure 4 is a flowchart of an embodiment of the storage block processing method provided in this application.
[0023] Figure 5 is a schematic diagram of the functional modules of the storage block processing device provided in the embodiment of this application.
[0024] Figure 6 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. Detailed Implementation
[0025] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions provided in this application will be described in detail below with reference to the accompanying drawings.
[0026] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, the described exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.
[0027] As used herein, the term "and / or" includes any and all combinations of one or more related enumerated purposes.
[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of a feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.
[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0030] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in the embodiments of this application.
[0031] Flash memory chips contain wafer dies, which are divided into multiple independent physical storage regions. Each physical storage region contains multiple storage blocks, and these storage blocks can be used to construct logical blocks for computation, operation, or to reserve space.
[0032] Flash memory chips may contain damaged blocks before leaving the factory or during use; these damaged blocks are called bad blocks, while the blocks that can be used normally are called good blocks. When bad blocks exist in a logical block, all the good blocks in that logical block will be discarded, resulting in a significant loss of the usable capacity of the flash memory chip.
[0033] In an exemplary technique, good blocks are separated from a logic block containing bad blocks, and new logic blocks are obtained by binding the separated good blocks. However, the above method of binding good blocks can only bind adjacent good blocks; non-adjacent good blocks cannot be bound together, resulting in some good blocks being unused, which means that the usable capacity of the flash memory chip is relatively small.
[0034] To address the problems existing in the aforementioned related technologies, embodiments of this application provide a storage block processing method, apparatus, electronic device, and storage medium. The method involves disassembling a first logical block containing good and bad blocks in a flash memory chip to obtain a first good block, disassembling a second logical block in the flash memory chip to obtain a second good block, binding the first and second good blocks to obtain a third logical block, configuring the logical block address of the third logical block, establishing a mapping table between the logical block address and the addresses of storage blocks within the third logical block, and storing the mapping table for accessing storage blocks within the third logical block. In this application, by disassembling logic blocks containing both bad and good blocks, and further disassembling logic blocks consisting entirely of good blocks, the good blocks obtained from both disassembly methods are bound together. Furthermore, the good blocks obtained from disassembling logic blocks containing bad blocks do not need to be adjacent; they can also be bound together using good blocks from logic blocks without bad blocks. This improves the binding flexibility of good blocks from logic blocks containing bad blocks. Moreover, by utilizing good blocks from logic blocks without bad blocks, the binding of good blocks from logic blocks containing bad blocks is maximized, thereby increasing the usable capacity of the flash memory chip.
[0035] Please refer to Figure 1, which is one of the flowcharts of the storage block processing method provided in this application embodiment. As shown in Figure 1, the storage block processing method includes: step S101, disassembling a first logic block containing good blocks and bad blocks in a flash memory chip to obtain a first good block.
[0036] In this embodiment, the execution entity is a storage block processing device, which can be a flash memory chip, a card opening tool, or a terminal device with storage block processing capabilities. For ease of description, the term "device" will be used to refer to the storage block processing device below.
[0037] Flash memory chips have a clear physical layer architecture, from largest to smallest: Chip → Die → Plane → Block → Page → Cell. Flash memory chips employ a Multi-Plane architecture, where a Multi-Plane refers to multiple independently processing logical units that handle data writing and execution of commands. In this embodiment, storage blocks within a Plane can form logical blocks, which can be logical operation blocks or logical pre-stored space blocks.
[0038] During operation, flash memory chips record unusable storage blocks, which are designated as bad blocks, while other usable blocks are considered good blocks. During the card activation phase, the device acquires this recorded information to determine the logical blocks containing both bad and good blocks; these logical blocks are defined as the first logical block. The card activation phase refers to the optimization of the flash memory chip's configuration performance. This involves using specialized tools to match the controller and flash memory samples, writing customized firmware, and configuring parameters. This enables the flash memory chip, which is essentially just a hardware carrier, to perform normal storage and read / write operations. The card activation phase can be a parameter optimization stage in both mass production and fault repair scenarios for storage products.
[0039] After determining the first logic block, the device disassembles the first logic block to obtain a good block, which is defined as the first good block. There may be multiple first logic blocks, so multiple first good blocks can be obtained.
[0040] Furthermore, the device obtains the total number of bad blocks in the flash memory chip. If the total number is greater than the number threshold, it can be determined that there are too many abandoned logic blocks containing bad blocks, which seriously reduces the usable capacity of the flash memory chip. In order to improve the usable capacity, it is necessary to utilize the good blocks in these abandoned logic blocks. Therefore, the first logic block containing both good and bad blocks in the flash memory chip is disassembled.
[0041] Step S102: Disassemble the second logic block in the flash memory chip to obtain the second good block. The second logic block is a logic block that does not contain bad blocks.
[0042] The device can also disassemble the second logic block in the flash memory chip to obtain a good block, which is defined as the second good block. The second logic block refers to a logic block that does not contain bad blocks.
[0043] In one example, any logic block in the flash memory chip that does not contain bad blocks can be used as the second logic block.
[0044] In another example, the logic block in the flash memory chip that is adjacent to the first good block and does not contain any bad blocks is identified as the second logic block.
[0045] Step S103: Bind the first good block and the second good block to obtain the third logical block, and configure the logical block address of the third logical block.
[0046] After obtaining the second good block, the first and second good blocks can be bound together to form a new logical block, which is defined as the third logical block. To ensure that the good blocks within the third logical block can be accessed, the device first configures the logical block address of the third logical block.
[0047] Step S104: Establish a mapping table between the address of the logical block and the address of the storage block in the third logical block, and store the mapping table. The mapping table is used to access the storage block in the third logical block.
[0048] After configuring the address of the third logical block, a mapping table is established between the logical block address and the addresses of the storage blocks within the third logical block, and this mapping table is stored. When subsequent data read / write operations use the third logical block, they can be guided to the actual storage block through the mapping table; in other words, the mapping table is used to access the storage blocks within the third logical block.
[0049] In this embodiment, a first logical block containing both good and bad blocks in a flash memory chip is disassembled to obtain a first good block. A second logical block in the flash memory chip is disassembled to obtain a second good block. The first and second good blocks are then bound together to obtain a third logical block. The logical block address of the third logical block is configured, and a mapping table is established between the logical block address and the addresses of the storage blocks within the third logical block. This mapping table is stored for accessing the storage blocks within the third logical block. In this embodiment, by disassembling both the logical block containing bad and good blocks and the logical block consisting entirely of good blocks, the good blocks obtained from both disassembly methods are bound together. Furthermore, the good blocks derived from a logical block containing bad blocks do not need to be adjacent; they can be bound using good blocks from a logical block without bad blocks. This improves the binding flexibility of good blocks from logical blocks containing bad blocks. By utilizing good blocks from logical blocks without bad blocks, the binding of good blocks from logical blocks containing bad blocks is maximized, thereby increasing the usable capacity of the flash memory chip.
[0050] Referring to Figure 2, which is a second schematic flowchart of the storage block processing method provided in the embodiment of this application, based on the embodiment shown in Figure 1, step S201 is included before step S102, and step S103 includes step S202, as follows: Step S201, in the flash memory chip, a target logic block is determined as a second logic block, and the distance between the target logic block and at least two first good blocks is less than a distance threshold.
[0051] In this embodiment, there are multiple first good blocks, and these first good blocks are not adjacent to each other. In this case, a logic block that is adjacent to two first good blocks can be found in the flash memory chip, and the storage blocks in this logic block are all good blocks. Therefore, the good blocks of this logic block can be further bound to their respective adjacent first good blocks. To this end, the device determines a target logic block as a second logic block in the flash memory chip. The distance between the target logic block and at least two first good blocks is less than a distance threshold, where less than the distance threshold means that the logic block is adjacent to a first good block.
[0052] Step S202: Bind the first good block to the second good block that is decomposed from the second logic block corresponding to the first good block to obtain the third logic block. The distance between the first good block and the bound second good block is less than the distance threshold.
[0053] After the second logic block is decomposed, the first good block is bound to the second good block decomposed from the corresponding second logic block to obtain the third logic block. The distance between the second good block and the second good block decomposed from the corresponding second logic block is less than the distance threshold.
[0054] In this embodiment, the second good block adjacent to the first good block can be bound in a nearby manner. See Figure 3. Figure 3 is a schematic flowchart of the storage block processing method provided in the embodiment of this application. Based on the embodiment shown in Figure 1 or Figure 2, before step S102, the method further includes: step S301, determining the first number of the first good block and the second number of storage blocks in the first logical block.
[0055] Step S302: Based on the first quantity and the second quantity, determine a third quantity of second logic blocks in the flash memory chip, wherein the sum of the number of second logic blocks subdivided from the third quantity of second logic blocks and the first quantity is an integer multiple of the second quantity.
[0056] In this embodiment, the device determines a first number of good blocks and a second number of storage blocks in the first logic block. The second number refers to the card opening mode. For example, if the card opening mode is 2-Plane mode, then the logic block is determined to be composed of 2 storage blocks, and when rebinding the good blocks, the 2 good blocks need to be bound together. If the card opening mode is 4-Plane mode, then the logic block is composed of 4 storage blocks, and therefore the 4 disassembled good blocks need to be combined.
[0057] The device determines a third number of second logic blocks in the flash memory chip based on a first number and a second number, and the sum of the number of second good blocks obtained from the third number of second logic blocks and the first number is an integer multiple of the second number. For example, if the number of first good blocks obtained is 6 and the card opening mode is 2Plane, then 3 second logic blocks need to be obtained.
[0058] In this embodiment, the number of second logical blocks from which good blocks need to be extracted is quickly and accurately determined by the number of first good blocks and the second number of storage blocks in the first logical block.
[0059] Referring to Figure 4, which is a flowchart of the storage block processing method provided in the embodiment of this application, based on the embodiment shown in Figure 1, step S103 includes: step S401, determining the target number of storage blocks in the second logical block.
[0060] In this embodiment, the device determines the target number of storage blocks in the second logic block. The target number is the card opening mode and the number of good blocks in the new logic block. For example, 2Plane requires binding 2 good blocks, and 4Plane requires binding 4 good blocks.
[0061] Step S402: Combine the first good block and the second good block to obtain multiple sets. The sum of the number of the first good block and the second good block in each set is the target number.
[0062] There are multiple first-good blocks and multiple second-good blocks. The first-good blocks and the second-good blocks can be combined to obtain multiple sets. The sum of the number of first-good blocks and the number of second-good blocks in each set is the target number.
[0063] Step S403: Bind the first good block and the second good block in each set to obtain the third logical block corresponding to each set.
[0064] The device binds the first and second good blocks within each set to obtain the third logic block corresponding to each first set.
[0065] In this embodiment, when there are multiple first good blocks and multiple second good blocks, the first good blocks and the second good blocks are combined to obtain multiple sets, and then the first good blocks and the second good blocks in the sets are bound to obtain new logic blocks.
[0066] In some embodiments, the device obtains a first number of first good blocks and a second number of storage blocks in the first logic. If the first number is an integer multiple of the second number, it can be determined that the sum of the number of first good blocks and the number of second good blocks obtained from the disassembly is an integer multiple of the second number. The device can then bind each first good block to maximize the utilization of all disassembled first good blocks, thereby increasing the usable capacity of the flash memory chip. Therefore, if the first number is an integer multiple of the second number, the second logic blocks in the flash memory chip are disassembled to obtain second good blocks.
[0067] Corresponding to the above-described storage block processing method, this application also provides a storage block processing apparatus. Figure 5 is a schematic diagram of the modules of a storage block processing apparatus provided in this application embodiment. The storage block processing apparatus 500 provided in this application embodiment includes: a first processing module 510, used to disassemble a first logical block containing good blocks and bad blocks in a flash memory chip to obtain a first good block; a second processing module 520, used to disassemble a second logical block in the flash memory chip to obtain a second good block, wherein the second logical block is a logical block that does not contain bad blocks; a binding module 530, used to bind the first good block and the second good block to obtain a third logical block, and configure the logical block address of the third logical block; and an establishment module 540, used to establish a mapping relationship table between the logical block address and the address of the storage block in the third logical block, and store the mapping relationship table, wherein the mapping relationship table is used to access the storage block in the third logical block.
[0068] In some implementations, the storage block processing device 500 is further configured to: determine a target logic block in the flash memory chip as a second logic block, wherein the distance between the target logic block and at least two first good blocks is less than a distance threshold; and bind the first good block and the second good block to obtain a third logic block, including: binding the first good block to a second good block decomposed from the second logic block corresponding to the first good block to obtain a third logic block, wherein the distance between the first good block and the bound second good block is less than a distance threshold.
[0069] In some implementations, the storage block processing device 500 is further configured to: determine a first number of first good blocks and a second number of storage blocks in the first logical block; and determine a third number of second logical blocks in the flash memory chip based on the first number and the second number, wherein the sum of the number of second good blocks subdivided from the third number of second logical blocks and the first number is an integer multiple of the second number.
[0070] In some implementations, the storage block processing device 500 is also used to: determine, in the flash memory chip, a logical block adjacent to the first block as a second logical block.
[0071] In some implementations, the storage block processing device 500 is further configured to: determine the target number of storage blocks in the second logical block; combine the first good block and the second good block to obtain multiple sets, wherein the sum of the number of the first good block and the second good block in each set is the target number; and bind the first good block and the second good block in each set to obtain a third logical block corresponding to each set.
[0072] In some implementations, the storage block processing device 500 is further configured to: determine a first number of first good blocks and a second number of storage blocks in the first logical block; and, if the first number is an integer multiple of the second number, disassemble the second logical block in the flash memory chip to obtain a second good block.
[0073] In some implementations, the storage block processing device 500 is also used to: obtain the total number of bad blocks in the flash memory chip; and if the total number is greater than a number threshold, disassemble the first logic block of the flash memory chip that contains both good and bad blocks.
[0074] The storage block processing apparatus and storage block processing method provided in the above embodiments of this application belong to the same application concept and can execute the storage block processing method provided in any of the above embodiments of this application, possessing the corresponding functional modules and beneficial effects for executing the storage block processing method. Technical details not described in detail in this embodiment can be found in the specific processing content of the storage block processing method provided in the above embodiments of this application, and will not be repeated here. The functions implemented by each module in the storage block processing apparatus can be implemented by the same or different processors, and this application embodiment does not limit this.
[0075] It should be understood that the modules in the above-described memory block processing device can be implemented by a processor calling firmware. For example, the system includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of each module of the device. The processor can be a general-purpose processor, such as a CPU or microprocessor, and the memory can be internal to the device or external to the system. Alternatively, the modules in the system can be implemented as hardware circuits. By designing the hardware circuits, some or all of the module functions can be implemented. The hardware circuits can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above modules are implemented by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented by a PLD, such as an FPGA, which can include a large number of logic gates. The connection relationships between the logic gates are configured through configuration files to implement the functions of some or all of the above modules. All modules of the above-described memory block processing device can be implemented entirely by a processor calling firmware, entirely by hardware circuits, or partially by a processor calling firmware with the remaining parts implemented by hardware circuits.
[0076] In this application embodiment, a processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the processor loading instructions to implement the functions of some or all of the above modules. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, or DPU.
[0077] As can be seen, each module in the above-mentioned storage block processing device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor types.
[0078] Furthermore, the modules in the above-mentioned memory block processing device can be integrated in whole or in part, or they can be implemented independently. In one implementation, these modules are integrated together and implemented in the form of a System-on-Chip (SoC). The SoC may include at least one processor for implementing any of the above methods or implementing the functions of the modules of the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.
[0079] Please refer to Figure 6, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. As shown in Figure 6, the electronic device 600 includes: one or more processors 610; and a memory 620 storing one or more programs thereon. When the one or more programs are executed by the one or more processors 610, the one or more processors 610 implement the memory block processing method described in any of the above embodiments.
[0080] Memory 620, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 620 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 620 may optionally include remotely located memories 620 relative to processor 610, which can be connected to processor 610 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0081] The memory 620 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 620 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 620 and is called and executed by the processor 610.
[0082] The processor 610 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.
[0083] In some embodiments, the electronic device further includes: an input / output interface for inputting and outputting information; a communication interface for communication and interaction between the device and other devices, which can be implemented via wired means (e.g., USB, Ethernet cable, etc.) or wireless means (e.g., mobile network, WIFI, Bluetooth, etc.); and a bus for inputting terminal information between various components of the device (e.g., processor 610, memory 620, input / output interface, and communication interface); wherein the processor 610, memory 620, input / output interface, and communication interface can be interconnected within the device via the bus.
[0084] One embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for performing the storage block processing method described in any of the above embodiments.
[0085] An embodiment of this application also provides a computer program product, including a computer program or computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform a storage block processing method as described in any of the above embodiments.
[0086] The system architecture and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that as system architectures evolve and new application scenarios emerge, the technical solutions provided in this application are also applicable to similar technical problems.
[0087] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0088] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0089] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0090] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of the invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this invention should be considered within the scope of this application.
Claims
1. A method for processing storage blocks, characterized in that, include: A first logical block containing both good and bad blocks in a flash memory chip is disassembled to obtain a first good block; a second logical block in the flash memory chip is disassembled to obtain a second good block, which is a logical block that does not contain bad blocks; the first good block and the second good block are bound together to obtain a third logical block, and the logical block address of the third logical block is configured; a mapping table between the logical block address and the address of the storage block in the third logical block is established and stored, and the mapping table is used to access the storage block in the third logical block.
2. The storage block processing method according to claim 1, characterized in that, Before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining a target logic block in the flash memory chip as the second logic block, wherein the distance between the target logic block and at least two first good blocks is less than a distance threshold; the method of binding the first good block and the second good block to obtain the third logic block includes: binding the first good block to the second good block disassembled from the second logic block corresponding to the first good block to obtain the third logic block, wherein the distance between the first good block and the bound second good block is less than a distance threshold.
3. The storage block processing method according to claim 1, characterized in that, Before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining a first number of the first good block and a second number of storage blocks in the first logic block; and determining a third number of second logic blocks in the flash memory chip based on the first number and the second number, wherein the sum of the number of second good blocks obtained by disassembling the third number of second logic blocks and the first number is an integer multiple of the second number.
4. The storage block processing method according to claim 1, characterized in that, Before disassembling the second logic block in the flash memory chip to obtain the second good block, the method further includes: determining, in the flash memory chip, a logic block adjacent to the first good block as the second logic block.
5. The storage block processing method according to claim 1, characterized in that, The step of binding the first good block and the second good block to obtain the third logical block includes: determining the target number of storage blocks in the second logical block; combining the first good block and the second good block to obtain multiple sets, wherein the sum of the number of the first good block and the second good block in each set is the target number; and binding the first good block and the second good block in each set to obtain the third logical block corresponding to each set.
6. The storage block processing method according to claim 1, characterized in that, The step of disassembling the second logic block in the flash memory chip to obtain the second good block includes: determining a first number of the first good block and a second number of storage blocks in the first logic block; and disassembling the second logic block in the flash memory chip to obtain the second good block when the first number is an integer multiple of the second number.
7. The storage block processing method according to any one of claims 1-6, characterized in that, The step of disassembling the first logic block containing good blocks and bad blocks in the flash memory chip includes: obtaining the total number of bad blocks in the flash memory chip; and disassembling the first logic block containing good blocks and bad blocks in the flash memory chip when the total number is greater than a threshold.
8. A storage block processing apparatus, characterized in that, include: The first processing module is used to disassemble the first logic block containing good blocks and bad blocks in the flash memory chip to obtain the first good block; The second processing module disassembles the second logic block in the flash memory chip to obtain a second good block, which is a logic block that does not contain bad blocks; A binding module is used to bind the first good block and the second good block to obtain a third logical block, and configure the logical block address of the third logical block; an establishment module is used to establish a mapping relationship table between the logical block address and the address of the storage block in the third logical block, and store the mapping relationship table, which is used to access the storage block in the third logical block.
9. An electronic device, characterized in that, include: One or more processors; A memory having one or more programs stored thereon, which, when executed by one or more processors, cause the one or more processors to implement a memory block processing method as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the memory block processing method as described in any one of claims 1-7.