Wake-up detection circuit, wake-up detection method, chip system and electronic equipment

Abstract

The invention provides a wake-up detection circuit, a wake-up detection method, a chip system and electronic equipment. The wake-up detection circuit comprises: a signal latch circuit configured to latch a level state of a wake-up port signal when a chip enters a sleep state; a signal generation circuit configured to generate a wake-up signal based on the level state of the wake-up port signal and the current level state of the wake-up port signal; wherein the wake-up signal is used for waking up the chip. In this way, the awakening scene that the chip is in the sleep state is not limited by the level state of the awakening pin of the chip before sleep, and therefore the flexibility of the awakening detection circuit can be improved.

Description

Wake-up detection circuit, wake-up detection method, chip system and electronic device Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a wake-up detection circuit, a wake-up detection method, a chip system, and an electronic device. Background Technology

[0002] When a chip enters sleep mode, all clock signals in the system containing the chip are usually turned off to reduce power consumption. If the system containing the chip needs to be woken up, the wake-up detection circuit needs to wake up the system by changing the level of the wake-up pin (also known as the wake-up port) on the chip.

[0003] In related technologies, if there is no clock signal, the level of the wake-up pin needs to be adjusted before the chip enters sleep mode so that it can toggle to generate the correct wake-up edge to wake up the system after the chip enters sleep mode. However, this solution is limited by the level of the wake-up pin before the chip enters sleep mode, resulting in poor flexibility of the wake-up detection circuit. Summary of the Invention

[0004] This application provides a wake-up detection circuit, a wake-up detection method, a chip system, and an electronic device, which can improve the flexibility of the wake-up detection circuit by not being limited by the level state of the wake-up pin of the chip before sleep when wake-up is required.

[0005] The technical solution of this application embodiment is implemented as follows: In a first aspect, this application embodiment provides a wake-up detection circuit, including: a signal latching circuit and a signal generating circuit, the signal latching circuit and the signal generating circuit being connected; wherein: the signal latching circuit is configured to latch the level state of the wake-up port signal when the chip enters a sleep state; the signal generating circuit is configured to generate a wake-up signal based on the latched level state of the wake-up port signal and the current level state of the wake-up port signal; wherein, the wake-up signal is used to wake up the chip.

[0006] Secondly, embodiments of this application provide a wake-up detection method applied to a wake-up detection circuit. The wake-up detection method includes: using a signal latching circuit to latch the level state of a wake-up port signal when the chip enters a sleep state; and using a signal generation circuit to generate a wake-up signal based on the latched level state of the wake-up port signal and the current level state of the wake-up port signal; wherein the wake-up signal is used to wake up the chip.

[0007] Thirdly, embodiments of this application provide a chip system including the wake-up detection circuit as described in the first aspect.

[0008] Fourthly, embodiments of this application provide an electronic device including the chip system described in the third aspect.

[0009] This application provides a wake-up detection circuit, a wake-up detection method, a chip system, and an electronic device. By latching the level state of the wake-up port signal of the chip when the chip enters a sleep state, the wake-up port signal can be latched as a reference value regardless of whether it was high or low before the chip entered sleep state. With the latched wake-up port signal level state, a wake-up signal is generated by combining it with the current level state of the wake-up port. This avoids the need to specifically adjust the wake-up port level state before the chip enters sleep state. In other words, the chip can be successfully woken up regardless of the wake-up port level state before it enters sleep state. This not only improves the flexibility of the wake-up detection circuit but also expands its application scenarios. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0011] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0012] Figure 1 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 2 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 3 is a schematic diagram of an asynchronous set / reset flip-flop according to an embodiment of this application; Figure 4 is a schematic diagram of an asynchronous set / reset flip-flop according to an embodiment of this application; Figure 5 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 6 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 7 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 8 is a schematic diagram of a wake-up detection circuit according to an embodiment of this application; Figure 9 is a schematic diagram of the working timing of a wake-up detection circuit according to an embodiment of this application; Figure 10 is a schematic diagram of the working timing of a wake-up detection circuit according to an embodiment of this application; Figure 11 is a schematic diagram of the working timing of a wake-up detection circuit according to an embodiment of this application; Figure 12 is a schematic diagram of the working timing of a wake-up detection circuit according to an embodiment of this application; Figure 13 is a flowchart of a wake-up detection method according to an embodiment of this application; Figure 14 is a schematic diagram of a chip system according to an embodiment of this application; Figure 15 is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0015] In the following description, references to "some embodiments," "this embodiment," "this application embodiment," and examples, etc., describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0016] The descriptions such as "first," "second," and "third" appearing in the embodiments of this application do not have a specific meaning (such as no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application), but are merely for the purpose of clearly describing the embodiments of this application and do not constitute any limitation on the embodiments of this application.

[0017] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies or terms of the embodiments of this application are described below. The following relevant technologies or terms are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0018] To address the problems mentioned in the background art, embodiments of this application provide the following wake-up detection circuit, wake-up detection method, chip system, and electronic device. The wake-up detection circuit includes: a signal latching circuit configured to latch the level state of the wake-up port signal when the chip enters a sleep state; and a signal generation circuit configured to generate a wake-up signal based on the latched level state of the wake-up port signal and the current level state of the wake-up port signal. The wake-up signal is used to wake up the chip. This embodiment latches the level state of the chip's wake-up port signal when the chip enters a sleep state. Thus, regardless of whether the wake-up port signal's level state is high or low before the chip enters sleep, it can be latched as a reference value. With the latched wake-up port signal's level state combined with the current level state of the wake-up port to generate the wake-up signal, the need to specifically adjust the wake-up port's level state before the chip enters sleep state can be avoided. In other words, successful wake-up can be achieved regardless of the wake-up port's level state before the chip enters sleep state. This not only improves the flexibility of the wake-up detection circuit but also expands its application scenarios, while simultaneously improving the overall chip performance and user experience.

[0019] The following sections will describe further optional implementations of the wake-up detection circuit, wake-up detection method, chip system, and electronic device, as well as related terms.

[0020] This application provides a wake-up detection circuit, as shown in FIG1. ​​The wake-up detection circuit 10 provided in this application includes a signal latch circuit 101 and a signal generation circuit 102.

[0021] Specifically, the signal latching circuit 101 and the signal generating circuit 102 are connected.

[0022] Among them: the signal latch circuit 101 is configured to latch the level state of the wake-up port signal wake_gpio when the chip enters the sleep state; the signal generation circuit 102 is configured to generate the wake-up signal gpio_wake_irq based on the latched level state of the wake-up port signal wake_gpio and the current level state of the wake-up port signal wake_gpio.

[0023] The wake-up signal gpio_wake_irq, also known as the wake-up interrupt signal, is used to wake up the chip.

[0024] It is understandable that the wake-up port signal wake_gpio is the signal at the wake-up port of the chip, which can also be called the wake-up pin.

[0025] In one example, the wake port signal wake_gpio can be a high-level wake port signal; in another example, the wake port signal wake_gpio can be a low-level wake port signal.

[0026] Understandably, the wake-up port signal's voltage level remains the same before the chip enters sleep mode. For example, if the wake-up port signal is low before the chip enters sleep mode, it will remain low when the chip enters sleep mode. Conversely, if the wake-up port signal is high before the chip enters sleep mode, it will remain high when the chip enters sleep mode.

[0027] It should be noted that the current level state of the wake-up port signal refers to the new level state of the wake-up port signal generated after the chip enters sleep state and the wake-up port is operated; compared with the current level state of the wake-up port signal, the level state of the wake-up port signal latched by the signal latch circuit 101 when the chip enters sleep state can be regarded as the historical level state of the wake-up port.

[0028] It is understandable that after the chip enters sleep mode, the new wake-up port signal generated after operating the wake-up port can be either low or high.

[0029] Understandably, in this embodiment, by latching the level of the wake-up port signal when the chip enters sleep mode, the level of the wake-up port signal can be latched as a reference value, regardless of whether the level of the wake-up port signal is high or low before the chip enters sleep mode. With the latched level of the wake-up port signal, the wake-up signal can be generated by combining it with the current level of the wake-up port signal. This avoids the need to specifically adjust the level of the wake-up port before the chip enters sleep mode. In other words, the chip can be successfully woken up regardless of the level of the wake-up port before it enters sleep mode. This not only improves the flexibility of the wake-up detection circuit but also expands the application scenarios of the wake-up detection circuit, while also improving the overall performance of the chip and the user experience.

[0030] As an optional embodiment, as shown in FIG2, the signal latching circuit 101 in this application embodiment may include a first flip-flop 101A and a second flip-flop 101B.

[0031] Specifically, the first output terminal of the first flip-flop 101A and the first output terminal of the second flip-flop 101B are respectively connected to the two input terminals of the signal generation circuit 102.

[0032] The first flip-flop 101A is configured to latch the first level state of the wake-up port signal when the chip enters sleep state; the second flip-flop 101B is configured to latch the second level state of the wake-up port signal when the chip enters sleep state.

[0033] The signal generation circuit 102 is configured to generate a wake-up signal gpio_wake_irq based on the first level state of the wake-up port signal, the second level state of the wake-up port signal, and the current level state of the wake-up port signal.

[0034] The first flip-flop 101A and the second flip-flop 101B can be asynchronous set-and-reset flip-flops. The type of asynchronous set-and-reset flip-flop can be an asynchronous set-and-reset D-type flip-flop, an asynchronous set-and-reset SR-type flip-flop, an asynchronous set-and-reset JK-type flip-flop, or even an asynchronous set-and-reset T-type flip-flop, etc. This application does not impose any particular limitation on this; the following description uses the example of both the first flip-flop 101A and the second flip-flop 101B being asynchronous set-and-reset D-type flip-flops for illustrative purposes.

[0035] In this application, the first level state and the second level state are two opposite level states. That is, if the first level state is low, then the second level state is high; if the first level state is high, then the second level state is low. This application does not impose any particular limitation on this, and the following explanation will use the example of the first level state being low and the second level state being high.

[0036] It is understood that in this embodiment, by using two independent triggers to latch different level states of the wake-up port signal and combining them with the current level state of the wake-up port signal, it can be ensured that the wake-up port level state before the chip enters sleep state is not affected, and the wake-up signal can be generated in the absence of a clock, which can improve the applicability of the wake-up detection circuit.

[0037] As an optional embodiment, as shown in Figure 3, the asynchronous set / asynchronous reset D-type flip-flop U includes at least a data input terminal D, an asynchronous set terminal SETB, an asynchronous reset terminal RESETB, and a first output terminal QN.

[0038] Furthermore, as an optional embodiment, as shown in FIG4, the asynchronous set / asynchronous reset D-type flip-flop U may also include a scan chain data output input terminal SCD, a scan chain mode enable terminal SCE, a clock terminal CLK, and a second output terminal Q.

[0039] It should be noted that the signal output by the first output terminal QN is the inverted signal of the signal output by the second output terminal Q, or it can be understood as the signal output by the second output terminal Q being the inverted signal of the signal output by the first output terminal QN.

[0040] It is understandable that different models of asynchronous set / asynchronous reset D-type flip-flops U have different truth tables.

[0041] For example, the asynchronous set / asynchronous reset D-type flip-flop U in this application embodiment is a device based on the HHG 90ULL process platform, and its truth table can be found in Table 1 below.

[0042] Table 1 Truth Table of Asynchronous Set / Reset D-Type Flip-Flop U under HHG 90ULL Process Platform

[0043] It should be noted that "×" in Table 1 indicates that the value of this terminal can be any value. "0" in Table 1 represents a low-level signal, "1" represents a high-level signal, "Q[n+1]" represents the current time of the second output terminal Q, "Q[n]" represents the previous time of the second output terminal Q, "QN[n+1]" represents the current time of the first output terminal QN, and "QN[n]" represents the previous time of the first output terminal QN.

[0044] For the asynchronous set / reset D-type flip-flop U under the HHG 90ULL process platform, as can be seen from the second row of Table 1, when the asynchronous set terminal SETB is 1, the asynchronous reset terminal RESETB is active low. At this time, the first output terminal QN outputs a signal, which appears as a high-level signal 1. When the asynchronous reset terminal RESETB is inactive high, the level of the first output terminal QN is determined by the data input terminal D, the scan chain data output input terminal SCD, the scan chain mode enable terminal SCE, and the clock terminal CLK.

[0045] Understandably, since the truth tables of different models of asynchronous set / reset D-type flip-flops U are different, adjustments can be made to the truth tables of different models of asynchronous set / reset D-type flip-flops U to achieve instantiation. That is, regardless of the model of the asynchronous set / reset D-type flip-flop U, it is connected according to a standard, and the required pins are made active according to a standard. For example, the truth tables of different models of asynchronous set / reset D-type flip-flops U can be adjusted to the truth tables of asynchronous set / reset D-type flip-flops U under the HHG 90ULL process platform shown in Table 1.

[0046] In an optional embodiment, the asynchronous set-asynchronous reset D-type flip-flop U shown in FIG3 can be applied to the first flip-flop 101A. That is, the first flip-flop 101A is an asynchronous set-asynchronous reset D-type flip-flop. For easy distinction, when the first flip-flop 101A is an asynchronous set-asynchronous reset D-type flip-flop, it is called the first asynchronous set-asynchronous reset flip-flop U1.

[0047] Specifically, as shown in Figures 5 to 8, the data input terminal D of the first asynchronous set / reset trigger U1 is used to receive the first data; the asynchronous set terminal SETB of the first asynchronous set / reset trigger U1 is connected to the reset port of the chip and is used to receive the reset signal rstn provided by the reset port of the chip; the asynchronous reset terminal RESETB of the first asynchronous set / reset trigger U1 is configured to output a first wake-up signal latched at the first level state through the first output terminal QN of the first asynchronous set / reset trigger U1 when the wake-up port signal is in the first level state.

[0048] For example, when the first level state is a low level state, the first wake-up signal is gpio_low_flag.

[0049] The purpose of the first asynchronous set / reset flip-flop U1 receiving the first data at its data input terminal D is to clear the signal output from its first output terminal QN after the chip's clock resumes, i.e., to clear the first wake-up signal gpio_low_flag. For example, the first data can be "1", which is a high-level signal.

[0050] In one embodiment, the configuration of the asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 can be implemented through hardware combinational logic.

[0051] Understandably, to implement the hardware combinational logic for the first asynchronous set / reset trigger U1 to latch the wake-up port signal when the chip is in a sleep state (low level), three conditions are required for setting the asynchronous reset terminal RESETB of the first asynchronous set / reset trigger U1: Condition 1: The chip's state is in sleep state (SLEEP). For example, as shown in Figures 5-8, the asynchronous reset terminal RESETB of the first asynchronous set / reset trigger U1 is connected to the output of the first signal logic operation circuit 20. The second input of the first signal logic operation circuit 20 is used to receive the detection result of the chip's state (state). That is, if the chip's state is detected as normal (NORMALL), the received state (state) detection result is state=1; if the chip's state is detected as sleep state (SLEEP), the received state (state) detection result is state=0. Condition 2: The wake-up port's level is low (gpio_low). For example, as shown in Figures 5-8, the asynchronous reset terminal RESETB of the first asynchronous set / reset trigger U1 is connected to the first signal logic operation circuit 20. The first input of the first signal logic operation circuit 20 is used to receive the detection result of the low level state gpio_low of the wake-up port signal. That is, if the low level state of the wake-up port signal is detected, the detection result of the low level state gpio_low of the received wake-up port signal is gpio_low=1; if the low level state of the wake-up port signal is not detected, the detection result of the low level state gpio_low of the received wake-up port signal is gpio_low=0; Condition 3, the first asynchronous set asynchronous reset flip-flop U1 can be in scan chain mode dft_mode The controllable state (i.e., detectable, i.e., dft_mode=1) is exemplarily shown in Figures 5 to 8. The asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 is connected to the output terminal of the first signal logic operation circuit 20. The third input terminal of the first signal logic operation circuit 20 is used to receive the detection result of the scan chain mode dft_mode. That is, if the scan chain mode is detected, the received scan chain mode detection result is dft_mode=1; if the scan chain mode is not detected, the received scan chain mode detection result is dft_mode=0.

[0052] Understandably, if the asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 is active high, then to enable the first asynchronous set / reset flip-flop U1 to latch the wake-up port signal in the low-level state during sleep through hardware combinational logic, the logical relationship between gpio_low, state=SLEEP, and dft_mode=1 is AND. Since the asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 under the HHG 90ULL process platform is active low, according to De Morgan's law, inverting (gpio_low and state=SLEEP and dft_mode=1) yields a NOT (gpio_low or state=SLEEP or dft_mode=1), i.e., NOT gpio_low OR NOT state=SLEEP OR NOT dft_mode=1.

[0053] This can be written as a combinational logic expression, for example, RESETB ((~gpio_low) | (state == NORMAL) | dft_mode).

[0054] Among them, "~gpio_low" means "not gpio_low"; "state == NORMAL" means "not state=SLEEP", that is, "state=1", which means that the chip's state is the normal state NORMAL; "dft_mode" means "not dft_mode=1", that is, "dft_mode=0"; "|" represents the logical relationship of "OR".

[0055] In other words, since the asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 under the HHG 90ULL process platform is active low, the combinational logic expression must be written as RESETB ((~gpio_low) | (state ==NORMAL) | dft_mode) to indicate that the asynchronous reset terminal RESETB of the first asynchronous set / reset flip-flop U1 is active low under the wake-up port signal when the chip is in sleep mode. Only in this way can the low-level wake-up port signal be latched, and then the first wake-up signal gpio_low_flag is output at the first output port QN.

[0056] The first signal logic operation circuit 20 may include logic gates such as AND gates, OR gates, and NOT gates to realize the combinational logic expression RESETB ((~gpio_low) | (state == NORMAL) | dft_mode).

[0057] It is understood that in this embodiment, by using an asynchronous reset and asynchronous set trigger to achieve stable latching of the first level state of the wake-up port signal, it can be independent of the clock signal control and reduce power consumption.

[0058] In an optional embodiment, the asynchronous set-asynchronous reset D-type flip-flop U shown in FIG3 can be applied to the second flip-flop 101B. That is, the second flip-flop 101B is an asynchronous set-asynchronous reset D-type flip-flop. For easy distinction, when the second flip-flop 101B is an asynchronous set-asynchronous reset D-type flip-flop, it is called the second asynchronous set-asynchronous reset flip-flop U2.

[0059] Specifically, as shown in Figures 5-8, the data input terminal D of the second asynchronous set / reset trigger U2 is used to receive the first data; the asynchronous set terminal SETB of the second asynchronous set / reset trigger U2 is connected to the reset port of the chip and is used to receive the reset signal rstn provided by the reset port of the chip; the asynchronous reset terminal RESETB of the second asynchronous set / reset trigger U2 is configured to output a second wake-up signal latched at the second level state through the first output terminal QN of the second asynchronous set / reset trigger U2 when the wake-up port signal is in the second level state.

[0060] For example, when the second level state is a high level state, the second wake-up signal is gpio_high_flag.

[0061] The purpose of the data input terminal D of the second asynchronous set / reset flip-flop U2 receiving the first data is to clear the signal output by the first output terminal QN of the second asynchronous set / reset flip-flop U1 after the chip clock is restored, that is, to clear the second wake-up signal gpio_high_flag.

[0062] In one embodiment, the configuration of the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 can be implemented through hardware combinational logic.

[0063] Understandably, to implement the second asynchronous set / reset trigger U2 latching the wake-up port signal when the chip is in sleep mode using hardware combinational logic, three conditions are required for setting the asynchronous reset terminal RESETB of the second asynchronous set / reset trigger U2: Condition 1: The chip's state is sleep mode (SLEEP). For example, continuing as shown in Figures 5-8, the asynchronous reset terminal RESETB of the second asynchronous set / reset trigger U2 is connected to the output of the second signal logic operation circuit 30. The second input of the second signal logic operation circuit 30 is used to receive the detection result of the chip's state (state). That is, if the chip's state is detected as normal (NORMALL), the received state detection result is state=1; if the chip's state is detected as sleep mode (SLEEP), the received state detection result is state=0. Condition 2: The wake-up port's level is high (gpio_high). For example, continuing as shown in Figures 5-8, the asynchronous reset terminal RESETB of the second asynchronous set / reset trigger U2 is connected to the output of the second signal logic operation circuit 30. At the output terminal, the first input terminal of the second signal logic operation circuit 30 is used to receive the detection result of the high-level state gpio_high of the wake-up port signal. That is, if the high-level state of the wake-up port signal is detected, the detection result of the high-level state gpio_high of the received wake-up port signal is gpio_high=1; if the high-level state of the wake-up port signal is not detected, the detection result of the low-level state gpio_high of the received wake-up port signal is gpio_high=0; Condition 3, the second asynchronous set / reset flip-flop U2 can be in scan chain mode dft_mod Under the condition that it is controllable (i.e., it can be tested, that is, dft_mode=1), for example, continuing as shown in Figures 5 to 8, the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 is connected to the output terminal of the second signal logic operation circuit 30. The third input terminal of the second signal logic operation circuit 30 is used to receive the detection result of the scan chain mode dft_mode. That is, if it is detected that it is in the scan chain mode, the received detection result of the scan chain mode is dft_mode=1, and if it is detected that it is not in the scan chain mode, the received detection result of the scan chain mode is dft_mode=0.

[0064] Understandably, if the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 is active high, then to enable the second asynchronous set / reset flip-flop U2 to latch the wake-up port signal in the high-level state during sleep mode through hardware combinational logic, the logical relationship between gpio_high, state=SLEEP, and dft_mode=1 is AND. Since the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 under the HHG 90ULL process platform is active low, according to De Morgan's law, inverting (gpio_high and state=SLEEP and dft_mode=1) yields a NOT (gpio_high or state=SLEEP or dft_mode=1), i.e., NOT gpio_high or NOT state=SLEEP or NOT dft_mode=1.

[0065] This can be written as a combinational logic expression, for example, RESETB ((~gpio_high) | (state == NORMAL) | dft_mode).

[0066] Here, "~gpio_high" means "not gpio_high".

[0067] In other words, since the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 under the HHG 90ULL process platform is active low, the combinational logic expression must be written as RESETB ((~gpio_high) | (state ==NORMAL) | dft_mode) to indicate that the asynchronous reset terminal RESETB of the second asynchronous set / reset flip-flop U2 is active under the wake-up port signal in the high-level state when the chip is in sleep mode. Only in this way can the high-level wake-up port signal be latched, and then the second wake-up signal gpio_high_flag is output at the first output port QN.

[0068] The second signal logic operation circuit 30 may include AND gates, OR gates, NOT gates and other logic operation gates to realize the combinational logic expression RESETB ((~gpio_high) | (state == NORMAL) | dft_mode).

[0069] It is understood that in this embodiment, by using an asynchronous reset and asynchronous set trigger to achieve stable latching of the second level state of the wake-up port signal, it can be independent of the clock signal control and reduce power consumption.

[0070] As an optional embodiment, as shown in FIG6, the signal generation circuit 102 provided in this application embodiment may include a signal logic circuit 102A and a third flip-flop 102B.

[0071] Specifically, the signal logic circuit 102A is configured to perform logical operations based on the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the current level state of the wake-up port signal to generate a wake-up edge signal wake_edge, which is then input to the reset terminal of the third flip-flop 102B.

[0072] The third flip-flop 102B is configured to output a wake-up signal gpio_wake_irq through the first output terminal of the third flip-flop when a wake-up edge signal wake_edge is received at the reset terminal of the third flip-flop 102B.

[0073] When the third flip-flop 102B is an asynchronous set and asynchronous reset flip-flop, the signal logic circuit 102A is also used to invert the wake-up edge signal wake_edge. Then the reset terminal of the third flip-flop 102B receives the inverted wake-up edge signal ~wake_edge.

[0074] In one embodiment, the configuration of the signal logic circuit 102A can be implemented by hardware combinational logic, such as including AND gates, OR gates, NOT gates and other logic operation gates, as long as they can realize combinational logic expressions.

[0075] For example, the combinational logic expression of signal logic circuit 102A is: assign wake_edge = wake_negedge ? (gpio_high&gpio_low_flag): wake_posedge ? (gpio_low&gpio_high_flag): 1'b0; where “wake_posedge” represents the rising edge trigger signal; “wake_negedge” represents the falling edge trigger signal; “gpio_high” indicates that the current level of the wake-up port signal is high, i.e., “gpio_high=1”; “gpio_low” indicates that the current level of the wake-up port signal is low, i.e., “gpio_low_flag”; “gpio_low_flag” indicates that the latched chip is in a sleep state when the wake-up port signal appears low, i.e., “gpio_low_flag=1”; “gpio_high_flag” indicates that the latched chip is in a sleep state when the wake-up port signal appears high, i.e., “gpio_high_flag=1”; “1'b0” represents a 1-bit wide binary number with a value of 0; “&” represents the logical relationship of “AND”.

[0076] It should be noted that when wake_negedge is true, wake_edge = (gpio_high&gpio_low_flag), which means that when the current level of the wake-up port signal is high and the level of the wake-up port signal in the latched sleep state is low, a falling edge trigger signal is generated, and the wake-up edge signal wake_edge is valid, that is, wake_edge=1.

[0077] It should be noted that when wake_negedge is false, wake_edge = wake_posedge ?(gpio_low&gpio_high_flag).

[0078] When wake_posedge is true, wake_edge = (gpio_low&gpio_high_flag), which means that when the current level of the wake-up port signal is low and the level of the wake-up port signal in the latched sleep state is high, a rising edge trigger signal is generated, and the wake-up edge signal wake_edge is valid, that is, wake_edge=1.

[0079] When wake_posedge is false, wake_edge=1'b0, and the output is low, i.e., wake_edge=0.

[0080] It should be noted that a valid wake-up edge signal (wake_edge) indicates that the type of the generated wake-up edge signal conforms to the preset edge signal trigger type. For example, if the preset edge signal trigger type is rising edge triggering, then the wake-up edge signal (wake_edge) is also a rising edge signal, and therefore valid (wake_edge = 1). Similarly, if the preset edge signal trigger type is falling edge triggering, then the wake-up edge signal (wake_edge) is also a falling edge signal, and therefore valid (wake_edge = 1). An invalid wake-up edge signal (wake_edge) indicates that the type of the generated wake-up edge signal does not conform to the preset edge signal trigger type; in this case, wake_edge = 0.

[0081] It is understood that in this embodiment, multiple wake-up signals are processed by signal logic circuits to generate accurate wake-up edge signals, and a stable wake-up signal is output through a third flip-flop. This ensures the reliability and timeliness of the wake-up process and reduces reliance on external software intervention.

[0082] In an optional embodiment, the asynchronous set / asynchronous reset D-type flip-flop U shown in FIG3 can be applied to the third flip-flop 102B. That is, the third flip-flop 102B is an asynchronous set / asynchronous reset D-type flip-flop. For easy distinction, when the third flip-flop 102B is an asynchronous set / asynchronous reset D-type flip-flop, it is called the third asynchronous set / asynchronous reset flip-flop U3.

[0083] Specifically, as shown in Figures 7 and 8, the asynchronous set terminal SETB of the third asynchronous set / reset flip-flop U3 is connected to the reset port of the chip to receive the reset signal rstn; the asynchronous reset terminal RESETB of the third asynchronous set / reset flip-flop U3 is connected to the output terminal of the signal logic circuit 102A; the data input terminal D of the third asynchronous set / reset flip-flop U3 is configured to receive the wake-up inverted signal ~gpio_wake_irq, or it is also configured to receive the interrupt clear signal gpio_wake_irq_clr.

[0084] Among them, the inverted wake-up signal ~gpio_wake_irq is used to keep the first output terminal QN of the third asynchronous set asynchronous reset flip-flop U3 and keep the output wake-up signal gpio_wake_irq; the interrupt clear signal gpio_wake_irq_clr is used to clear the wake-up signal gpio_wake_irq.

[0085] In one embodiment, the configuration of the data input terminal D of the third asynchronous set / reset flip-flop U3 can be implemented by hardware circuitry.

[0086] For example, continuing as shown in Figures 7 and 8, the first output terminal QN of the third asynchronous set / reset flip-flop U3 is connected to the first input terminal of the third signal logic operation circuit 40, the second input terminal of the third signal logic operation circuit 40 is used to receive the interrupt clear signal gpio_wake_irq_clr, and the output terminal of the third signal logic operation circuit 40 is connected to the data input terminal D of the third asynchronous set / reset flip-flop U3.

[0087] The third signal logic operation circuit 40 may include logic operation gates such as AND gates, OR gates, and NOT gates. After receiving the interrupt clear signal gpio_wake_irq_clr and the wake-up signal gpio_wake_irq, it performs logic operations to ensure that the first output terminal QN of the third asynchronous set-asynchronous reset flip-flop U3 maintains the output wake-up signal gpio_wake_irq, while also allowing the software to clear the wake-up signal gpio_wake_irq. In other words, it needs to implement the hardware combinational logic expression (gpio_wake_irq_clr | (~gpio_wake_irq_)).

[0088] It is understood that in this embodiment, by introducing an inverted signal or an interrupt clear signal for the wake-up signal, the holding and clearing of the wake-up signal can be flexibly controlled. This ensures the stability of the wake-up signal and facilitates the clearing of the wake-up signal after the chip is woken up, thereby enhancing the controllability and maintainability of the wake-up detection circuit. In addition, by using an asynchronous reset and asynchronous set trigger to hold and clear the wake-up signal, it can be independent of the clock signal and reduce power consumption.

[0089] As another alternative implementation, the asynchronous set and asynchronous reset triggers shown in FIG4 can be applied to the first trigger 101A, the second trigger 101B and the third trigger 102B.

[0090] As shown in Figure 8, the first asynchronous set / reset trigger U1 may further include a scan chain data input terminal SCD, a scan chain mode enable terminal SCE, a clock terminal CLK, and a second output terminal Q; the second asynchronous set / reset trigger U2 may further include a scan chain data input terminal SCD, a scan chain mode enable terminal SCE, a clock terminal CLK, and a second output terminal Q; the third asynchronous set / reset trigger U3 may further include a scan chain data output / input terminal SCD, a scan chain mode enable terminal SCE, a clock terminal CLK, and a second output terminal Q.

[0091] As shown in Figure 8, at this time, the scan chain data input terminal SCD and the scan chain mode enable terminal SCE of the first asynchronous set / reset flip-flop U1 are used to receive the second data; the clock terminal CLK of the first asynchronous set / reset flip-flop U1 is used to receive the clock signal clk.

[0092] As shown in Figure 8, at this time, the scan chain data input terminal SCD and the scan chain mode enable terminal SCE of the second asynchronous set / reset flip-flop U2 are used to receive the second data; the clock terminal CLK of the second asynchronous set / reset flip-flop U2 is used to receive the clock signal clk.

[0093] As shown in Figure 8, at this time, the scan chain data input terminal SCD and the scan chain mode enable terminal SCE of the third asynchronous set / reset flip-flop U3 are used to receive the second data; the clock terminal CLK of the third asynchronous set / reset flip-flop U3 is used to receive the clock signal clk.

[0094] The second data can be "0", which is a low-level signal.

[0095] The clock signal clk can come from the chip's clock. When the chip's clock is enabled (i.e., clock recovery), it can generate a clock signal clk, which is then input to the clock terminals CLK of the first asynchronous set / reset flip-flop U1, the second asynchronous set / reset flip-flop U2, and the third asynchronous set / reset flip-flop U3, respectively.

[0096] In one embodiment, the function of latching the low-level state of the wake-up port signal when the latch chip enters sleep state is implemented by reasonably connecting the various ports of the first asynchronous set asynchronous reset flip-flop U1. The hardware combinational logic expression is as follows: For example: TLSCL7CNMV0_SDFBBP_1 u_gpio_low_flag(.Q (),.QN (gpio_low_flag),.D (1'b1),.CLK (clk),.SETB (rstn),.RESETB ((~gpio_low) | (state == NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0)); where "TLSCL7CNMV0_SDFBBP_1" represents a model of an asynchronous reset asynchronous set D flip-flop under the HHG 90ULL process platform; "1'b1" represents a 1-bit wide binary number with a value of 1.

[0097] Similarly, the function of latching the high-level state of the wake-up port signal when the latch chip enters sleep state, implemented by the second asynchronous set / reset trigger U2, is achieved by reasonably connecting the various ports of the second asynchronous set / reset trigger U2. The hardware combinational logic expression is as follows: For example: TLSCL7CNMV0_SDFBBP_1 u_gpio_high_flag(.Q (),.QN (gpio_high_flag),.D (1'b1),.CLK (clk),.SETB (rstn),.RESETB ((~gpio_high) | (state == NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0)); Similarly, the function of generating the wake-up signal gpio_wake_irq when the latch chip enters sleep state, implemented by the third asynchronous set / reset trigger U3, is also achieved by reasonably connecting the various ports of the second asynchronous set / reset trigger U3. The hardware combinational logic expression is as follows: For example: assign wake_edge = wake_negedge ? (gpio_high&gpio_low_flag):wake_posedge ? (gpio_low&gpio_high_flag ): 1'b0;TLSCL7CNMV0_SDFBBP_1 u_gpio_wake_irq(.Q (),.QN (gpio_wake_irq),.D (gpio_wake_irq_clr | (~gpio_wake_irq_)),.CLK (clk),.SETB (rstn),.RESETB ((~wake_edge) | (state==NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0));The working principle of the wake-up detection circuit provided in the embodiments of this application will be described in detail below with reference to Figure 8 and Figures 9 to 12.

[0098] As shown in Figure 9, before entering sleep mode, the chip's clock is enabled, and the clock enable signal clk_en is clk_en=1, allowing the output of the clock signal clk. If the wake-up port signal wake_gpio is low before entering sleep mode, then gpio_low=1, and gpio_high=0. When the chip enters sleep mode, the clock is disabled, and the clock enable signal clk_en is clk_en=0, preventing the output of the clock signal clk. At this time, the first asynchronous set / reset trigger U1 latches the low-level (first level) wake-up port signal gpio_low=1, outputting the first wake-up signal gpio_low_flag. Since gpio_low_flag=1, the second asynchronous set / reset trigger U2 is ineffective, and the second wake-up signal gpio_high_flag is gpio_high_flag=0.

[0099] If the chip's trigger type is rising edge trigger wake-up, then the current level of the wake-up port signal is in a high level state. This can be achieved by pulling the wake-up port high. At this time, the wake-up port signal wake_gpio is in a high level state, i.e., gpio_high=1.

[0100] By pulling the wake-up port 20 high, the wake-up port signal wake_gpio is flipped from its latched first level (low level) to its current high level, generating a first rising edge trigger signal (i.e., generating a wake-up edge signal that satisfies rising edge trigger wake-up). At this time, the wake-up edge signal wake_edge is valid, i.e., wake_edge=1. After inversion, the third asynchronous set / reset flip-flop U3 is valid, outputting the wake-up signal gpio_wake_irq=1. The wake-up signal gpio_wake_irq turns on the chip's clock, meaning the chip's clock is re-enabled. The clock enable signal clk_en is displayed as clk_en=1, and the clock signal clk can continue to be output. The wake-up signal gpio_wake_irq will remain at 1. Then, after the chip's state machine receives the clock signal clk, it switches to the normal state. At this time, the software can generate an interrupt clear signal gpio_wake_irq_clr to clear the wake-up signal gpio_wake_irq by clearing the interrupt.

[0101] As shown in Figure 10, before entering sleep mode, the chip's clock is enabled, and the clock enable signal clk_en is clk_en=1, allowing the output of the clock signal clk. If the wake-up port signal wake_gpio is high before entering sleep mode, then gpio_high=1, and gpio_low=0. When the chip enters sleep mode, the clock is off, and the clock enable signal clk_en is clk_en=0, preventing the output of the clock signal clk. At this time, the second asynchronous set / reset trigger U2 latches the high-level (second-level) wake-up port signal gpio_high=1 and outputs the second wake-up signal gpio_high_flag, which is now gpio_high_flag=1. The first asynchronous set / reset trigger U1 is ineffective, so the first wake-up signal gpio_low_flag is gpio_low_flag=0.

[0102] If the chip's trigger type is rising edge triggered wake-up, the current level of the wake-up port signal can be flipped from low to high by first pulling the wake-up port low and then high. First, pull the wake-up port low; at this point, the wake-up port signal wake_gpio is low (gpio_low=1). The first asynchronous set / reset flip-flop U1 latches the low-level wake-up port signal gpio_low=1 and outputs the first wake-up signal gpio_low_flag, at which point gpio_low_flag=1. Then, pull the wake-up port high; at this point, the wake-up port signal wake_gpio is high (gpio_high=1).

[0103] By first pulling the wake-up port low and then pulling it high, the wake-up port signal wake_gpio can be flipped from the latched second level state (i.e., high level state) to low level state, and then flipped back to the current high level state, in order to generate the second rising edge trigger signal (i.e., generate the wake-up edge signal that satisfies the rising edge trigger wake-up). At this time, the wake-up edge signal wake_edge is valid, i.e., wake_edge=1. After inversion, the third asynchronous set and asynchronous reset flip-flop U3 is valid, and the wake-up signal gpio_wake_irq=1 is output. The wake-up signal gpio_wake_irq turns on the chip's clock, that is, the chip's clock is re-enabled. The clock enable signal clk_en is clk_en=1, and the clock signal clk can continue to be output. The wake-up signal gpio_wake_irq will remain at 1. Then, after the chip's state machine receives the clock signal clk, it switches to the normal state. At this time, the software can generate an interrupt clear signal gpio_wake_irq_clr to clear the wake-up signal gpio_wake_irq by clearing the interrupt.

[0104] It is understood that in this embodiment, by dynamically adjusting the wake-up port when the first level state of the latched wake-up port signal is low or when the second level state of the latched wake-up port signal is high, thereby changing the level state of the wake-up port signal, a wake-up edge signal that satisfies the rising edge trigger wake-up can be actively generated. Thus, regardless of the initial level of the wake-up port signal, the wake-up condition can be met, significantly improving the universal applicability of the wake-up detection circuit.

[0105] As shown in Figure 11, before entering sleep mode, the chip's clock is enabled, and the clock enable signal clk_en is clk_en=1, allowing the output of the clock signal clk. If the wake-up port signal wake_gpio is low before entering sleep mode, then gpio_low=1, and gpio_high=0. When the chip enters sleep mode, the clock is disabled, and the clock enable signal clk_en is clk_en=0, preventing the output of the clock signal clk. At this time, the first asynchronous set / reset trigger U1 latches the low-level wake-up port signal gpio_low=1 and outputs the first wake-up signal gpio_low_flag, which is now gpio_low_flag=1. The second asynchronous set / reset trigger U2 is ineffective, so the second wake-up signal gpio_high_flag is gpio_high_flag=0.

[0106] If the chip's trigger type is falling edge triggered wake-up, the current level of the wake-up port signal can be flipped from high to low by first pulling the wake-up port high and then low. First, pull the wake-up port high; at this point, the wake-up port signal `wake_gpio` is high (`gpio_high=1`). The second asynchronous set / reset flip-flop U2 latches the high-level wake-up port signal `gpio_high=1` and outputs the second wake-up signal `gpio_high_flag`, which is now 1. Then, pull the wake-up port low; at this point, the wake-up port signal `wake_gpio` is low (`gpio_low=1`).

[0107] By first pulling the wake-up port high and then pulling it low, the wake-up port signal wake_gpio can be flipped from the latched first level state (i.e., low level state) to a high level state, and then flipped back to the current low level state, in order to generate the first falling edge trigger signal (i.e., generate a wake-up edge signal that satisfies the falling edge trigger wake-up). At this time, the wake-up edge signal wake_edge is valid, i.e., wake_edge=1. After inversion, the third asynchronous set and asynchronous reset flip-flop U3 is valid, and the wake-up signal gpio_wake_irq=1 is output. The wake-up signal gpio_wake_irq turns on the chip's clock, that is, the chip's clock is re-enabled. The clock enable signal clk_en is represented as clk_en=1, and the clock signal clk can continue to be output. The wake-up signal gpio_wake_irq will remain at 1. Then, after the chip's state machine receives the clock signal clk, it switches to the normal state. At this time, the software can generate an interrupt clear signal gpio_wake_irq_clr to clear the wake-up signal gpio_wake_irq by clearing the interrupt.

[0108] As shown in Figure 12, before entering sleep mode, the chip's clock is enabled, and the clock enable signal clk_en is clk_en=1, allowing the output of the clock signal clk. If the wake-up port signal wake_gpio is high before entering sleep mode, then gpio_high=1, and gpio_low=0. When the chip enters sleep mode, the clock is off, and the clock enable signal clk_en is clk_en=0, preventing the output of the clock signal clk. At this time, the second asynchronous set / reset trigger U2 latches the high-level wake-up port signal gpio_high=1 and outputs the second wake-up signal gpio_high_flag, which is now gpio_high_flag=1. The first asynchronous set / reset trigger U1 is ineffective, so the first wake-up signal gpio_low_flag is gpio_low_flag=0.

[0109] If the chip's trigger type is falling edge triggered wake-up, then the current level of the wake-up port signal is in a low state, which can be achieved by pulling the wake-up port low. Pulling the wake-up port low will cause the wake-up port signal wake_gpio to be in a low state, i.e., gpio_low=1.

[0110] By pulling the wake-up port low, the wake-up port signal wake_gpio is flipped from the latched second level (i.e., high level) to the current low level, generating the second falling edge trigger signal (i.e., generating a wake-up edge signal that satisfies falling edge trigger wake-up). At this time, the wake-up edge signal wake_edge is valid, i.e., wake_edge=1. After inversion, the third asynchronous set / reset flip-flop U3 is valid, outputting the wake-up signal gpio_wake_irq=1. The wake-up signal gpio_wake_irq turns on the chip's clock, that is, the chip's clock is re-enabled, and the clock enable signal clk_en is displayed as clk_en=1, and the clock signal clk can continue to be output. The wake-up signal gpio_wake_irq will remain at 1. Then, after the chip's state machine receives the clock signal clk, it switches to the normal state. At this time, the software can generate an interrupt clear signal gpio_wake_irq_clr to clear the wake-up signal gpio_wake_irq by clearing the interrupt.

[0111] It is understood that in this embodiment, by dynamically adjusting the wake-up port when the first level state of the latched wake-up port signal is low or when the second level state of the latched wake-up port signal is low, thereby changing the level state of the wake-up port signal, a wake-up edge signal that satisfies the falling edge trigger wake-up can be actively generated. Thus, regardless of the initial level of the wake-up port signal, the wake-up condition can be met, significantly improving the universal applicability of the wake-up detection circuit.

[0112] In the embodiments of this application, a wake-up detection method is also provided, which is applied to the wake-up detection circuit 10. As shown in FIG13, the wake-up detection method includes the following steps: S1301, using a signal latching circuit to latch the level state of the wake-up port signal when the chip enters a sleep state.

[0113] Among them, the signal latch circuit is the signal latch circuit 101 in the wake-up detection circuit 10; when the chip enters the sleep state, the level of the wake-up port signal wake_gpio can be either high or low.

[0114] S1302. Using a signal generation circuit, a wake-up signal is generated based on the level state of the latched wake-up port signal and the current level state of the wake-up port signal.

[0115] The signal generation circuit is the signal generation circuit 101 in the wake-up detection circuit 10; the wake-up signal gpio_wake_irq is used to wake up the chip.

[0116] It should be noted that the current level state of the wake-up port signal refers to the new level state of the wake-up port signal generated after the chip enters sleep state and the wake-up port is operated; compared with the current level state of the wake-up port signal, the level state of the wake-up port signal latched by the signal latch circuit 101 when the chip enters sleep state can be regarded as the historical level state of the wake-up port.

[0117] It is understandable that after the chip enters sleep mode, the new wake-up port signal generated after operating the wake-up port can be either low or high.

[0118] Understandably, in this embodiment, by latching the level of the wake-up port signal of the chip when the chip enters sleep mode, the level of the wake-up port signal can be latched as a reference value, regardless of whether the level of the wake-up port signal is high or low before the chip enters sleep mode. With the latched level of the wake-up port signal, the correct wake-up signal can be generated by combining it with the current level of the wake-up port. This avoids the need to specifically adjust the level of the wake-up port before the chip enters sleep mode. In other words, the chip can be successfully woken up regardless of the level of the wake-up port before it enters sleep mode, which improves the flexibility of the wake-up detection circuit and enhances the user experience.

[0119] As an optional embodiment, when the signal latch circuit 101 includes a first flip-flop 101A and a second flip-flop 101B, the wake-up detection method provided in this application embodiment further includes the following steps: S1301A, using the first flip-flop 101A, latching the first level state of the wake-up port signal when the chip enters the sleep state.

[0120] In one optional embodiment, the first trigger 101A can be an asynchronous set and asynchronous reset trigger. In this case, when the wake-up port signal is in the first level state, the first output terminal of the first trigger 101A outputs a first wake-up signal that latches the first level state.

[0121] S1301B uses the second flip-flop 101B to latch the second level state of the wake-up port signal when the chip enters sleep state.

[0122] As another alternative embodiment, the second flip-flop 101B can be an asynchronous set and asynchronous reset flip-flop. In this case, when the wake-up port signal is in the second level state, the asynchronous reset terminal of the second flip-flop 101B can be used to output a second wake-up signal that latches the second level state through the first output terminal of the second flip-flop 101B.

[0123] The first level state and the second level state are two opposite level states.

[0124] That is, when the first level state is high, the second level state is low; and when the first level state is low, the second level state is high. This application does not impose any particular limitation on this; the following explanation will use an example where the first level state is low and the second level state is high. In this case, the first wake-up signal latched for the first level state is the first wake-up signal gpio_low_flag; and the second wake-up signal latched for the second level state is the second wake-up signal gpio_high_flag.

[0125] S1302A: The signal generation circuit 102 generates a wake-up signal based on the first level state of the wake-up port signal, the second level state of the wake-up port signal, and the current level state of the wake-up port signal.

[0126] Understandably, by using two independent flip-flops to latch different level states of the wake-up port signal and combining them with the current level state of the wake-up port signal, it can be ensured that the wake-up port level state before the chip enters sleep state is not affected, and the wake-up edge signal can be generated in the absence of a clock, which can improve the applicability of the wake-up detection circuit.

[0127] Understandably, by using an asynchronous reset and asynchronous set trigger to stably latch the first and second level states of the wake-up port signal, it can be independent of the clock signal and reduce power consumption.

[0128] As an optional embodiment, the signal generation circuit 102 may include a signal logic circuit 102A and a third flip-flop 102B. In this case, the wake-up detection method provided in this application embodiment includes: using the signal logic circuit 102A to perform logical operations based on the current level state of the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the wake-up port signal wake_gpio, generating a wake-up edge signal wake_edge, and inputting it to the reset terminal of the third flip-flop 102B.

[0129] The wake-up edge signal wake_edge is input to the reset terminal of the third flip-flop 102B, and the wake-up signal gpio_wake_irq is generated through the first output terminal of the third flip-flop 102B.

[0130] The wake-up signal gpio_wake_irq is used to turn on the chip's clock to wake it up.

[0131] In one example, the third flip-flop 102B can be an asynchronous set / reset flip-flop. In this case, the reset terminal of the third flip-flop 102B is the asynchronous reset terminal RESETB of the asynchronous set / reset flip-flop; the first output terminal of the third flip-flop 102B is the first output terminal QN of the asynchronous reset flip-flop. It should be noted that when the third flip-flop 102B is an asynchronous set / reset flip-flop, the signal logic circuit 102A also needs to invert the wake-up edge signal wake_edge, so that the asynchronous reset terminal RESETB of the third flip-flop 102B is valid, and the wake-up signal gpio_wake_irq can be output at the first output terminal of the third flip-flop 102B.

[0132] Understandably, by integrating multiple wake-up signals through signal logic circuits to generate precise wake-up edge signals and outputting stable wake-up signals through a third flip-flop, the reliability and timeliness of the wake-up process can be ensured, while also reducing reliance on external software intervention.

[0133] In one example, using signal logic circuit 102A to perform logical operations based on the current level states of the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the wake-up port signal wake_gpio to generate a wake-up edge signal wake_edge may include: using signal logic circuit 102A, when the chip's trigger type is rising edge trigger wake-up and the first wake-up signal is in a low level state, controlling the current level state of the wake-up port signal to be in a high level state to generate a wake-up edge signal that satisfies rising edge trigger wake-up.

[0134] One way to control the wake-up port signal is to keep it at a high level by pulling it high.

[0135] Understandably, when the chip enters sleep mode, the wake-up port signal is at a low level. The first flip-flop 101A latches the low-level wake-up port signal and outputs the first wake-up signal gpio_low_flag=1. When the chip's trigger type is rising edge trigger wake-up, since the wake-up port signal is at a low level when the chip enters sleep mode, in order to generate a rising edge, the wake-up port of the chip is pulled high, which allows the wake-up port signal to flip from the latched low level state (i.e., the first level state) to the current high level state. This generates a wake-up edge signal that satisfies rising edge trigger wake-up. The wake-up edge signal in this case is called the first rising edge trigger signal. At this time, the wake-up edge signal wake_edge is valid.

[0136] In one example, using signal logic circuit 102A to perform logical operations based on the current level states of the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the wake-up port signal wake_gpio to generate a wake-up edge signal wake_edge may include: using signal logic circuit 102A, when the chip's trigger type is rising edge trigger wake-up and the second wake-up signal is in a high level state, controlling the current level state of the wake-up port signal to flip from a low level state to a high level state to generate a wake-up edge signal that satisfies rising edge trigger wake-up.

[0137] One method is to first pull the wake-up port low and then pull it high to change the current level of the wake-up port signal from low to high.

[0138] Understandably, when the chip enters sleep mode, the wake-up port signal is at a high level. The second flip-flop 101B latches the high-level wake-up port signal and outputs the second wake-up signal gpio_high_flag=1. When the chip's trigger type is rising edge trigger wake-up, since the wake-up port signal is at a high level when the chip enters sleep mode, in order to generate a rising edge, by first pulling the chip's wake-up port low and then pulling it high, the wake-up port signal can be flipped from the latched high level state (i.e., the second level state) to a low level state and then to the current high level state. This generates a wake-up edge signal that satisfies rising edge trigger wake-up. The wake-up edge signal in this case is called the second rising edge trigger signal. At this time, the wake-up edge signal wake_edge is valid.

[0139] It is understood that in this embodiment, by dynamically adjusting the wake-up port when the first level state of the latched wake-up port signal is low or when the second level state of the latched wake-up port signal is high, the level state of the wake-up port signal can be changed, thereby actively generating a wake-up edge signal that satisfies the rising edge triggering wake-up. Thus, regardless of the initial level, the wake-up condition can be met, significantly improving the universal applicability of the wake-up detection circuit.

[0140] In one example, using signal logic circuit 102A to perform logical operations based on the current level states of the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the wake-up port signal wake_gpio to generate a wake-up edge signal wake_edge may include: using signal logic circuit 102A, when the chip's trigger type is falling edge trigger wake-up and the first wake-up signal is in a low level state, controlling the current level state of the wake-up signal to flip from a high level state to a low level state to generate a wake-up edge signal that satisfies falling edge trigger wake-up.

[0141] One method is to first pull the wake-up port high and then pull it low to change the current level of the wake-up port signal from high to low.

[0142] It is understandable that when the chip enters sleep mode, the wake-up port signal is at a low level. The first flip-flop 101A latches the low-level wake-up port signal and outputs the first wake-up signal gpio_low_flag=1. When the chip's trigger type is falling edge trigger wake-up, since the wake-up port signal is at a low level when the chip enters sleep mode, in order to generate a falling edge, by pulling the chip's wake-up port high and then pulling it low, the wake-up port signal can be flipped from the latched low level state (i.e., the first level state) to a high level state and then to the current low level state. This generates a wake-up edge signal that satisfies falling edge trigger wake-up. The wake-up edge signal in this case is called the first falling edge trigger signal. At this time, the wake-up edge signal wake_edge is valid.

[0143] In one example, using signal logic circuit 102A to perform logical operations based on the current level states of the first wake-up signal gpio_low_flag, the second wake-up signal gpio_high_flag, and the wake-up port signal wake_gpio to generate a wake-up edge signal wake_edge may include: using signal logic circuit 102A, when the chip's trigger type is falling edge trigger wake-up and the second wake-up signal is in a high level state, controlling the current level state of the wake-up port signal to be in a low level state to generate a wake-up edge signal that satisfies falling edge trigger wake-up.

[0144] One way to control the wake-up port signal is to keep it at a low level by pulling it down.

[0145] Understandably, when the chip enters sleep mode, the wake-up port signal is at a high level. The second flip-flop 101B latches the high-level wake-up port signal and outputs the second wake-up signal gpio_high_flag=1. When the chip's trigger type is falling edge trigger wake-up, since the wake-up port signal is at a high level when the chip enters sleep mode, in order to generate a falling edge, the wake-up port of the chip is pulled low, which allows the wake-up port signal to flip from the latched high level (i.e., the second level state) to the current low level state. This generates a wake-up edge signal that satisfies falling edge trigger wake-up. The wake-up edge signal in this case is called the second falling edge trigger signal. At this time, the wake-up edge signal wake_edge is valid.

[0146] It is understood that in this embodiment, by dynamically adjusting the wake-up port when the first level state of the latched wake-up port signal is low or when the second level state of the latched wake-up port signal is low, thereby changing the level state of the wake-up port signal, a wake-up edge signal that satisfies the falling edge trigger wake-up can be actively generated. Thus, regardless of the initial level, the wake-up condition can be met, significantly improving the universal applicability of the wake-up detection circuit.

[0147] Based on the same inventive concept as the foregoing embodiments, this application also provides a chip system, as shown in FIG14, the chip system 50 including a wake-up detection circuit 10.

[0148] It should be noted that a detailed description of the wake-up detection circuit 10 can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0149] It should be noted that the chip system 50 provided in this application embodiment may refer to a system-on-a-chip, or simply a chip, such as a microcontroller unit (MCU).

[0150] As an optional embodiment, continuing as shown in FIG14, the chip system 50 provided in this application embodiment also includes a processor 501.

[0151] The wake-up detection circuit 10 is configured to latch the level state of the wake-up port signal when the chip enters the sleep state using the signal latch circuit 101 in the wake-up detection circuit 10; and to generate a wake-up signal gpio_wake_irq based on the level state of the wake-up port signal and the current level state of the wake-up port signal using the signal generation circuit 102 in the wake-up detection circuit 10.

[0152] The processor 501 is configured to configure wake-up parameters before the chip enters a sleep state; and to clear the wake-up signal gpio_wake_irq generated by the wake-up detection circuit 10 after the chip is woken up.

[0153] For example, the wake-up parameters may include the level state of the chip's wake-up port, that is, the level state of the wake-up port signal is pre-configured so that the chip can enter a sleep state.

[0154] For example, the processor 501 can execute a software program after the chip is woken up to generate an interrupt clear signal gpio_wake_irq_clr and output the interrupt clear signal gpio_wake_irq_clr to the wake-up detection circuit 10 to clear the wake-up signal gpio_wake_irq generated by the wake-up detection circuit 10.

[0155] In one example, processor 501 may be a processing unit in chip system 50. In another example, processor 501 may be a microprocessor in chip system 50.

[0156] Based on the same inventive concept as the foregoing embodiments, this application also provides an electronic device, as shown in FIG15, the electronic device 60 may include a chip system 50.

[0157] It should be noted that a detailed description of the chip system 50 can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0158] In one example, electronic device 60 may include wake-up detection circuitry 10. Alternatively, in another example, electronic device 60 may include wake-up detection circuitry 10 and processor 501, which will not be described further here.

[0159] The following examples illustrate possible implementation schemes of the wake-up detection circuit described in one or more of the above embodiments.

[0160] When an MCU enters sleep mode, all clocks are turned off to reduce power consumption. However, to wake it up, it needs to be activated by a level change on the wake-up pin. Since there is no clock, the current level is often compared with the state at the last moment before entering sleep mode to determine if a corresponding wake-up edge has occurred. This means that the level of the wake-up pin (i.e., the wake-up port) must be adjusted before entering sleep mode to generate the correct wake-up edge after sleep mode is activated. For example, a rising edge wake-up requires the wake-up pin to be low before entering sleep mode, and a falling edge wake-up requires the wake-up pin to be high before entering sleep mode. This ensures that the correct wake-up edge can be generated after sleep mode is activated. This imposes limitations on hardware (e.g., printed circuit board, PCB) design and software usage.

[0161] To address the aforementioned issues, this embodiment provides a wake-up detection circuit. After the chip enters sleep mode, it latches the state of the chip's wake-up pin (i.e., wake-up port) and compares it with the current level state of the wake-up pin to generate a correct wake-up interrupt signal (i.e., wake-up signal). Using this implementation method, PCB design and software usage can handle scenarios where the chip is woken up by the edge of the wake-up pin while in sleep mode, without being limited by the wake-up pin level before entering sleep mode, thus improving the flexibility of the wake-up detection circuit.

[0162] The wake-up detection circuit provided in this embodiment consists of three asynchronous reset and asynchronous set D flip-flops. Since the truth tables of different standard cell libraries are different, the instantiation connection needs to be adjusted for the truth tables of different standard cell libraries.

[0163] For example, the following description is based on cells from the standard cell library under the HHG 90ULL process platform.

[0164] The structure of the asynchronous reset and asynchronous set D flip-flop under the HHG 90ULL process platform can be seen in Figure 4. As shown in Figure 4, it includes a data input terminal D, an asynchronous set terminal SETB, an asynchronous reset terminal RESETB, a first output terminal QN, a scan chain data output input terminal SCD, a scan chain mode enable terminal SCE, a clock terminal CLK, and a second output terminal Q.

[0165] The truth table for the asynchronous reset and asynchronous set D flip-flop under the HHG 90ULL process platform can be found in Table 1. As shown in Table 1, for the asynchronous set and asynchronous reset D flip-flop U under the HHG 90ULL process platform, the second row indicates that when the asynchronous reset terminal RESETB is active low, the first output terminal QN outputs a signal, exhibiting a high-level signal 1; when the asynchronous reset terminal RESETB is inactive high, the first output terminal QN does not output a signal, exhibiting a low-level signal 0.

[0166] The first asynchronous reset and asynchronous set D flip-flop is used to latch whether the wake-up pin has been low in sleep mode.

[0167] The first asynchronous reset and asynchronous set D flip-flop's asynchronous set terminal, SETB, is connected to the chip's reset port 110 (a reset controllable by the scan chain). The first asynchronous reset and asynchronous set terminal, RESETB, is the inverse of the wake-up pin's low-level active state (i.e., 1 if the wake-up pin is low, i.e., gpio_low=1; otherwise, 0, i.e., gpio_low=0) ORed with the chip's non-sleep indicator (i.e., normal state; 1 if the chip is in normal state, NORMAL, otherwise 0) ORed with the DFT. In the scan chain mode, the data input D of the first asynchronous reset and set D flip-flop is fixed to 1 (i.e., the first data). The first output QN of the first asynchronous reset and set outputs whether a low-level status bit has occurred (if it has, then the first output QN of the first asynchronous reset and set outputs gpio_low_flag=1; if it has not, then the first output QN of the first asynchronous reset and set outputs gpio_low_flag=0). SCD and SCE are DFT (i.e., scan chain) related signals, which are fixed to 0 (i.e., the second data) during the Register Transfer Level (RTL) design phase.

[0168] When implementing the function of the first asynchronous reset and asynchronous set D flip-flop using hardware combinational logic expressions, the hardware combinational logic expressions are as follows: For example: TLSCL7CNMV0_SDFBBP_1 u_gpio_low_flag(.Q (),.QN (gpio_low_flag),.D (1'b1),.CLK (clk),.SETB (rstn),.RESETB ((~gpio_low) | (state == NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0)); The second asynchronous reset and asynchronous set D flip-flop is used to latch whether the wake-up pin has been high in the sleep state (if it has been high, the first output terminal QN of the second asynchronous reset and asynchronous set D flip-flop outputs gpio_high_flag=1; if it has not been high, the first output terminal QN of the second asynchronous reset and asynchronous set D flip-flop outputs gpio_high_flag=0).

[0169] The connection relationship of the second asynchronous set / reset D flip-flop is the same as that of the first asynchronous reset / set D flip-flop, except that the connection relationship of the asynchronous reset terminal RESETB is changed from the low-level active state of the wake-up pin in the first asynchronous set / reset D flip-flop to the high-level active state of the wake-up pin in the second asynchronous set / reset D flip-flop.

[0170] When implementing the function of the second asynchronous reset and asynchronous set D flip-flop using hardware combinational logic expressions, the hardware combinational logic expressions are as follows: For example: TLSCL7CNMV0_SDFBBP_1 u_gpio_high_flag(.Q (),.QN (gpio_high_flag),.D (1'b1),.CLK (clk),.SETB (rstn),.RESETB ((~gpio_high) | (state == NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0)); The third asynchronous reset and asynchronous set D flip-flop is used to generate the wake-up interrupt signal gpio_wake_irq (i.e., the wake-up signal gpio_wake_irq).

[0171] The asynchronous set terminal (SETB) of the third asynchronous reset / set D flip-flop is connected to the chip's reset port (which can be controlled by the scan chain). The asynchronous reset terminal (RESETB) of the third asynchronous reset / set D flip-flop is the inverse OR of the wake-up edge state (i.e., wake_edge=1 if wake-up edge is valid, wake_edge=0 if wake-up edge is invalid) or the chip's non-sleep indicator (i.e., normal state; 1 if the chip is in normal state NORMAL, otherwise 0) or dft_mode (scan chain mode). The data input terminal (D) of the third asynchronous reset / set D flip-flop is the inverse of the wake-up interrupt signal (i.e., the inverted wake-up interrupt signal). The signal ~gpio_wake_irq) or the interrupt clear signal gpio_wake_irq_clr, the first output terminal QN of the third asynchronous reset and asynchronous set D flip-flop outputs whether the wake-up interrupt signal gpio_wake_irq has occurred (if it has occurred, the first output terminal QN of the third asynchronous reset and asynchronous set D flip-flop outputs gpio_wake_irq=1; if it has not occurred, the first output terminal QN of the third asynchronous reset and asynchronous set D flip-flop outputs gpio_wake_irq=0). SCD and SCE are DFT-related signals, which are fixed to 0 (i.e., the second data) during the RTL design phase.

[0172] When implementing the function of the third asynchronous reset and asynchronous set D flip-flop using hardware combinational logic expressions, the hardware combinational logic expression is as follows: For example: assign wake_edge = wake_negedge ? (gpio_high&gpio_low_flag): wake_posedge ? (gpio_low&gpio_high_flag): 1'b0;TLSCL7CNMV0_SDFBBP_1 u_gpio_wake_irq(.Q (),.QN (gpio_wake_irq),.D (gpio_wake_irq_clr | (~gpio_wake_irq_)),.CLK (clk),.SETB (rstn),.RESETB ((~wake_edge) | (state==NORMAL) | dft_mode),.SCD (1'b0),.SCE (1'b0)); As shown in Figures 9 to 12, after entering sleep mode, all clocks are turned off, that is, the clock enable signal clk_en=0, and state enters the SLEEP state (the value of state == NORMAL is 0). Case 1: Wake up using the rising edge.

[0173] As shown in Figure 9, 1) Before entering sleep, the wake-up pin is low: At this time, the wake-up pin (wake_gpio) is low, so gpio_high is 0, gpio_high_flag is 0, gpio_low is 1, and gpio_low_flag is 1; In order to generate a rising edge, the wake-up pin is pulled high. At this time, gpio_high is 1, wake_edge is valid, triggering gpio_wake_irq to be 1. gpio_wake_irq turns on the clock, and gpio_wake_irq will always be 1. Then, after the state machine has the clock, it switches to the NORMAL state. At this time, the software can clear gpio_wake_irq by clearing the interrupt.

[0174] As shown in Figure 10, 2) Before entering sleep, the wake-up pin is at a high level: At this time, the wake-up pin (wake_gpio) is at a high level, so gpio_high is 1, gpio_high_flag is 1, gpio_low is 0, and gpio_low_flag is 0; In order to generate a rising edge, the wake-up pin is first pulled low, at which time gpio_low is 1 and gpio_low_flag is 1; then the wake-up pin is pulled high, at which time gpio_high is 1, wake_edge is valid, triggering gpio_wake_irq to be 1, gpio_wake_irq turns on the clock, and gpio_wake_irq will always be 1. Then, after the state machine has the clock, it switches to the NORMAL state. At this time, the software can clear gpio_wake_irq by clearing the interrupt.

[0175] Case 2: Wake up using the falling edge.

[0176] As shown in Figure 11, 1) Before entering sleep, the wake-up pin is low: At this time, the wake-up pin (wake_gpio) is low, so gpio_high is 0, gpio_high_flag is 0, gpio_low is 1, and gpio_low_flag is 1; In order to generate a falling edge, the wake-up pin is first pulled high, at which time gpio_high is 1 and gpio_high_flag is 1; then the pin is pulled low, at which time gpio_low is 1, wake_edge is valid, triggering gpio_wake_irq to be 1, gpio_wake_irq turns on the clock, and gpio_wake_irq will always be 1. Then, after the state machine has the clock, it switches to the NORMAL state. At this time, the software can clear gpio_wake_irq by clearing the interrupt.

[0177] As shown in Figure 12, 2) Before entering sleep, the wake-up pin is at a high level: At this time, the wake-up pin (wake_gpio) is at a high level, so gpio_high is 1, gpio_high_flag is 1, gpio_low is 0, and gpio_low_flag is 0; In order to generate a falling edge, the wake-up pin is pulled low. At this time, gpio_low is 1, wake_edge is valid, triggering gpio_wake_irq to be 1. gpio_wake_irq turns on the clock, and gpio_wake_irq will always remain at 1. Then, after the state machine has the clock, it switches to the NORMAL state. At this time, the software can clear gpio_wake_irq by clearing the interrupt.

[0178] Using the wake-up detection circuit provided in this embodiment to implement the counting method allows PCB design and software use to address scenarios where the chip is woken up by the edge of the wake-up pin while in sleep mode, without being limited by the wake-up pin level before entering sleep mode, thus improving the flexibility of the wake-up detection circuit.

[0179] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps; or steps from different embodiments may be combined into a new technical solution.

[0180] It should be noted that the module division in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or have two or more units integrated into one unit. The integrated units can be implemented in hardware, as software functional units, or a combination of software and hardware.

[0181] It should be noted that, in the embodiments of this application, if the above-described methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0182] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0183] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0184] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0185] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0186] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0187] In addition, each functional module in the various embodiments of this application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the integrated modules can be implemented in hardware or in the form of hardware plus software functional units.

[0188] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0189] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0190] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0191] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0192] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0193] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A wake-up detection circuit, characterized in that, include: A signal latching circuit and a signal generating circuit are connected; wherein: the signal latching circuit is configured to latch the level state of the wake-up port signal when the chip enters a sleep state; the signal generating circuit is configured to generate a wake-up signal based on the latched level state of the wake-up port signal and the current level state of the wake-up port signal; wherein the wake-up signal is used to wake up the chip.

2. The wake-up detection circuit according to claim 1, characterized in that, The signal latching circuit includes: a first flip-flop and a second flip-flop, wherein the first output terminal of the first flip-flop and the first output terminal of the second flip-flop are respectively connected to the two input terminals of the signal generation circuit; wherein: the first flip-flop is configured to latch a first level state of the wake-up port signal when the chip enters a sleep state; the second flip-flop is configured to latch a second level state of the wake-up port signal when the chip enters a sleep state; the signal generation circuit is configured to generate the wake-up signal based on the first level state of the wake-up port signal, the second level state of the wake-up port signal, and the current level state of the wake-up port signal; wherein the first level state and the second level state are two opposite level states.

3. The wake-up detection circuit according to claim 2, characterized in that, The first trigger is an asynchronous reset and asynchronous set trigger; wherein: the asynchronous set terminal of the first trigger is connected to the reset port of the chip; the asynchronous reset terminal of the first trigger is configured to output a first wake-up signal that latches the first level state through the first output terminal of the first trigger when the wake-up port signal is in the first level state; the data input terminal of the first trigger is configured to clear the first wake-up signal after the clock of the chip is restored.

4. The wake-up detection circuit according to claim 3, characterized in that, The second flip-flop is an asynchronous reset and asynchronous set flip-flop; wherein: the asynchronous set terminal of the second flip-flop is connected to the reset port of the chip; the asynchronous reset terminal of the second flip-flop is configured to output a second wake-up signal that latches the second level state through the first output terminal of the second flip-flop when the wake-up port signal is in the second level state; the data input terminal of the second flip-flop is configured to clear the second wake-up signal after the clock is restored.

5. The wake-up detection circuit according to claim 4, characterized in that, The signal generation circuit includes a signal logic circuit and a third flip-flop, wherein the output terminal of the signal logic circuit is connected to the reset terminal of the third flip-flop; wherein: the signal logic circuit is configured to perform logical operations based on the current level state of the first wake-up signal, the second wake-up signal and the wake-up port signal to generate a wake-up edge signal; the third flip-flop is configured to output the wake-up signal through the first output terminal of the third flip-flop when the wake-up edge signal is received at the reset terminal of the third flip-flop.

6. The wake-up detection circuit according to claim 5, characterized in that, The third flip-flop is an asynchronous reset and asynchronous set flip-flop; wherein: the asynchronous set terminal of the third flip-flop is connected to the reset port of the chip; the asynchronous reset terminal of the third flip-flop is connected to the output terminal of the signal logic circuit; the data input terminal of the third flip-flop is configured to receive the inverted signal of the wake-up signal, the inverted signal of the wake-up signal is used to maintain the first output terminal of the third flip-flop outputting the wake-up signal; or, it is further configured to receive an interrupt clear signal, the interrupt clear signal is used to clear the wake-up signal.

7. A wake-up detection method, characterized in that, The wake-up detection method, applied to a wake-up detection circuit, includes: using a signal latching circuit to latch the level state of a wake-up port signal when the chip enters a sleep state; and using a signal generation circuit to generate a wake-up signal based on the latched level state of the wake-up port signal and the current level state of the wake-up port signal; wherein the wake-up signal is used to wake up the chip.

8. The wake-up detection method according to claim 7, characterized in that, In the case that the signal latching circuit includes a first flip-flop and a second flip-flop, the wake-up detection method further includes: using the first flip-flop to latch a first level state of the wake-up port signal when the chip enters a sleep state; using the second flip-flop to latch a second level state of the wake-up port signal when the chip enters a sleep state; and using the signal generation circuit to generate the wake-up signal based on the first level state of the wake-up port signal, the second level state of the wake-up port signal, and the current level state of the wake-up port signal; wherein the first level state and the second level state are two opposite level states.

9. The wake-up detection method according to claim 8, characterized in that, Both the first trigger and the second trigger are asynchronous set and asynchronous reset triggers. The wake-up detection method further includes: when the wake-up port signal is in the first level state, outputting a first wake-up signal that latches the first level state through the first output terminal of the first trigger; and when the wake-up port signal is in the second level state, outputting a second wake-up signal that latches the second level state through the first output terminal of the second trigger.

10. The wake-up detection method according to claim 9, characterized in that, The signal generation circuit includes a signal logic circuit and a third flip-flop. The wake-up detection method further includes: using the signal logic circuit to perform logical operations based on the current level state of the first wake-up signal, the second wake-up signal and the wake-up port signal to generate a wake-up edge signal; inputting the wake-up edge signal to the reset terminal of the third flip-flop, and outputting the wake-up signal through the first output terminal of the third flip-flop.

11. The wake-up detection method according to claim 10, characterized in that, The wake-up detection method further includes: using the signal logic circuit, when the chip's trigger type is rising edge trigger wake-up and the first wake-up signal is in a low-level state, controlling the current level state of the wake-up port signal to be in a high-level state to generate the wake-up edge signal that satisfies rising edge trigger wake-up; or, using the signal logic circuit, when the chip's trigger type is rising edge trigger wake-up and the second wake-up signal is in a high-level state, controlling the current level state of the wake-up port signal to flip from a low-level state to a high-level state to generate the wake-up edge signal that satisfies rising edge trigger wake-up.

12. The wake-up detection method according to claim 10 or 11, characterized in that, The wake-up detection method further includes: using the signal logic circuit, when the chip's trigger type is falling edge trigger wake-up and the first wake-up signal is in a low-level state, controlling the current level state of the wake-up port signal to flip from a high-level state to a low-level state to generate the wake-up edge signal that satisfies falling edge trigger wake-up; or, using the signal logic circuit, when the chip's trigger type is falling edge trigger wake-up and the second wake-up signal is in a high-level state, controlling the current level state of the wake-up port signal to a low-level state to generate the wake-up edge signal that satisfies falling edge trigger wake-up.

13. A chip system, characterized in that, Includes the wake-up detection circuit as described in any one of claims 1 to 6.

14. The chip system according to claim 13, characterized in that, It also includes a processor; wherein: the wake-up detection circuit is configured to latch the level state of the wake-up port signal when the chip enters a sleep state using a signal latch circuit; and to generate a wake-up signal using a signal generation circuit based on the level state of the wake-up port signal and the current level state of the wake-up port signal; the processor is configured to configure wake-up parameters before the chip enters a sleep state; and to clear the wake-up signal generated by the wake-up detection circuit after the chip is woken up.

15. An electronic device, characterized in that, Including the chip system as described in claim 13 or 14.

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