IBIS model reconstruction method for FPGA chip

Abstract

The invention relates to an IBIS model reconstruction method for an FPGA chip. An IBIS (Input and Output Buffer) model provided by an existing FPGA (Field Programmable Gate Array) chip manufacturer globally and fuzzily overviews a pin position number, a signal network name of a pin, a working mode of the pin and the like of a chip, and has no clear and specific definition. Therefore, an original IBIS model provided by a chip manufacturer cannot be directly used during signal integrity simulation analysis, and simulation analysis cannot be carried out. In order to solve the problem, the invention provides the reconstruction processing method for the IBIS model of the FPGA chip, a schematic circuit diagram is not used, key information is extracted from a PCB drawing so as to reconstruct the IBIS model, and the processed IBIS model can be directly used for efficient design and accurate simulation analysis of a circuit.

Description

A Method for Reconstructing IBIS Models for FPGA Chips Technical Field

[0001] This invention relates to a method for reconstructing the IBIS (Input and Output Buffer) model of FPGA (Field Programmable Gate Array) chips, belonging to the field of digital modeling of integrated circuit chips. Background Technology

[0002] An FPGA chip is a hardware-reconfigurable integrated circuit chip. Its internal structure can be changed through programming, allowing it to be assigned specific functions according to user needs. Due to the reconfigurable nature of FPGA functions, unlike other fixed-function chips, the pin functions are defined by the user based on their specific requirements. The IBIS models provided by chip manufacturers offer only a general and vague overview of pin numbers, pin signal network names, and pin operating modes, lacking clear and specific definitions. This renders the original IBIS models provided by chip manufacturers unusable for circuit simulation analyses such as signal integrity analysis, thus hindering simulation performance.

[0003] For PCB designs of high-speed signal circuits such as DDR (Double Data Rate) buses, the correctness of the circuit design and the stability and reliability of the circuit operation cannot be predicted without simulation analysis. If related problems are only discovered during circuit debugging, and the board design and production are modified, additional design and manufacturing costs will be incurred, and the development cycle will be doubled.

[0004] Therefore, there is an urgent need to provide a method for reconstructing IBIS models for FPGA chips. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and solve the problem of insufficient definition of chip pin information in the IBIS model provided by existing chip manufacturers. It provides an IBIS model reconstruction method for FPGA chips. The reconstructed IBIS model can be directly read by EDA software and used in the design and accurate simulation analysis of high-speed circuits.

[0006] The objective of this invention is achieved through the following technical solutions:

[0007] A method for reconstructing IBIS models for FPGA chips is proposed. This method does not require the circuit design schematic and directly extracts key information from the PCB drawing. The extracted information is used to reconstruct the pin reference numbers, pin signal network names, and pin operating modes in the original IBIS model, so that the IBIS model can be directly used for the design and accurate simulation analysis of high-speed circuits.

[0008] The method includes the following steps:

[0009] Step 1: Extract and save the FPGA chip pin network mapping information from the PCB diagram;

[0010] Step 2: Process the FPGA pin network mapping information and save the FPGA chip pin number and network name data; the FPGA chip pins include signal pins and differential signal pins;

[0011] Step 3: Group the pins of the DDR bus section of the FPGA chip according to the data, address, clock, and data strobe function modes to obtain the pin grouping data of the DDR bus of the FPGA chip.

[0012] Step 4, replace the signal pin data in the original IBIS model data; replace the signal pins, signal network names and operating modes of the original IBIS model data with the FPGA chip DDR bus pin data processed in step (3);

[0013] Step 5: Replace the differential signal pin data in the original IBIS model data with the differential signal pin data that has been grouped in step (2);

[0014] Step 6: Redefine the working mode selector module in the IBIS model; using the working mode description of the corresponding pin in the FPGA chip datasheet provided by the chip manufacturer, write the selectable working modes in the FPGA chip DDR bus pin data that has been grouped and processed in step (3) to generate the reconstructed IBIS model.

[0015] Furthermore, in step 1, the FPGA pin network mapping information includes: chip reference number, pin name and reference number, and pin network mapping.

[0016] Furthermore, in step 1, the tools that support extracting FPGA pin network mapping relationship information files include: Mentor Expedition, Altium Designer, and Candence.

[0017] Furthermore, the reconstructed IBIS model is directly read by EDA software (Electronic Design Automation) for simulation analysis of the waveform quality, timing, transmission loss, and voltage amplitude of digital signals in high-speed circuits. The EDA software includes HyperLynx, ADS, and SI Wave.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] (1) The method of extracting key information directly from PCB (printed circuit board) drawings and then reconstructing the IBIS model was adopted, which achieved the effect of EDA (electronic design automation) software directly reading the processed IBIS model. Using the reconstructed IBIS model for signal integrity simulation, the simulation accuracy can reach more than 95% of the SPICE model while increasing the simulation speed by 25 times.

[0020] (2) The method of reconstructing the IBIS model was adopted. The reconstructed IBIS model was used for signal integrity simulation analysis, which achieved the effect of improving the first-time success rate of circuit design and saving more than 50% of the redesign and processing costs. Attached Figure Description

[0021] Figure 1 is a flowchart of the method of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0023] Figure 1 shows the flowchart of the IBIS model reconstruction method for FPGA chips implemented in this invention. The specific steps are described as follows:

[0024] A method for reconstructing an IBIS model for an FPGA chip includes the following steps:

[0025] Step 1: Extract and save the FPGA chip pin network mapping information from the PCB layout. This information includes: chip reference designator, pin name and reference designator, and pin network mapping. Tools that support extracting FPGA pin network mapping information files include: Mentor Expedition, Altium Designer, and Candence.

[0026] Step 2: Process the FPGA pin network mapping information and save the FPGA chip pin number and network name data; the FPGA chip pins include signal pins and differential signal pins;

[0027] Step 3: Group the pins of the DDR bus section of the FPGA chip according to the data, address, clock, and data strobe function modes to obtain the pin grouping data of the DDR bus of the FPGA chip.

[0028] Step 4, replace the signal pin data in the original IBIS model data; replace the signal pins, signal network names and operating modes of the original IBIS model data with the FPGA chip DDR bus pin data processed in step (3);

[0029] Step 5: Replace the differential signal pin data in the original IBIS model data with the differential signal pin data that has been grouped in step (2);

[0030] Step 6: Redefine the working mode selector module in the IBIS model; using the working mode description of the corresponding pin in the FPGA chip datasheet provided by the chip manufacturer, write the selectable working modes in the FPGA chip DDR bus pin data that has been grouped and processed in step (3) to generate the reconstructed IBIS model.

[0031] The reconstructed IBIS model is directly read by EDA software (Electronic Design Automation) for simulation analysis of waveform quality, timing, transmission loss, and voltage amplitude of digital signals in high-speed circuits. The EDA software includes HyperLynx, ADS, and SI Wave.

[0032] The contents not described in detail in this specification are common knowledge to those skilled in the art.

[0033] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for reconstructing an IBIS model for an FPGA chip, characterized in that, Includes the following steps: Step 1: Extract and save the FPGA chip pin network mapping information from the PCB diagram; Step 2: Process the FPGA pin network mapping information and save the FPGA chip pin reference number and network name data; The FPGA chip pins include signal pins and differential signal pins; Step 3: Group the pins of the FPGA chip's double data rate DDR bus section according to data, address, clock, and data strobe function modes to obtain the FPGA chip's double data rate DDR bus pin grouping data; Step 4: Replace the signal pin data in the original IBIS model data; Replace the signal pin, signal network name, and working mode of the original IBIS model data with the FPGA chip DDR bus pin data processed in step (3); Step 5: Replace the differential signal pin data in the original IBIS model data with the differential signal pin data processed by grouping in step (2); Step 6: Redefine the working mode selector module in the IBIS model; Use the working mode description of the corresponding pins in the FPGA chip datasheet provided by the chip manufacturer to write the selectable working modes in the FPGA chip DDR bus pin data processed by grouping in step (3) to generate the reconstructed IBIS model.

2. The IBIS model reconstruction method for FPGA chips according to claim 1, characterized in that, In step 1, the FPGA pin network mapping information includes: chip reference number, pin name and reference number, and pin network mapping.

3. The IBIS model reconstruction method for FPGA chips according to claim 1, characterized in that, In step 1, the tools that support extracting FPGA pin network mapping relationship information files include: Mentor Expedition, Altium Designer, and Candence.

4. The IBIS model reconstruction method for FPGA chips according to claim 1, characterized in that, The reconstructed IBIS model is directly read by EDA software (electronic design automation software) and used for simulation analysis of the waveform quality, timing, transmission loss, and voltage amplitude of digital signals in high-speed circuits.

5. The IBIS model reconstruction method for FPGA chips according to claim 4, characterized in that, The EDA software includes HyperLynx, ADS, and SI Wave.

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