Electronic device and method of driving same

Abstract

The invention discloses an electronic device and a method of driving the same. The electronic device includes: a display panel including a first display area operating in a first mode and a second display area operating in the first mode or a second mode; and an afterimage compensation circuit that compensates a first input image signal for the first display area and a second input image signal for the second display area based on the degradation information of the first display area and the degradation information of the second display area, respectively. A first block is defined in the first display area, and a second block is defined in the second display area to have a different size than a size of the first block. The afterimage compensation circuit includes a cumulative memory including a first memory region that accumulates first degraded data of a first block and a second memory region that accumulates second degraded data of a second block.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices and methods of driving such electronic devices, and more specifically, to electronic devices capable of compensating for residual images and methods of driving such electronic devices. Background Technology

[0002] Multimedia electronic devices such as televisions, cellular phones, tablet computers, navigation systems, and game consoles include electronic devices that display images. Furthermore, electronic devices can be provided inside the vehicle.

[0003] In addition to common input devices such as buttons, keyboards, or mice, electronic devices may also include input sensors to provide a touch-based input method that allows users to easily and intuitively type information or commands. Summary of the Invention

[0004] Embodiments of this disclosure provide an electronic device capable of reducing the size of an accumulation memory used to compensate for afterimages.

[0005] Embodiments of this disclosure provide a method for a driving electronics device capable of reducing the size of an accumulation memory used to compensate for afterimages.

[0006] According to an embodiment of the present disclosure, an electronic device includes: a display panel including a first display area operating in a first mode and a second display area operating in a first mode or a second mode; and a redundant image compensation circuit configured to receive a first input image signal for the first display area and a second input image signal for the second display area, and to generate a first compensated image signal and a second compensated image signal by compensating the first input image signal and the second input image signal based on degradation information of the first display area and the second display area, respectively.

[0007] In one embodiment, a plurality of first blocks are defined in a first display area, and a plurality of second blocks are defined in a second display area, each of the plurality of second blocks having a size different from that of each of the plurality of first blocks. The afterimage compensation circuit includes an accumulation memory comprising: a first storage area configured to accumulate first degraded data for each of the plurality of first blocks; and a second storage area configured to accumulate second degraded data for each of the plurality of second blocks.

[0008] In an embodiment, the second storage area includes: a first mode storage area configured to accumulate second degraded data of each of a plurality of second blocks in a first mode; and a second mode storage area configured to accumulate second degraded data of each of a plurality of second blocks in a second mode.

[0009] According to embodiments of the present disclosure, in a method of driving an electronic device, the electronic device includes a first display area operating in a first mode and a second display area operating in a first mode or a second mode.

[0010] The method of driving the electronic device includes: receiving a first input image signal for a first display area and a second input image signal for a second display area; generating a first compensated image signal and a second compensated image signal by compensating the first input image signal and the second input image signal based on degradation information of the first display area and the second display area, respectively; displaying images in the first display area and the second display area based on the first compensated image signal and the second compensated image signal, respectively; and accumulating first degradation data generated based on the first compensated image signal in a first storage area of ​​an accumulation memory, and accumulating second degradation data generated based on the second compensated image signal in a second storage area of ​​the accumulation memory.

[0011] In one embodiment, a plurality of first blocks are defined in a first display area, and a plurality of second blocks are defined in a second display area, each of the plurality of second blocks having a size different from that of each of the plurality of first blocks.

[0012] In an embodiment, the second storage area includes: a first mode storage area, which accumulates the 2-1st degraded data of each of the plurality of second blocks in the first mode; and a second mode storage area, which accumulates the 2-2nd degraded data of each of the plurality of second blocks in the second mode.

[0013] According to an embodiment of the present disclosure, an electronic device includes: a display panel including a first display area operating in a first mode or a second mode and a second display area operating in the first mode or the second mode; and a residual image compensation circuit configured to receive a first input image signal for the first display area and a second input image signal for the second display area, and to generate a first compensated image signal and a second compensated image signal by compensating the first input image signal and the second input image signal respectively based on degradation information of the first display area and the second display area.

[0014] The afterimage compensation circuit includes an accumulation memory, which includes a first storage area and a second storage area. The second storage area includes: a first mode storage area configured to accumulate 2-1 degraded data of the second display area in a first mode; and a second mode storage area configured to accumulate 2-2 degraded data of the second display area in a second mode. The first storage area includes: a third mode storage area configured to accumulate 1-1 degraded data of the first display area in the first mode; and a fourth mode storage area configured to accumulate 1-2 degraded data of the first display area in the second mode. Attached Figure Description

[0015] The above and other objects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0016] Figure 1 This is a view illustrating the interior of a vehicle including electronic devices disposed therein, according to an embodiment of the present disclosure.

[0017] Figure 2A The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area and a second display area operating in a first mode.

[0018] Figure 2B The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a second display area operating in a second mode.

[0019] Figure 2C The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a mode switching area in a second display area operating in a second mode.

[0020] Figure 3A The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area and a second display area operating in a first mode.

[0021] Figure 3B The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a first mode switching area and a second mode switching area in a second display area operating in a second mode.

[0022] Figure 4A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0023] Figure 4B This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0024] Figure 5A It is shown in the figure. Figure 4A The figure shows an enlarged cross-sectional view of a portion of the electronic device.

[0025] Figure 5B It is shown in the figure. Figure 4B The figure shows an enlarged cross-sectional view of a portion of the electronic device.

[0026] Figure 6 This is a block diagram of a display panel according to an embodiment of the present disclosure.

[0027] Figure 7This is a circuit diagram of the second pixel according to an embodiment of the present disclosure.

[0028] Figure 8 It is used to describe Figure 7 The waveform diagram of the operation of the second pixel is shown in the figure.

[0029] Figure 9A This is a view illustrating a wide light-emitting element turned on in a first mode according to an embodiment of the present disclosure.

[0030] Figure 9B This is a view illustrating a narrow light-emitting element turned on in a second mode according to an embodiment of the present disclosure.

[0031] Figure 10A It is along Figure 9A The figure shows a cross-sectional view taken by line I-I'.

[0032] Figure 10B It is along Figure 9B The cross-sectional view taken by line II-II' shown in the figure.

[0033] Figure 11A This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0034] Figure 11B This is a block diagram of a residual image compensation circuit according to an embodiment of the present disclosure.

[0035] Figure 12A and Figure 12B It is a view illustrating the status of indicator signals depending on the operating mode of the electronic device.

[0036] Figure 13A The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0037] Figure 13B The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0038] Figure 14A The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0039] Figure 14B The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0040] Figure 15A and Figure 15B It is a view illustrating the state of the first and second flag signals depending on the operating mode of the electronic device.

[0041] Figure 16 The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0042] Figure 17 This is a flowchart illustrating the operation process of an electronic device according to an embodiment of the present disclosure.

[0043] Figure 18A It is shown in the diagram Figure 17 The flowchart shown in Figure S120 illustrates the method for operating the compensation signal.

[0044] Figure 18B It is shown in the diagram Figure 17 The flowchart shown in Figure S140 illustrates the method for accumulating degraded data.

[0045] Figure 19 This is a diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0046] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0047] In this specification, the statements that a first component (or area, layer, or portion) is "on" a second component, "connected to" or "attached to" a second component mean that the first component is directly on, directly connected to, or attached to the second component, or that a third component is inserted between them.

[0048] The term “and / or” includes any and all combinations of one or more related components.

[0049] Although the terms “first” or “second” may be used to describe various components, these components should not be construed as being limited to these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0050] Furthermore, the terms "below," "at the bottom," "above," and "upper" are used to describe the relationships between the various components illustrated in the accompanying drawings. These terms are relative and will be described with reference to the directions indicated in the drawings.

[0051] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0052] It should be understood that, unless the context clearly indicates otherwise, the description of each feature or aspect within each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments.

[0053] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the (said)” are intended to include the plural forms as well.

[0054] For ease of description, spatial relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature as illustrated in the figures and another element(s). It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations.

[0055] It will be understood that when a component is referred to as being "on" another component, "connected to," "linked to," or "adjacent to" another component, it can be directly on, directly connected to, linked to, or adjacent to that other component, or there may be intervening components. It will be understood that when a component is referred to as being "between" two components, it can be the only component between those two components, or there may be one or more intervening components. It will also be understood that when a component is referred to as "covering" another component, it can be the only component covering that other component, or one or more intervening components may also cover that other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0056] Here, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it will be understood that these elements or values ​​are the same, equal to each other within measurement error, or, if there are measurable inequalities, are sufficiently close in value to be functionally equivalent, as will be understood by those skilled in the art. For example, taking into account the measurement in question and the error associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term “approximately” as used herein includes the stated value and means within an acceptable deviation for a particular value as determined by those skilled in the art. For example, “approximately” may mean within one or more standard deviations as understood by those skilled in the art, such as within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, it will be understood that while a parameter may be described herein as having an “approximately” specific value, according to an embodiment, the parameter may be exactly that specific value, or approximately that specific value within a measurement error as will be understood by those skilled in the art. Other uses of these terms to describe relationships between components, and similar terms, should be interpreted in a similar manner.

[0057] It will be further understood that the terms “comprising,” “including,” or “having,” and variations thereof, specify the presence of the described features, quantities, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0058] Embodiments of this disclosure relate to electronic devices, and more specifically, to electronic devices comprising multiple display areas operating in different modes and a persistent image compensation circuit configured to improve visual quality by precisely compensating for area-specific image degradation. As display panels become more complex and adaptable to different usage scenarios (such as public viewing modes and private viewing modes), the need for intelligent compensation mechanisms to address uneven aging and usage issues in different parts of the screen is increasing.

[0059] For example, embodiments provide an afterimage compensation circuit that divides a display panel into a first display area and a second display area, the latter selectively operating in either a first mode or a second mode. Each area can be subdivided into blocks of different sizes, which can improve memory usage and compensation accuracy. A mode-aware memory configuration can be used to accumulate degradation data separately for each area and each mode. By compensating the image signal based on such refined and mode-specific degradation data, the electronic device according to embodiments of the present disclosure can reduce afterimage artifacts while reducing memory overhead, which can improve long-term image quality and user experience.

[0060] Figure 1This is a view illustrating the interior of a vehicle including electronic devices provided therein, according to an embodiment of the present disclosure.

[0061] refer to Figure 1 The electronic device DD can be provided inside the vehicle's AM. The electronic device DD can be provided inside the vehicle's AM to provide various information snippets to the driver's (or user's) DV. The electronic device DD can provide the driver's DV with images such as weather, speed, maps, or video. The electronic device DD can be a touch-based electronic device operable in response to touch input from the driver's DV.

[0062] although Figure 1 The illustration shows an electronic device DD implemented in a vehicle, but embodiments of this disclosure are not limited thereto. For example, the electronic device DD according to embodiments of this disclosure can be used in electronic devices such as smartphones, digital cameras, laptops, monitors, and smart TVs to provide images to a user.

[0063] Figure 2A The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area and a second display area operating in a first mode. Figure 2B The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a second display area operating in a second mode. Figure 2C The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a mode switching area in a second display area operating in a second mode.

[0064] refer to Figure 2A and Figure 2B The electronic device DD may have a plane defined by a first direction DR1 and a second direction DR2 that intersect each other. The electronic device DD may have a longer side (relative to a shorter side) extending in the first direction DR1 and a shorter side (relative to the longer side) extending in the second direction DR2. While the electronic device DD may have a rectangular shape, its shape is not limited to this. For example, the electronic device DD may have various shapes. Furthermore, the corners of the electronic device DD connecting the longer side to the shorter side may have a curved shape.

[0065] Although the front surface of the electronic device DD can be defined as a display surface, this front surface can have a plane defined by a first direction DR1 and a second direction DR2. Images generated from the electronic device DD can be provided to the user through the display surface.

[0066] An electronic device DD may include a display area DA and a non-display area NDA surrounding the display area DA. An image may be displayed in the display area DA, and an image may not be displayed in the non-display area NDA. The non-display area NDA may surround the display area DA and may define the edge of the electronic device DD, which is printed with a specific color. For example, the non-display area NDA may correspond to the border of the electronic device DD.

[0067] According to embodiments of this disclosure, the display area DA includes a first display area DA1 and a second display area DA2. The first display area DA1 and the second display area DA2 may be adjacent to each other in a first direction DR1, wherein an intermediate area CA is interposed between the first display area DA1 and the second display area DA2. A first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. The first display area DA1 is positioned in the vehicle AM ​​(see [reference]). Figure 1 The first display area DA1 is located in front of the driver's seat (e.g., positioned closer to the front of the driver's seat than the area closer to the front of the passenger seat), and the second display area DA2 may be located in front of the passenger seat (e.g., positioned closer to the front of the passenger seat than the area closer to the front of the driver's seat). In some embodiments, the intermediate area CA between the first display area DA1 and the second display area DA2 may be omitted.

[0068] According to embodiments of this disclosure, the first display area DA1 and the second display area DA2 can operate independently of each other. For example, the first display area DA1 can display an image only in a first mode, while the second display area DA2 can selectively operate in either the first or second mode. In this case, the first mode can be referred to as a public mode or a wide-viewing-angle mode, and the second mode can be referred to as a private mode or a narrow-viewing-angle mode. When the second display area DA2 operates in the second mode, the field of view of the displayed image can be narrowed, making the image primarily visible only when viewed from directly in front. As a result, a nearby viewer (e.g., a driver) such as someone sitting to the side of a user in front of the second display area DA2 cannot see the image displayed in the second display area DA2. In contrast, when both the first display area DA1 and the second display area DA2 operate in the first mode, the field of view is widened, allowing the image to be seen even from a side angle.

[0069] In embodiments of this disclosure, the independent mode operation of the first display area DA1 and the second display area DA2 can affect how image signals are processed and compensated. Because the second display area DA2 can operate in either the first or second mode, the image output characteristics can vary depending on the selected mode. For example, when operating in the second mode, the narrowed viewing angle can cause light to be directed more narrowly forward, while the first mode allows light to be distributed more widely. These differences can lead to different degradation behaviors in each display area and in each mode, which, if not properly managed, can affect long-term image quality.

[0070] To address this issue, embodiments of this disclosure may employ a zone-aware and mode-aware image compensation system. For example, degradation characteristics may be tracked independently for each display zone and for each mode of the second display zone. By maintaining separate compensation data depending on whether the second display zone DA2 operates in the first or second mode, more accurate afterimage correction and brightness stabilization can be achieved, which can improve long-term display quality and reduce artifacts that may additionally arise from mixed-mode operation.

[0071] This approach also supports efficient use of memory resources. The system can partition the memory to independently accumulate degradation data associated with each partition and each mode, rather than storing overlapping degradation histories that mix behaviors from different modes. This architecture enables precise compensation without excessive memory or processing overhead.

[0072] like Figure 2A As illustrated, the first display area DA1 and the second display area DA2 can operate in a first mode. In the first mode, in addition to the first image IM1 displayed in the first display area DA1, the driver's DV in the vehicle AM ​​can also see the second image IM2 displayed in the second display area DA2. Furthermore, in the first mode, in addition to the second image IM2 displayed in the second display area DA2, the passenger sitting in the passenger seat can also see the first image IM1 displayed in the first display area DA1.

[0073] like Figure 2B As illustrated, the first display area DA1 can operate in a first mode, and the second display area DA2 can operate in a second mode. In this case, although the driver's DV can see the first image IM1 displayed in the first display area DA1, the driver's DV cannot see the second image IM2 displayed in the second display area DA2.

[0074] According to embodiments of this disclosure, mode switching in the second display area DA2 (e.g., switching from a first mode to a second mode, or vice versa) can be performed automatically depending on the driving speed of the vehicle AM. For example, when the vehicle AM's driving speed is approximately equal to or less than a certain reference speed, the second display area DA2 can operate in the first mode. However, when the vehicle AM's driving speed exceeds the reference speed, the operating mode of the second display area DA2 can be switched to the second mode. Accordingly, in embodiments, when the driving speed exceeds the reference speed, the driver DV cannot see the second image IM2 displayed in the second display area DA2. In embodiments, mode switching in the second display area DA2 can be performed by user intervention (e.g., manual intervention), regardless of driving speed.

[0075] like Figure 2C As illustrated, the first display area DA1 can operate in the first mode, and a portion of the second display area DA2 (i.e., the mode switching area CDA) can operate in the second mode. Although the mode switching area CDA in the second display area DA2 operates in the second mode, the remaining areas in the second display area DA2 other than the mode switching area CDA (i.e., the outer area SDA) can operate in the first mode. In this case, while the driver's DV can see the outer image displayed on the outer area SDA in the second display area DA2, the driver's DV cannot see the center image displayed on the mode switching area CDA in the second display area DA2.

[0076] Figure 3A The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area and a second display area operating in a first mode. Figure 3B The figure illustrates the state of an electronic device according to an embodiment of the present disclosure, the electronic device including a first display area operating in a first mode and a first mode switching area and a second mode switching area in a second display area operating in a second mode.

[0077] like Figure 3AAs illustrated, the first display area DA1 and the second display area DA2 can operate in a first mode. In the first mode, in addition to the first image IM1 displayed in the first display area DA1, the driver's DV of the vehicle AM ​​can also see the second image IM2 displayed in the second display area DA2. According to embodiments of the present disclosure, the second display area DA2 may include a first mode switching area CDA1 displaying the first center image CIM1, a second mode switching area CDA2 displaying the second center image CIM2, and an outer area SDA surrounding the first mode switching area CDA1 and the second mode switching area CDA2. The first mode switching area CDA1 and the second mode switching area CDA2 may be spaced apart from each other in a first direction DR1. However, the present disclosure is not limited thereto. For example, according to embodiments, the first mode switching area CDA1 and the second mode switching area CDA2 may be spaced apart from each other in a direction different from the first direction DR1 (e.g., a second direction DR2). Furthermore, the number and shape of the mode switching areas provided in the second display area DA2 may vary. When the second display area DA2 is operating in the first mode, the first mode switching area CDA1, the second mode switching area CDA2, and the outer area SDA can operate in the first mode.

[0078] like Figure 3B As illustrated, the first display area DA1 can operate in the first mode, and a portion of the second display area DA2 (i.e., at least one of the first mode switching area CDA1 and the second mode switching area CDA2) can operate in the second mode. In this case, the outer area SDA in the second display area DA2 can operate in the first mode. When the first mode switching area CDA1 and the second mode switching area CDA2 operate in the second mode, the driver's DV can see the outer image on the outer area SDA in the second display area DA2, but cannot see the first center image CIM1 and the second center image CIM2 displayed on the first mode switching area CDA1 and the second mode switching area CDA2 in the second display area DA2, respectively.

[0079] Figure 4A This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure, and Figure 4B This is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. Figure 5A It is shown in the figure. Figure 4A The figure shows an enlarged cross-sectional view of a portion of the electronic device. Figure 5B It is shown in the figure. Figure 4B The figure shows an enlarged cross-sectional view of a portion of the electronic device.

[0080] refer to Figure 4A An electronic device DD may include a display panel DP and an input sensing layer ISP. The input sensing layer ISP may be referred to as an input sensing panel.

[0081] The display panel DP may include a first substrate layer BS1, a display circuit layer DP_CL, a display element layer DP_ED, a second substrate layer BS2, and a connection component SLM. The input sensing layer ISP may be disposed on the second substrate layer BS2.

[0082] Each of the first substrate layer BS1 and the second substrate layer BS2 may be a stacked structure including, for example, a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or multiple insulating layers.

[0083] The display circuit layer DP_CL can be disposed on the first substrate layer BS1. The display circuit layer DP_CL may include a semiconductor layer, multiple insulating layers, and multiple conductive layers. The multiple conductive layers of the display circuit layer DP_CL can constitute the control circuitry for signal lines or pixels.

[0084] The display element layer DP_ED can be disposed on the display circuit layer DP_CL. The display element layer DP_ED can include light-emitting elements. For example, the display element layer DP_ED can include organic light-emitting diodes, inorganic light-emitting diodes, quantum dots, quantum rods, micron LEDs, or nano LEDs.

[0085] A second substrate layer BS2 can be disposed on the display element layer DP_ED. A specific space can be defined between the second substrate layer BS2 and the display element layer DP_ED. This space can be filled with air or an inert gas. Furthermore, according to embodiments of this disclosure, this space can be filled with a filler layer FL, such as a silicone polymer, epoxy resin, or acrylic resin (see [link to documentation]). Figure 5A ).

[0086] The connecting member SLM can be inserted between the first substrate layer BS1 and the second substrate layer BS2. The connecting member SLM can connect the first substrate layer BS1 to the second substrate layer BS2. The connecting member SLM can include organic materials such as light-curable resins or photoplastic resins, or inorganic materials such as glass solder sealants, but this disclosure is not limited to any one embodiment.

[0087] The input sensing layer (ISP) may include multiple insulating layers and multiple conductive layers. The multiple conductive layers may form sensing electrodes for sensing external inputs, sensing lines electrically connected to the sensing electrodes, and sensing pads electrically connected to the sensing lines.

[0088] The electronic device DD may further include an optical path control layer (OSL). The OSL may be disposed on the input sensing layer (ISP). The OSL may include structures for controlling the path of light output from the display panel DP.

[0089] refer to Figure 4B The electronic device DD_1 may include a display panel DP_1, an input sensing layer ISP_1, and an optical path control layer OSL_1.

[0090] The display panel DP_1 may include a substrate layer BS, a display circuit layer DP_CL, a display element layer DP_ED, and a packaging layer TFE. The substrate layer BS may be flexible. The input sensing layer ISP_1 may be disposed on the packaging layer TFE. According to embodiments of this disclosure, the display panel DP_1 and the input sensing layer ISP_1 can be formed by a continuous process. In other words, the input sensing layer ISP_1 may be formed directly on the packaging layer TFE.

[0091] The optical path control layer OSL_1 can be disposed on the input sensing layer ISP_1. The optical path control layer OSL_1 can be formed through a continuous process with the display panel DP_1 and the input sensing layer ISP_1, such that the optical path control layer OSL_1 is directly disposed on the input sensing layer ISP_1. However, this disclosure is not limited thereto. For example, the optical path control layer OSL_1 can be bonded to the input sensing layer ISP_1 through an adhesive layer. (See reference...) Figure 10A and Figure 10B Let's describe the configuration of the optical path control layer OSL_1 in more detail.

[0092] refer to Figure 4A and Figure 5A At least one inorganic layer can be formed on the top surface of the first substrate layer BS1 in the display panel DP. The inorganic layer may include at least one of, for example, aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, and hafnium oxide. The inorganic layer may have a multilayer structure. The inorganic layers in the multilayer may form barrier layers and / or buffer layers. According to an embodiment, the display panel DP is illustrated to include a buffer layer BFL.

[0093] The buffer layer BFL can improve the bonding strength between the first substrate layer BS1 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0094] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor patterns may include polycrystalline silicon (e.g., low-temperature polycrystalline silicon). However, this disclosure is not limited thereto. For example, the semiconductor patterns may include amorphous silicon or oxide semiconductors.

[0095] Figure 5AOnly a portion of the semiconductor pattern is illustrated, and this semiconductor pattern may be further disposed in another region. The semiconductor pattern may be provided across pixels according to specific rules. The semiconductor pattern may have electrical characteristics that vary depending on the doping state. The semiconductor pattern may include a first region with higher conductivity and a second region with lower conductivity. The first region may be doped with N-type or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second region may be undoped, or it may be doped at a lower concentration than the first region.

[0096] The conductivity of the first region can be greater than that of the second region, and it can be essentially used as an electrode or signal line. The second region can essentially correspond to the channel region (or active region) of a transistor. In other words, a portion of the semiconductor pattern can be the channel portion of a transistor, another portion of the semiconductor pattern can be the source or drain, and yet another portion of the semiconductor pattern can be a connecting electrode or a connecting signal line.

[0097] Each pixel may have an equivalent circuit comprising multiple transistors, at least one capacitor, and at least one light-emitting element, and the equivalent circuit of a pixel may be modified in various forms. Figure 5A The middle image shows a transistor 100PC and a light-emitting element 100PE included in a pixel.

[0098] Transistor 100PC may include a source S1, a channel portion CH1, a drain D1, and a gate G1. The source S1, the channel portion CH1, and the drain D1 may be formed by a semiconductor pattern. When viewed in a cross-sectional view, the source S1 and the drain D1 may extend from the channel region CH1 in opposite directions. Figure 5A The middle diagram shows a portion of the connection signal line SCL formed by a semiconductor pattern. When viewed in a plan view, the connection signal line SCL can be connected to the drain D1 of transistor 100PC.

[0099] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may commonly overlap with multiple pixels and may cover a semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of, for example, aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. According to an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the display circuit layer DP_CL, which will be described below, may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above, but this disclosure is not limited thereto.

[0100] Gate G1 is disposed on the first insulating layer 10. Gate G1 may be part of a metal pattern. Gate G1 overlaps with the channel portion CH1. Gate G1 may function as a mask in a process of doping a semiconductor pattern.

[0101] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G1. The second insulating layer 20 may commonly overlap with multiple pixels. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. According to an embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0102] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0103] The first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL through the contact hole CNT-1 formed through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0104] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0105] The second connecting electrode CNE2 can be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 formed through the fourth insulating layer 40 and the fifth insulating layer 50.

[0106] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0107] The display element layer DP_ED can be disposed on the display circuit layer DP_CL. The display element layer DP_ED may include a light-emitting element 100PE and a pixel defining layer 70. For example, the display element layer DP_ED may include organic light-emitting materials, inorganic light-emitting materials, quantum dots, quantum rods, micron LEDs, or nano LEDs. The following description will assume that the light-emitting element 100PE is an organic light-emitting element, but this disclosure is not limited thereto.

[0108] The light-emitting element 100PE may include a first electrode AE, a light-emitting layer EL, and a second electrode CE. The first electrode AE ​​may be disposed on a sixth insulating layer 60. The first electrode AE ​​may be connected to a second connecting electrode CNE2 through a contact hole CNT-3 formed through the sixth insulating layer 60. The first electrode AE ​​may be referred to as the anode.

[0109] A pixel defining layer 70 may be disposed on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE.

[0110] Display area DA (see Figure 2A The electrode may include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA may surround the light-emitting region PXA. According to an embodiment, the light-emitting region PXA is defined to correspond to the portion of the first electrode AE ​​exposed through the opening 70-OP.

[0111] The light-emitting layer EL can be disposed on the first electrode AE. The light-emitting layer EL can be disposed in the area corresponding to the opening 70-OP. In other words, the light-emitting layer EL can be formed individually in each pixel. When the light-emitting layer EL is formed individually in each pixel, each of the light-emitting layer EL can emit light of at least one color selected from blue, red, and green. However, this disclosure is not limited thereto. For example, the light-emitting layer EL can be commonly formed in multiple pixels. In this case, the light-emitting layer EL can provide blue light or it can provide white light.

[0112] The second electrode CE can be disposed on the light-emitting layer EL. The second electrode CE can be formed integrally and can be commonly disposed in multiple pixels. The second electrode CE can be referred to as the cathode.

[0113] A hole control layer can be interposed between the first electrode AE ​​and the light-emitting layer EL. The hole control layer can be commonly disposed in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer can be disposed between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer can be commonly formed in multiple pixels using an aperture mask.

[0114] The second substrate layer BS2 can be disposed on the display element layer DP_ED. According to embodiments of this disclosure, the first substrate layer BS1 and the second substrate layer BS2 can be of a rigid type.

[0115] The filler layer FL can be disposed between the first base layer BS1 and the second base layer BS2. The filler layer FL can be disposed between the first base layer BS1 and the second base layer BS2, connected to the component SLM (see [link to component SLM]). Figure 4A In a sealed space. The filler layer FL may include thermosetting materials.

[0116] The input sensing layer (ISP) can be located on the display panel (DP). For example, the input sensing layer (ISP) can be located on the second substrate layer (BS2).

[0117] refer to Figure 4B and Figure 5B The encapsulation layer TFE can be disposed on the display element layer DP_ED. The encapsulation layer TFE may include inorganic layers, organic layers and inorganic layers stacked in sequence, and the layers constituting the encapsulation layer TFE are not limited to these.

[0118] The inorganic layer protects the display element layer DP_ED from factors such as moisture and oxygen, while the organic layer protects the display element layer DE_ED from foreign matter such as dust particles. The inorganic layer may include, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include acrylic organic layers, but this disclosure is not limited thereto.

[0119] The input sensing layer ISP_1 can be disposed on the display panel DP_1 through a continuous process. In this case, it can be stated that the input sensing layer ISP_1 is directly disposed on the display panel DP_1 (e.g., the encapsulation layer TFE). "The input sensing layer ISP_1 can be directly disposed on the display panel DP_1" means that no third component is inserted between the input sensing layer ISP_1 and the display panel DP_1. In other words, when one layer is directly disposed on another, no additional adhesive or connecting component is provided between the input sensing layer ISP_1 and the display panel DP_1. In embodiments, the input sensing layer ISP_1 can be attached to the display panel DP_1 by an adhesive component or a connecting component. The adhesive component can include conventional adhesives or conventional glues.

[0120] refer to Figure 5A and Figure 5B The input sensing layers ISP and ISP_1 may include a substrate insulating layer 201, a first conductive layer 202, an intermediate insulating layer 203, a second conductive layer 204, and a cover insulating layer 205.

[0121] In one embodiment, the substrate insulating layer 201 may be an inorganic layer comprising, for example, at least one of silicon nitride, silicon oxynitride, and silicon oxide. In another embodiment, the substrate insulating layer 201 may be an organic layer comprising, for example, epoxy resin, acrylate resin, or imide resin. The substrate insulating layer 201 may have a monolayer structure, or it may be a structure in which multiple layers are stacked on a third-direction DR3.

[0122] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure or a multi-layer structure comprising multiple layers stacked on the third-direction DR3.

[0123] The conductive layer of a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide, indium zinc oxide, zinc oxide, or indium zinc tin oxide. Furthermore, the transparent conductive layer may include, for example, conductive polymers (such as PEDOT), metal nanowires, or graphene.

[0124] The conductive layer in a multilayer structure may include a metal layer. The metal layer may, for example, have a three-layer structure of titanium / aluminum / titanium. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0125] At least one of the intermediate insulating layer 203 and the cover insulating layer 205 may include an inorganic film. The inorganic film may include at least one of, for example, alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0126] At least one of the intermediate insulating layer 203 and the cover insulating layer 205 may include an organic film. The organic film may include at least one of, for example, acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0127] Figure 6 This is a block diagram of a display panel according to an embodiment of the present disclosure.

[0128] refer to Figure 6 A display panel (DP) can be a component configured to generate and display images. A display panel (DP) can be an emissive display panel. For example, a display panel (DP) can be an organic light-emitting display panel, a quantum dot display panel, a micron-LED display panel, or a nano-LED display panel.

[0129] The display panel DP includes the display area DP_DA and the non-display area DP_NDA surrounding and adjacent to the display area DP_DA. The display area DP_DA can be... Figure 2AThe area corresponding to the display area DA shown in the diagram, and the non-display area DP_NDA can be the same as the area in the diagram. Figure 2A The diagram shows the area corresponding to the non-display area NDA. The display area DP_DA can be the area where the image is displayed, and the non-display area DP_NDA can be the border area where the image is not displayed.

[0130] The display area DP_DA includes a first display area DP_DA1 and a second display area DP_DA2. The first display area DP_DA1 can be... Figure 2A The area corresponding to the first display area DA1 shown in the figure, and the second display area DP_DA2 can be the area corresponding to... Figure 2A The area corresponding to the second display area DA2 shown in the figure. Although Figure 6 The diagram illustrates the structure of the non-display area DP_NDA surrounding the first display area DP_DA1 and the second display area DP_DA2, but this disclosure is not limited thereto. In embodiments, the non-display area DP_NDA may be provided only on at least one side of the first display area DP_DA1 and the second display area DP_DA2.

[0131] although Figure 6 The illustration shows that the size of the second display area DP_DA2 is smaller than the size of the first display area DP_DA1, but this disclosure is not limited thereto. For example, in an embodiment, the size of the first display area DP_DA1 and the size of the second display area DP_DA2 may be approximately equal to each other.

[0132] The display panel DP includes a plurality of pixels and signal lines connected to the plurality of pixels. Each of the plurality of pixels may include a light-emitting element. The signal lines may include, for example, data lines, scan lines, light-emitting control lines, and power lines. In this case, the pixel disposed in the first display area DP_DA1 is referred to as the first pixel PX1, and the pixel disposed in the second display area DP_DA2 is referred to as the second pixel PX2. According to embodiments of the present disclosure, the first pixel PX1 and the second pixel PX2 may have the same shape and the same size. However, the present disclosure is not limited thereto, and in some embodiments, the first pixel PX1 and the second pixel PX2 may have different shapes and different sizes.

[0133] Electronic device DD (see Figure 2A The system further includes a driving circuit for driving the display panel DP. The driving circuit may include multiple driving chips, a scanning driving circuit SDC, and a light-emitting driving circuit EDC. The multiple driving chips may include a first driving chip DIC1 and a second driving chip DIC2 connected to the first display area DP_DA1, and a third driving chip DIC3 connected to the second display area DP_DA2. The number of driving chips may vary depending on the size and resolution of the display area.

[0134] The scan driving circuit SDC includes a first scan driving circuit SDC1 connected to the first display area DP_DA1 and a second scan driving circuit SDC2 connected to the second display area DP_DA2. The light emission driving circuit EDC includes a first light emission driving circuit EDC1 connected to the first display area DP_DA1 and a second light emission driving circuit EDC2 connected to the second display area DP_DA2.

[0135] According to embodiments of this disclosure, a first scan driving circuit SDC1 and a first light-emitting driving circuit EDC1 are disposed on one side (e.g., the left side) of the first display area DP_DA1, and a second scan driving circuit SDC2 and a second light-emitting driving circuit EDC2 are disposed on one side (e.g., the right side) of the second display area DP_DA2. In embodiments, the first scan driving circuit SDC1 and the first light-emitting driving circuit EDC1 may be disposed on opposite sides of the first display area DP_DA1, and the second scan driving circuit SDC2 and the second light-emitting driving circuit EDC2 may be disposed on opposite sides of the second display area DP_DA2.

[0136] The first switch line MSL1 and the second switch line MSL2 can be located on one side (e.g., the right side) of the second display area DP_DA2. The first switch line MSL1 and the second switch line MSL2 are connected to the second pixel PX2.

[0137] The first switch line MSL1 and the second switch line MSL2 can be controlled by the drive controller T_CON, which controls the scanning drive circuit SDC and the light-emitting drive circuit EDC, respectively (see [link to controller T_CON]). Figure 11A ) Receives the first switch signal MS1 and the second switch signal MS2 (see Figure 7 ).

[0138] Figure 7 This is a circuit diagram of the second pixel according to an embodiment of the present disclosure. Figure 8 It is used to describe Figure 7 The waveform diagram of the operation of the second pixel is shown in the figure. Figure 7 The diagram shows... Figure 6 The diagram shows the equivalent circuit diagram of one of the multiple second pixels PX2, namely PX2_ij. In the following description, for ease of description, since each of the second pixels PX2 has the same circuit structure, the circuit structure of the second pixel PX2_ij will be described representatively, and the details of the other second pixels will be omitted.

[0139] refer to Figure 7The second pixel PX2_ij is connected to the i-th data line DLi (hereinafter referred to as a data line) among multiple data lines, and to the j-th initialization scan line SILj (hereinafter referred to as an initialization scan line), the j-th compensation scan line SCLj (hereinafter referred to as a compensation scan line), the j-th write scan line SWLj (hereinafter referred to as a write scan line), and the j-th black scan line SBLj (hereinafter referred to as a black scan line) among multiple scan lines, and to the j-th light emission control line EMLj (hereinafter referred to as a light emission control line) among multiple light emission control lines, where each of i and j is a positive integer. According to an embodiment of this disclosure, the second pixel PX2_ij is connected to the first switch line MSL1 and the second switch line MSL2.

[0140] The second pixel PX2_ij includes a first light-emitting element (or wide light-emitting element) ED1, a second light-emitting element (or narrow light-emitting element) ED2, and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, a first capacitor Cst, and a second capacitor Chold. Each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and ninth transistor T9 can be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and ninth transistor T9 can be P-type transistors. However, this disclosure is not limited thereto. For example, according to an embodiment, the first transistor T1 to the ninth transistor T9 can all be N-type transistors. According to embodiments, some of the first transistors T1 to the ninth transistor T9 may be P-type transistors, and the remaining transistors may be N-type transistors. For example, among the first transistors T1 to the ninth transistor T9, the first transistor T1, the second transistor T2, and the fifth transistors T5 to the ninth transistor T9 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors including an oxide semiconductor layer. However, the configuration of the pixel circuit PXC according to embodiments of this disclosure is not limited. Figure 7 The embodiment shown in the figure. Figure 7 The pixel circuit PXC illustrated herein is provided for illustrative purposes only, and the configuration of the pixel circuit PXC can be modified according to embodiments. For example, the first transistor T1 to the ninth transistor T9 can all be P-type transistors or N-type transistors.

[0141] The initialization scan line SILj, compensation scan line SCLj, write scan line SWLj, black scan line SBLj, and emission control line EMLj can respectively apply the j-th initialization scan signal SIj (hereinafter referred to as the initialization scan signal), the j-th compensation scan signal SCj (hereinafter referred to as the compensation scan signal), the j-th write scan signal SWj (hereinafter referred to as the write scan signal), the j-th black scan signal SBj (hereinafter referred to as the black scan signal), and the j-th emission control signal EMj (hereinafter referred to as the emission control signal) to the second pixel PX2_ij. The data line DLi applies the data signal Di to the second pixel PX2_ij. The first switch line MSL1 can apply the first switch signal MS1 to the second pixel PX2_ij, and the second switch line MSL2 can apply the second switch signal MS2 to the second pixel PX2_ij.

[0142] The first driving voltage line VL1 and the second driving voltage line VL2 can supply the first driving voltage ELVDD and the second driving voltage ELVSS to the second pixel PX2_ij, respectively. The second pixel PX2_ij can receive the first initialization voltage VINT and the second initialization voltage VAINT through the first initialization voltage line VIL and the second initialization voltage line VAIL, respectively. The second pixel PX2_ij can further receive the reference voltage VREF through the reference voltage line VRL. Although... Figure 7 The diagram shows the structure in which five voltage lines are connected to the second pixel PX2_ij, but the number of voltage lines connected to the second pixel PX2_ij can be changed differently.

[0143] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1, a second electrode electrically connected to the common node CN via the sixth transistor T6, and a gate electrode connected to the first terminal (or the first node N1) of the second capacitor Chold. The first transistor T1 can receive the data signal Di transmitted via the data line DLi in response to the switching operation of the second transistor T2, and can supply the drive current Id to the common node CN.

[0144] The second transistor T2 may include a second-first transistor T2_1 and a second-second transistor T2_2. The second-first transistor T2_1 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the second-second transistor T2_2, and a gate electrode connected to the write scan line SWLj. The second-second transistor T2_2 includes a first electrode connected to the second electrode of the second-first transistor T2_1, a second electrode connected to the second terminal (or referred to as the "second node" N2) of the second capacitor Chold, and a gate electrode connected to the write scan line SWLj. The second-first transistor T2_1 and the second-second transistor T2_2 may be turned on in response to a write scan signal SWj received via the write scan line SWLj, to transmit the data signal Di received via the data line DLi to the gate electrode of the first transistor T1.

[0145] The first terminal of the first capacitor Cst is connected to the second node N2, and the second terminal of the first capacitor Cst is connected to the first drive voltage line VL1.

[0146] The third transistor T3 may include a third-first transistor T3_1 and a third-second transistor T3_2. The third-first transistor T3_1 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode of the third-second transistor T3_2, and a gate electrode connected to the compensation scan line SCLj. The third-second transistor T3_2 includes a first electrode connected to the second electrode of the third-first transistor T3_1, a second electrode connected to the gate electrode of the first transistor T1 (i.e., the first node N1), and a gate electrode connected to the compensation scan line SCLj. The third-first transistor T3_1 and the third-second transistor T3_2 can be turned on in response to a compensation scan signal SCj transmitted via the compensation scan line SCLj. Accordingly, the gate electrode and the second electrode of the first transistor T1 are connected to each other to diode-connect the first transistor T1.

[0147] The fourth transistor T4 may include a fourth-first transistor T4_1, a fourth-second transistor T4_2, and a fourth-third transistor T4_3. These transistors may be connected in series between the first node N1 and the first initialization voltage line VIL. Each transistor has a gate electrode that is commonly connected to the initialization scan line SILj to receive the initialization scan signal SIj. When these transistors are turned on in response to the initialization scan signal SIj, the gate electrode of the first transistor T1 (i.e., the first node N1) can be initialized with the first initialization voltage VINT.

[0148] The fifth transistor T5 may include a fifth-first transistor T5_1 and a fifth-second transistor T5_2. The fifth-first transistor T5_1 and the fifth-second transistor T5_2 may be connected in series between the second node N2 and the reference voltage line VRL. The fifth-first transistor T5_1 and the fifth-second transistor T5_2 have gate electrodes that are commonly connected to the compensation scan line SCLj to receive the compensation scan signal SCj. When the fifth-first transistor T5_1 and the fifth-second transistor T5_2 are turned on in response to the compensation scan signal SCj, the second node N2 can be initialized with the reference voltage VREF.

[0149] The sixth transistor T6 (or "light-emitting control transistor") includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the common node CN, and a gate electrode connected to the light-emitting control line EMLj.

[0150] The sixth transistor T6 is turned on in response to the light-emitting control signal EMj received via the light-emitting control line EMLj. The drive current Id can be transmitted to the common node CN through the turned-on sixth transistor T6.

[0151] The seventh transistor T7 may include a 7-1 transistor T7_1 and a 7-2 transistor T7_2. The 7-1 transistor T7_1 (or referred to as the "first initialization transistor") includes a first electrode connected to the anode of the first light-emitting element ED1, a second electrode connected to the second initialization voltage line VAIL, and a gate electrode connected to the black scan line SBLj. The 7-2 transistor T7_2 (or referred to as the "second initialization transistor") includes a first electrode connected to the anode of the second light-emitting element ED2, a second electrode connected to the second initialization voltage line VAIL, and a gate electrode connected to the black scan line SBLj. The 7-1 transistor T7_1 and the 7-2 transistor T7_2 have a common gate electrode connected to the black scan line SBLj to receive the black scan signal SBj. When the 7-1 transistor T7_1 and the 7-2 transistor T7_2 are turned on in response to the black scan signal SBj, the anodes of the first light-emitting element ED1 and the second light-emitting element ED2 can be initialized using the second initialization voltage VAINT.

[0152] The cathodes of the first light-emitting element ED1 and the second light-emitting element ED2 can be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS.

[0153] A first switching circuit SW1 is inserted between a common node CN and a first light-emitting element ED1, and a second switching circuit SW2 is inserted between a common node CN and a second light-emitting element ED2. According to an embodiment of this disclosure, the first switching circuit SW1 includes an eighth transistor T8, and the second switching circuit SW2 includes a ninth transistor T9. The eighth transistor T8 may be referred to as a first-mode switching transistor, and the ninth transistor T9 may be referred to as a second-mode switching transistor. The eighth transistor T8 includes a first electrode connected to the common node CN, a second electrode connected to the anode of the first light-emitting element ED1, and a gate electrode connected to the first switching line MSL1. The ninth transistor T9 includes a first electrode connected to the common node CN, a second electrode connected to the anode of the second light-emitting element ED2, and a gate electrode connected to the second switching line MSL2.

[0154] In the first mode, the eighth transistor T8 can be turned on in response to the first switching signal MS1 received through the first switching line MSL1, and the first light-emitting element ED1 can receive the drive current Id through the turned-on eighth transistor T8. Since the ninth transistor T9 is turned off in the first mode, the drive current Id can be provided only to the first light-emitting element ED1. The second pixel PX2 (see...) Figure 6 In the first mode, the eighth transistor T8 of the second pixel PX2 can be fully turned on in response to the first switch signal MS1, and the ninth transistor T9 of the second pixel PX2 can be fully turned off in response to the second switch signal MS2. In the second mode, the ninth transistor T9 can be turned on in response to the second switch signal MS2 received through the second switch line MSL2, and the second light-emitting element ED2 can receive the drive current Id through the turned-on ninth transistor T9. Since the eighth transistor T8 is turned off in the second mode, the drive current Id can be provided only to the second light-emitting element ED2. In the second mode, the ninth transistor T9 of the second pixel PX2 can be fully turned on in response to the second switch signal MS2, and the eighth transistor T8 of the second pixel PX2 can be fully turned off in response to the first switch signal MS1.

[0155] The second pixel PX2_ij can display an image using the first light-emitting element ED1 in a first mode, and can display an image using the second light-emitting element ED2 in a second mode. However, this disclosure is not limited thereto. For example, in an embodiment, the second pixel PX2_ij can display an image using both the first light-emitting element ED1 and the second light-emitting element ED2 in a first mode, and can display an image using only the second light-emitting element ED2 in a second mode. In this case, in the first mode, the eighth transistor T8 and the ninth transistor T9 can be turned on simultaneously.

[0156] refer to Figure 7 and Figure 8 When an initialization scan signal SIj at a low level is provided through the initialization scan line SILj during the initialization period of frame f1, transistors 4-1 to 4-3 are turned on in response to the low-level initialization scan signal SIj. The first initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 (i.e., the first node N1) through the turned-on transistors 4-1 to 4-3, and the gate electrode of the first transistor T1 is initialized by the first initialization voltage VINT.

[0157] Next, when a low-level compensation scan signal SCj is supplied through the compensation scan line SCLj during the compensation period of frame f1, transistors T3_1 (3-1) and T3_2 (3-2) are turned on. The compensation period can be non-overlapping with the initialization period. The activation period of the compensation scan signal SCj is defined as the period during which the compensation scan signal SCj is low, and the activation period of the initialization scan signal SIj is defined as the period during which the initialization scan signal SIj is low. The activation period of the compensation scan signal SCj can be non-overlapping with the activation period of the initialization scan signal SIj. The activation period of the initialization scan signal SIj can be earlier than the activation period of the compensation scan signal SCj.

[0158] During the compensation period, the first transistor T1 is connected to a diode via the conducting third-1 transistor T3_1 and third-2 transistor T3_2, and is forward biased. Furthermore, the compensation period may include a data writing period in which a write scan signal SWj is generated at a low level. During the data writing period, the second-1 transistor T2_1 and the second-2 transistor T2_2 are turned on in response to the low-level write scan signal SWj. Then, a compensation voltage (Di-Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the data signal Di supplied by the data line DL1 is applied to the gate electrode of the first transistor T1. In other words, the potential of the gate electrode of the first transistor T1 can be the compensation voltage (Di-Vth).

[0159] The first driving voltage ELVDD and the data signal Di can be applied to the opposite ends of the first capacitor Cst respectively, and the charge corresponding to the voltage difference between the opposite ends of the first capacitor Cst can be stored in the first capacitor Cst.

[0160] Simultaneously, transistors 7-1 (T7_1) and 7-2 (T7_2) are turned on by receiving the low-level black scan signal SBLj via the black scan line SBLj. A portion of the drive current Id can flow out from transistors 7-1 (T7_1) and 7-2 (T7_2) as bypass current.

[0161] Next, the light-emitting control signal EMj supplied from the light-emitting control line EMLj is changed from a high level to a low level. The sixth transistor T6 is turned on in response to the low-level light-emitting control signal EMj. Subsequently, a drive current Id can be generated due to the voltage difference between the gate voltage across the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and this drive current Id can be provided to the common node CN through the sixth transistor T6. The drive current Id can be provided to the first light-emitting element ED1 or the second light-emitting element ED2 through the eighth transistor T8 or the ninth transistor T9, which is turned on depending on the mode.

[0162] Figure 9A This is a view illustrating a wide light-emitting element turned on in a first mode according to an embodiment of the present disclosure. Figure 9B This is a view illustrating a narrow light-emitting element turned on in a second mode according to an embodiment of the present disclosure. Figure 10A It is along Figure 9A The figure shows a cross-sectional view taken by line I-I'. Figure 10B It is along Figure 9B The cross-sectional view taken by line II-II' shown in the figure.

[0163] refer to Figure 9A and Figure 9B Multiple second pixels PX2 (see Figure 6 ) is set in the second display area DA2 in units of pixel units PXU (see Figure 6 )middle.

[0164] According to embodiments of this disclosure, a pixel unit PXU may include a red pixel R_PX, a green pixel G_PX, and a blue pixel B_PX. The red pixel R_PX includes a red pixel circuit PXC1, a first red light-emitting element R_ED1, and a second red light-emitting element R_ED2. The green pixel G_PX includes a green pixel circuit PXC2, a first green light-emitting element G_ED1, and a second green light-emitting element G_ED2. The blue pixel B_PX includes a blue pixel circuit PXC3, a first blue light-emitting element B_ED1, a second-first blue light-emitting element B_ED21, and a second-second blue light-emitting element B_ED22. In this case, the first red light-emitting element R_ED1, the first green light-emitting element G_ED1, and the first blue light-emitting element B_ED1 can be referred to as wide light-emitting elements, and the second red light-emitting element R_ED2, the second green light-emitting element G_ED2, and the second-first blue light-emitting elements B_ED21 and B_ED22 can be referred to as narrow light-emitting elements.

[0165] According to embodiments of this disclosure, the first red light-emitting element R_ED1 may have a larger size than the second red light-emitting element R_ED2, and the first green light-emitting element G_ED1 may have a larger size than the second green light-emitting element G_ED2. The first blue light-emitting element B_ED1 may have a larger size than the second-first blue light-emitting element B_ED21 and the second-second blue light-emitting element B_ED22. The second-first blue light-emitting element B_ED21 and the second-second blue light-emitting element B_ED22 may have approximately equal sizes to each other.

[0166] although Figure 9A and Figure 9B The illustration shows a wide light-emitting element having a larger size than a narrow light-emitting element, but this disclosure is not limited thereto. For example, according to embodiments of this disclosure, a first red light-emitting element R_ED1 may have a size approximately equal to that of a second red light-emitting element R_ED2, and a first green light-emitting element G_ED1 may have a size approximately equal to that of a second green light-emitting element G_ED2.

[0167] Multiple light-absorbing partition walls (LAWs) can be formed on a narrow light-emitting element. These multiple light-absorbing partition walls can overlap with the narrow light-emitting element and can also be in a non-overlapping state with a wide light-emitting element. Multiple light-absorbing partition walls (LAWs) can be included in... Figures 4A to 5BThe optical path control layers OSL and OSL_1 are shown in the figure. According to embodiments of this disclosure, a plurality of light-absorbing partition walls LAW can overlap with the light-emitting areas of the second red light-emitting element R_ED2, the second green light-emitting element G_ED2, the second-first blue light-emitting element B_ED21, and the second-second blue light-emitting element B_ED22. According to embodiments of this disclosure, the plurality of light-absorbing partition walls LAW can extend in the second direction DR2 and can be spaced apart from each other in the first direction DR1. The light-absorbing partition walls LAW can absorb a portion of the light traveling in the lateral direction (referred to as sidelight) of the light output from the second red light-emitting element R_ED2, the second green light-emitting element G_ED2, the second-first blue light-emitting element B_ED21, and the second-second blue light-emitting element B_ED22. Sidelight can refer to light emitted in a direction inclined at a specific angle or greater relative to a line perpendicular to the light-emitting surface of the narrow light-emitting element.

[0168] The pixel unit PXU can display an image using a wide light-emitting element in a first mode and a narrow light-emitting element in a second mode. Because the sidelight in the light output through the narrow light-emitting element is absorbed by the light-absorbing separator LAW in the second mode, the viewing angle of the image displayed in the second mode can be narrower than that displayed in the first mode. Accordingly, when the second display area DP_DA2 operates in the second mode, the driver DV (see...) Figure 2B The second image IM2 cannot be seen (see...) Figure 2B ).

[0169] According to embodiments of this disclosure, using different light-emitting elements in a first mode and a second mode may result in different optical and electrical stress distributions over time. For example, a wide light-emitting element used in the first mode may operate at different current densities or emission durations compared to a narrow light-emitting element used in the second mode. Even within the same pixel unit (PXU), these operational differences can lead to asymmetrical aging or degradation characteristics between the two types of elements. To maintain consistent image quality and prevent afterimage artifacts, embodiments of this disclosure can independently track degradation information for each mode or for each type of light-emitting element and apply compensation accordingly. This approach can provide precise brightness control and improved visual performance in both public and private display modes.

[0170] When the first switch signal MS1 is activated in the first mode, the red pixel R_PX, green pixel G_PX, and blue pixel B_PX can display images using the first red light-emitting element R_ED1, the first green light-emitting element G_ED1, and the first blue light-emitting element B_ED1, respectively. Since the second switch signal MS2 is deactivated in the first mode, the second red light-emitting element R_ED2, the second green light-emitting element G_ED2, the second-first blue light-emitting element B_ED21, and the second-second blue light-emitting element B_ED22 remain off.

[0171] Simultaneously, when the second switch signal MS2 is activated in the second mode, the red pixel R_PX, green pixel G_PX, and blue pixel G_PX can display images using the second red light-emitting element R_ED2, the second green light-emitting element G_ED2, and the second-1 blue light-emitting element B_ED21 and the second-2 blue light-emitting element B_ED22, respectively. Since the first switch signal MS1 is deactivated in the second mode, the first red light-emitting element R_ED1, the first green light-emitting element G_ED1, and the first blue light-emitting element B_ED1 remain off.

[0172] refer to Figure 10A and Figure 10B The first blue light-emitting element B_ED1 includes a first blue anode AE1, a first blue light-emitting layer EL1, and a cathode CE. The pixel defining layer 70 has a first blue opening 70-OP1 provided in the pixel defining layer 70 to expose the first blue anode AE1, and the first blue light-emitting layer EL1 is disposed on the first blue anode AE1 exposed through the first blue opening 70-OP1.

[0173] The second-1 blue light-emitting element B_ED21 includes a second blue anode AE2, a second-1 blue light-emitting layer EL21, and a cathode CE, and the second-2 blue light-emitting element B_ED22 includes a second blue anode AE2, a second-2 blue light-emitting layer EL22, and a cathode CE. The pixel defining layer 70 has a second-1 blue opening 70-OP21 and a second-2 blue opening 70-OP22 provided in the pixel defining layer 70 to expose the second blue anode AE2. The second-1 blue light-emitting layer EL21 is disposed on the second blue anode AE2 exposed through the second-1 blue opening 70-OP21, and the second-2 blue light-emitting layer EL22 is disposed on the second blue anode AE2 exposed through the second-2 blue opening 70-OP22.

[0174] The cathode CE is disposed on the first blue light-emitting layer EL1, the second-first blue light-emitting layer EL21, and the second-second blue light-emitting layer EL22. The cathode CE is covered by the encapsulation layer TFE.

[0175] The base insulating layer 201, the intermediate insulating layer 203, and the cover insulating layer 205 can be sequentially stacked on the encapsulation layer TFE. The second conductive layer 204 can be disposed in the non-light-emitting region NPXA. The first conductive layer 202 (see...) Figure 5A and Figure 5B The light-emitting element (NPXA) can be further disposed within the non-emitting region. The optical path control layer (OSL_1) can be disposed on the covering insulating layer 205. The optical path control layer (OSL_1) may include multiple light absorption partition walls (LAWs) configured to correspond to the emitting region (PXA) of the narrow light-emitting element. Since the first blue light-emitting element (B_ED1) is a wide light-emitting element, no multiple light absorption partition walls (LAWs) are disposed above it. Since the second-first blue light-emitting element (B_ED21) and the second-second blue light-emitting element (B_ED22) are narrow light-emitting elements, multiple light absorption partition walls (LAWs) are disposed above them.

[0176] According to embodiments of this disclosure, each of the plurality of light-absorbing partition walls (LAWs) may include a plurality of black substrates. Although Figure 10A and Figure 10B The figure illustrates the structure of each of the plurality of light-absorbing partition walls LAWs comprising three black substrates (hereinafter referred to as "first black substrate BM1, second black substrate BM2, and third black substrate BM3"), but the structure of each of the plurality of light-absorbing partition wall LAWs is not limited thereto. For example, each of the plurality of light-absorbing partition wall LAWs may include one black substrate or at least two or four black substrates.

[0177] A first black substrate BM1 can be disposed on the covering insulating layer 205 and can be covered by a first transparent insulating layer 301. A second black substrate BM2 can be disposed on the first transparent insulating layer 301 and can be covered by a second transparent insulating layer 302. A third black substrate BM3 can be disposed on the second transparent insulating layer 302 and can be covered by a third transparent insulating layer 303. Each of the first black substrate BM1, the second black substrate BM2, and the third black substrate BM3 may include a light-absorbing material or a light-blocking material. Accordingly, light incident on the first black substrate BM1, the second black substrate BM2, and the third black substrate BM3 can be absorbed and not reflected. Each of the first transparent insulating layer 301, the second transparent insulating layer 302, and the third transparent insulating layer 303 may include a transparent organic material.

[0178] The range of light emitted from the 2-1 blue emitting element B_ED21 and the 2-2 blue emitting element B_ED22 can be controlled by multiple light-absorbing partition walls (LAW). In other words, the side light emitted from the 2-1 blue emitting element B_ED21 and the 2-2 blue emitting element B_ED22 is absorbed by the light-absorbing partition walls (LAW) and not emitted. The range of light emitted from the 2-1 blue emitting element B_ED21 and the 2-2 blue emitting element B_ED22 can be narrowed by the light-absorbing partition walls (LAW). Accordingly, in the second mode, in the display area DA (see...) Figure 2A The viewpoint of the image displayed in () can be narrowed.

[0179] For example, the range of light emitted by the second-first blue light-emitting element B_ED21 and the second-second blue light-emitting element B_ED22 can be limited by multiple light-absorbing partition walls (LAW). For instance, side-emitted light from these blue light-emitting elements can be absorbed by the light-absorbing partition walls (LAW), preventing outward emission of light. As a result, the emission range of the second-first blue light-emitting element B_ED21 and the second-second blue light-emitting element B_ED22 can be reduced, and in the second mode, in the display area DA (see...) Figure 2A The viewpoint of the image displayed in the image can be narrowed accordingly.

[0180] The optical path control layer OSL_1 may further include a peripheral partition wall P_LAW configured to correspond to the non-emitting region NPXA. The peripheral partition wall P_LAW may have a structure comprising multiple peripheral black matrices P_BM1, P_BM2, and P_BM3. In an embodiment, the peripheral partition wall P_LAW may be omitted from the optical path control layer OSL_1.

[0181] Figure 11A This is a block diagram of an electronic device according to an embodiment of the present disclosure. Figure 11B This is a block diagram of a residual image compensation circuit according to an embodiment of the present disclosure. Figure 12A and Figure 12B It is a view illustrating the status of indicator signals depending on the operating mode of the electronic device.

[0182] refer to Figure 11A and Figure 11B The drive controller T_CON receives the input image signal RGB and the control signal CTRL from the main processor MCU (e.g., a microcontroller or graphics controller). The drive controller T_CON converts the input image signal RGB to generate image data and generates drive control signals, such as the scan control signal SCS and the transmit control signal ECS, based on the control signal CTRL. The image data can be provided to multiple drive chips, and the drive control signals can be applied to drive circuits (i.e., multiple drive chips DIC1 to DIC3 (see...)). Figure 6 ); Scan drive circuit SDC (see Figure 6 ); and the light-emitting drive circuit EDC (see Figure 6 The drive control signal is applied to the display panel DP by driving multiple driver chips DIC1 to DIC3, scanning driver circuit SDC, and light-emitting driver circuit EDC.

[0183] The drive controller T_CON may include a ghost image compensation circuit 100. The ghost image compensation circuit 100 receives the input image signal RGB and compensates for the input image signal RGB based on degradation information to generate a compensated image signal RGB'. The input image signal RGB may include data for the first display area DA1 (see...). Figure 2A The first input image signal RGB1 and the second display area DA2 (see...) Figure 2A The second input image signal RGB2 is the first input image signal RGB1. The afterimage compensation circuit 100 can compensate the first input image signal RGB1 and the second input image signal RGB2 to generate the first compensated image signal RGB1' and the second compensated image signal RGB2', respectively.

[0184] In embodiments of this disclosure, the degradation information used by the afterimage compensation circuit 100 may differ between the first display area DA1 and the second display area DA2, depending on their respective operating modes and the characteristics of the light-emitting elements used in each zone. For example, if the second display area DA2 operates in the second mode (narrow viewing angle) using a different set of light-emitting elements or driving conditions, its degradation distribution may differ significantly from that of the first display area DA1 operating only in the first mode. To address this issue, the afterimage compensation circuit 100 can apply different compensation parameters to the first input image signal RGB1 and the second input image signal RGB2, which enables precise brightness correction and a reduction in image persistence artifacts specific to each zone. This independent compensation strategy can provide improved long-term image quality.

[0185] although Figure 11A The figure illustrates the structure in which the afterimage compensation circuit 100 is included in the drive controller T_CON, but this disclosure is not limited thereto. For example, according to an embodiment, the afterimage compensation circuit 100 may be provided as a component independent of the drive controller T_CON, rather than being included in the drive controller T_CON.

[0186] refer to Figure 11B , Figure 12A and Figure 12BThe afterimage compensation circuit 100 includes a compensation unit 110 (also referred to as a compensation circuit), an accumulation memory 120, a sampling unit 130 (also referred to as a sampling circuit), a data processing unit 140 (also referred to as a data processing circuit), and a volatile memory 150.

[0187] The compensation unit 110 receives the first input image signal RGB1 and the second input image signal RGB2, and compensates the first input image signal RGB1 and the second input image signal RGB2 based on the first accumulated data ADD1 and the second accumulated data ADD21 / ADD22 stored in the accumulated memory 120, and generates the first compensated image signal RGB1' and the second compensated image signal RGB2'.

[0188] The accumulation memory 120 includes a first storage area 121 and a second storage area 122. First degraded data IDD1 of the first display area DA1 is accumulated in the first storage area 121, and second degraded data IDD21 / IDD22 of the second display area DA2 are accumulated in the second storage area 122. According to an embodiment of this disclosure, the accumulation memory 120 can receive a flag signal FMP_FLAG. The flag signal FMP_FLAG can be a signal that is deactivated when the second display area DA2 operates in a first mode and activated when the second display area DA2 operates in a second mode.

[0189] According to embodiments of this disclosure, the compensation unit 110 dynamically adjusts its compensation strategy based on the operating mode of the second display area DA2, as indicated by the flag signal FMP_FLAG. For example, when the flag signal FMP_FLAG is activated, indicating that the second display area DA2 is operating in a second mode (e.g., a private mode with a limited viewing angle), the compensation unit 110 accesses the second accumulated data ADD21 / ADD22 stored in the second storage area 122 and applies degradation compensation specifically tailored for the narrow viewing angle configuration. Conversely, when the flag signal FMP_FLAG is deactivated, the compensation is based on the first accumulated data ADD1 stored in the first storage area 121, which corresponds to the common mode operation of the second display area DA2. Even with differentiated stress and aging distributions associated with different light-emitting elements or usage modes, this selective compensation method enables the embodiments to maintain consistent brightness performance across different modes and viewing conditions. By maintaining separate storage areas within the accumulation memory 120 (e.g., a first storage area 121 for the first display area DA1 and a second storage area 122 for the second display area DA2), the embodiments allow degraded data to be retained in a pattern-specific manner, which allows for more accurate and localized afterimage prevention and image fidelity correction.

[0190] According to embodiments of this disclosure, the second storage area 122 may include a first mode storage area MSA1 and a second mode storage area MSA2. Accordingly, the accumulation memory 120 accumulates second degraded data in the first mode storage area MSA1 in response to a deactivated flag signal FMP_FLAG (e.g., a logic "0" state), and accumulates second degraded data in the second mode storage area MSA2 in response to an activated flag signal FMP_FLAG (e.g., a logic "1" state). The second degraded data accumulated in the first mode storage area MSA1 is referred to as second-1st degraded data IDD21, and the second degraded data accumulated in the second mode storage area MSA2 is referred to as second-2nd degraded data IDD22.

[0191] The accumulation memory 120 stores first accumulated data ADD1 obtained by accumulating first degraded data IDD1 to first previously accumulated data stored in the first storage area 121. The first accumulated data ADD1 stored in the first storage area 121 can be provided to the compensation unit 110, and the compensation unit 110 can compensate the first input image signal RGB1 based on the first accumulated data ADD1 to generate a first compensated image signal RGB1'.

[0192] Accumulation memory 120 stores second accumulated data ADD21 and ADD22 obtained by accumulating second degraded data IDD21 and IDD22 to second previously accumulated data stored in second storage area 122. For example, accumulation memory 120 stores second-first accumulated data ADD21 obtained by accumulating second-first degraded data IDD21 to second-first previously accumulated data previously stored in first mode storage area MSA1 of second storage area 122. Furthermore, accumulation memory 120 stores second-second accumulated data ADD22 obtained by accumulating second-second degraded data IDD22 to second-second previously accumulated data previously stored in second mode storage area MSA2 of second storage area 122.

[0193] The second accumulated data ADD21 and ADD22 stored in the second storage area 122 are provided to the compensation unit 110, and the compensation unit 110 compensates the second input image signal RGB2 based on the second accumulated data ADD21 and ADD22 to generate the second compensated image signal RGB2'.

[0194] In embodiments of this disclosure, the accumulation memory 120 can achieve mode-aware compensation by dividing the second storage area 122 into separate sub-areas for each operating mode of the second display area DA2. For example, the first mode storage area MSA1 can accumulate second-1st degradation data IDD21 corresponding to operation in the first mode, while the second mode storage area MSA2 can accumulate second-2nd degradation data IDD22 corresponding to operation in the second mode. These degradation values ​​can be continuously updated as accumulated data ADD21 and ADD22, respectively, and provided to the compensation unit 110. This configuration allows the compensation unit 110 to generate a precisely compensated image signal RGB2' for the second display area DA2 based on the specific mode in use rather than applying a general correction. As a result, even under asymmetrical usage conditions (e.g., frequent switching between public and private display modes), image fidelity can be maintained over time.

[0195] According to embodiments of this disclosure, compensation unit 110 may receive a flag signal FMP_FLAG. In response to the deactivated (e.g., logic "0") flag signal FMP_FLAG, compensation unit 110 reads second-first accumulated data ADD21 from accumulated memory 120 and compensates the second input image signal RGB2 based on the second-first accumulated data ADD21 to generate a second compensated image signal RGB2'. Simultaneously, in response to the activated (e.g., logic "1") flag signal FMP_FLAG, compensation unit 110 reads second-second accumulated data ADD22 from accumulated memory 120 and compensates the second input image signal RGB2 based on the second-second accumulated data ADD22 to generate a second compensated image signal RGB2'.

[0196] For example, in embodiments of this disclosure, compensation unit 110 may selectively access mode-specific accumulated data from accumulated memory 120 based on the logic state of flag signal FMP_FLAG. When the second display area DA2 operates in a first mode (e.g., public mode), compensation unit 110 may use second-first accumulated data ADD21 to correct the second input image signal RGB2. Conversely, when operating in a second mode (e.g., private mode), compensation unit 110 may switch to second-second accumulated data ADD22 to perform compensation. This selective readout mechanism allows the image compensation process to reflect the different degradation behaviors associated with each mode, thereby maintaining accurate brightness correction even when the display switches between different usage scenarios.

[0197] The sampling unit 130 can receive a first compensated image signal RGB1' and a second compensated image signal RGB2' from the compensation unit 110, and perform sampling operations on some of the image signals in the first compensated image signal RGB1' and the second compensated image signal RGB2'. According to embodiments of this disclosure, the sampling unit 130 can perform sampling operations on a frame-by-frame basis. The signal obtained by performing a sampling operation on the first compensated image signal RGB1' is called the first sampled signal. The signal obtained by performing a sampling operation on the second compensated image signal RGB2' is called the second sampled signal. The first sampled signal and the second sampled signal are provided to the data processing unit 140. (Refer to...) Figure 13A and Figure 13B The sampling operation process of sampling unit 130 will be described in further detail.

[0198] For example, in embodiments of this disclosure, sampling unit 130 can support effective degradation tracking by selectively sampling portions of the first compensated image signal RGB1' and portions of the second compensated image signal RGB2', respectively. This sampling can be performed on a per-frame basis, enabling embodiments to monitor representative brightness behavior over time without continuously processing the entire frame of data. The resulting first and second sampled signals provide a bandwidth-reduced version of the compensated image data that still provides useful information; these sampled signals are transmitted to data processing unit 140 for use in updating or verifying degradation information. This sampling-based strategy balances compensation accuracy with processing efficiency.

[0199] The data processing unit 140 can generate first degraded data IDD1 for the first display area DA1 based on the first sampling signal, and can generate second degraded data IDD21 and IDD22 for the second display area DA2 based on the second sampling signal. The data processing unit 140 can accumulate the first degraded data IDD1 and the second degraded data IDD21 and IDD22 in the accumulation memory 120.

[0200] For example, according to an embodiment, the data processing unit 140 can analyze the first and second sampled signals received from the sampling unit 130 to calculate updated degradation data for each display area. For instance, the data processing unit 140 can generate first degradation data IDD1 for the first display area DA1, and separately generate second degradation data IDD21 and IDD22 for the second display area DA2 corresponding to its operation in the first and second modes, respectively. These values ​​can reflect the cumulative aging or stress experienced by the light-emitting element over time. Once the calculation is complete, the degradation data can be accumulated in an appropriate sub-region of the accumulation memory 120, thereby providing a basis for future compensation operations of the compensation unit 110. This feedback-driven architecture allows the embodiments to dynamically adapt to real-world usage patterns and maintain image quality under various viewing conditions.

[0201] The volatile memory 150 can store first accumulated data ADD1 and second accumulated data ADD21 and ADD22. The volatile memory 150 can further store frame numbers associated with the current sampling operation.

[0202] Figure 13A The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure. Figure 13B The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0203] refer to Figure 13A Multiple first blocks SB1 are defined within a first display area DA1, and multiple second blocks SB2 are defined within a second display area DA2 and have dimensions different from those of the first blocks SB1. Each of the first blocks SB1 may have a size of p × q, and each of the second blocks SB2 may have a size of p × 2q. In this case, each of "p" and "q" can be an integer greater than or equal to "1".

[0204] According to embodiments of this disclosure, although Figure 13A The diagram shows "p" as "4" and "q" as "4", but this disclosure is not limited thereto. In other words, each of the first SB1 can have a size of 4×4, and each of the second SB2 can have a size of 4×8. In other words, each of the first SB1 has 16 sampled pixels, and each of the second SB2 has 32 sampled pixels.

[0205] Sampling unit 130 (see Figure 11BThe sampling unit 130 can perform sampling operations within each preset sampling period. For example, during a first sampling period, the sampling unit 130 can output a signal corresponding to the first sampled pixel located in the first row of the first block SB1 from the first compensated image signal RGB1' as a sampling signal. For example, during a fourth sampling period, the sampling unit 130 can output a signal corresponding to the first sampled pixel located in the fourth row of the first block SB1 from the first compensated image signal RGB1' as a sampling signal. For example, during a fifth sampling period, the sampling unit 130 can output a signal corresponding to the second sampled pixel located in the first row of the first block SB1 from the first compensated image signal RGB1' as a sampling signal. This process is repeated to extract the sampling signals of all sampled pixels provided in the first block SB1.

[0206] The sampled signal extracted from the first block SB1 can be processed into the first degraded data IDD1 (see...). Figure 11B The data is then accumulated in the first storage area 121. According to embodiments of this disclosure, the first storage area 121 may include multiple unit storage areas. In each unit storage area of ​​the first storage area 121, the first degraded data IDD1 associated with the first block SB1 may be accumulated.

[0207] For example, sampling unit 130 may output a signal corresponding to the first sampled pixel located in the first row of the second block SB2 from the second compensated image signal RGB2' as a sampling signal during a first sampling period. For example, sampling unit 130 may output a signal corresponding to the first sampled pixel located in the fourth row of the second block SB2 from the second compensated image signal RGB2' as a sampling signal during a fourth sampling period. For example, sampling unit 130 may output a signal corresponding to the second sampled pixel located in the first row of the second block SB2 from the second compensated image signal RGB2' as a sampling signal during a fifth sampling period. This process is repeated to extract sampling signals from all sampled pixels provided in the second block SB2.

[0208] When the second display area DA2 operates in the first mode, the sampled signal extracted from the second block SB2 can be processed into the 2-1 degraded data IDD21 (see...). Figure 11B The sampled signal extracted from the second block SB2 can be processed into the first mode storage area MSA1 of the second storage area 122, and then accumulated in the first mode storage area MSA1 of the second storage area 122. When the second display area DA2 operates in the second mode, the sampled signal can be processed into the second-second degraded data IDD22 (see [reference]). Figure 11B ), and then accumulated in the second mode storage area MSA2 of the second storage area 122.

[0209] For example, refer to Figure 13AAccording to embodiments of this disclosure, sampling unit 130 can extract sampling signals from defined pixel blocks within sequential sampling periods to generate degradation data specific to each operating mode and each display area. A first block SB1 (e.g., a 4×4 pixel area) corresponds to a first display area DA1 and is periodically sampled line by line, wherein accumulated data is stored in individual unit areas of a first storage area 121. A second block SB2 (e.g., a 4×8 pixel area) corresponds to a second display area DA2, and the extracted sampling signals are conditionally processed based on whether the second display area DA2 operates in a first mode or a second mode. This block-based mode-aware sampling framework can achieve localized degradation tracking while maintaining temporal resolution, thereby allowing embodiments to perform precise afterimage compensation tailored to both the display area and the viewing mode.

[0210] According to embodiments of this disclosure, the second storage area 122 may include multiple unit storage areas. In this case, the first mode storage area MSA1 may include unit storage areas SA1c and SA3c located in odd-numbered columns, and the second mode storage area MSA2 may include unit storage areas SA2c and SA4c located in even-numbered columns. Degraded data IDD21 (2-1) may be accumulated in unit storage areas SA1c and SA3c located in odd-numbered columns, and degraded data IDD22 (2-2) may be accumulated in unit storage areas SA2c and SA4c located in even-numbered columns.

[0211] The size of the second block SB2 defined in the second display area DA2 operating in the first mode or the second mode is set to be different from the size of the first block SB1 defined in the first display area DA1 operating in the first mode, thereby preventing the accumulation memory 120 from being increased. In addition, degraded data for each mode of the second display area DA2 can be accumulated precisely without increasing the size of the accumulation memory 120, thereby preventing the afterimage compensation performance from being degraded.

[0212] Because the size of each of the first SB1 and the second SB2 is reduced, the afterimage compensation is performed more accurately, thereby improving the afterimage compensation performance.

[0213] For example, according to embodiments of this disclosure, in order to achieve mode-specific accumulation of degraded data while maintaining a compact memory footprint, the second storage area 122 can be subdivided into unit storage areas arranged in columns. For example, the first mode storage area MSA1 can use unit storage areas located in odd-numbered columns (e.g., SA1c and SA3c), while the second mode storage area MSA2 can use unit storage areas located in even-numbered columns (e.g., SA2c and SA4c). This interleaved storage strategy allows degraded data of the second display area DA2 in both the first and second modes to be stored in different ways without using separate memory modules. Furthermore, by adjusting the block size of the second block SB2 to be different from that of the first block SB1, embodiments can reduce memory overhead while maintaining accurate tracking. Due to the use of a smaller block size, the granularity of degradation compensation is increased, which improves the accuracy and effectiveness of afterimage correction.

[0214] although Figure 13B The diagram shows "p" as "2" and "q" as "4", but this disclosure is not limited thereto. In other words, each of the first SB1a can have a size of 2×4, and each of the second SB2a can have a size of 2×8. In other words, each of the first SB1a provides 8 sampled pixels, and each of the second SB2a provides 16 sampled pixels.

[0215] According to embodiments of this disclosure, the first storage area 121 may include a plurality of unit storage areas SAa. In each unit storage area SAa of the first storage area 121, first degraded data IDD1 related to the first block SB1a can be accumulated. In this case, each of the unit storage areas SAa may have a higher density than... Figure 13A The size of each unit storage area SA shown in the figure is smaller (e.g., about half the size).

[0216] When the second display area DA2 operates in the first mode, the sampled signal extracted from the second block SB2a can be processed into degraded data IDD21 (2-1st), and subsequently accumulated in the first mode storage area MSA1 of the second storage area 122. When the second display area DA2 operates in the second mode, the sampled signal extracted from the second block SB2a can be processed into degraded data IDD22 (2-2nd), and subsequently accumulated in the second mode storage area MSA2 of the second storage area 122.

[0217] For example, according to an embodiment, the first storage area 121 can be organized into multiple unit storage areas SAa, each unit storage area SAa being dedicated to storing the first degraded data IDD1 of the corresponding first block SB1a. These unit storage areas SAa can be configured in a reduced size (e.g., for Figure 13A (Approximately half the size of the unit storage area SA shown), thus enabling finer granularity in tracking degradation characteristics without increasing memory usage. Similarly, degradation data for the second display area DA2 can be divided by operating mode and accumulated in different sub-areas of the second storage area 122: a first mode storage area MSA1 for degradation data IDD21 (2-1) and a second mode storage area MSA2 for degradation data IDD22 (2-2). This selective data routing enables precise degradation characteristic analysis tailored to operating modes, thereby improving the accuracy of image compensation in both public and private viewing scenarios.

[0218] According to embodiments of this disclosure, the second storage area 122 may include multiple unit storage areas. In this case, the first mode storage area MSA1 may include unit storage areas SA1ca and SA3ca located in odd-numbered columns, and the second mode storage area MSA2 may include unit storage areas SA2ca and SA4ca located in even-numbered columns. Degraded data IDD21 (2-1) may be accumulated in unit storage areas SA1ca and SA3ca located in odd-numbered columns, and degraded data IDD22 (2-2) may be accumulated in unit storage areas SA2ca and SA4ca located in even-numbered columns.

[0219] In this case, each of the unit storage areas SA1ca and SA3ca located in the odd-numbered columns can have a higher density than... Figure 13A The unit storage areas SA1c and SA3c in the odd-numbered columns shown in the diagram are each smaller than (e.g., about half) in size. In this case, each of the unit storage areas SA2ca and SA4ca in the even-numbered columns can have a size smaller than... Figure 13A The size of each of the unit storage areas SA2c and SA4c located in the even-numbered columns shown in the figure is smaller (e.g., about half the size).

[0220] For example, according to an embodiment, the second storage area 122 can be subdivided into finer-sized unit storage areas, which can improve the accuracy of degraded data management. For example, the first mode storage area MSA1 may include smaller unit storage areas SA1ca and SA3ca located in odd-numbered columns, while the second mode storage area MSA2 may include similarly reduced-size unit storage areas SA2ca and SA4ca located in even-numbered columns. Each of these finer-sized storage areas SA1ca to SA4ca can be Figure 13AThe corresponding regions shown are approximately half the size. This reduction in region size enables the localized accumulation of pattern-specific degraded data (IDD21 and IDD22), which can improve the granularity of compensation without increasing the overall memory size or compromising processing efficiency.

[0221] Figure 14A The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure. Figure 14B The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0222] refer to Figure 14A Multiple first blocks SB1 are defined within a first display area DA1, and multiple second blocks SB2b are defined within a second display area DA2 and have dimensions different from those of the first blocks SB1. Each of the first blocks SB1 may have a size of p × q, and each of the second blocks SB2b may have a size of 2p × q. In this case, each of "p" and "q" can be an integer greater than or equal to "1".

[0223] According to embodiments of this disclosure, although Figure 14A The diagram shows "p" as "4" and "q" as "4", but this disclosure is not limited thereto. In other words, each of the first SB1 can have a size of 4×4, and each of the second SB2b can have a size of 8×4. In other words, each of the first SB1 is provided with 16 sampled pixels, and each of the second SB2b is provided with 32 sampled pixels.

[0224] When the second display area DA2 operates in the first mode, the sampled signal extracted from the second block SB2b can be processed into degraded data IDD21 (2-1st), and subsequently accumulated in the first mode storage area MSA1 of the second storage area 122. When the second display area DA2 operates in the second mode, the sampled signal extracted from the second block SB2b can be processed into degraded data IDD22 (2-2nd), and subsequently accumulated in the second mode storage area MSA2 of the second storage area 122.

[0225] According to embodiments of this disclosure, the second storage area 122 may include multiple unit storage areas. In this case, the first mode storage area MSA1 may include unit storage areas SA1r1 and SA1r2 located in odd-numbered rows, and the second mode storage area MSA2 may include unit storage areas SA2r1 and SA2r2 located in even-numbered rows. Degraded data IDD21 (2-1) may be accumulated in unit storage areas SA1r1 and SA1r2 located in odd-numbered rows, and degraded data IDD22 (2-2) may be accumulated in unit storage areas SA2r1 and SA2r2 located in even-numbered rows.

[0226] although Figure 14B The diagram shows "p" as "4" and "q" as "2", but this disclosure is not limited thereto. In other words, each of the first SB1c can have a size of 4×2, and each of the second SB2c can have a size of 8×2. In other words, each of the first SB1c provides 8 sampled pixels, and each of the second SB2c provides 16 sampled pixels.

[0227] According to embodiments of this disclosure, the first storage area 121 may include a plurality of unit storage areas SAb. In each unit storage area SAb of the first storage area 121, first degraded data IDD1 related to the first block SB1c can be accumulated. In this case, each of the unit storage areas SAb may have a higher density than... Figure 14A The size of each unit storage area SA shown in the figure is smaller (e.g., about half the size).

[0228] According to embodiments of this disclosure, the second storage area 122 may include multiple unit storage areas. In this case, the first mode storage area MSA1 may include unit storage areas SA1ra and SA1rb located in odd-numbered rows, and the second mode storage area MSA2 may include unit storage areas SA2ra and SA2rb located in even-numbered rows. Degraded data IDD21 (2-1) may be accumulated in unit storage areas SA1ra and SA1rb located in odd-numbered rows, and degraded data IDD22 (2-2) may be accumulated in unit storage areas SA2ra and SA2rb located in even-numbered rows.

[0229] In this case, each of the unit storage areas SA1ra and SA1rb located in odd-numbered rows can have a higher density than... Figure 14A The unit storage areas SA1r1 and SA1r2, located in the odd-numbered rows, are each smaller than (e.g., about half) in size. In this case, each of the unit storage areas SA2ra and SA2rb, located in the even-numbered rows, can have a size smaller than... Figure 14AThe size of each of the unit storage areas SA2r1 and SA2r2 located in the even-numbered rows shown in the figure is smaller (e.g., about half the size).

[0230] Figure 15A and Figure 15B It is a view illustrating the state of the first and second flag signals depending on the operating mode of the electronic device. Figure 16 The figure illustrates a pattern-dependent sampling operation for a first display area and a second display area according to an embodiment of the present disclosure.

[0231] refer to Figure 15A and Figure 15B The second display area DA2 can operate in either the first or second mode, and the first display area DA1 can operate in either the first or second mode. In this case, the afterimage compensation circuit 100 (see...) Figure 11B It can receive two flag signals (i.e., the first flag signal FMP_FLAG1 and the second flag signal FMP_FLAG2).

[0232] The first flag signal FMP_FLAG1 can be a signal that is deactivated when the first display area DA1 operates in the first mode and activated when the first display area DA1 operates in the second mode. The second flag signal FMP_FLAG2 can be a signal that is deactivated when the second display area DA2 operates in the first mode and activated when the second display area DA2 operates in the second mode.

[0233] refer to Figure 16 Multiple first SBa blocks are defined in a first display area DA1, and multiple second SB2 blocks are defined in a second display area DA2 and have the same dimensions as the first SBa blocks. First storage area 121 includes a third mode storage area MSA3 and a fourth mode storage area MSA4, and second storage area 122 includes a first mode storage area MSA1 and a second mode storage area MSA2. First mode storage area MSA1 may include unit storage areas SA1c and SA3c located in odd-numbered columns, and second mode storage area MSA2 may include unit storage areas SA2c and SA4c located in even-numbered columns. Third mode storage area MSA3 may include unit storage areas SAaa and SAcc located in odd-numbered columns, and fourth mode storage area MSA4 may include unit storage areas SAbb and SAdd located in even-numbered columns.

[0234] The afterimage compensation circuit 100 accumulates first degraded data in the third mode memory area MSA3 in response to the first flag signal FMP_FLAG1 being deactivated (e.g., a logic "0" state), and accumulates the first degraded data in the fourth mode memory area MSA4 in response to the first flag signal FMP_FLAG1 being activated (e.g., a logic "1" state). The first degraded data accumulated in the third mode memory area MSA3 is referred to as the first-1 degraded data, and the first degraded data accumulated in the fourth mode memory area MSA4 is referred to as the first-2 degraded data.

[0235] The afterimage compensation circuit 100 stores first-1 accumulated data obtained by accumulating first-1 degraded data into first-1 previously accumulated data previously stored in the third mode storage area MSA3 of the first storage area 121. Furthermore, the afterimage compensation circuit 100 stores first-2 accumulated data obtained by accumulating first-2 degraded data into first-2 previously accumulated data previously stored in the fourth mode storage area MSA4 of the first storage area 121.

[0236] Already referenced Figure 13A The second storage area 122 of the afterimage compensation circuit 100 is described, and its details will be omitted below to avoid redundancy.

[0237] Figure 17 This is a flowchart illustrating the operation process of an electronic device according to an embodiment of the present disclosure. Figure 18A It is shown in the diagram Figure 17 The flowchart shown in Figure S120 illustrates the method for operating the compensation signal. Figure 18B It is shown in the diagram Figure 17 The flowchart shown in Figure S140 illustrates the method for accumulating degraded data.

[0238] refer to Figure 11B and Figure 17 When the electronic device DD starts operating, the afterimage compensation circuit 100 receives data for the first display area DA1 (see...). Figure 12A The first input image signal RGB1 and the second display area DA2 (see...) Figure 12A The second input image signal RGB2 (operation S110).

[0239] The afterimage compensation circuit 100 can compensate the first input image signal RGB1 and the second input image signal RGB2 based on degradation information to generate the first compensated image signal RGB1' and the second compensated image signal RGB2' (operation S120). The degradation information can be generated based on the first accumulated data ADD1 and the second accumulated data ADD21 and ADD22 read from the accumulated memory 120.

[0240] The electronic device DD can display images in the first display area DA1 and the second display area DA2 based on the first compensated image signal RGB1' and the second compensated image signal RGB2' respectively (operation S130).

[0241] The afterimage compensation circuit 100 accumulates the first degraded data IDD1 generated based on the first compensated image signal RGB1' in the first storage area 121 of the accumulation memory 120, and accumulates the second degraded data IDD21 and IDD22 generated based on the second compensated image signal RGB2' in the second storage area 122 of the accumulation memory 120 (operation S140).

[0242] refer to Figure 18A When the operation of compensating the first input image signal RGB1 and the second input image signal RGB2 (operation S120) begins, the afterimage compensation circuit 100 determines whether the first input image signal RGB1 and the second input image signal RGB2 are for the first display area DA1 or for the second display area DA2 (operation S121). In other words, when it is determined that the first input image signal RGB1 is for the first display area DA1, operation S123 is executed. When it is determined that the second input image signal RGB2 is for the second display area DA2, operation S122 is executed.

[0243] In operation S122, the afterimage compensation circuit 100 can determine the state of the flag signal FMP_FLAG. When the flag signal FMP_FLAG is deactivated (logic "0"), operation S125 is executed. When the flag signal FMP_FLAG is activated (logic "1"), operation S127 is executed.

[0244] In operation S123, the afterimage compensation circuit 100 reads the first accumulated data ADD1 from the first storage area 121. Thereafter, the afterimage compensation circuit 100 compensates the first input image signal RGB1 based on the first accumulated data ADD1 to generate the first compensated image signal RGB1' (operation S124).

[0245] In operation S125, the afterimage compensation circuit 100 reads the second-to-first accumulated data ADD21 from the first mode storage area MSA1 of the second storage area 122. Thereafter, the afterimage compensation circuit 100 compensates the second input image signal RGB2 based on the second-to-first accumulated data ADD21 to generate the second compensated image signal RGB2' (operation S126).

[0246] In operation S127, the afterimage compensation circuit 100 reads the second-second accumulated data ADD22 from the second mode storage area MSA2 of the second storage area 122. Thereafter, the afterimage compensation circuit 100 compensates the second input image signal RGB2 based on the second-second accumulated data ADD22 to generate the second compensated image signal RGB2' (operation S128).

[0247] refer to Figure 18B When operation S140, used to accumulate the first and second degraded data, begins, the afterimage compensation circuit 100 determines whether the sampling signal is for the first display area DA1 or the second display area DA2 (operation S141). When the sampling signal is not for the second display area DA2, operation S143 is executed. When the sampling signal is for the second display area DA2, operation S142 is executed.

[0248] In operation S142, the afterimage compensation circuit 100 can determine the state of the flag signal FMP_FLAG. When the flag signal FMP_FLAG is deactivated (logic "0"), operation S145 is executed. When the flag signal FMP_FLAG is activated (logic "1"), operation S147 is executed.

[0249] In operation S143, the afterimage compensation circuit 100 generates first degraded data IDD1 of the first block SB1 of the first display area DA1 based on the sampled signal, and accumulates the first degraded data IDD1 in the first storage area 121 of the accumulation memory 120 (operation S144).

[0250] In operation S145, the afterimage compensation circuit 100 generates the second-1st degraded data IDD21 of the second block SB2 of the second display area DA2 operating in the first mode based on the sampled signal. Thereafter, the afterimage compensation circuit 100 accumulates the second-1st degraded data IDD21 in the first mode storage area MSA1 of the second storage area 122 (operation S146).

[0251] In operation S147, the afterimage compensation circuit 100 generates the second-second degraded data IDD22 of the second block SB2 of the second display area DA2 operating in the second mode based on the sampled signal. Thereafter, the afterimage compensation circuit 100 accumulates the second-second degraded data IDD22 in the second mode storage area MSA2 of the second storage area 122 (operation S148).

[0252] Figure 19 This is a diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0253] refer to Figure 19According to embodiments of the present disclosure, the electronic device 1000 can output various information (e.g., images, text, music, etc.) through the display module 1140. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide the application information to the user through the display panel 1141.

[0254] In some embodiments, electronic device 1000 may be configured as a smartphone, camera, smart TV, monitor, smartwatch, tablet computer, automotive display, or AR / VR headset. For example, electronic device 1000 may be a smartphone including a touch-sensitive display area for interaction and a non-display area containing sensors and circuitry for enhanced functionality. For example, electronic device 1000 may be a TV or monitor including a large display area for high-resolution video playback and a non-display area containing driving circuitry or a connection module for external input. For example, electronic device 1000 may be a smartwatch including a display area optimized for compact and high-definition visual effects and a non-display area integrating biometric sensors for health monitoring. In some cases, electronic device 1000 may be an AR / VR headset.

[0255] In some embodiments, memory 1120 may store information such as software code for operating application 1123. Application 1123 may include software designed to perform specific tasks or provide functionality to a user. Application 1123 may operate under the control of processor 1110 and utilize the data stored in memory 1120 to provide a wide variety of functionalities, such as productivity tools, multimedia streaming and playback, file or email delivery, or communication services. Application 1123 interacts seamlessly with user interface 1161 or touchscreen 1142, allowing the user to launch, navigate, and use the program via user input, such as touch, tap, gesture, or voice interaction.

[0256] After a user selects an application via touchscreen 1142 or user interface 1161, processor 1110 can execute application program 1123 corresponding to the selected application retrieved from memory 1120 to perform the application's functions. For example, when a user selects a camera application by tapping an icon (or camera application icon) displayed on display panel 1141, processor 1110 activates the camera module. Processor 1110 can then transfer image data corresponding to a captured image obtained by the camera module to display module 1140. Display module 1140 can then display the image corresponding to the captured image via display panel 1141.

[0257] As another example, when a user wishes to make a phone call, they tap a phone icon displayed on display module 1140, and processor 1110 can execute a phone application stored in memory 1120. A phone keypad can be displayed on display panel 1141 for the user to type in the phone number to dial.

[0258] As another example, the display module 1140 can be integrated into an electronic device 1000 such as a laptop computer, smart TV, or tablet computer. Users wishing to access multimedia streaming applications (e.g., watching music videos or movies) can do so by tapping the corresponding icon. This action activates the application, allowing the user to watch the streamed content.

[0259] Processor 1110 may include a main processor 1111 and an auxiliary or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU). The main processor 1111 may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0260] The coprocessor 1112 may include a controller 1112-1. The controller 1112-1 may include interface conversion circuitry and timing control circuitry. The controller 1112-1 can receive image signals from the main processor 1111, convert the data format of the image signals to match the interface specifications of the display module 1140, and output the image data. The controller 1112-1 can output various control signals to drive the display module 1140. For example, the controller 1112-1 can drive the display module 1140 to display icons suitable for user selection on the screen, thereby causing the execution of the application program 1123.

[0261] Memory 1120 may store various data used by one or more applications 1123 and at least one component of electronic device 1000 (e.g., processor 1110 or user interface 1161), as well as input or output data for commands associated therewith. For example, camera applications, GPS applications, augmented reality and virtual reality applications, and other applications may be executed by processor 1110 after the user selects a corresponding icon presented on the display screen (or display panel 1141) via touchscreen 1142 or user interface 1161. Furthermore, various setting data corresponding to user settings may be stored in memory 1120. Memory 1120 may include volatile memory 1121 and non-volatile memory 1122.

[0262] Display module 1140 can output visual information (images) to the user. Display module 1140 may include display panel 1141, gate driver, source driver, voltage generation circuit, and touch screen 1142. Display module 1140 may further include a window, chassis, and bracket to protect display panel 1141.

[0263] User interface 1161 serves as an interaction medium between the user and electronic device 1000. User interface 1161 can detect input made by a part of the user's body (e.g., a finger) or by a pen or mouse, and generate an electrical signal or data value corresponding to the input. User interface 1161 includes a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0264] The fingerprint sensor 1162 can sense fingerprints for biometric identification of a user and can also measure one or more biometric signals (such as blood pressure, water content, or weight).

[0265] Input sensor 1163 can sense user interactions including touch, taps, gestures, motion, voice commands, and eye movements. Input sensor 1163 includes optical sensors for image capture, eye tracking, or motion and gesture detection. The optical sensors can be infrared or semiconductor photodetectors. Input sensor 1163 includes audio and acoustic sensors, which can be MEMS microphones for voice recognition or voice-based interaction. The audio and acoustic sensors can be mounted as part of user interface 1161 or embedded in display panel 1141.

[0266] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of input made by a pen or mouse to control the movement of the screen cursor. The digitizer 1164 can generate the electromagnetic change caused by the input as this data value. The digitizer 1164 can detect input made by a passive pen, or transmit and receive data using an active pen or remote control.

[0267] At least one of the fingerprint sensor 1162, the input sensor 1163, and the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 by a process that is continuous with the process of forming the various elements (e.g., light-emitting elements and transistors) included in the display panel 1141.

[0268] Furthermore, the user interface 1161 may further include, for example, a gesture sensor, a gyroscope sensor for sensing rotational motion, an accelerometer sensor for tracking translational motion, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyroscope sensor, accelerometer sensor, and infrared emitter and camera sensor may be particularly suitable for AR / VR headset functionality.

[0269] Touchscreen 1142 includes a touch sensor embedded in a semiconductor layer of display panel 1141 to sense pressure applied to the top layer (screen) of display panel 1141. The touch sensor can be capacitive or resistive. Touchscreen 1142 can be used as a main interface for users to select and navigate applications, control electronic device 1000, and interact with electronic device 1000.

[0270] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and there are no particular limitations on the type of display panel 1141. The display panel 1141 may be of a rigid type or a flexible type that can be rolled or folded. The display module 1140 may further include supports, brackets, and heat dissipation components for supporting the display panel 1141.

[0271] Power module 1150 can supply power to various components of electronic device 1000. Power module 1150 may include a battery that is charged by a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the components described above, including display module 1140.

[0272] As is customary in the art of this disclosure, embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where these blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0273] As described above, regardless of whether operating in the first mode or the second mode, the size of the second block used for sampling operations in the second display area can be set differently from the size of the first block used for sampling operations in the first display area operating in the first mode. This configuration helps prevent an increase in the size of the accumulation memory provided in the afterimage compensation circuit, while still allowing accurate accumulation of degraded data for each mode of the second display area.

[0274] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the claims.

Claims

1. An electronic device comprising: The display panel includes a first display area that operates in a first mode and a second display area that operates in either the first mode or the second mode. as well as The image compensation circuit is configured to receive a first input image signal for the first display area and a second input image signal for the second display area, and to generate a first compensated image signal and a second compensated image signal by compensating the first input image signal and the second input image signal based on degradation information of the first display area and the second display area, respectively. The first display area defines a plurality of first blocks, and the second display area defines a plurality of second blocks, each of the plurality of second blocks having a different size than each of the plurality of first blocks. The residual image compensation circuit includes an accumulation memory, which comprises: a first storage area configured to accumulate first deterioration data for each of the plurality of first blocks; and a second storage area configured to accumulate second deterioration data for each of the plurality of second blocks. The second storage area includes: A first-mode storage area is configured to accumulate the second degraded data in the first mode for each of the plurality of second blocks; and The second mode storage area is configured to accumulate the second degraded data in the second mode for each of the plurality of second blocks.

2. The electronic device according to claim 1, wherein, Each of the plurality of first blocks has a size of p×q. Each of the plurality of second blocks has a size of p×2q, and In this context, each of p and q is an integer greater than or equal to 1.

3. The electronic device according to claim 2, wherein, The second storage area comprises multiple unit storage areas. The first mode storage area includes the unit storage area located in the odd-numbered column among the plurality of unit storage areas, and The second mode storage area includes the unit storage area located in the even-numbered column among the plurality of unit storage areas.

4. The electronic device according to claim 1, wherein, Each of the plurality of first blocks has a size of p×q. Each of the plurality of second blocks has a size of 2p×q, and In this context, each of p and q is an integer greater than or equal to 1.

5. The electronic device according to claim 4, wherein, The second storage area comprises multiple unit storage areas. The first mode storage area includes the unit storage area located in the odd-numbered row among the plurality of unit storage areas, and The second mode storage area includes the unit storage area located in the even-numbered row among the plurality of unit storage areas.

6. The electronic device according to claim 1, wherein, The residual image compensation circuit further includes a compensation circuit. The compensation circuit receives first accumulated data stored in the first storage area as the degradation information of the first display area, and generates the first compensated image signal by compensating the first input image signal based on the first accumulated data. The compensation circuit receives second accumulated data stored in the second storage area as the degradation information of the second display area, and generates the second compensated image signal by compensating the second input image signal based on the second accumulated data.

7. The electronic device according to claim 6, wherein, The supernumerary image compensation circuit is further configured as follows: In the first mode, the second-1st accumulated data stored in the first mode storage area is read, and the second input image signal is compensated based on the second-1st accumulated data; and In the second mode, the second-second accumulated data stored in the second mode storage area is read, and the second input image signal is compensated based on the second-second accumulated data.

8. The electronic device according to claim 1, wherein, The supernumerary image compensation circuit is further configured as follows: Receive a flag signal that is deactivated in the first mode and activated in the second mode; and In response to the flag signal, one of the first mode storage area and the second mode storage area is selected.

9. The electronic device according to any one of claims 1 to 8, wherein, The display panel includes pixels provided in the first display area and the second display area, and The pixels include: First light-emitting element; Second light-emitting element; and The pixel circuit is configured to drive the first light-emitting element and the second light-emitting element.

10. The electronic device according to claim 9, wherein, The first mode is a first-view mode that outputs images from a first-view perspective. The second mode is a second-view mode that outputs the image from a narrower second-view perspective than the first viewpoint, and The electronic device further includes: An optical path control layer is disposed on the second light-emitting element and configured to control the range of light output from the second light-emitting element in the second mode.

11. The electronic device according to claim 10, wherein, The optical path control layer includes: The light-absorbing partition wall overlaps with the second light-emitting element when viewed in a plan view.

12. The electronic device according to claim 9, wherein, The pixel circuit includes: A first switching circuit, electrically connected to the first light-emitting element, and configured to apply a first driving current to the first light-emitting element in response to a first switching signal activated in the first mode; and A second switching circuit is electrically connected to the second light-emitting element and is configured to apply a second driving current to the second light-emitting element in response to a second switching signal activated in the second mode.

13. A method of driving an electronic device, the electronic device including a first display area operating in a first mode and a second display area operating in the first mode or a second mode, the method comprising: Receive a first input image signal for the first display area and a second input image signal for the second display area; A first compensated image signal and a second compensated image signal are generated by compensating the first input image signal and the second input image signal based on the degradation information of the first display area and the second display area, respectively. Images are displayed in the first display area and the second display area based on the first compensated image signal and the second compensated image signal, respectively. as well as The first degraded data generated based on the first compensated image signal is accumulated in the first storage area of ​​the accumulation memory, and the second degraded data generated based on the second compensated image signal is accumulated in the second storage area of ​​the accumulation memory. The first display area defines a plurality of first blocks, and the second display area defines a plurality of second blocks, each of the plurality of second blocks having a different size than each of the plurality of first blocks. The second storage area includes: A first-mode storage area is configured to accumulate the 2-1st degraded data of each of the plurality of second blocks in the first mode; and The second mode storage area is configured to accumulate the second-second degraded data of each of the plurality of second blocks in the second mode.

14. The method according to claim 13, wherein, Compensating the first input image signal and the second input image signal includes: Determine whether the first input image signal and the second input image signal are for the first display area or for the second display area; When the first input image signal is directed to the first display area, the first input image signal is compensated based on the first accumulated data of the first display area. When the second input image signal is directed to the second display area, the state of the flag signal is determined; When the flag signal is deactivated, the second input image signal is compensated based on the second-to-first accumulated data of the second display area in the first mode; and When the flag signal is activated, the second input image signal is compensated based on the second-to-second cumulative data of the second display area in the second mode.

15. The method according to claim 13, wherein, The accumulated first degradation data and second degradation data include: Determine whether the sampling signal is for the first display area or the second display area; When the sampling signal is not directed to the second display area, the first degraded data of the first block is generated based on the sampling signal, and the first degraded data is accumulated in the first storage area. When the sampling signal is directed at the second display area, the state of the flag signal is determined; When the flag signal is deactivated, the second block of the second-1st degraded data in the first mode is generated, and the second-1st degraded data is accumulated in the first mode storage area; and When the flag signal is activated, the second block of the second-second degraded data in the second mode is generated, and the second-second degraded data is accumulated in the second mode storage area.

16. The method according to claim 13, wherein, Each of the plurality of first blocks has a size of p×q. Each of the plurality of second blocks has a size of p×2q, and In this context, each of p and q is an integer greater than or equal to 1.

17. The method according to claim 16, wherein, The second storage area comprises multiple unit storage areas. The first mode storage area includes the unit storage area located in the odd-numbered column among the plurality of unit storage areas, and The second mode storage area includes the unit storage area located in the even-numbered column among the plurality of unit storage areas.

18. The method according to claim 13, wherein, Each of the plurality of first blocks has a size of p×q. Each of the plurality of second blocks has a size of 2p×q, and In this context, each of p and q is an integer greater than or equal to 1.

19. The method according to claim 18, wherein, The second storage area comprises multiple unit storage areas. The first mode storage area includes the unit storage area located in the odd-numbered row among the plurality of unit storage areas, and The second mode storage area includes the unit storage area located in the even-numbered row among the plurality of unit storage areas.

20. An electronic device comprising: The display panel includes a first display area that operates in a first mode or a second mode and a second display area that operates in the first mode or the second mode. as well as The image compensation circuit is configured to receive a first input image signal for the first display area and a second input image signal for the second display area, and to generate a first compensated image signal and a second compensated image signal by compensating the first input image signal and the second input image signal based on degradation information of the first display area and the second display area, respectively. The residual image compensation circuit includes an accumulation memory, which comprises a first storage area and a second storage area. The second storage area includes: A first-mode storage area is configured to accumulate the second-to-first degraded data of the second display area in the first mode; and The second mode storage area is configured to accumulate the second-second degraded data of the second display area in the second mode, and The first storage area includes: A third-mode storage area is configured to accumulate the first-to-first degraded data of the first display area in the first mode; and The fourth mode storage area is configured to accumulate the first-second degraded data of the first display area in the second mode.

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