Electronic device and driving method of electronic device

Abstract

An electronic device and a driving method of the electronic device are provided, the electronic device including: a display panel including pixels; a driving controller configured to receive an input image signal and a control signal, and configured to output a voltage control signal; and a voltage generator configured to generate a bias voltage based on the voltage control signal. The driving controller controls to drive a first display area of the display panel at a first frequency and to drive a second display area of the display panel at a second frequency different from the first frequency in a multi-frequency mode. The drive controller outputs a voltage control signal in a multi-frequency mode such that the bias voltage has a first bias voltage level based on driving the first display area, and the bias voltage has a second voltage level different from the first bias voltage level based on driving the second display area.

Description

Electronic devices and methods of driving electronic devices

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0150568, filed on October 30, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more exemplary embodiments of this disclosure described herein relate to electronic devices and methods of driving electronic devices. Background Technology

[0003] Electronic devices (such as smartphones, digital cameras, laptops, navigation devices, monitors, and smart TVs) can display images.

[0004] The electronic device includes a plurality of pixels for displaying an image and driving circuitry for controlling the plurality of pixels. Each of the plurality of pixels may include a light-emitting element and pixel circuitry for controlling the light-emitting element. The pixel circuitry may include a plurality of transistors organically connected to each other.

[0005] As electronic devices are used in more diverse fields, multiple different images can be displayed on a single electronic device. Summary of the Invention

[0006] One or more exemplary embodiments of this disclosure provide an electronic device and a driving method thereof capable of reducing power consumption and preventing display quality degradation.

[0007] According to an aspect of an example embodiment, an electronic device includes: a display panel including pixels; a drive controller configured to receive an input image signal and a control signal, and further configured to output a voltage control signal; and a voltage generator configured to generate a bias voltage based on the voltage control signal, wherein the pixels include: a first transistor including a first electrode, a second electrode, and a gate electrode; and a second transistor including a first electrode connected to the first electrode of the first transistor, a second electrode connected to a bias voltage line receiving the bias voltage, and a gate electrode, wherein the drive controller is further configured to: in a multi-frequency mode, control to drive a first display area of ​​the display panel at a first frequency, and drive a second display area of ​​the display panel at a second frequency different from the first frequency, and wherein the drive controller is further configured to: in a multi-frequency mode, output the voltage control signal such that the bias voltage has a first bias voltage level based on driving the first display area, and the bias voltage has a second voltage level different from the first bias voltage level based on driving the second display area.

[0008] According to an example embodiment, a method for driving an electronic device is provided, the electronic device including a display panel comprising pixels, each pixel including a first transistor and a second transistor connected between a first electrode of the first transistor and a bias voltage line receiving a bias voltage. The method includes: confirming, in a multi-frequency mode, a first frequency of a first display area of ​​the display panel, a second frequency of a second display area of ​​the display panel, and a starting position of a second display area; determining whether an operating mode is a boundary region compensation mode; and controlling a voltage level of a bias voltage based on determining that the operating mode is a boundary region compensation mode, wherein the step of controlling the voltage level of the bias voltage includes: controlling the bias voltage to have a first bias voltage level based on driving the first display area in the multi-frequency mode; and controlling the bias voltage to have a second voltage level different from the first bias voltage level based on driving a boundary region adjacent to the first display area within the second display area in the multi-frequency mode.

[0009] According to an aspect of an example embodiment, an electronic device includes: a display panel including pixels; and a drive controller configured to control the display panel, wherein the drive controller is further configured to: drive a first display area of ​​the display panel at a first frequency and drive a second display area of ​​the display panel at a second frequency, wherein the drive controller is further configured to: output a voltage control signal such that a bias voltage input to a pixel corresponding to the first display area has a first bias voltage level, and a bias voltage input to a pixel corresponding to the second display area based on driving the second display area has a second bias voltage level different from the first bias voltage level, and wherein the drive controller is further configured to: output a voltage control signal such that the first bias voltage level and the second bias voltage level have a difference based on the difference between the first frequency and the second frequency. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become apparent from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a plan view of an electronic device according to one or more embodiments of the present disclosure.

[0012] Figures 2A and 2B are perspective views of an electronic device according to one or more embodiments of the present disclosure.

[0013] Figure 3A is a diagram illustrating the operation of an electronic device according to one or more embodiments of the present disclosure in single-frequency mode.

[0014] Figure 3B is a diagram illustrating the operation of an electronic device according to one or more embodiments of the present disclosure in a multi-frequency mode.

[0015] Figure 4 is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0016] Figure 5 is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0017] Figure 6 illustrates examples of scanning signals in single-frequency and multi-frequency modes according to one or more embodiments of the present disclosure.

[0018] Figure 7 illustrates examples of scanning signals in single-frequency and multi-frequency modes according to one or more embodiments of the present disclosure.

[0019] Figure 8A is a timing diagram illustrating the operation of a pixel in a second frame of a multi-frequency mode according to one or more embodiments of the present disclosure.

[0020] Figure 8B is a timing diagram illustrating the operation of a pixel in a second frame of a multi-frequency mode according to one or more embodiments of the present disclosure.

[0021] Figures 9A and 9B are diagrams illustrating the variation of the threshold voltage of a first transistor according to one or more embodiments of the present disclosure as a function of a pixel.

[0022] Figure 10 shows images displayed on a display panel in single-frequency mode and multi-frequency mode according to one or more embodiments of the present disclosure.

[0023] Figure 11 is a flowchart illustrating the operation of a drive controller in an electronic device according to one or more embodiments of the present disclosure.

[0024] Figure 12 is a graph showing the voltage levels of the bias voltage in a boundary region compensation mode according to one or more embodiments of the present disclosure.

[0025] Figure 13 is a graph showing the voltage levels of the bias voltage during a first compensation mode, a second compensation mode, and a third compensation mode according to one or more embodiments of the present disclosure.

[0026] Figure 14 is a graph showing the voltage levels of the bias voltage according to the operating mode according to one or more embodiments of the present disclosure.

[0027] Figure 15 is a graph showing the voltage levels of the bias voltage according to the operating mode according to one or more embodiments of the present disclosure.

[0028] Figure 16 is a flowchart illustrating the operation of a drive controller in an electronic device according to one or more embodiments of the present disclosure.

[0029] Figure 17 is a graph showing the voltage levels of the bias voltage according to the operating mode of one or more embodiments of the present disclosure.

[0030] Figure 18 is a diagram illustrating a second initialization voltage according to an operating mode of one or more embodiments of the present disclosure.

[0031] Figure 19 is a diagram illustrating a second initialization voltage according to an operating mode of one or more embodiments of the present disclosure.

[0032] Figure 20 is a diagram illustrating bias voltages according to operating modes according to one or more embodiments of the present disclosure.

[0033] Figure 21 is a diagram illustrating bias voltages according to operating modes according to one or more embodiments of the present disclosure.

[0034] Figure 22 is a block diagram illustrating some components of an electronic device according to one or more embodiments of the present disclosure. Detailed Implementation

[0035] In the specification, the statement that the first component (or region, layer, part, etc.) is "on" the second component, "connected to" the second component, or "combined with" the second component means that the first component is directly on the second component, directly connected to the second component, or directly combined with the second component, or that the third component is placed between the first component and the second component.

[0036] The same reference numerals refer to the same components. Furthermore, in the drawings, for the effective description of the technical content, the thickness, scale, and dimensions of the components may be exaggerated. The term "and / or" may include one or more combinations of the relevant listed items, as well as the individual items listed.

[0037] Although the terms “first,” “second,” etc., can be used to describe various components, the components should not be construed as being limited by the terms. The terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The articles “a,” “an,” and “the” are singular because they have a single indicator, but the use of the singular form in the specification should not preclude the existence of more than one indicator.

[0038] Furthermore, the terms "below," "under," "on," and "above" are used to describe the relationships between the components shown in the accompanying drawings. The terms are relative and described with reference to the directions indicated in the drawings.

[0039] It will be understood that the terms “comprising,” “including,” “having,” etc., indicate the presence of the features, quantities, steps, operations, elements, components, and / or combinations thereof described in the specification, without excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0040] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0041] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0042] Figure 1 is a plan view of an electronic device ED according to an embodiment of the present disclosure.

[0043] Referring to FIG1, a portable terminal (e.g., a display device) is shown as an example of an electronic device ED according to one or more embodiments of the present disclosure. Portable terminals may include, for example, but not limited to, tablet PCs, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, watch-type electronic devices, etc. However, the present disclosure is not limited thereto. The present disclosure can be used for small and / or medium-sized electronic devices (such as, but not limited to, personal computers, laptops, self-service kiosks, car navigation units, and cameras) and / or large electronic devices (such as, but not limited to, televisions or billboards). The above examples are provided only as embodiments, and it will be understood that the present disclosure can be applied to any other electronic device(s) without departing from the spirit of the present disclosure.

[0044] As shown in Figure 1, the electronic device ED may include a display device, and the display surface on which the first image IM1 and the second image IM2 are displayed may be parallel to a plane defined by a first direction DR1 and a second direction DR2. The display surface of the electronic device ED may include multiple regions. The display surface may include a display area DA in which the first image IM1 and the second image IM2 are displayed and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. For example, the display area DA may have a rectangular shape. The non-display area NDA may surround the display area DA. Furthermore, the electronic device ED may include a partially curved shape. Therefore, although not shown, a region of the display area DA may have a curved shape.

[0045] The display area DA of an electronic device ED may include a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 may be displayed in the first display area DA1, and a second image IM2 may be displayed in the second display area DA2. For example, the first image IM1 may be a video, and the second image IM2 may be a still image or an image with a low frequency of change (i.e., not frequently changing) (e.g., a keyboard for game control, text information, etc.).

[0046] According to an embodiment, the electronic device ED can drive a first display area DA1, in which video is displayed, at a first frequency higher than or equal to a reference frequency (or a normal frequency), and can drive a second display area DA2, in which still images or images with low frequency variations are displayed, at a second frequency lower than the reference frequency. The electronic device ED can reduce power consumption by lowering the frequency of the second display area DA2.

[0047] The size of each of the first display area DA1 and the second display area DA2 can be a predetermined size and can be changed by an application. In one embodiment, when a still image is displayed in the first display area DA1 and video is displayed in the second display area DA2, the first display area DA1 can be driven at a second frequency lower than a reference frequency, and the second display area DA2 can be driven at a first frequency higher than or equal to the reference frequency. In another embodiment, the display area DA can be divided into three or more display areas. The frequency of each display area can be determined according to the type of image displayed in each display area (e.g., still image or video).

[0048] Figures 2A and 2B are perspective views of an electronic device ED2 according to one or more embodiments of the present disclosure. Figure 2A shows the electronic device ED2 in an unfolded state. Figure 2B shows the electronic device ED2 in a folded state.

[0049] As shown in Figures 2A and 2B, the electronic device ED2 may include a display area DA and a non-display area NDA. The electronic device ED2 can display an image in the display area DA. In its unfolded state, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the electronic device ED2 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, a front surface (or upper surface) and a rear surface (or lower surface) including one or more components of the electronic device ED2 may be defined based on the third direction DR3. For example, the display area DA may have a rectangular shape. The non-display area NDA may surround the display area DA. However, this disclosure is not limited thereto.

[0050] The display area DA may include a first non-foldable area NFA1, a foldable area FA, and a second non-foldable area NFA2. The foldable area FA may lie between the first non-foldable area NFA1 and the second non-foldable area NFA2. The foldable area FA may be bent about a folding axis FX extending in a second direction DR2. The foldable area FA may be bent inward or outward based on the folding axis FX.

[0051] When the electronic device ED2 is folded (e.g., folded inward), the first non-folded region NFA1 and the second non-folded region NFA2 can face each other along the third direction DR3. Therefore, when fully folded, the display area DA may not be exposed to the outside of the electronic device ED2, which may be referred to as "inward folding" (or "inward folding state" or "inward folding operation"). However, the embodiments are not limited to this, and the operation and construction of the electronic device ED2 are not limited to this.

[0052] In embodiments of this disclosure, when the electronic device ED2 is folded (e.g., folded outwards), the first non-folded region NFA1 and the second non-folded region NFA2 can be opposite each other and facing away from each other. Therefore, when folded (partially or completely), the first non-folded region NFA1, the second non-folded region NFA2, and the folded region FA (or display region DA) can be exposed to the outside, which can be referred to as "outward folding" (or "outward folding state" or "outward folding operation").

[0053] Electronic device ED2 can be configured to perform only one of the inward folding and outward folding operations. Optionally, electronic device ED2 can be configured to perform both inward folding and outward folding operations. In this case, the same area of ​​electronic device ED2 (e.g., folding area FA) can be both foldable inward and foldable outward. Optionally, at least one area of ​​electronic device ED2 can be foldable inward, and at least one other area can be foldable outward.

[0054] Figures 2A and 2B show one folded region and two non-folded regions, but the number of folded and non-folded regions is not limited thereto. For example, electronic device ED2 may include more than two non-folded regions and multiple folded regions, each positioned between adjacent non-folded regions.

[0055] Figures 2A and 2B show the folding axis FX parallel to the minor axis of the electronic device ED2. However, this disclosure is not limited thereto. For example, the folding axis FX may extend in a direction parallel to the major axis of the electronic device ED2 (e.g., a first direction DR1).

[0056] Figures 2A and 2B show that the first non-folded region NFA1, the folded region FA, and the second non-folded region NFA2 can be arranged sequentially in the first direction DR1. However, this disclosure is not limited thereto. For example, the first non-folded region NFA1, the folded region FA, and the second non-folded region NFA2 can be arranged sequentially in the second direction DR2.

[0057] Multiple display areas DA1 and DA2 can be defined within the display area DA of the electronic device ED2. Figure 2A shows two display areas DA1 and DA2 as an example. However, the number of display areas DA1 and DA2 is not limited to this.

[0058] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area in which a second image IM2 is displayed. However, this disclosure is not limited thereto. For example, the first image IM1 may be a video, and the second image IM2 may be a still image or an image with a low frequency of change (e.g., text information, etc.).

[0059] The electronic device ED2 according to the embodiment can operate according to different operating modes. The operating modes may include a single-frequency mode and a multi-frequency mode. In single-frequency mode, the electronic device ED2 can drive both the first display area DA1 and the second display area DA2 at a reference frequency. In the embodiment, in multi-frequency mode, the electronic device ED2 can drive the first display area DA1 displaying the first image IM1 at a first frequency, and can drive the second display area DA2 displaying the second image IM2 at a second frequency lower than the first frequency. In the embodiment, the first frequency may be equal to or higher than the reference frequency.

[0060] The size of each of the first display area DA1 and the second display area DA2 can be a predetermined size and can be changed by an application. In an embodiment, the first display area DA1 can correspond to the first non-folding area NFA1, and the second display area DA2 can correspond to the second non-folding area NFA2. In an embodiment, the first portion of the folding area FA can correspond to the first display area DA1, and the second portion of the folding area FA can correspond to the second display area DA2.

[0061] In an embodiment, the entire folded area FA may correspond to only one of the first display area DA1 and the second display area DA2.

[0062] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the size of the second display area DA2 may be larger than the size of the first display area DA1.

[0063] In this embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2, and the second display area DA2 may correspond to a second portion of the second non-foldable area NFA2. That is, the size of the first display area DA1 may be larger than the size of the second display area DA2.

[0064] As shown in Figure 2B, when the folded area FA is folded, the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the folded area FA and the second non-folded area NFA2.

[0065] Figures 2A and 2B illustrate an example of an electronic device ED2 having a folded area as a display device. However, this disclosure is not limited thereto. For example, this disclosure can also be applied to display devices having two or more folded areas, rollable display devices, or slidable display devices.

[0066] In the following description, the electronic device ED shown in Figure 1 will be used as an example. However, the electronic device ED shown in Figure 1 can be applied to the electronic devices ED2 shown in Figures 2A and 2B.

[0067] Figure 3A is a diagram illustrating the operation of an electronic device ED according to one or more embodiments of the present disclosure in single-frequency mode (SFM). Figure 3B is a diagram illustrating the operation of an electronic device ED according to one or more embodiments of the present disclosure in multi-frequency mode (MFM).

[0068] Referring to FIG3A, the first image IM1 displayed in the first display area DA1 can be a video. The second image IM2 displayed in the second display area DA2 can be a still image or an image with a low frequency of change (e.g., a keyboard used to manipulate a game). The first image IM1 displayed in the first display area DA1 and the second image IM2 displayed in the second display area DA2 shown in FIG1 are merely examples, and various images can be displayed on the electronic device ED.

[0069] In Single Frequency Mode (SFM), each of the first display area DA1 and the second display area DA2 of the electronic device ED can operate at a first frequency. For example, the first frequency can be 120Hz. When the first frequency is 120Hz, the images of the first frame F1 to the 120th frame F120 of the first image IM1 and the second image IM2 can be displayed for 1 second in the first display area DA1 and the second display area DA2.

[0070] Referring to Figure 3B, in Multi-Frequency Mode (MFM), the electronic device ED can set the frequency of a first display area DA1, in which a first image IM1 (e.g., video) is displayed, to a first frequency, and can set the frequency of a second display area DA2, in which a second image IM2 (e.g., still image) is displayed, to a second frequency lower than the first frequency. For example, the first frequency can be 120Hz, and the second frequency can be 1Hz. The first and second frequencies can be changed differently. For example, when the reference frequency is 120Hz, the first frequency can be the same as the reference frequency, 120Hz, or, as an example, 144Hz, higher than the reference frequency. As an example, the second frequency can be one of 60Hz, 30Hz, 15Hz, 10Hz, and 1Hz, which are lower than the reference frequency.

[0071] In Multi-Frequency Mode (MFM), when the first frequency is 120Hz and the second frequency is 1Hz, the first image IM1 can be displayed for 1 second in the first display area DA1 of the electronic device ED during the first frame F1 to the 120th frame F120. The second image IM2 can be displayed in the second display area DA2 only during the 1-second period of the first frame F1, and no image can be displayed during the second frames F2 to the 120th frame F120. In an embodiment, in the second display area DA2, for each of the second frames F2 to the 120th frame F120, the same image as the first frame F1 can be repeatedly displayed as a replacement.

[0072] Figure 4 is a block diagram of an electronic device ED according to one or more embodiments of the present disclosure.

[0073] Referring to Figure 4, the electronic device ED may include a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0074] The drive controller 100 can receive image signals RGB and control signals CTRL. The drive controller 100 can generate image data signals DATA by converting the data format of the image signals RGB into an interface specification suitable for the data drive circuit 200. The drive controller 100 can output scan control signals SCS, data control signals DCS, and transmit drive control signals ECS. In an embodiment, the drive controller 100 can output voltage control signals VCTRL according to the operating mode.

[0075] The data driving circuit 200 can receive a data control signal DCS and an image data signal DATA from the drive controller 100. The data driving circuit 200 can convert the image data signal DATA into a data signal and then output the data signal to multiple data lines DL1 to DLm, which will be described later. The data signal can refer to an analog voltage corresponding to the grayscale level of the image data signal DATA. The multiple data lines DL1 to DLm can extend from the data driving circuit 200 in a first direction DR1 and can be arranged spaced apart from each other in a second direction DR2.

[0076] Voltage generator 300 can generate voltages for operating the display panel DP. In an embodiment, voltage generator 300 can generate a first drive voltage ELVDD, a second drive voltage ELVSS, a reference voltage VREF, a first initialization voltage VINT, a second initialization voltage VAINT, and a bias voltage Vbias. In an embodiment, voltage generator 300 can determine the voltage level of bias voltage Vbias in response to a voltage control signal VCTRL. In an embodiment, voltage generator 300 can determine the voltage level of second initialization voltage VAINT in response to a voltage control signal VCTRL.

[0077] The display panel DP may include scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, emission control lines EML1a to EMLna and EML1b to EMLnb, data lines DL1 to DLm (where n and m can both be natural numbers greater than 1), and pixels PX. The display panel DP may also include a scan drive circuit SD and an emission drive circuit EDC. In an embodiment, the scan drive circuit SD may be arranged on a first side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn may extend from the scan drive circuit SD in a second direction DR2.

[0078] The transmit drive circuit EDC can be arranged on the second side of the display panel DP. The transmit control lines EML1a to EMLna and EML1b to EMLnb extend from the transmit drive circuit EDC in the opposite direction to the second direction DR2.

[0079] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, as well as the transmit control lines EML1a to EMLna and EML1b to EMLnb, can be arranged spaced apart from each other in the first direction DR1.

[0080] In the example shown in Figure 4, the scan driving circuit SD and the emission driving circuit EDC can be arranged facing each other, with the pixel PX positioned between the scan driving circuit SD and the emission driving circuit EDC; however, this disclosure is not limited thereto. For example, the scan driving circuit SD and the emission driving circuit EDC can be positioned adjacent to each other on one of the first and second sides of the display panel DP. In an embodiment, the scan driving circuit SD and the emission driving circuit EDC can be implemented using a single circuit.

[0081] Multiple pixels (PX) can be electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, emission control lines EML1a to EMLna and EML1b to EMLnb, and data lines DL1 to DLm. Each of the multiple pixels (PX) can be electrically connected to four scan lines and two emission control lines. For example, as shown in Figure 4, the pixels in the first row can be connected to scan lines GIL1, GCL1, GWL1 and GBL1 and emission control lines EML1a and EML1b. Furthermore, the pixels in the second row can be connected to scan lines GIL2, GCL2, GWL2 and GBL2 and emission control lines EML2a and EML2b. The pixels in the nth row can be connected to scan lines GILn, GCLn, GWLn and GBLn and emission control lines EMLna and EMLnb.

[0082] Each of the multiple pixels (PX) may include a light-emitting diode (also referred to below as a "light-emitting element") LD (see Figure 5) and a pixel circuit PXC (see Figure 5) for controlling the light emission of the light-emitting diode LD. The pixel circuit PXC may include one or more transistors and one or more capacitors. The scan drive circuit SD and the emitter drive circuit EDC may include transistors formed using the same process as the transistors in the pixel circuit PXC.

[0083] Each of the multiple pixels PX can receive a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage VREF, a first initialization voltage VINT, a second initialization voltage VAINT, and a bias voltage Vbias from the voltage generator 300.

[0084] The scan drive circuit SD can receive the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn.

[0085] The transmit drive circuit EDC can output transmit control signals to the transmit control lines EML1a to EMLna and EML1b to EMLnb in response to the transmit drive control signal ECS received from the drive controller 100.

[0086] According to embodiments of the present disclosure, the drive controller 100 can determine the operating mode of the electronic device ED, and control the data drive circuit 200, the scan drive circuit SD, and the transmit drive circuit EDC according to the determined operating mode. In embodiments, the operating mode may include a single-frequency mode and a multi-frequency mode.

[0087] Figure 5 is a circuit diagram of a pixel PX according to one or more embodiments of the present disclosure.

[0088] Figure 5 shows the equivalent circuit diagram of pixel PX, which is connected to the i-th data line DL1 to DLm, the j-th scan lines GILj, GCLj, GWLj and GBLj among the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, and the j-th emission control lines EMLja and EMLjb among the emission control lines EML1a to EMLna and EML1b to EMLnb shown in Figure 4.

[0089] Each of the multiple pixels PX shown in Figure 4 can have the same circuit construction as the equivalent circuit diagram of pixel PX shown in Figure 5.

[0090] Referring to FIG5, a pixel PX included in an electronic device ED (referring to FIG4) according to an embodiment may include a pixel circuit PXC and at least one light-emitting diode LD. In an embodiment, a pixel PX may include one light-emitting diode LD.

[0091] The pixel circuit (PXC) may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, as well as capacitors Chold and Cst. In an embodiment, each of the first transistor T1 and the sixth transistors T6 through T9 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and each of the second transistors T2 through T5 may be an N-type transistor having an oxide semiconductor layer, but this disclosure is not limited thereto. In an embodiment, all of the first transistors T1 through T9 may be either P-type or N-type transistors. In an embodiment, at least one of the first transistors T1 through T9 may be a P-type transistor, and the remaining transistors may be N-type transistors.

[0092] Furthermore, the circuit construction of pixel PX according to the embodiments of this disclosure is not limited to the embodiment shown in FIG5. The pixel PX shown in FIG5 is merely an example, and the circuit construction of pixel PX can be modified and implemented.

[0093] Scan lines GILj, GCLj, GWLj, and GBLj can transmit scan signals GIj, GCj, GWj, and GBj, respectively. Transmit control lines EMLja and EMLjb can transmit transmit control signals EMja and EMjb, respectively. Data line DLi can transmit data signal Di. Data signal Di can have a voltage level corresponding to the image signal RGB (see Figure 4) input to the electronic device ED. First voltage lines VL1 to sixth voltage lines VL6 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the reference voltage VREF, the first initialization voltage VINT, the second initialization voltage VAINT, and the bias voltage Vbias to pixel PX, respectively.

[0094] Capacitor Chold can be connected between the first voltage line VL1 and the first node N1. Capacitor Cst can be connected between the first node N1 and the second node N2.

[0095] The first transistor T1 may include a first electrode electrically connected to the first voltage line VL1 via a sixth transistor T6, a second electrode electrically connected to the anode of the light-emitting diode LD via a seventh transistor T7, and a gate electrode connected to the second node N2.

[0096] The second transistor T2 may include a first electrode connected to the data line DLi, a second electrode connected to the first node N1, and a gate electrode connected to the scan line GWLj. The second transistor T2 may transmit the data signal Di received via the data line DLi to the first node N1 in response to the scan signal GWj received via the scan line GWLj.

[0097] The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the second node N2, and a gate electrode connected to the scan line GCLj. The third transistor T3 may electrically connect the gate electrode of the first transistor T1 and the second electrode of the first transistor T1 in response to the scan signal GCj received through the scan line GCLj.

[0098] The fourth transistor T4 may include a first electrode connected to the second node N2, a second electrode connected to the fourth voltage line VL4 (or the first initialization voltage line), and a gate electrode connected to the scan line GILj. The fourth transistor T4 may, in response to the scan signal GIj received via the scan line GILj, transmit the first initialization voltage VINT received via the fourth voltage line VL4 to the second node N2.

[0099] The fifth transistor T5 may include a first electrode connected to the first node N1, a second electrode connected to the third voltage line VL3 (or the reference voltage line), and a gate electrode connected to the scan line GCLj. The fifth transistor T5 may be turned on in response to a scan signal GCj received through the scan line GCLj to pass the reference voltage VREF to the first node N1.

[0100] The sixth transistor T6 may include a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emitter control line EMLja. The sixth transistor T6 may be turned on in response to an emitter control signal EMja received via the emitter control line EMLja, so as to electrically connect the first voltage line VL1 to the first electrode of the first transistor T1.

[0101] The seventh transistor T7 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode LD, and a gate electrode connected to the emission control line EMLjb. The seventh transistor T7 may be turned on in response to an emission control signal EMjb received via the emission control line EMLjb, so as to electrically connect the second electrode of the first transistor T1 to the light-emitting diode LD.

[0102] The eighth transistor T8 may include a first electrode connected to the anode of the light-emitting diode LD, a second electrode connected to the fifth voltage line VL5 (or the second initialization voltage line), and a gate electrode connected to the scan line GBLj. The eighth transistor T8 may be turned on in response to a scan signal GBj received via the scan line GBLj to bypass the current of the anode of the light-emitting diode LD to the fifth voltage line VL5. Optionally, the eighth transistor T8 may be turned on in response to a scan signal GBj received via the scan line GBLj to initialize the anode of the light-emitting diode LD to the second initialization voltage VAINT.

[0103] The ninth transistor T9 (or bias transistor) may include a first electrode connected to the first electrode of the first transistor T1, a second electrode connected to the sixth voltage line VL6 (or bias voltage line), and a gate electrode connected to the scan line GBLj. The ninth transistor T9 may be turned on in response to a scan signal GBj received through the scan line GBLj to electrically connect the sixth voltage line VL6 to the first electrode of the first transistor T1.

[0104] A light-emitting diode (LD) may include an anode connected to the second electrode of a seventh transistor T7 and a cathode connected to a second voltage line VL2.

[0105] Figure 6 illustrates examples of scan signals GI1 to GI3840 under single-frequency mode (SFM) and multi-frequency mode (MFM) according to one or more embodiments of the present disclosure.

[0106] Figure 6 illustrates 3840 scan signals GI1 to GI3840, but this disclosure is not limited thereto. The number of scan signals can vary depending on the size and resolution of the display panel DP.

[0107] Referring to Figures 5 and 6, in Single Frequency Mode (SFM), the frequency of scan signals GI1 to GI3840 can be 120Hz. In Single Frequency Mode (SFM), scan signals GI1 to GI3840 can be activated as high-level in each of the first frame F1 to the 120th frame F120.

[0108] In an embodiment, under the multi-frequency mode MFM, among the scan signals GI1 to GI3840, scan signals GI1 to GI1920 can correspond to the first display area DA1 of the electronic device ED shown in FIG1, and scan signals GI1921 to GI3840 can correspond to the second display area DA2 of the electronic device ED shown in FIG1.

[0109] In Multi-Frequency Mode (MFM), scan signals GI1 to GI1920 can be activated as high in each of the first frame F1 to the 120th frame F120, and scan signals GI1921 to GI3840 can be activated as high only in the first frame F1. That is, in MFM, the frequency of scan signals GI1 to GI1920 corresponding to the first display area DA1 displaying the first image IM1 (e.g., video) can be 120Hz, and the frequency of scan signals GI1921 to GI3840 corresponding to the second display area DA2 displaying the second image IM2 (e.g., still image) can be 1Hz.

[0110] The scan signals GC1 to GCn and GW1 to GWn transmitted through the scan lines GCL1 to GCLn and GWL1 to GWLn shown in Figure 4 can have waveforms similar to those of the scan signals GI1 to GI3840 shown in Figure 6. That is, in single-frequency mode (SFM), the frequency of each of the scan signals GC1 to GCn and GW1 to GWn can be a first frequency. In multi-frequency mode (MFM), the frequency of the scan signal corresponding to the first display area DA1 among the scan signals GC1 to GCn and GW1 to GWn can be the first frequency, and the frequency of the scan signal corresponding to the second display area DA2 can be a second frequency lower than the first frequency.

[0111] Figure 7 illustrates examples of scan signals GB1 to GB3840 under single-frequency mode SFM and multi-frequency mode MFM according to one or more embodiments of the present disclosure.

[0112] Figure 7 illustrates 3840 scan signals GB1 to GB3840, but this disclosure is not limited thereto. The number of scan signals can vary depending on the size and resolution of the display panel DP.

[0113] Referring to Figures 4 and 7, in single-frequency mode (SFM), the frequency of scan signals GB1 to GB3840 can be 120Hz. In multi-frequency mode (MFM), the frequency of scan signals GB1 to GB3840 can also be 120Hz. In other words, in multi-frequency mode (MFM), the frequency of scan signals GB1 to GB3840 can be the same as the frequency in single-frequency mode (SFM).

[0114] In the embodiment, under the multi-frequency mode MFM, among the scan signals GB1 to GB3840, scan signals GB1 to GB1920 can correspond to the first display area DA1 of the electronic device ED shown in FIG1, and scan signals GB1921 to GB3840 can correspond to the second display area DA2 of the electronic device ED shown in FIG1.

[0115] In the embodiments, in single-frequency mode (SFM) and multi-frequency mode (MFM), the frequency of the transmit control signals EM1a to EMna and EM1b to EMnb transmitted through the transmit control lines EML1a to EMLna and EML1b to EMLnb shown in Figure 4 can be 120Hz, which is the same as the frequency of the scan signals GB1 to GB3840.

[0116] Figure 8A is a timing diagram illustrating the operation of pixel PX in the second frame F2 of multi-frequency mode MFM according to one or more embodiments of the present disclosure.

[0117] In this embodiment, it is assumed that "j" is 1. That is, FIG8A is a timing diagram for describing the operation of pixel PX connected to the first scan lines GIL1, GCL1, GWL1 and GBL1 and the first emission control lines EML1a and EML1b corresponding to the first display area DA1 (refer to FIG1).

[0118] Referring to Figures 5 and 8A, a high-level scan signal GI1 can be provided via scan line GIL1 during the first time period in the second frame F2. When the fourth transistor T4 is turned on in response to the high-level scan signal GI1, the first initialization voltage VINT can be supplied to the gate electrode of the first transistor T1 through the fourth transistor T4 to initialize the first transistor T1.

[0119] When a high-level scan signal GC1 is supplied via scan line GCL1 during the second time period in the second frame F2, the third transistor T3 and the fifth transistor T5 can be turned on. When the third transistor T3 is turned on, the first transistor T1 can be turned on via the diode connection of the third transistor T3 to be forward biased. During the second time period, because the transmit control signal EM1a is at a low level, a voltage that reduces the threshold voltage of the first transistor T1 from the first drive voltage ELVDD can be provided to the second node N2 (e.g., the second electrode of capacitor Cst). Furthermore, during the second time period, when the fifth transistor T5 is turned on, the reference voltage VREF can be passed to the first node N1 via the fifth transistor T5.

[0120] When a high-level scan signal GW1 is supplied via scan line GWL1 during the third time period in the second frame F2, the second transistor T2 can be turned on. Then, the data signal Di supplied from data line DLi can be transmitted to the first node N1 (e.g., the first electrode of capacitor Cst) via the second transistor T2.

[0121] When a low-level scan signal GB1 is supplied through scan line GBL1 during the fourth time period in the second frame F2, the eighth transistor T8 and the ninth transistor T9 can be turned on. When the eighth transistor T8 is turned on, the anode of the light-emitting element LD can be initialized to the second initialization voltage VAINT. When the ninth transistor T9 is turned on, the bias voltage Vbias can be provided to the first electrode of the first transistor T1.

[0122] When both control signals EM1a and EM1b are at a low level during the fifth time period in the second frame F2, the sixth transistor T6 and the seventh transistor T7 can be turned on. When the sixth transistor T6 and the seventh transistor T7 are turned on, a drive current Ids (see Figures 9A and 9B) can be generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Ids (see Figures 9A and 9B) can be supplied to the light-emitting element LD through the seventh transistor T7, so the light-emitting element LD can emit light.

[0123] Figure 8B is a timing diagram illustrating the operation of pixel PX in the second frame F2 of multi-frequency mode MFM according to one or more embodiments of the present disclosure.

[0124] In this embodiment, it is assumed that "j" is 3840. That is, FIG8B is a timing diagram for describing the operation of pixel PX connected to the 3840 scan lines GIL3840, GCL3840, GWL3840 and GBL3840 and the 3840 emission control lines EML3840a and EML3840b corresponding to the second display area DA2 (refer to FIG1).

[0125] Referring to Figures 5 and 8B, during the second frame F2, all of the scan signals GI3840, GC3840, and GW3840 can be kept at a low level. Therefore, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 remain off.

[0126] When a low-level scan signal GB3840 is supplied through the scan line GBL3840, the eighth transistor T8 and the ninth transistor T9 can be turned on. When the eighth transistor T8 is turned on, the anode of the light-emitting element LD can be initialized to the second initialization voltage VAINT. When the ninth transistor T9 is turned on, the bias voltage Vbias can be provided to the first electrode of the first transistor T1.

[0127] When both the transmit control signals EM3840a and EM3840b are at a low level, the sixth transistor T6 and the seventh transistor T7 can be turned on. When the sixth transistor T6 and the seventh transistor T7 are turned on, a drive current Ids (see Figures 9A and 9B) can be generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Ids (see Figures 9A and 9B) can be supplied to the light-emitting element LD through the seventh transistor T7, so the light-emitting element LD can emit light.

[0128] As shown in Figures 8A and 8B, in the second frame F2 of the multi-frequency mode MFM, when the pixel PX corresponding to the first display area DA1 has scan signals GI1, GC1, GW1 and GB1 that have been converted to active levels, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the ninth transistor T9 can be turned on. Therefore, various voltages can be applied to the first electrode, the second electrode and the gate electrode of the first transistor T1, thereby increasing the stress on the first transistor T1.

[0129] On the other hand, in the second frame F2 of the multi-frequency mode MFM, when the scan signal GB3840 becomes active, the ninth transistor T9 can be turned on in the pixel PX corresponding to the second display area DA2, and the bias voltage Vbias can be provided to the first electrode of the first transistor T1. Therefore, the stress of the first transistor T1 in the pixel PX of the first display area DA1 is higher than the stress of the first transistor T1 in the pixel PX of the second display area DA2.

[0130] Figures 9A and 9B are graphs illustrating the variation of the threshold voltage of the first transistor T1 according to one or more embodiments of the present disclosure as a function of the pixel PX.

[0131] Referring to Figures 5 and 9A, the threshold voltage of the first transistor T1 can initially be referred to as the "base threshold voltage Vth_B". When the first initialization voltage VINT is provided to the gate electrode of the first transistor T1, the gate-source voltage Vgs of the first transistor T1 can be a voltage below 0V. In this case, the threshold voltage of the first transistor T1 can be changed from the base threshold voltage Vth_B to a negatively shifted first threshold voltage Vth_I.

[0132] Referring to Figures 5 and 9B, when both the transmit control signals EMja and EMjb transition to a low level, the gate-source voltage Vgs of the first transistor T1 can be 0V. In this case, the threshold voltage of the first transistor T1 can be changed to the second threshold voltage Vth_E.

[0133] The extent to which the threshold voltage of the first transistor T1 changes from the first threshold voltage Vth_I to the second threshold voltage Vth_E can be determined by the stress level of the first transistor T1.

[0134] Figure 10 shows images displayed on a display panel DP in single-frequency mode (SFM) and multi-frequency mode (MFM) according to one or more embodiments of the present disclosure.

[0135] Referring to Figure 10, in Multi-Frequency Mode (MFM), a first image IM1 can be displayed in the first display area DA1, and a second image IM2 can be displayed in the second display area DA2. Pixels PX of the first display area DA1 can be driven at a first frequency (see Figure 5), and pixels PX of the second display area DA2 can be driven at a second frequency lower than the first frequency (see Figure 5).

[0136] Referring to Figures 5, 9A, 9B, and 10, when the stress deviation (or stress difference) between the first transistor T1 in pixel PX of the first display area DA1 and the first transistor T1 in pixel PX of the second display area DA2 is large, the deviation between the second threshold voltage Vth_E of the first transistor T1 in pixel PX of the first display area DA1 and the second threshold voltage Vth_E of the first transistor T1 in pixel PX of the second display area DA2 may increase.

[0137] Even when the operating mode is changed to single-frequency mode (SFM) after maintaining multi-frequency mode (MFM) for an extended period, and images with the same grayscale are displayed in the first display area DA1 and the second display area DA2, a brightness difference may still exist between the two display areas. This may be due to the difference between the second threshold voltage Vth_E of the first transistor T1 in pixel PX of the first display area DA1 and the second threshold voltage Vth_E of the first transistor T1 in pixel PX of the second display area DA2.

[0138] Figure 11 is a flowchart illustrating the operation of a drive controller 100 in an electronic device ED according to one or more embodiments of the present disclosure.

[0139] Referring to Figures 4 and 11, the drive controller 100 can determine the operating mode (operation S100) based on the image signal RGB and the control signal CTRL.

[0140] In one embodiment, the drive controller 100 may determine the operating mode based on mode information included in the control signal CTRL. In another embodiment, the drive controller 100 may determine the operating mode based on the pattern of the image signal RGB.

[0141] When the determined operating mode is multi-frequency mode, the drive controller 100 can confirm the first frequency of the first display area DA1, the second frequency of the second display area DA2, and the starting position of the second display area DA2 (operation S110).

[0142] When the determined operating mode is not multi-frequency mode, the drive controller 100 can operate in single-frequency mode (operation S200).

[0143] In multi-frequency mode, the drive controller 100 can operate in a compensation mode used to compensate for the brightness difference between the first display area DA1 and the second display area DA2. The compensation mode may include a boundary area compensation mode and a normal compensation mode. The drive controller 100 can operate in either the boundary area compensation mode or the normal compensation mode.

[0144] The drive controller 100 can operate in a predetermined compensation mode, or the compensation mode can be selected based on the compensation mode information included in the control signal CTRL.

[0145] When the predetermined compensation mode is the boundary region compensation mode, the drive controller 100 can control the bias voltage Vbias used to compensate the boundary region (e.g., BR in FIG. 12) (operation S130). In an embodiment, in the boundary region compensation mode, the drive controller 100 can provide a voltage control signal VCTRL to the voltage generator 300 for controlling the bias voltage Vbias. The voltage generator 300 can change the voltage level of the bias voltage Vbias in response to the voltage control signal VCTRL.

[0146] Figure 12 is a graph showing the voltage level of the bias voltage Vbias in the boundary region compensation mode according to one or more embodiments of the present disclosure.

[0147] Referring to Figure 12, when the first display area DA1 is driven in boundary area compensation mode, the bias voltage Vbias can have a default bias voltage level Vs.

[0148] In boundary region compensation mode, the second display area DA2 may include the boundary region BR and the non-boundary region NBR. The boundary region BR may be a region in the second display area DA2 that is adjacent to the first display area DA1.

[0149] In boundary region compensation mode, when driving the boundary region BR within the second display region DA2, the bias voltage Vbias can have a compensation voltage level different from the default bias voltage level Vs. In an embodiment, the compensation voltage level can include a first voltage level V1, a second voltage level V2, a third voltage level V3, and a fourth voltage level V4. When driving the boundary region BR, the bias voltage Vbias can sequentially change to the first voltage level V1, the second voltage level V2, the third voltage level V3, the fourth voltage level V4, and the default bias voltage level Vs. In an embodiment, the first voltage level V1, the second voltage level V2, the third voltage level V3, the fourth voltage level V4, and the default bias voltage level Vs can have a relationship of "V1>V2>V3>V4>Vs". In other words, at the beginning of the second display region DA2, the bias voltage Vbias can have the highest first voltage level V1 and gradually decrease.

[0150] In the non-boundary region NBR, the bias voltage Vbias can have the same default bias voltage level Vs, which is the level of the bias voltage Vbias applied when driving the first display region DA1. However, this is merely an example, and the present disclosure is not limited thereto. In an embodiment, in the non-boundary region NBR, the bias voltage Vbias can have a higher voltage level than the default bias voltage level Vs.

[0151] The drive controller 100 shown in Figure 4 can output a voltage control signal VCTRL, such that the bias voltage Vbias has any one of a first voltage level V1, a second voltage level V2, a third voltage level V3, a fourth voltage level V4, and a default bias voltage level Vs. The voltage generator 300 can generate a bias voltage Vbias with a voltage level corresponding to the voltage control signal VCTRL.

[0152] In pixel PX shown in Figure 5, a bias voltage Vbias can be provided to the first electrode of the first transistor T1. The higher the bias voltage Vbias provided to the first electrode of the first transistor T1, the greater the stress on the first transistor T1.

[0153] As described above, because the stress level of the first transistor T1 in pixel PX of the second display area DA2 is lower than that of the first transistor T1 in pixel PX of the first display area DA1, a brightness deviation may occur between the first display area DA1 and the second display area DA2. In the embodiments of this disclosure, when the bias voltage Vbias provided to pixel PX of the second display area DA2 increases, the stress level of the first transistor T1 in pixel PX of the second display area DA2 increases, thereby minimizing the brightness deviation between the first display area DA1 and the second display area DA2.

[0154] Specifically, the brightness difference perceived by the user in the boundary region BR can be reduced by increasing the voltage level of the bias voltage Vbias in the boundary region BR adjacent to the first display region DA1 of the second display region DA2.

[0155] Referring back to Figure 11, when the predetermined compensation mode in operation S120 is not the boundary region compensation mode (e.g., when the predetermined compensation mode is the normal compensation mode), the drive controller 100 can calculate the stress index SI (operation S140). The stress index SI can be determined based on a first frequency of the first display area DA1 and a second frequency of the second display area DA2. In an embodiment, the stress index SI can be calculated based on the ratio between the first frequency and the second frequency (e.g., (first frequency) / (second frequency)). For example, when the first frequency is 120 Hz and the second frequency is 1 Hz, the stress index can be 120. The drive controller 100 can determine the compensation mode based on the stress index SI.

[0156] Table 1 shows examples of stress index SI and compensation modes based on the first and second frequencies.

[0157] [Table 1]

[0158] When the stress index SI is greater than or equal to 1 and less than 30 ("Yes" in operation S150), the drive controller 100 can operate in the first compensation mode (operation S160).

[0159] When the stress index SI is greater than or equal to 30 and less than 60 ("Yes" in operation S170), the drive controller 100 can operate in the second compensation mode (operation S180).

[0160] When the stress index SI is greater than or equal to 60 (No in operation S170), the drive controller 100 can operate in the third compensation mode (operation S190).

[0161] Figure 13 is a graph showing the voltage levels of the bias voltage Vbias during a first compensation mode, a second compensation mode, and a third compensation mode according to one or more embodiments of the present disclosure.

[0162] Referring to Figures 12 and 13, during single-frequency mode (SFM), the bias voltage Vbias can have a default bias voltage level Vs.

[0163] When driving the first display area DA1 in multi-frequency mode MFM, the bias voltage Vbias can have the default bias voltage level Vs.

[0164] When the second display area DA2 is driven in the first compensation mode of the multi-frequency mode MFM, the bias voltage Vbias can have a first compensation voltage level Vs1.

[0165] When the second display area DA2 is driven in the second compensation mode of the multi-frequency mode MFM, the bias voltage Vbias can have the second compensation voltage level Vs2.

[0166] When driving the second display area DA2 in the third compensation mode of the multi-frequency mode MFM, the bias voltage Vbias can have a third compensation voltage level Vs3.

[0167] In other words, when driving the second display area DA2 in multi-frequency mode MFM, the greater the difference (or stress index SI) between the first frequency of the first display area DA1 and the second frequency of the second display area DA2, the higher the bias voltage Vbias for the second display area DA2 under multi-frequency mode MFM. Therefore, the brightness deviation based on the difference between the first frequency of the first display area DA1 and the second frequency of the second display area DA2 can be minimized.

[0168] Figure 14 is a graph showing the voltage levels of the bias voltage Vbias according to the operating mode of one or more embodiments of the present disclosure.

[0169] Referring to Figure 14, during single-frequency mode (SFM), the bias voltage Vbias can have a default bias voltage level Vs.

[0170] In multi-frequency mode (MFM), the first display area DA1 can be divided into a non-boundary area NBR1 and a boundary area BR1 adjacent to the non-boundary area NBR1 of the first display area DA1 and the second display area DA2. The boundary area BR1 of the first display area DA1 can be located between the non-boundary area NBR1 of the first display area DA1 and the second display area DA2. When the boundary area BR1 within the first display area DA1 is driven, the bias voltage Vbias gradually decreases from the default bias voltage level Vs to the eleventh voltage level V11, the twelfth voltage level V12, the thirteenth voltage level V13, and the fourteenth voltage level V14.

[0171] When driving the second display area DA2 in multi-frequency mode MFM, the bias voltage Vbias can have the default bias voltage level Vs.

[0172] If the bias voltage Vbias is not controlled in the boundary region BR1 between the non-boundary region NBR1 of the first display area DA1 and the second display area DA2, the brightness deviation between the first display area DA1 and the second display area DA2 may be clearly visible to the user in the portion adjacent to the non-boundary region NBR1 of the first display area DA1 and the second display area DA2. When driving the boundary region BR1 in the first display area DA1 adjacent to the second display area DA2, the stress level of the first transistor T1 (see Figure 5) in the pixel PX (see Figure 5) can be reduced by gradually decreasing the bias voltage Vbias. Therefore, the brightness deviation in the portion adjacent to the non-boundary region NBR1 of the first display area DA1 and the second display area DA2 can be minimized.

[0173] Figure 15 is a graph showing the voltage levels of the bias voltage Vbias according to an operating mode in one or more embodiments of the present disclosure.

[0174] Referring to Figure 15, during single-frequency mode (SFM), the bias voltage Vbias can have a default bias voltage level Vs.

[0175] In Multi-Frequency Mode (MFM), the first display area DA1 can be divided into a non-boundary area NBR1 and a boundary area BR1 adjacent to the non-boundary area NBR1 of the first display area DA1 and the second display area DA2. The boundary area BR1 of the first display area DA1 can be located between the non-boundary area NBR1 of the first display area DA1 and the second display area DA2. When driving the boundary area BR1 in the first display area DA1, the bias voltage Vbias can be gradually reduced from the default bias voltage level Vs.

[0176] In multi-frequency mode MFM, the second display area DA2 can be divided into a non-boundary area NBR2 and a boundary area BR2 adjacent to both the second display area DA2 and the first display area DA1. The boundary area BR2 of the second display area DA2 lies between the non-boundary area NBR2 and the first display area DA1. When driving the boundary area BR2 adjacent to the first display area DA1 within the second display area DA2 in multi-frequency mode MFM, the bias voltage Vbias can be gradually reduced from the default bias voltage level Vs. Therefore, the brightness deviation in the boundary areas BR1 and BR2 can be minimized.

[0177] When driving the non-boundary area NBR2 of the second display area DA2, the bias voltage Vbias can gradually increase again and then return to the default bias voltage level Vs. When driving the second display area DA2 ends and the first display area DA1 is driven again, the bias voltage Vbias can return to the default bias voltage level Vs. Therefore, display quality degradation caused by rapid changes in the bias voltage Vbias can be prevented.

[0178] Figure 16 is a flowchart illustrating the operation of a drive controller 100 in an electronic device ED according to one or more embodiments of the present disclosure.

[0179] Referring to Figures 4 and 16, the drive controller 100 can determine the operating mode (operation S300) based on the image signal RGB and the control signal CTRL.

[0180] In one embodiment, the drive controller 100 may determine the operating mode based on mode information included in the control signal CTRL. In another embodiment, the drive controller 100 may determine the operating mode based on the pattern of the image signal RGB.

[0181] When the determined operating mode is multi-frequency mode, the drive controller 100 can confirm the first frequency of the first display area DA1, the second frequency of the second display area DA2, and the starting position of the second display area DA2 (operation S310).

[0182] When the determined operating mode is not multi-frequency mode, the drive controller 100 can operate in single-frequency mode (operation S400).

[0183] In multi-frequency mode, the drive controller 100 can operate in a compensation mode used to compensate for the brightness difference between the first display area DA1 and the second display area DA2. In an embodiment, the compensation mode can be a boundary area compensation mode.

[0184] The drive controller 100 can calculate the stress index SI (operation S320). The stress index SI can be determined based on a first frequency of the first display area DA1 and a second frequency of the second display area DA2. In an embodiment, the stress index SI can be calculated based on the ratio between the first frequency and the second frequency (e.g., (first frequency) / (second frequency)). For example, when the first frequency is 120 Hz and the second frequency is 1 Hz, the stress index can be 120. The drive controller 100 can determine the boundary region compensation mode based on the stress index SI.

[0185] Table 2 shows examples of stress index SI and boundary region compensation modes based on the first and second frequencies.

[0186] [Table 2]

[0187] When the stress index SI is greater than or equal to 1 and less than 30 ("Yes" in operation S330), the drive controller 100 can operate in the first boundary region compensation mode (operation S340).

[0188] When the stress index SI is greater than or equal to 30 and less than 60 ("Yes" in operation S350), the drive controller 100 can operate in the second boundary region compensation mode (operation S360).

[0189] When the stress index SI is greater than or equal to 60 (No in operation S350), the drive controller 100 can operate in the third boundary region compensation mode (operation S370).

[0190] Figure 17 is a graph showing the voltage levels of the bias voltage Vbias according to the operating mode of one or more embodiments of the present disclosure.

[0191] Referring to Figures 16 and 17, when the first display area DA1 is driven in boundary area compensation mode, the bias voltage Vbias can have a default bias voltage level Vs.

[0192] During the first boundary region compensation mode, the second display region DA2 may include a boundary region BRa and a non-boundary region NBRa. The boundary region BRa of the second display region DA2 may be between the non-boundary region NBRa of the second display region DA2 and the first display region DA1. When the boundary region BRa within the second display region DA2 is driven in the first boundary region compensation mode, the bias voltage Vbias may gradually decrease from the eleventh voltage level Vm11. In the non-boundary region NBRa, the bias voltage Vbias may have the same default bias voltage level Vs, which is the level of the bias voltage Vbias applied when driving the first display region DA1.

[0193] During the second boundary region compensation mode, the second display region DA2 may include a boundary region BRb and a non-boundary region NBRb. The boundary region BRb of the second display region DA2 may be between the non-boundary region NBRb of the second display region DA2 and the first display region DA1. When driving the boundary region BRb within the second display region DA2 in the second boundary region compensation mode, the bias voltage Vbias may gradually decrease from the twelfth voltage level Vm12. In the non-boundary region NBRb, the bias voltage Vbias may have the same default bias voltage level Vs, which is the level of the bias voltage Vbias applied when driving the first display region DA1.

[0194] During the third boundary region compensation mode, the second display region DA2 may include a boundary region BRc and a non-boundary region NBRc. The boundary region BRc of the second display region DA2 may be between the non-boundary region NBRc of the second display region DA2 and the first display region DA1. When driving the boundary region BRc within the second display region DA2 in the third boundary region compensation mode, the bias voltage Vbias may gradually decrease from the thirteenth voltage level Vm13. In the non-boundary region NBRc, the bias voltage Vbias may have the same default bias voltage level Vs, which is the level of the bias voltage Vbias applied when driving the first display region DA1.

[0195] The eleventh voltage level Vm11, the twelfth voltage level Vm12, and the thirteenth voltage level Vm13 may have a relationship of "Vm11 < Vm12 < Vm13".

[0196] That is, as the difference between the first frequency of the first display region DA1 and the second frequency of the second display region DA2 becomes larger, in the boundary region, the highest voltage level to which the bias voltage Vbias is controlled to change can be higher. Therefore, the luminance deviation between the first display region DA1 and the second display region DA2 can be minimized.

[0197] Although only the first boundary region compensation mode to the third boundary region compensation mode are shown and described in FIGS. 16 and 17, the present disclosure is not limited thereto. The number of boundary region compensation modes may be changed according to the stress index SI.

[0198] FIG. 18 is a diagram showing a second initialization voltage VAINT according to an operation mode according to one or more embodiments of the present disclosure.

[0199] Referring to Figures 4 and 18, during single-frequency mode (SFM), the second initialization voltage VAINT can have a default initialization voltage level Va. When driving the first display area DA1 in multi-frequency mode, the second initialization voltage VAINT can also have a default initialization voltage level Va.

[0200] When driving the second display area DA2 in multi-frequency mode, the second initialization voltage VAINT can have a compensated initialization voltage level. The compensated initialization voltage level can be gradually increased from the minimum initialization voltage level Vam.

[0201] In the example shown in Figure 10, the second frequency of the second display area DA2 can be lower than the first frequency of the first display area DA1. When the operating mode of the electronic device ED changes from multi-frequency mode (MFM) to single-frequency mode (SFM), the brightness of the second display area DA2 may be brighter than the brightness of the first display area DA1. Specifically, the greater the difference between the first and second frequencies, the greater the brightness deviation between the first display area DA1 and the second display area DA2 may be.

[0202] As shown in Figure 5, because the second initialization voltage VAINT in pixel PX is low, the voltage level of the anode of the light-emitting element LD can be reduced, thus delaying the emission of light from the light-emitting element LD. Therefore, when driving the second display area DA2, the voltage level of the second initialization voltage VAINT can be reduced to minimize the brightness deviation between the first display area DA1 and the second display area DA2.

[0203] Figure 19 is a diagram illustrating the second initialization voltage VAINT according to an operating mode of one or more embodiments of the present disclosure.

[0204] Referring to Figures 4 and 19, during single-frequency mode (SFM), the second initialization voltage VAINT can have a default initialization voltage level Va. When driving the first display area DA1 in multi-frequency mode, the second initialization voltage VAINT can also have a default initialization voltage level Va.

[0205] When driving the second display area DA2 in multi-frequency mode, the second initialization voltage VAINT can have one of the first initialization voltage level Va1, the second initialization voltage level Va2, and the third initialization voltage level Va3.

[0206] In an embodiment, as the difference (or stress index) between the first frequency of the first display area DA1 and the second frequency of the second display area DA2 increases, the voltage level of the second initialization voltage VAINT in the second display area DA2 can decrease more significantly.

[0207] In the example shown in Figure 10, the second frequency of the second display area DA2 may be lower than the first frequency of the first display area DA1. When the operating mode of the electronic device ED changes from multi-frequency mode (MFM) to single-frequency mode (SFM), the brightness of the second display area DA2 may be brighter than the brightness of the first display area DA1. Specifically, the greater the difference between the first and second frequencies, the greater the brightness deviation between the first display area DA1 and the second display area DA2 may be.

[0208] As shown in Figure 5, because the second initialization voltage VAINT in pixel PX is low, the voltage level of the anode of the light-emitting element LD can be reduced, thus delaying the emission of light from the light-emitting element LD. Therefore, when driving the second display area DA2, the voltage level of the second initialization voltage VAINT can be reduced to minimize the brightness deviation between the first display area DA1 and the second display area DA2.

[0209] Figure 20 is a graph illustrating the bias voltage Vbias according to an operating mode of one or more embodiments of the present disclosure.

[0210] Referring to Figures 4 and 20, during single-frequency mode (SFM), the bias voltage Vbias can have a default bias voltage level Vs. In multi-frequency mode, the display area DA (refer to Figure 1) can be divided into a first display area DA1, a second display area DA2, and a third display area DA3. In this embodiment, it is assumed that the first frequency of the first display area DA1, the second frequency of the second display area DA2, and the third frequency of the third display area DA3 have a relationship of "first frequency > second frequency > third frequency".

[0211] When driving the first display area DA1 in multi-frequency mode, the bias voltage Vbias can have a default bias voltage level Vs. When driving the second display area DA2 in multi-frequency mode, the bias voltage Vbias can gradually decrease from the twenty-first voltage level Vm21. When driving the third display area DA3 in multi-frequency mode, the bias voltage Vbias can gradually decrease from the twenty-second voltage level Vm22. The difference between the first frequency and the third frequency can be greater than the difference between the first frequency and the second frequency, and therefore the twenty-second voltage level Vm22 can be higher than the twenty-first voltage level Vm21. Therefore, the brightness deviation between the first display area DA1 and the second display area DA2, as well as the brightness deviation between the second display area DA2 and the third display area DA3, can be minimized.

[0212] Figure 21 is a graph illustrating the bias voltage Vbias according to an operating mode of one or more embodiments of the present disclosure.

[0213] Referring to Figures 4 and 21, during single-frequency mode (SFM), the bias voltage Vbias can have a default bias voltage level Vs. In multi-frequency mode, the display area DA (refer to Figure 1) can be divided into a first display area DA1, a second display area DA2, and a third display area DA3. In this embodiment, it is assumed that the first frequency of the first display area DA1, the second frequency of the second display area DA2, and the third frequency of the third display area DA3 have a relationship of "first frequency > second frequency > third frequency".

[0214] When driving the first display area DA1 in multi-frequency mode, the bias voltage Vbias can have a default bias voltage level Vs. When driving the second display area DA2 in multi-frequency mode, the bias voltage Vbias can have a twenty-first voltage level Vs21. When driving the third display area DA3 in multi-frequency mode, the bias voltage Vbias can have a twenty-second voltage level Vs22. The difference between the first frequency and the third frequency can be greater than the difference between the first frequency and the second frequency, and therefore the twenty-second voltage level Vs22 can be higher than the twenty-first voltage level Vs21. Therefore, the brightness deviation between the first display area DA1 and the second display area DA2, and the brightness deviation between the second display area DA2 and the third display area DA3, can be minimized.

[0215] Figure 22 is a block diagram illustrating some components of an electronic device ED according to one or more embodiments of the present disclosure.

[0216] Referring to FIG22, the electronic device ED may include at least one processor AP and a drive controller 100. The at least one processor AP may provide the drive controller 100 with image signals RGB, control signals CTRL, and mode signals MD.

[0217] The drive controller 100 can determine the operating mode of the electronic device ED based on the mode signal MD. The operating mode may include a single-frequency mode and a multi-frequency mode. In an embodiment, the multi-frequency mode may include a boundary region compensation mode and a normal compensation mode. The operation of the electronic device ED according to the operating mode can be as described in Figures 5 to 21.

[0218] An electronic device according to one or more embodiments of the present disclosure can be configured to operate in a multi-frequency mode, driving a first display area at a first frequency and driving a second display area at a second frequency. In the multi-frequency mode, the bias voltage provided to the pixels of the first display area can be at a first voltage level, and the bias voltage provided to the pixels of the second display area can be at a second voltage level different from the first voltage level. Therefore, in the multi-frequency mode, the brightness deviation between the first display area and the second display area caused by the frequency difference between the first frequency and the second frequency can be compensated.

[0219] Although described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to this disclosure without departing from the spirit and scope of the disclosure as set forth in the claims. Furthermore, the embodiments of this disclosure are not intended to limit the technical spirit of the disclosure. All technical spirit within the scope of the claims and all their equivalents should be construed as being included within the scope of this disclosure.

[0220] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the claims and their equivalents.

Claims

1. An electronic device, the electronic device comprising: The display panel includes pixels; the drive controller is configured to receive input image signals and control signals, and is also configured to output voltage control signals; The system also includes a voltage generator configured to generate a bias voltage based on the voltage control signal, wherein the pixel comprises: a first transistor including a first electrode, a second electrode, and a gate electrode; and a second transistor including a first electrode connected to the first electrode of the first transistor, a second electrode connected to a bias voltage line receiving the bias voltage, and a gate electrode, wherein the drive controller is configured to: in a multi-frequency mode, control to drive a first display area of ​​the display panel at a first frequency, and drive a second display area of ​​the display panel at a second frequency different from the first frequency, and wherein the drive controller is further configured to: in the multi-frequency mode, output the voltage control signal such that the bias voltage has a first bias voltage level based on driving the first display area, and the bias voltage has a second voltage level different from the first bias voltage level based on driving the second display area.

2. The electronic device according to claim 1, wherein, The second frequency is lower than the first frequency, and the second voltage level is higher than the first bias voltage level.

3. The electronic device according to claim 2, wherein, In the multi-frequency mode, the second display area of ​​the display panel includes a boundary area adjacent to the first display area and a non-boundary area adjacent to the boundary area.

4. The electronic device according to claim 3, wherein, The first bias voltage level corresponds to the default bias voltage level, and the voltage generator is further configured to: gradually reduce the bias voltage from the second voltage level to the default bias voltage level based on the boundary region of the second display area driven in the multi-frequency mode.

5. The electronic device according to claim 2, wherein, The voltage generator is further configured to: determine the second voltage level of the bias voltage based on a stress index according to the ratio between the first frequency and the second frequency, based on driving the second display area in the multi-frequency mode.

6. The electronic device according to claim 5, wherein, The voltage generator is further configured to: determine the second voltage level as having a first compensation voltage level based on the stress index being a first value, and determine the second voltage level as having a second compensation voltage level higher than the first compensation voltage level based on the stress index being a second value greater than the first value.

7. The electronic device according to claim 2, wherein, The first bias voltage level corresponds to the default bias voltage level. In the multi-frequency mode, the first display area includes a first boundary area adjacent to the second display area and a first non-boundary area adjacent to the first boundary area. The voltage generator is further configured to gradually reduce the bias voltage from the default bias voltage level based on driving the first boundary area.

8. The electronic device according to claim 1, wherein, The pixel further includes: a light-emitting element, including an anode and a cathode; and a third transistor, including a first electrode connected to the anode of the light-emitting element, a second electrode connected to an initialization voltage line receiving an initialization voltage, and a gate electrode, wherein the voltage generator is further configured to generate the initialization voltage based on the voltage control signal.

9. The electronic device according to claim 8, wherein, The drive controller is further configured to output the voltage control signal such that, in the multi-frequency mode, the initialization voltage has a default initialization voltage level based on driving the first display area, and the initialization voltage has a compensated initialization voltage level lower than the default initialization voltage level based on driving the second display area.

10. The electronic device according to claim 9, wherein, The voltage generator is further configured to: based on driving a boundary region adjacent to the first display region within the second display region in the multi-frequency mode, gradually increase the initialization voltage from the compensated initialization voltage level to the default initialization voltage level.

11. The electronic device according to claim 9, wherein, The voltage generator is further configured to: determine the compensated initialization voltage level of the initialization voltage based on the stress index of the ratio between the first frequency and the second frequency, based on driving the second display area in the multi-frequency mode.

12. The electronic device according to claim 11, wherein, The voltage generator is further configured to: determine the compensation initialization voltage level as having a first compensation initialization voltage level based on the stress index being a first value, and determine the compensation initialization voltage level as having a second compensation initialization voltage level lower than the first compensation initialization voltage level based on the stress index being a second value greater than the first value.

13. The electronic device according to claim 1, further comprising: At least one processor is configured to provide the input image signal, the control signal, and the mode signal, wherein the drive controller is further configured to determine an operating mode based on the mode signal, the operating mode including a single-frequency mode and the multi-frequency mode.

14. A method of driving an electronic device including a display panel, the display panel including pixels, each pixel including a first transistor and a second transistor connected between a first electrode of the first transistor and a bias voltage line receiving a bias voltage, the method comprising: In multi-frequency mode, the first frequency of the first display area of ​​the display panel, the second frequency of the second display area of ​​the display panel, and the starting position of the second display area are confirmed. Determine whether the operation mode is the boundary area compensation mode; The method involves controlling the voltage level of the bias voltage based on determining that the operating mode is the boundary region compensation mode, wherein the step of controlling the voltage level of the bias voltage includes: controlling the bias voltage to have a first bias voltage level based on driving the first display area in the multi-frequency mode; and controlling the bias voltage to have a second voltage level different from the first bias voltage level based on driving a boundary region adjacent to the first display area within the second display area in the multi-frequency mode.

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