Pixel driving circuit, layout structure, display panel and pixel driving method

Abstract

The invention discloses a pixel driving circuit, a layout structure, a display panel and a pixel driving method. The pixel driving circuit comprises a constant current power supply unit used for providing constant current; the driving control unit is connected between the constant-current power supply unit and the light-emitting element and is used for providing constant current for the light-emitting element; the scanning control unit is used for writing data voltage into a storage node between the scanning control unit and the driving control unit; and a potential modulation unit for superimposing a time-varying signal to the storage node, in which, if the voltage on the storage node exceeds a predetermined range, the driving control unit is turned off to stop providing the constant current to the light emitting element. The pixel driving circuit is based on a 3T1C extremely simple circuit topology, the light emitting duration of the light emitting element is controlled by using analog data voltage, data is displayed while being written, and the pixel driving circuit has the advantages of being small in circuit area, low in cost, good in display effect, free of frame delay and the like.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and more specifically, to a pixel driving circuit, layout structure, display panel, and pixel driving method. Background Technology

[0002] With the development of technology, self-emissive display technology has been gradually applied to various fields, such as smartphones, automotive dashboards, augmented reality / virtual reality (AR / VR) near-eye devices, and wearable medical monitoring.

[0003] Based on grayscale writing methods, existing self-emissive display technologies can be broadly categorized into two types: one is the Memory-in-Pixel (MIP) scheme, which integrates Static Random Access Memory (SRAM) or a counter within the pixel, using digital pulse width modulation (PWM) to control the emissivity duration; the other is the traditional PWM scheme, which directly writes data voltage / current into the gate of the driver transistor, using the voltage-current continuity relationship to adjust brightness. The former requires a large pixel area to store storage and logic units, while the latter requires integrating a frame buffer of equal size to the resolution on the driver IC, resulting in high dynamic power consumption.

[0004] Furthermore, both of these solutions rely on a "cache before display" frame queue mechanism, introducing at least one frame delay. In AR / VR scenarios, this delay directly amplifies the time difference between head movement and the screen, inducing dizziness and becoming a bottleneck restricting the immersive experience.

[0005] Therefore, the industry urgently needs a driving architecture that can break through the pixel area limit, eliminate frame buffer overhead, and achieve zero frame latency to meet the needs of micro-displays and ultra-low latency. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide a pixel driving circuit, layout structure, display panel and pixel driving method, so as to reduce the pixel circuit area and reduce the cost of driving chip while ensuring good display effect.

[0007] According to a first aspect of the present invention, a pixel driving circuit is provided, comprising: A constant current power supply unit is used to provide a constant current. A drive control unit, connected between the constant current power supply unit and the light-emitting element, is used to provide the constant current to the light-emitting element; The scan control unit is configured to write data voltage to the storage node between the scan control unit and the drive control unit; and A potential modulation unit is used to superimpose time-varying signals onto the storage node. If the voltage on the storage node exceeds a predetermined range, the drive control unit is turned off to stop providing the constant current to the light-emitting element.

[0008] Optionally, the constant current power supply unit includes a first transistor, the source of which is connected to a high-potential power supply, and a control terminal receiving a bias voltage. The difference between the high-potential power supply and the bias voltage is greater than the absolute value of the threshold voltage of the first transistor, so that the first transistor operates in the saturation region to output a constant current at its drain.

[0009] Optionally, it further includes: a bias modulation unit for providing the bias voltage to the first transistor. The bias voltage includes a compensation component that is synchronized with the time-varying signal. When the conduction state of the drive control unit changes, causing a change in the drain potential of the first transistor, the compensation component reversely adjusts the gate-source voltage of the first transistor to counteract the channel length modulation effect and keep the constant current stable.

[0010] Optionally, the constant current power supply unit further includes a high-impedance element connected in series between the gate of the first transistor and the bias voltage, wherein the gate and drain of the first transistor have a coupling capacitance. When the drive control unit is turned off, causing a potential step change at the drain of the first transistor, the potential step change is coupled to the gate of the first transistor through the coupling capacitor, instantaneously reducing the gate-source voltage of the first transistor, thereby suppressing the constant current, and gradually restoring the constant current through the high-impedance element.

[0011] Optionally, the drive control unit includes a second switching transistor, the source of which is connected to the constant current power supply unit to receive the constant current, the drain of which is connected to the light-emitting element to provide the constant current, and the gate of which is connected to the memory node.

[0012] Optionally, the voltage value of the time-varying signal increases or decreases linearly with time, or the voltage value of the time-varying signal increases or decreases non-linearly with time, or the voltage value of the time-varying signal remains within the predetermined range during a predetermined time period and exceeds the predetermined range outside the predetermined time period.

[0013] Optionally, the parasitic capacitance between the gate and source of the second switch forms a positive feedback path. When the second switch changes from being turned on to being turned off, causing a change in its source potential, the change in source potential is fed back to its gate through the parasitic capacitance to accelerate the turn-off process.

[0014] Optionally, the potential modulation unit includes a capacitor element for coupling an external time-varying signal to the storage node. The capacitor element is selected from any of the following or a combination capacitor formed by connecting any two or more of the following structures in parallel: metal-oxide-metal parallel plate capacitor, metal-insulator-metal multilayer capacitor, polysilicon-insulator-polysilicon capacitor, gate oxide capacitor, PN junction capacitor or metal oxide semiconductor varactor structure.

[0015] According to a second aspect of the present invention, a layout structure is provided for forming at least a portion of the pixel driving circuit as described above, wherein the constant current power supply unit includes a first transistor, the active region of the first transistor is arranged in a folded layout to extend the channel length; or, the gate region and the drain region of the first transistor have overlapping areas to enhance drain-gate feedback coupling. The drive control unit includes a second switching transistor, the source of which is connected to the constant current power supply unit to receive the constant current, the drain of which is connected to the light-emitting element to provide the constant current, and the gate of which is connected to the memory node. The source metal layer of the second switching transistor is connected between the constant current power supply unit and the drive control unit. The source metal layer is configured with a geometry that surrounds or covers the gate region to increase the parasitic capacitance between the gate and the source.

[0016] According to a third aspect of the present invention, a display panel is provided, comprising: Multiple light-emitting elements; and Multiple pixel driving circuits as described above are used to drive the multiple light-emitting elements.

[0017] According to a fourth aspect of the present invention, a pixel driving method is provided, comprising: A data voltage is written to the storage node to conduct a constant current to the light-emitting element, causing the light-emitting element to start emitting light; A time-varying signal is superimposed on the storage node to control the light-emitting time of the light-emitting element; If the voltage on the storage node exceeds a predetermined range, the path of the constant current to the light-emitting element is shut off to stop supplying the constant current to the light-emitting element.

[0018] Optionally, the constant current is provided using a first transistor connected to a high-potential power supply. The gate of the first transistor receives a bias voltage, which includes a compensation component synchronized with the time-varying signal. When the conduction state of the drive control unit changes, causing a change in the drain potential of the first transistor, the compensation component reversely adjusts the gate-source voltage of the first transistor to counteract the channel length modulation effect and keep the constant current stable.

[0019] Optionally, when the path of the constant current to the light-emitting element is turned off, causing a potential step change at the drain of the first transistor, the potential step change is coupled to the gate of the first transistor through the coupling capacitance between the gate and the drain of the first transistor, instantaneously reducing the gate-source voltage of the first transistor, thereby suppressing the constant current, and gradually restoring the constant current through a high-impedance element connected in series between the gate of the first transistor and the bias voltage.

[0020] Optionally, the path of the constant current to the light-emitting element is turned on or off using the second switch. The parasitic capacitance between the gate and source of the second switch forms a positive feedback path. When the second switch changes from being turned on to being turned off, causing a change in its source potential, the change in source potential is fed back to its gate through the parasitic capacitance to accelerate the turn-off process.

[0021] Optionally, the voltage value of the time-varying signal increases or decreases linearly with time, or the voltage value of the time-varying signal increases or decreases non-linearly with time, or the voltage value of the time-varying signal remains within the predetermined range during a predetermined time period and exceeds the predetermined range outside the predetermined time period.

[0022] Optionally, the pixel driving method drives multiple light-emitting elements located in the display panel respectively. The time-varying signal is provided row by row, and the multiple light-emitting elements emit light row by row; or The time-varying signal is provided frame by frame, and the multiple light-emitting elements emit light frame by frame.

[0023] The pixel driving circuit, layout structure, display panel, and pixel driving method provided by this invention are based on a simplified 3T1C circuit topology and use analog data voltage to control the light-emitting duration of the light-emitting element. During the data writing phase, only the initial potential of the storage node is determined; the light-emitting duration is automatically turned off by an external time-varying signal coupled to the storage node, thus achieving grayscale in an analog manner. Since multi-bit memory, counters, or high-precision current mirrors are not required, the number of switches in the pixel driving circuit can be reduced to three, significantly reducing the circuit area compared to traditional digital PWM schemes. This circuit structure can maintain brightness uniformity within a very short row charging time and significantly reduce dynamic power consumption, meeting the comprehensive requirements of high-resolution, high-refresh-rate micro-displays for small size, low power consumption, and low cost. Furthermore, the data voltage is immediately converted into light-emitting pulses after row scanning, achieving a zero-frame latency effect of "data written and displayed instantly."

[0024] In some optional embodiments, the present invention utilizes the gate-source parasitic capacitance of the driving transistor itself as a positive feedback path. When the second switching transistor is turned off, it feeds the source potential back to the gate to form a bootstrap cutoff, which significantly sharpens the current falling edge and effectively suppresses the ghosting caused by the residual charge of the light-emitting element.

[0025] In some optional embodiments, the first transistor of the present invention is biased in the saturation region, with its gate connected to a bias voltage, its source connected to a high-potential power supply, and its drain outputting a constant current. Since the voltage difference between the bias voltage and the high-potential power supply is set to be greater than the absolute value of the first transistor's threshold voltage and remains constant, the drain current of the first transistor is controlled only by the gate-source voltage and is almost independent of changes in the drain potential. Therefore, when the second switch switches between on and off, causing a jump in its source voltage, fluctuations in the constant current provided by the first transistor are suppressed to a very small range, ensuring that the light-emitting element obtains a stable current amplitude throughout the entire light-emitting phase, fundamentally avoiding uneven brightness and color shift caused by current drift.

[0026] In some alternative embodiments, the capacitor element in the potential modulation unit is formed by parallel connection of a metal edge overlap structure and a metal insulator stack, both of which share the back-end interconnect process without increasing the photolithography layers; sufficient coupling can be obtained within a small footprint, so that the ramp signal can be completely injected into the memory node. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 A block diagram of a pixel driving circuit according to an embodiment of the present invention is shown; Figure 2 A circuit diagram of a pixel driving circuit according to an embodiment of the present invention is shown; Figure 3a A timing diagram of a pixel driving circuit according to a first embodiment of the present invention is shown; Figure 3b A timing diagram of a pixel driving circuit according to a second embodiment of the present invention is shown; Figure 4 A flowchart of a pixel-driving method according to an embodiment of the present invention is shown. Detailed Implementation

[0028] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0029] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0030] It should be understood that the connection / coupling of A and B in the embodiments of this application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices. The embodiments of this application do not limit this.

[0031] The embodiments of the filtering device provided in this application will now be described with reference to the accompanying drawings.

[0032] Figure 1 A block diagram of a pixel driving circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the pixel driving circuit 100 includes a constant current power supply unit 110, a driving control unit 120, a scanning control unit 130, and a potential modulation unit 140. The pixel driving circuit 100 drives the light-emitting element 200. By sampling the data voltage Vdata, it controls the conduction duration of the constant current flowing through the light-emitting element 200 in a time-width manner during the light-emitting phase, thereby achieving adjustable grayscale light-emitting display.

[0033] The constant current power supply unit 110 is used to provide a constant current with stable amplitude at the intermediate node NodeX. In some embodiments, the constant current power supply unit 110 includes a first transistor whose source is connected to a high-potential power supply. A control terminal receives a bias voltage, and the difference between the high-potential power supply and the bias voltage is greater than the absolute value of the threshold voltage of the first transistor, causing the first transistor to operate in the saturation region to output a highly stable constant current at its drain. In other embodiments, the constant current power supply unit 110 may also employ a cascode current mirror, a self-biased reference, a thick-oxygen high-voltage transistor structure, or other constant current source structures to achieve higher output impedance at the same or similar area cost, further suppressing power supply disturbances and temperature drift, ensuring constant current stability, and maintaining a smaller circuit layout area.

[0034] The drive control unit 120 is connected to the constant current power supply unit 110 to receive a constant current. It is controlled by the potential of the storage node Nstore to determine whether to introduce the constant current into the light-emitting element 200 according to the potential of the storage node Nstore, thereby controlling the light-emitting time of the light-emitting element 200.

[0035] In some embodiments, the drive control unit 120 includes a second switch transistor. The source of the second switch transistor is connected to the constant current power supply unit 110 to receive a constant current, the drain is connected to the light-emitting element 200 to provide a constant current, and the gate is connected to the memory node Nstore. When the potential of the memory node Nstore is within a predetermined range, the second switch transistor is turned on, and the constant current provided by the constant current power supply unit 110 flows into the light-emitting element 200 through the second switch transistor, causing it to emit light. When the potential of the memory node Nstore exceeds the predetermined range, the second switch transistor is turned off, the constant current is blocked, and the light-emitting element 200 stops emitting light, thereby achieving modulation of the light intensity in the time dimension.

[0036] In this embodiment of the invention, the voltage value of the time-varying signal Vtvs remains within a predetermined range during a predetermined time period and exceeds the predetermined range outside the predetermined time period. For example, the voltage value of the time-varying signal Vtvs may increase or decrease linearly with time, or it may increase or decrease non-linearly with time. Another example is that the time-varying signal Vtvs is a half-wave signal. Yet another example is that the time-varying signal Vtvs exceeds the predetermined range in a first time period, remains within the predetermined range in a second time period, and exceeds the predetermined range in a third time period, where the first, second, and third time periods are continuous time periods.

[0037] For example, if the second switch is implemented as a P-type switch, then the threshold voltage of the P-type switch is negative. The predetermined range is defined as the interval where the potential of the storage node Nstore is lower than this negative threshold voltage. Taking the time-varying signal Vtvs gradually increasing over time as an example, once the time-varying signal Vtvs continues to rise, causing the potential of the storage node Nstore to exceed the negative threshold voltage, i.e., exceeding the predetermined range, the P-type switch changes from the on state to the off state, thereby cutting off the constant current flowing to the light-emitting element 200. Taking the time-varying signal Vtvs gradually decreasing over time as an example, the initial voltage value of the time-varying signal Vtvs causes the second switch to turn off, cutting off the constant current flowing to the light-emitting element 200; once the time-varying signal Vtvs continues to decrease, causing the potential of the storage node Nstore to be less than or equal to the negative threshold voltage, i.e., entering the predetermined range, the P-type switch changes from the off state to the on state, thereby providing a constant current to the light-emitting element 200.

[0038] Accordingly, if the second switch is implemented as an N-type switch, then the threshold voltage of the N-type switch is positive. The predetermined range corresponds to the interval where the potential of the storage node Nstore is higher than this positive threshold voltage. Taking the time-varying signal Vtvs gradually decreasing over time as an example, when the time-varying signal Vtvs decreases and causes the potential of the storage node Nstore to fall below the positive threshold voltage, i.e., exceeding the predetermined range, the N-type switch changes from the on state to the off state, thereby cutting off the constant current flowing to the light-emitting element 200.

[0039] As an example, the voltage value of the time-varying signal Vtvs increases or decreases linearly with time. As another example, since the sensitivity of the human eye to light is not linear, to make the brightness of the light-emitting element 200 more consistent with the characteristic curve of the human eye, the voltage value of the time-varying signal Vtvs changes non-linearly with time. Specifically, the time-varying signal Vtvs is configured to rise at a slower slope in the initial stage of each frame period, causing the potential of the storage node Nstore to remain in the lower grayscale range for a longer time, thereby extending the conduction time of the second switch in the micro-conduction state; while in the mid-to-high grayscale region, the slope of the time-varying signal Vtvs gradually increases, causing the Nstore potential to quickly cross the threshold range of the second switch, shortening the duration of the corresponding brightness stage. Through the above non-linear time-voltage mapping, the pixel driving circuit, while maintaining the accuracy of digital PWM, corrects the actual photon output curve of the light-emitting element 200 to a perceptual linearity of approximately gamma 2.2, avoiding the visible color banding that occurs in the low grayscale stage due to excessive quantization steps in traditional linear ramps.

[0040] In a further example, the nonlinear time-varying signal Vtvs is generated by an on-chip ramp generator, which includes a counter, a nonlinear resistor string, and a buffer amplifier. The counter increments under a clock provided by the timing controller, and its output code value serves as a tap node in the address gating resistor string. The resistance values ​​of the resistor string are preset according to a gamma lookup table, so that the voltage difference between adjacent taps monotonically increases with address. The buffer amplifier performs impedance transformation on the selected tap voltage and outputs the time-varying signal Vtvs, ensuring that its driving capability is sufficient to charge and discharge the memory node Nstore within a very short setup time. By rewriting the lookup table coefficients in the field-programmable registers, the same driver chip can adapt to gamma values ​​in the range of 2.0 to 2.4, or quickly switch perception curves for different application scenarios such as VR and automotive, without modifying pixel-level hardware connections.

[0041] In other embodiments, the drive control unit 120 further includes a fourth switch, which forms a common-source, common-gate structure with the second switch. The source of the fourth switch is connected to the drain of the second switch, and the drain of the fourth switch is connected to the light-emitting element 200. The gate of the fourth switch receives a fixed bias voltage. This fixed bias voltage is set to be higher than the sum of the highest cathode potential of the light-emitting element 200 and the threshold voltage of the fourth switch, so that the fourth switch always operates in the saturation region throughout the light-emitting phase, thereby shielding the influence of voltage changes at the light-emitting element 200 on the drain potential of the second switch and maintaining the stability of the constant current.

[0042] The scan control unit 130 receives the data voltage Vdata at its input terminal and its output terminal is connected to the storage node Nstore. During the data writing phase, the scan control unit 130 is turned on, sampling the data voltage Vdata to the storage node Nstore.

[0043] Optionally, the scan control unit 130 includes a third switch transistor. The gate of the third switch transistor is connected to the scan signal Scan, the source receives the data voltage Vdata, and the drain is directly coupled to the memory node Nstore. When the scan signal Scan transitions to an active level, the third switch transistor is turned on, and the data voltage Vdata charges or discharges the memory node Nstore through its channel until the Nstore potential equals Vdata, completing the write operation. After the write operation is completed, Scan returns to an inactive level, the third switch transistor is turned off, and the memory node Nstore remains floating, maintaining the voltage just sampled, providing a stable gate control reference for subsequent light emission stages.

[0044] The input of the potential modulation unit 140 receives a time-varying signal Vtvs, and its output is connected to the storage node Nstore. During the light-emitting phase, the potential modulation unit 140 further superimposes the time-varying signal Vtvs onto the data voltage Vdata of the storage node Nstore. The time-varying signal Vtvs continuously adjusts the potential of the storage node Nstore until the drive control unit 120 is turned off, thereby corresponding grayscale information with a time domain width.

[0045] Optionally, the potential modulation unit 140 includes a capacitor element for coupling an external time-varying signal to the storage node. The capacitor element is selected from any of the following or a combination capacitor composed of any two or more of the following structures connected in parallel: metal-oxide-metal (MOM) parallel plate capacitor, metal-insulator-metal (MIM) multilayer capacitor, polysilicon-insulator-polysilicon (PIP) capacitor, gate oxide capacitor, PN junction capacitor, or metal-oxide-semiconductor (MOS) varactor structure. All of the above-mentioned capacitors can be implemented using existing layers in standard CMOS or LTPS backplane processes without additional photolithography layers, thus saving area while maintaining process compatibility. When using a combined capacitor scheme, different capacitor types complement each other in terms of voltage linearity, temperature coefficient, and capacitance per unit area, so that the total coupling capacitance remains relatively stable over a wide voltage swing and temperature range, ensuring that the time-varying signal Vtvs can accurately modulate the potential of the memory node Nstore according to the preset gamma curve.

[0046] There is a parasitic capacitance between the storage node Nstore and the intermediate node NodeX, which forms a positive feedback path. During the shutdown phase, the drive control unit 120 switches from on to off, causing a change in the potential of the intermediate node NodeX. This potential change is fed back to the storage node Nstore via the parasitic capacitance to further increase the potential of the storage node Nstore, thereby accelerating the shutdown process of the drive control unit 120.

[0047] Optionally, the pixel driving circuit further includes a sixth switch and a seventh switch. The first conducting terminal of the sixth switch is connected to the anode of the light-emitting element 200, and the first conducting terminal of the seventh switch is connected to the storage node Nstore. The second conducting terminals of the sixth and seventh switches are connected to the reference ground potential, and the control terminal receives a reset signal. When the drive control unit 120 stops providing a constant current to the light-emitting element 200, the timing controller sets the reset signal to an active level during the retrace period. The sixth and seventh switches are turned on, and the potential of the storage node Nstore and the anode potential of the light-emitting element 200 are quickly clamped to the reference ground potential to avoid residual charge from the previous frame causing ghosting or grayscale shift.

[0048] The light-emitting element 200 can be a self-emissive element such as an active matrix organic light-emitting diode (AMOLED), a micro light-emitting diode (Micro-LED), a mini light-emitting diode (Mini-LED), or a silicon-based organic light-emitting diode (Si-OLED).

[0049] Figure 2 A circuit diagram of a pixel driving circuit according to an embodiment of the present invention is shown.

[0050] like Figure 2 As shown, in the pixel driving circuit 100 of this embodiment, the constant current power supply unit includes a first transistor T1, the driving control unit includes a second switch T2, the scanning control unit includes a third switch T3, the potential modulation unit includes a capacitor C1, and the time-varying signal is a ramp signal Ramp that changes linearly with time.

[0051] The source of the first transistor T1 is connected to the high-potential power supply VDD, and its drain is connected to the intermediate node NodeX along with the source of the second switch T2. Its gate is connected to the bias voltage Vbias to form a constant current source. The drain of the second switch T2 is connected to the anode of the light-emitting element 200, and its gate is connected to the storage node Nstore. Its on / off state is determined by the Nstore potential, thereby sending the constant current to the light-emitting element 200. The gate of the third switch T3 is connected to the scan signal Scan, its source is connected to the data voltage Vdata, and its drain is directly connected to the storage node Nstore. When Scan is valid, Vdata is sampled into Nstore. The first plate of capacitor C1 is connected to the storage node Nstore, and the second plate is connected to the ramp signal Ramp. This is used to couple the ramp voltage of the ramp signal Ramp to Nstore during the light-emitting phase, thereby achieving PWM modulation of the conduction time of the second switch T2. The anode of the light-emitting element 200 is connected to the drain of the second switch T2, and its cathode is connected to the common voltage VCOM.

[0052] The first transistor T1 is the core component of the constant current power supply unit. In some embodiments, the gate of the first transistor T1 receives a fixed bias voltage. The difference between the high-potential power supply and the bias voltage is greater than the absolute value of the threshold voltage of the first transistor T1. Therefore, the voltage change of the intermediate node NodeX on the first transistor T1 is negligible, so as to provide a stable constant current.

[0053] In some embodiments, the pixel driving circuit 100 further includes a bias modulation unit (not shown) for providing a bias voltage to the first transistor T1. The bias voltage includes a compensation component synchronized with the ramp signal Ramp. When a change in the conduction state of the second switch T2 causes a change in the drain potential of the first transistor T1, the compensation component reversely adjusts the gate-source voltage of the first transistor T1 to counteract the channel length modulation effect, thus maintaining a stable constant current. For example, when the second switch T2 switches from off to on, the drain potential of the first transistor T1 decreases, the channel length increases, and the current tends to increase; at this time, the compensation component synchronously lowers the gate potential, causing the gate-source voltage to decrease and counteract the current increase. Conversely, when the second switch T2 switches from on to off, the drain potential rises, the channel length shortens, and the current tends to decrease; the compensation component synchronously raises the gate potential, causing the gate-source voltage to increase and counteract the current decrease. By real-time reverse adjustment of the gate-source voltage, the channel length modulation effect is continuously neutralized, the first transistor maintains a constant current output throughout the entire switching cycle, and the pixel brightness remains uniform.

[0054] Optionally, the bias voltage is connected to the gate of the first transistor T1 via a high-impedance element (not shown), and a coupling capacitor (not shown, which can be a transistor parasitic capacitance or an external capacitor) is further provided between the gate and drain of the first transistor T1. When the second switch T2 is suddenly turned off, the potential step change of the intermediate node NodeX due to the sudden interruption of current is instantaneously coupled to the gate through the coupling capacitor, causing the gate potential of the first transistor T1 to rise synchronously. Since the high-impedance element cannot discharge the coupled charge instantaneously, the gate-source voltage of the first transistor T1 is instantaneously reduced, the operating point moves from the subthreshold region to the deep cutoff region, and its output current decreases exponentially, forming a "self-braking" effect. This mechanism can suppress the tail current in a very short time (e.g., 10ns to 100ns), significantly shortening the waveform tail time under extremely low current conditions; after the coupled charge is slowly released through the high-impedance element, the gate automatically returns to the DC potential set by the bias voltage, and the first transistor T1 re-enters the constant current state, waiting for the next switching cycle.

[0055] The second switch T2 has a parasitic capacitance Cgs between its source and gate. This parasitic capacitance Cgs is formed by the vertical overlap of the gate polysilicon and source metal traces and the sidewall edge electric field. Its capacitance varies approximately linearly with the minimum linewidth and gate oxide thickness. During the data writing stage, when the third switch T3 is turned on and transmits the data voltage Vdata to the memory node Nstore, if the data voltage Vdata has a step relative to the potential of the intermediate node NodeX, the parasitic capacitance Cgs will introduce an offset ΔV proportional to the step amplitude on the memory node Nstore through the charge redistribution effect, causing the actual write potential to deviate from the target grayscale voltage. To suppress this offset, this embodiment keeps the bias voltage Vbias constant in timing within the write window and clamps the intermediate node NodeX to the high-potential power supply VDD through the low-impedance path of the first transistor T1, thereby limiting the charge injection path of Cgs to between the high-potential power supply VDD and the memory node Nstore, significantly reducing the impact of ΔV on the low grayscale consistency.

[0056] In this embodiment of the invention, the first transistor T1, the second switch T2, and the third switch T3 can all be N-type metal-oxide-semiconductor field-effect transistors (NMOS) or P-type metal-oxide-semiconductor field-effect transistors (PMOS). Furthermore, the first transistor T1 can also be a junction field-effect transistor (JFET) or an insulated gate bipolar transistor (IGBT), and the second switch T2 and the third switch T3 can also be bipolar junction transistors (BJTs), unijunction transistors (UJTs), or thin-film transistors (TFTs), which have both selection and isolation functions.

[0057] The present invention also provides a layout structure for forming, as shown in 1 or Figure 2 At least a portion of the pixel driving circuit shown. Figure 2 For example, the drive control unit includes a second switch T2. The source of the second switch T2 is connected to the constant current power supply unit to receive a constant current, the drain is connected to the light-emitting element 200 to provide a constant current, and the gate is connected to the storage node Nstore. The source metal layer of the second switch T2 is connected between the constant current power supply unit and the drive control unit. The source metal layer is set to a geometry that surrounds or covers the gate region (such as U-shaped, comb-shaped, or finger-shaped) to increase the parasitic capacitance between the gate and the source.

[0058] During the light-emitting stage, the parasitic capacitance Cgs also couples to the potential modulation unit: when the ramp signal Ramp rises or falls linearly, the parasitic capacitance Cgs and capacitor C1 form a series voltage divider network, causing the actual swing of the storage node Nstore to be less than the design value, thereby shortening or lengthening the conduction time of the second switch T2, resulting in brightness deviation. To compensate for this effect, the plate area of ​​capacitor C1 can be designed to be m times the estimated value of the parasitic capacitance Cgs in the layout structure, and the slope of the ramp signal Ramp can be finely adjusted by simulation after parasitic extraction, so that the net coupling of the storage node Nstore is kept within the error range from the ideal value; at the same time, a dummy poly strip is added to the outside of the gate of the second switch T2 to absorb the edge electric field and reduce the process fluctuation of the parasitic capacitance Cgs, thereby ensuring that the brightness uniformity of the panel meets the display driving specifications of the light-emitting element in different batches and temperatures.

[0059] The constant current power supply unit includes a first transistor T1, whose active region adopts a folded layout to extend the channel length to several times that of the original linear layout without increasing the unit area. The folded layout can be, for example, L-shaped or serpentine, meandering back and forth within a rectangular region where pixel aperture ratio is limited. Furthermore, the folded layout can be planar or three-dimensional. By extending the channel, the output current under the same bias voltage is proportionally reduced, directly meeting the low grayscale requirements. Simultaneously, the equivalent damping of drain-source voltage changes by the channel resistance is increased, intrinsically weakening the channel length modulation effect and thus improving the voltage tolerance of the constant current. Rounded corners are provided at the inner corners of the folded path to alleviate sharp electric field concentration and avoid long-term threshold drift caused by hot carrier injection.

[0060] As a supplement or alternative to the folded layout, the gate and drain regions of the first transistor have an artificially designed overlapping area. During the layout stage, the drain metal or diffusion region is extended outward along the channel width direction, so that it forms an overlapping area with the gate conductor on the vertical projection plane that is larger than the default process value, thereby constructing a controllable drain-gate parasitic capacitance. This overlapping capacitance works in conjunction with the compensation component provided by the subsequent bias modulation unit. When the drive control unit is momentarily turned off and the drain potential jumps, the overlapping capacitance couples the change to the gate, generating negative feedback in the same direction as the folded long channel effect, further compressing current overshoot. In the steady state stage, the overlapping capacitance is an open circuit to the DC high impedance element and does not affect the gate DC bias, thus not sacrificing the low current advantage brought by the folded long channel. Through the combined configuration of folded geometry and controllable overlapping capacitance, the constant current power supply unit simultaneously achieves low current, high impedance voltage modulation, and fast self-braking within a pixel-level area, providing a stable and predictable constant current source for the entire drive circuit.

[0061] Furthermore, to balance the dual requirements of high integration and low power consumption in microdisplays, the aforementioned constant current bias scheme employs deep-well isolation and thick-oxygen high-voltage technology at the layout level: the first transistor is placed in an independent deep well, and its source metal is directly connected to a high-potential power supply ring through a wide metal trace to reduce power supply impedance; the gate polysilicon uses a silicide process to reduce resistance, allowing the bias voltage trace to extend across the entire column without significant voltage drop. Within a wide operating temperature range, the output current of the first transistor changes smoothly with temperature. Even under extremely high resolution and extremely short row charging times, the constant current stability remains within a very narrow fluctuation range, providing a reliable current reference for ultra-high-definition, high-refresh-rate silicon-based organic light-emitting microdisplays.

[0062] Furthermore, the present invention also provides a display panel, including a plurality of light-emitting elements and a plurality of light-emitting elements such as 1 or 2. Figure 2 The pixel driving circuit shown is used to drive multiple light-emitting elements. For example, a display panel includes multiple pixel circuits arranged in an array, each pixel circuit including a pixel driving circuit and a light-emitting element. Optionally, in this display panel, the ramp signal can be uniformly generated by a row driving chip, and multiple pixel driving circuits in each row share the same ramp signal. Optionally, the ramp signal line is driven by a buffer amplifier at the edge of the panel to compensate for line resistance-capacitance delay. Therefore, a single chip can serve multiple pixel driving circuits simultaneously, significantly reducing chip cost.

[0063] Figure 3a A timing diagram of a pixel driving circuit according to a first embodiment of the present invention is shown; Figure 3b A timing diagram of a pixel driving circuit according to a second embodiment of the present invention is shown. Figure 3a and 3b Taking a pixel driving circuit where all switches are P-type switches as an example, a ramp signal Ramp that increases linearly with time is used. The following detailed explanation of the working principle of the pixel driving circuit of this application is provided in conjunction with timing diagrams.

[0064] like Figure 3aThe diagram illustrates an example of row-by-row driving of the light-emitting element. Within one frame period, the scan signal Scan increments sequentially from row 1 to row N in a row-selective manner. When the scan signal Scan[n] of row n transitions to a high level, the third switch T3 is turned on, and the data voltage Vdata[n] is written to the corresponding row's storage node Nstore. Subsequently, the scan signal Scan[n] of row n returns to a low level, and the storage node Nstore enters a floating state and maintains the sampling potential. At the same time, the bias voltage Vbias and the high-potential power supply VDD remain constant. The first transistor T1 continuously provides a constant current to the intermediate node NodeX, while the ramp signal Ramp begins to change over time immediately after the falling edge of the scan signal Scan[n] of row n or after a safe interval, ensuring that the potentials of each row's Nstore are stably isolated. Subsequently, the linear rise of the ramp signal Ramp is coupled to Nstore through capacitor C1, causing the second switch T2 to generate a conduction duration proportional to the data voltage during the light-emitting phase, thus achieving PWM dimming. Subsequently, the (n+1)th row scan signal Scan[n+1] transitions to a high level, and the above process is repeated until all N rows of pixel driving circuits have completed the data writing stage, the light emission stage, and the shutdown stage. Throughout the entire frame period, the high-potential power supply VDD and the bias voltage Vbias remain regulated to avoid inter-line brightness differences caused by power supply fluctuations.

[0065] like Figure 3b The image shows an example of frame-by-frame driving of the light-emitting element. Unlike line-by-line driving, during the data writing stage, the scan signals Scan[1] to Scan[n] are set to the effective level, so that the third switch T3 is turned on line by line. After the entire frame data voltage Vdata is written to the corresponding storage node Nstore through the column driver chip, all pixel driving circuits enter the light-emitting stage. During the light-emitting stage, all scan signals Scan are flipped synchronously, and all storage nodes Nstore of the display panel enter the floating state at the same time. Then, the ramp signal Ramp is superimposed on all storage nodes Nstore of the display panel. Its slope and amplitude are set by the global gamma register. Since the data voltage Vdata has been written to each row storage node Nstore, the coupling effect of the ramp signal Ramp is highly consistent throughout the entire display panel. The conduction time of the second switch T2 depends only on its own data voltage and is not related to the row sequence, thereby eliminating the horizontal stripes caused by the ramp delay difference in line-by-line driving.

[0066] Optionally, at the end of the frame, a certain amount of reset time is reserved to pull the anode of the light-emitting element and the storage node Nstore to the reference potential together, completing the frame-wide synchronous reset and preparing for the parallel writing of the next frame.

[0067] The foregoing has described some examples of pixel driving circuits according to embodiments of the present invention. However, the embodiments of the present invention are not limited thereto, and there may be other extensions and modifications.

[0068] For example, the capacitor provided in the embodiments of this application can be a lumped parameter capacitor element, or it can be other equivalent elements with similar functions to a capacitor. The equivalent structure described herein is, for example, but not limited to, a microstrip line, a varactor, a conductor structure with a certain pattern, or other structures that can provide capacitive impedance.

[0069] For example, the aforementioned pixel driving circuit can be a discrete device or a single circuit unit. In other implementations, the aforementioned pixel driving circuit can be packaged in a device, while the light-emitting element can serve as a load structure surrounding that device.

[0070] Furthermore, those skilled in the art will recognize that the structures and methods described in conjunction with the embodiments disclosed herein can be used with different configuration or adjustment methods to achieve the described functions for each structure or reasonable variations thereof, but such implementations should not be considered beyond the scope of this application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0071] Figure 4 A flowchart of a pixel-driving method according to an embodiment of the present invention is shown.

[0072] like Figure 4 As shown, the pixel driving method includes steps S401 to S403. This pixel driving method can be used for, for example... Figure 1 or Figure 2 For details on the implementation of the pixel driving circuit shown, please refer to [reference needed]. Figures 1 to 3b The description will not be repeated here.

[0073] In step S401, a data voltage is written to the storage node to conduct a constant current to the light-emitting element, causing the light-emitting element to start emitting light.

[0074] In step S402, a time-varying signal is superimposed on the storage node to control the light emission time of the light-emitting element.

[0075] In step S403, if the voltage on the storage node exceeds a predetermined range, the path of constant current to the light-emitting element is turned off to stop supplying constant current to the light-emitting element.

[0076] In this step, the path of constant current to the light-emitting element is used to turn the second switch on or off. The parasitic capacitance between the gate and source of the second switch forms a positive feedback path. When the second switch switches from on to off, causing a change in its source potential, the change in source potential is fed back to its gate through the parasitic capacitance to accelerate the off process.

[0077] Optionally, the pixel driving method is used to drive multiple light-emitting elements located in the display panel respectively, with time-varying signals provided line by line and multiple light-emitting elements emitting light line by line; or time-varying signals provided frame by frame and multiple light-emitting elements emitting light frame by frame.

[0078] The pixel driving circuit, layout structure, display panel, and pixel driving method provided by this invention are based on a simplified 3T1C circuit topology and use analog data voltage to control the light-emitting duration of the light-emitting element. During the data writing phase, only the initial potential of the storage node is determined; the light-emitting duration is automatically turned off by an external time-varying signal coupled to the storage node, thus achieving grayscale in an analog manner. Since multi-bit memory, counters, or high-precision current mirrors are not required, the number of switches in the pixel driving circuit can be reduced to three, significantly reducing the circuit area compared to traditional digital PWM schemes. This circuit structure can maintain brightness uniformity within a very short row charging time and significantly reduce dynamic power consumption, meeting the comprehensive requirements of high-resolution, high-refresh-rate micro-displays for small size, low power consumption, and low cost. Furthermore, the data voltage is immediately converted into light-emitting pulses after row scanning, achieving a zero-frame latency effect of "data written and displayed instantly."

[0079] In some optional embodiments, the present invention utilizes the gate-source parasitic capacitance of the driving transistor itself as a positive feedback path. When the second switching transistor is turned off, it feeds the source potential back to the gate to form a bootstrap cutoff, which significantly sharpens the current falling edge and effectively suppresses the ghosting caused by the residual charge of the light-emitting element.

[0080] In some optional embodiments, the first transistor of the present invention is biased in the saturation region, with its gate connected to a bias voltage, its source connected to a high-potential power supply, and its drain outputting a constant current. Since the voltage difference between the bias voltage and the high-potential power supply is set to be greater than the absolute value of the first transistor's threshold voltage and remains constant, the drain current of the first transistor is controlled only by the gate-source voltage and is almost independent of changes in the drain potential. Therefore, when the second switch switches between on and off, causing a jump in its source voltage, fluctuations in the constant current provided by the first transistor are suppressed to a very small range, ensuring that the light-emitting element obtains a stable current amplitude throughout the entire light-emitting phase, fundamentally avoiding uneven brightness and color shift caused by current drift.

[0081] In some alternative embodiments, the capacitor element in the potential modulation unit is formed by parallel connection of a metal edge overlap structure and a metal insulator stack, both of which share the back-end interconnect process without increasing the photolithography layers; sufficient coupling can be obtained within a small footprint, so that the ramp signal can be completely injected into the memory node.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0083] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel driving circuit, comprising: A constant current power supply unit is used to provide a constant current. A drive control unit, connected between the constant current power supply unit and the light-emitting element, is used to provide the constant current to the light-emitting element; A scanning control unit is used to write data voltage to the storage node between the scanning control unit and the drive control unit; as well as A potential modulation unit is used to superimpose time-varying signals onto the storage node. If the voltage on the storage node exceeds a predetermined range, the drive control unit is turned off to stop providing the constant current to the light-emitting element.

2. The pixel driving circuit according to claim 1, wherein, The constant current power supply unit includes a first transistor, the source of which is connected to a high-potential power supply, and a control terminal receiving a bias voltage. The difference between the high-potential power supply and the bias voltage is greater than the absolute value of the threshold voltage of the first transistor, so that the first transistor operates in the saturation region to output a constant current at its drain.

3. The pixel driving circuit according to claim 2 further includes: A bias modulation unit is used to provide the bias voltage to the first transistor. The bias voltage includes a compensation component that is synchronized with the time-varying signal. When the conduction state of the drive control unit changes, causing a change in the drain potential of the first transistor, the compensation component reversely adjusts the gate-source voltage of the first transistor to counteract the channel length modulation effect and keep the constant current stable.

4. The pixel driving circuit according to claim 2 or 3, wherein, The constant current power supply unit further includes a high-impedance element connected in series between the gate of the first transistor and the bias voltage. The gate and drain of the first transistor have a coupling capacitance. When the drive control unit is turned off, causing a potential step change at the drain of the first transistor, the potential step change is coupled to the gate of the first transistor through the coupling capacitor, instantaneously reducing the gate-source voltage of the first transistor, thereby suppressing the constant current, and gradually restoring the constant current through the high-impedance element.

5. The pixel driving circuit according to claim 1, wherein, The drive control unit includes a second switching transistor, the source of which is connected to the constant current power supply unit to receive the constant current, the drain of which is connected to the light-emitting element to provide the constant current, and the gate of which is connected to the memory node.

6. The pixel driving circuit according to claim 5, wherein, The voltage value of the time-varying signal increases or decreases linearly with time, or increases or decreases non-linearly with time, or the voltage value of the time-varying signal remains within the predetermined range during a predetermined time period and exceeds the predetermined range outside the predetermined time period.

7. The pixel driving circuit according to claim 5, wherein, The parasitic capacitance between the gate and source of the second switch forms a positive feedback path. When the second switch changes from being turned on to being turned off, causing a change in its source potential, this change in source potential is fed back to its gate through the parasitic capacitance to accelerate the turn-off process.

8. The pixel driving circuit according to claim 1, wherein, The potential modulation unit includes a capacitor element for coupling external time-varying signals to the storage node. The capacitor element is selected from any of the following or a combination capacitor formed by connecting any two or more of the following structures in parallel: metal-oxide-metal parallel plate capacitor, metal-insulator-metal multilayer capacitor, polysilicon-insulator-polysilicon capacitor, gate oxide capacitor, PN junction capacitor or metal oxide semiconductor varactor structure.

9. A layout structure for forming at least a portion of the pixel driving circuitry as described in any one of claims 1 to 8, wherein, The constant current power supply unit includes a first transistor, the active region of which adopts a folded layout to extend the channel length; or, the gate region and drain region of the first transistor have overlapping areas to enhance drain-gate feedback coupling. The drive control unit includes a second switching transistor, the source of which is connected to the constant current power supply unit to receive the constant current, the drain of which is connected to the light-emitting element to provide the constant current, and the gate of which is connected to the memory node. The source metal layer of the second switching transistor is connected between the constant current power supply unit and the drive control unit. The source metal layer is configured with a geometry that surrounds or covers the gate region to increase the parasitic capacitance between the gate and the source.

10. A display panel, comprising: Multiple light-emitting elements; as well as A plurality of pixel driving circuits as described in any one of claims 1 to 8 are used to drive the plurality of light-emitting elements.

11. A pixel driving method, comprising: A data voltage is written to the storage node to conduct a constant current to the light-emitting element, causing the light-emitting element to start emitting light; A time-varying signal is superimposed on the storage node to control the light-emitting time of the light-emitting element; If the voltage on the storage node exceeds a predetermined range, the path of the constant current to the light-emitting element is shut off to stop supplying the constant current to the light-emitting element.

12. The pixel driving method according to claim 11, wherein, The constant current is provided by a first transistor connected to a high-potential power supply. The gate of the first transistor receives a bias voltage, which includes a compensation component synchronized with the time-varying signal. When the conduction state of the drive control unit changes, causing a change in the drain potential of the first transistor, the compensation component reversely adjusts the gate-source voltage of the first transistor to counteract the channel length modulation effect and keep the constant current stable.

13. The pixel driving method according to claim 12, wherein, When the path of the constant current to the light-emitting element is turned off, causing a potential step change at the drain of the first transistor, the potential step change is coupled to the gate of the first transistor through the coupling capacitance between the gate and the drain of the first transistor, instantaneously reducing the gate-source voltage of the first transistor, thereby suppressing the constant current, and gradually restoring the constant current through a high-impedance element connected in series between the gate of the first transistor and the bias voltage.

14. The pixel driving method according to claim 11, wherein, By using the second switch to turn on or off the path of the constant current to the light-emitting element, the parasitic capacitance between the gate and source of the second switch forms a positive feedback path. When the second switch changes from being on to being off, causing a change in its source potential, this change in source potential is fed back to its gate through the parasitic capacitance to accelerate the off process.

15. The pixel driving method according to claim 11, wherein, The voltage value of the time-varying signal increases or decreases linearly with time, or increases or decreases non-linearly with time, or the voltage value of the time-varying signal remains within the predetermined range during a predetermined time period and exceeds the predetermined range outside the predetermined time period.

16. The pixel driving method according to claim 11 or 15, wherein, The pixel driving method drives multiple light-emitting elements located in the display panel respectively. The time-varying signal is provided row by row, and the multiple light-emitting elements emit light row by row; or The time-varying signal is provided frame by frame, and the multiple light-emitting elements emit light frame by frame.

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