Display circuit, display screen, electronic equipment and display method
By alternating pixel circuits and individually controlling their reset periods in an AMOLED display, the problem of black stripes in high frame rate displays was solved, resulting in better display performance and flicker optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- VIVO MOBILE COMM CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-05-01
AI Technical Summary
AMOLED displays are prone to black stripes when displaying at high frame rates, resulting in poor display quality.
By alternating multiple rows of first pixel circuits and multiple rows of second pixel circuits in the pixel array, and controlling them individually by a control circuit, the time difference between the reset periods of any two adjacent rows of pixel circuits is made greater than a preset duration, so as to avoid the overlap of the reset periods of adjacent pixel circuits.
It effectively reduces the generation of black stripes, improves the display effect of the display circuit, reduces flicker, and enhances display quality.
Smart Images
Figure CN121963643A_ABST
Abstract
Description
Display circuits, displays, electronic devices and display methods Technical Field
[0001] This application relates to the field of display technology, specifically to a display circuit, display screen, electronic device, and display method. Background Technology
[0002] Among related technologies, Organic Matrix / Organic Light Emitting Diode (AMOLED) displays are widely used in mid-to-high-end models due to their thinness and power efficiency. AMOLED's light-emitting technology is an active-matrix technology. Due to the characteristics of the Thin Film Transistor (TFT) in AMOLED, the backplane driving circuit needs to be reset and recharged for each frame during TFT light emission. During this reset period, the TFT cannot emit light. The OLED pixel driving circuit (Gate on array, GOA) timing in related technologies turns on line by line. Within a frame, when the GOA timing is high, the OLED pixels are turned off, displaying black. When the display is at a high frame rate, such as during high-speed camera shooting, black stripes can easily appear in the screen, resulting in poor display quality. Summary of the Invention
[0003] This application provides a display circuit, a display screen, an electronic device, and a display method, which can solve the problem of poor display effect of display circuits in related technologies.
[0004] In a first aspect, a display circuit is provided, comprising: a pixel array, a first driving unit, a second driving unit, and a control circuit, wherein the pixel array includes multiple rows of first pixel circuits and multiple rows of second pixel circuits, and the multiple rows of first pixel circuits and the multiple rows of second pixel circuits are arranged alternately along the column direction of the pixel array.
[0005] The control circuit is electrically connected to the multi-row first pixel circuit through the first driving unit, and the control circuit is electrically connected to the multi-row second pixel circuit through the second driving unit.
[0006] During the operation of the display circuit, the control circuit is used to control the time difference of the reset period corresponding to any two adjacent rows of pixel circuits in the pixel array to be greater than a preset duration. The two adjacent rows of pixel circuits include a first row of pixel circuits and a second row of pixel circuits. The preset duration is related to the total duration of the reset period.
[0007] In a second aspect, a display screen is provided, including the display circuit described in the first aspect.
[0008] Thirdly, an electronic device is provided, including the display screen described in the second aspect.
[0009] Fourthly, a display method is provided, applied to the electronic device described in the third aspect, the method comprising:
[0010] During the operation of the display screen, the time difference between the reset periods of any two adjacent rows of pixel circuits in the pixel array is greater than a preset duration, based on the control circuit. The two adjacent rows of pixel circuits include a first row of pixel circuits and a second row of pixel circuits. The preset duration is related to the total duration of the reset period.
[0011] In this embodiment, a pixel array, a first driving unit, a second driving unit, and a control circuit are used. The pixel array includes multiple rows of first pixel circuits and multiple rows of second pixel circuits, which are arranged alternately along the column direction of the pixel array. The control circuit is electrically connected to the multiple rows of first pixel circuits through the first driving unit and to the multiple rows of second pixel circuits through the second driving unit. Thus, during the operation of the display circuit, the control circuit independently controls the first and second pixel circuits through the first and second driving units respectively. This ensures that the time difference between the reset periods of any two adjacent rows of pixel circuits in the pixel array is greater than a preset duration. Therefore, when a row of pixel circuits is turned off, the adjacent pixel driving circuit can be in an on state. This results in the OLED appearing half-on when the human eye observes the area where the off pixel circuit is located, making black stripes imperceptible and improving the display effect of the display circuit. Attached Figure Description
[0012] Figure 1 is a schematic diagram of the display circuit provided in an embodiment of this application;
[0013] Figure 2 is a schematic diagram of the pixel driving circuit in an embodiment of this application;
[0014] Figure 3 is one of the GOA timing diagrams in the embodiments of this application;
[0015] Figure 4 is a schematic diagram of the OLED state during the process of controlling the display circuit according to the GOA timing diagram shown in Figure 3.
[0016] Figure 5 shows one of the brightness waveforms as seen by the human eye during the display process of the display circuit.
[0017] Figure 6 is the second brightness waveform diagram as seen by the human eye during the display process of the display circuit;
[0018] Figure 7(a) is one of the brightness waveforms seen by the human eye during the display process of the display circuit before improvement;
[0019] Figure 7(b) is the second brightness waveform diagram seen by the human eye during the display process of the improved display circuit;
[0020] Figure 8 is a second GOA timing diagram in the embodiments of this application;
[0021] Figure 9 is a schematic diagram of the OLED state during the process of controlling the display circuit according to the GOA timing diagram shown in Figure 8.
[0022] Figure 10(a) is one of the brightness waveforms seen by the human eye during the display process of the display circuit before improvement;
[0023] Figure 10(b) is the second brightness waveform diagram seen by the human eye during the display process of the improved display circuit;
[0024] Figure 11 is a schematic diagram of the spectral response characteristics of the human eye;
[0025] Figure 12 is a schematic diagram of the frequency response characteristics of the human eye;
[0026] Figure 13 is a cross-sectional schematic diagram of the display screen in an embodiment of this application;
[0027] Figure 14 is a flowchart illustrating a display method according to an embodiment of this application. Detailed Implementation
[0028] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.
[0029] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or more. Furthermore, "or" in this application indicates at least one of the connected objects. For example, the scope of protection for "A or B" covers at least three scenarios: Scenario 1: including A but not B; Scenario 2: including B but not A; Scenario 3: including both A and B. In addition, the terms "A and / or B," "at least one of A and B," and "at least one of A or B" also cover at least the above three scenarios. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0030] The display circuit, display screen, electronic device, and display method provided in this application will be described in detail below with reference to the accompanying drawings and through some embodiments and application scenarios.
[0031] Please refer to Figures 1 and 2. This application provides a display circuit, including: a pixel array 100, a first driving unit 210, a second driving unit 220, and a control circuit 300. The pixel array 100 includes multiple rows of first pixel circuits 110 and multiple rows of second pixel circuits 120, which are arranged alternately along the column direction of the pixel array 100.
[0032] The control circuit 300 is electrically connected to the multi-row first pixel circuit 110 through the first driving unit 210, and the control circuit 300 is electrically connected to the multi-row second pixel circuit 120 through the second driving unit 220.
[0033] During the operation of the display circuit, the control circuit 300 is used to control the time difference of the reset period corresponding to any two adjacent rows of pixel circuits in the pixel array 100 to be greater than a preset duration. The two adjacent rows of pixel circuits include a first pixel circuit 110 and a second pixel circuit 120. The preset duration is related to the total duration of the reset period.
[0034] In the pixel array 100 described above, one pixel circuit can be considered as a pixel row, that is, one first pixel circuit 110 can be considered as a pixel row, and simultaneously, one second pixel circuit 120 can be considered as a pixel row. In some embodiments of this application, the pixel array 100 may include N pixel rows, and each pixel row may include multiple pixels arranged along the row direction.
[0035] In this embodiment, the N rows of pixel circuits included in the pixel array 100 can be referred to from top to bottom as: row 1 pixel circuit, row 2 pixel circuit, ..., row i pixel circuit, ..., row N pixel circuit. Here, 1, 2, ..., i, ..., N represent the row numbers of the N pixel circuits. Pixel circuits with odd row numbers are referred to as first pixel circuits 110, such as row 1, row 3, row 5, etc. Correspondingly, pixel circuits with even row numbers are referred to as second pixel circuits 120, such as row 2, row 4, row 6, etc. It is understood that in some embodiments of this application, pixel circuits with odd row numbers can also be referred to as second pixel circuits 120, and pixel circuits with even row numbers can be referred to as first pixel circuits 110, depending on the specific requirements.
[0036] It is understandable that the structures of the first pixel circuit 110 and the second pixel circuit 120 may be different. The difference lies in their positions in the pixel array 100. Specifically, one of the first pixel circuit 110 and the second pixel circuit 120 is located in the odd-numbered row of the pixel array 100, while the other is located in the even-numbered row of the pixel array 100.
[0037] In some embodiments of this application, both the first driving unit 210 and the second driving unit 220 may include various types of GOA circuits to drive the pixel circuits. The control circuit 300 can independently control the first driving unit 210 and the second driving unit 220, thereby enabling individual control of the odd-numbered row pixel circuits and even-numbered row pixel circuits in the pixel array 100.
[0038] In related technologies, the OLED GOA timing is turned on line by line. Therefore, within one frame, the OLED pixels are turned off when the GOA timing is high, and the display is black. Correspondingly, the low-level period is the display period, so black stripes can be seen when taking pictures with a high-speed camera.
[0039] Please refer to Figure 3, which is a GOA timing diagram in an embodiment of this application. The high-level period in Figure 3 is the reset period, and the low-level period is the display period. The time difference between the reset periods corresponding to any two adjacent rows of pixel circuits being greater than a preset duration can mean either that the time difference between the start times of the reset periods corresponding to any two adjacent rows of pixel circuits is greater than a preset duration, or that the time difference between the end times of the reset periods corresponding to any two adjacent rows of pixel circuits is greater than a preset duration. All pixel circuits have the same reset period duration.
[0040] It is understandable that the longer the overlap of the reset periods of two adjacent rows of pixel circuits, the more likely black stripes will be generated. This is because the OLED pixels of the corresponding pixel circuit are off during the reset period. Therefore, if two adjacent pixel circuits are both in the reset period, the OLED pixels of both rows of pixel circuits in that area will be off, thus easily generating black stripes. However, if the reset periods of two adjacent rows of pixel circuits are staggered by a certain distance, when the OLED pixels of one pixel circuit are off, the OLED pixels of the other pixel circuit are on. This makes the OLED appear half-on when the human eye observes the area where the pixel circuit is off, making the black stripes imperceptible. Therefore, in this embodiment, by making the time difference of the reset periods of any two adjacent rows of pixel circuits greater than a preset duration, the overlap of the reset periods of adjacent pixel rows can be minimized, thereby reducing the probability of black stripes being generated.
[0041] The preset duration can be set as needed; for example, it can be greater than or equal to half the reset duration. In some embodiments of this application, the reset periods of two adjacent rows of pixel circuits may partially overlap. In some embodiments of this application, the reset periods of two adjacent rows of pixel circuits may also be completely staggered. When the reset periods of two adjacent rows of pixel circuits are completely staggered, when one row of pixel circuits is turned off, the adjacent pixel driving circuit can be in an on state, resulting in a half-on effect of the OLED, making the black stripes imperceptible to the human eye, thereby improving the display effect of the display circuit.
[0042] To facilitate understanding, this application embodiment takes the example of the reset periods of two adjacent rows of pixel circuits being completely staggered to further explain the working principle of the display circuit in this application embodiment: Please refer to Figure 3, which is a schematic diagram of the GOA timing in this application embodiment. In Figure 3, the high-level period is the reset period, and the low-level period is the display period. The above-mentioned completely staggered reset periods of any two adjacent rows of pixel circuits 110 can mean that the reset periods of the two pixel driving circuits corresponding to any two adjacent rows of pixel circuits do not overlap. As shown in Figure 3, in this application embodiment, the GOA design is changed to a non-row-by-row opening design, and the GOA high-level times of the Nth row and the N+1th row are completely staggered. The reset period of the above-mentioned pixel driving circuit is the GOA high-level period in Figure 3. Therefore, when the Nth row of OLED pixels is turned off, the N+1th row of OLED pixels is turned on. When the human eye observes the corresponding area, the OLED will be seen to be in a half-open state, as shown in Figure 4.
[0043] Please refer to Figures 5 and 6. The visual fatigue felt by the human eye is affected by the amplitude and frequency of changes in screen brightness. When the frequency of screen brightness changes is fixed, the amplitude drop ratio of screen brightness changes becomes particularly important.
[0044] It should be noted that the key values affecting flicker are frequency and the amplitude of brightness changes. This application provides the following two implementation methods to optimize flicker:
[0045] While keeping the frequency constant, the brightness variation amplitude is changed: In related technologies, adjacent rows are brightened or darkened together when they differ by 1 row, resulting in a larger brightness amplitude. However, in this embodiment, the brightness of adjacent rows is completely reversed. That is, when the Nth row is bright, the corresponding N+1th row is dark. Since the human eye responds to light integrally, the cumulative brightness variation will be smaller, thus optimizing flicker.
[0046] Both frequency and brightness variation amplitude are changed: Based on the above method, the distance between the timing of the first group of GOA and the second group of GOA is increased. This not only reduces the brightness drop ratio, but also doubles the frequency of screen brightness variation, thus making it more effective in reducing flicker.
[0047] Please refer to Figure 5. When the brightness level of the display fluctuates as shown in Figure 5, the display can be considered as a component with AC power added to a DC component. The flicker amount is defined as (AC component) / (DC component), referred to as the "contrast flicker value". Referring to the above principle, the AC component and DC component are defined as follows:
[0048] AC value = Vmax - Vmin
[0049] DC value = (Vmax + Vmin) / 2
[0050] The flicker value can be calculated using the following formula:
[0051]
[0052] Where Flicker represents the flicker value, Vmax corresponds to the maximum brightness value in the brightness waveform, Vmin corresponds to the minimum brightness value in the brightness waveform, AC value is the brightness drop ratio of a single frame, and DC value is actually the brightness value fitted under DC conditions.
[0053] Figure 5 shows the brightness waveform as perceived by the human eye, not a single-line brightness waveform, but the brightness waveform as seen by the integration of the human eye. Referring to the illustration in Figure 5, Vmax corresponds to the maximum brightness value in the brightness waveform, Vmin corresponds to the minimum brightness value, AC value is the single-frame brightness drop ratio, DC value is actually the brightness value fitted under DC conditions, and flicker value can be calculated as follows: The most significant factor here is the AC value, which is the brightness drop ratio. In this application embodiment, flicker can be optimized by optimizing the AC value, i.e., optimizing the brightness drop ratio.
[0054] As shown in Figure 7, after controlling the display circuit according to the GOA timing shown in Figure 3, since half of the OLEDs are off and half of the OLEDs are on, the brightness drop ratio received by the human eye is significantly reduced, which can significantly improve the screen flicker effect.
[0055] In this embodiment, the pixel array 100, the first driving unit 210, the second driving unit 220, and the control circuit 300 are configured such that the pixel array 100 includes multiple rows of first pixel circuits 110 and multiple rows of second pixel circuits 120, which are arranged alternately along the column direction of the pixel array 100; the control circuit 300 is electrically connected to the multiple rows of first pixel circuits 110 through the first driving unit 210, and the control circuit 300 is electrically connected to the multiple rows of second pixel circuits 120 through the second driving unit 220. Thus, during the operation of the display circuit, the control circuit 300 controls the first pixel circuit 110 and the second pixel circuit 120 separately through the first driving unit 210 and the second driving unit 220, so that the time difference of the reset period corresponding to any two adjacent rows of pixel circuits in the pixel array 100 is greater than a preset duration. In this way, when a row of pixel circuits is turned off, the adjacent pixel driving circuit can be in the open state, so that when the human eye observes the area where the pixel circuit in the closed state is located, the OLED will appear to be in a half-open state, making it impossible for the human eye to perceive black stripes, thereby improving the display effect of the display circuit.
[0056] Optionally, the first driving unit 210 includes a plurality of first pixel driving circuits 211 corresponding one-to-one with the multi-row first pixel circuits 110, and the output terminal of the first pixel driving circuit 211 is electrically connected to the input terminal of the corresponding first pixel driving circuit 211.
[0057] The control circuit 300 is electrically connected to the input terminal of one of the plurality of first pixel driving circuits 211. Among the plurality of first pixel driving circuits 211, the output terminal of the first pixel driving circuit 211 with the serial number p is electrically connected to the input terminal of the first pixel driving circuit 211 with the serial number p+1, where p is an integer greater than or equal to 1. The serial number of the first pixel driving circuit 211 is obtained by numbering the plurality of first pixel driving circuits 211 according to the arrangement order of the first pixel driving circuits 211, starting from the position of the first pixel driving circuit 211 connected to the control circuit 300.
[0058] The first pixel driving circuit 211 can be any type of GOA circuit. Since there is a one-to-one correspondence between multiple rows of first pixel circuits 110 and multiple first pixel driving circuits 211, the row number of the first pixel circuit 110 can be the same as the row number of the corresponding first pixel driving circuit 211, that is, the first pixel circuit 110 and the corresponding first pixel driving circuit 211 can be located in the same row of the pixel array 100.
[0059] It is understood that the control circuit 300 described above can be electrically connected to the input terminal of any one of the plurality of first pixel driving circuits 211. For example, when the control circuit 300 is electrically connected to the first first pixel driving circuit 211 among the plurality of first pixel driving circuits 211, the sequence number of the first first pixel driving circuit 211 is 1. Referring to Figure 1, when the first pixel circuit 110 is an odd-numbered row pixel circuit of the pixel array 100, the first first pixel driving circuit 211 is the first row pixel driving circuit of the pixel array 100. Correspondingly, the sequence number of the next first pixel driving circuit 211 after the first first pixel driving circuit 211 is 2, that is, the sequence number of the third row pixel driving circuit of the pixel array 100 is 2, and so on, with the sequence number increasing as the row number progresses.
[0060] For example, when the control circuit 300 is electrically connected to the first first pixel driving circuit 211 among the plurality of first pixel driving circuits 211, the sequence number of the first first pixel driving circuit 211 is 1. When the first pixel circuit 110 is an even-numbered row pixel circuit of the pixel array 100, the first first pixel driving circuit 211 is the second row pixel driving circuit of the pixel array 100. Correspondingly, the sequence number of the next first pixel driving circuit 211 after the first first pixel driving circuit 211 is 2, that is, the sequence number of the fourth row pixel driving circuit of the pixel array 100 is 2, and so on, with the sequence number increasing as the row number increases.
[0061] For example, when the control circuit 300 is electrically connected to the second first pixel driving circuit 211 among the plurality of first pixel driving circuits 211, the sequence number of the second first pixel driving circuit 211 is 1. Please refer to Figure 1. When the first pixel circuit 110 is an odd-numbered row pixel circuit of the pixel array 100, the second first pixel driving circuit 211 is the third row pixel driving circuit of the pixel array 100. Correspondingly, the number of the fifth row pixel driving circuit is 2. If the sequence number of the last first pixel driving circuit 211 is k, then after completing the numbering of the last first pixel driving circuit 211, we return to the first first pixel driving circuit 211. Since the first first pixel driving circuit 211 has not yet been numbered, the sequence number of the first first pixel driving circuit 211 is set to k+1, until the numbering of all first pixel driving circuits 211 is completed.
[0062] It is understood that in the above embodiments, the numbering of the first pixel driving circuits 211 is performed in a top-to-bottom order according to the arrangement of the plurality of first pixel driving circuits 211. In fact, it can also be set to be numbered from bottom to top as needed. For example, when the control circuit 300 is electrically connected to the first first pixel driving circuit 211 among the plurality of first pixel driving circuits 211, the sequence number of the first first pixel driving circuit 211 is 1. Please refer to Figure 1. When the first pixel circuit 110 is an odd-numbered row pixel circuit of the pixel array 100, the first first pixel driving circuit 211 can be the last odd-numbered row pixel driving circuit in the pixel array 100, and the sequence number of the second-to-last odd-numbered row pixel driving circuit in the pixel array 100 is 2, and so on, with the sequence number being larger as the row number comes earlier.
[0063] It is understood that, since the first pixel driving circuit 211 with the largest sequence number does not have a subsequent first pixel driving circuit 211, the output terminal of the first pixel driving circuit 211 with the largest sequence number is only electrically connected to the corresponding first pixel circuit 110. That is, the value of p is less than s1, where s1 is the number of first pixel driving circuits 211 included in the first driving unit 210.
[0064] Please refer to Figure 1. In this embodiment, the first pixel circuit 110 is an odd-numbered row pixel circuit of the pixel array 100, and the control circuit 300 is electrically connected to the first first pixel driving circuit 211 among the plurality of first pixel driving circuits 211, to further explain the driving principle of the display circuit. Referring to Figure 1, in some embodiments of this application, during the operation of the display circuit, the control circuit 300 can send a display signal to the input terminal of the first row first pixel driving circuit 211. The output terminal of the first row first pixel driving circuit 211 can output a corresponding control signal to the corresponding first pixel circuit 110. Simultaneously, this control signal can be cascaded to the next first pixel driving circuit 211, that is, cascaded to the input terminal of the third row pixel driving circuit. Thus, cascading occurs sequentially in the first driving unit 210 according to the row number, thereby controlling the display process of all first pixel circuits 110.
[0065] In this embodiment, the first driving unit 210 includes a plurality of first pixel driving circuits 211 corresponding one-to-one with the multiple rows of first pixel circuits 110. The output terminal of the first pixel driving circuit 211 is electrically connected to the input terminal of the corresponding first pixel driving circuit 211. The control circuit 300 is electrically connected to the input terminal of one of the plurality of first pixel driving circuits 211. In the plurality of first pixel driving circuits 211, the output terminal of the first pixel driving circuit 211 with the sequence number p is electrically connected to the input terminal of the first pixel driving circuit 211 with the sequence number p+1. In this way, each of the first pixel driving circuits 211 is connected in sequence, so that the relevant control signal received by the first pixel driving circuit 211 with the sequence number 1 can be transmitted to each of the first pixel driving circuits 211 in sequence according to the sequence number. Therefore, the control circuit 300 can control the connected first pixel driving circuits 211 to achieve unified control of all the first pixel driving circuits 211.
[0066] Optionally, the second driving unit 220 includes a plurality of second pixel driving circuits 221 that correspond one-to-one with the multi-row second pixel circuits 120, and the output terminal of the second pixel driving circuit 221 is electrically connected to the input terminal of the corresponding second pixel driving circuit 221.
[0067] The control circuit 300 is electrically connected to the input terminal of one of the plurality of second pixel driving circuits 221. Among the plurality of second pixel driving circuits 221, the output terminal of the second pixel driving circuit 221 with the serial number j is electrically connected to the input terminal of the second pixel driving circuit 221 with the serial number j+1, where j is an integer greater than or equal to 1. The serial number of the second pixel driving circuit 221 is obtained by numbering the plurality of second pixel driving circuits 221 according to the arrangement order of the second pixel driving circuits 221, starting from the position of the second pixel driving circuit 221 connected to the control circuit 300.
[0068] In some embodiments of this application, the first driving unit 210 can be referred to as the first group of GOAs, and the second driving unit 220 can be referred to as the second group of GOAs. Referring to Figure 1, the first group of GOAs includes all the GOA circuits within the dashed boxes in Figure 1, and the second group of GOAs includes all the GOA circuits within the solid boxes in Figure 1. That is, the driving circuit of the display circuit consists of two groups of GOAs, and the control circuit 300 can control each of the two groups of GOAs independently.
[0069] The first pixel driving circuit 211 can be any type of GOA circuit. Since multiple rows of first pixel circuits 110 correspond one-to-one with multiple first pixel driving circuits 211, the row number of the first pixel circuit 110 can be the same as the row number of the corresponding first pixel driving circuit 211; that is, the first pixel circuit 110 and its corresponding first pixel driving circuit 211 can be located in the same row of the pixel array 100. Correspondingly, since multiple rows of second pixel circuits 120 correspond one-to-one with multiple second pixel driving circuits 221, the row number of the second pixel circuit 120 can be the same as the row number of the corresponding second pixel driving circuit 221; that is, the second pixel circuit 120 and its corresponding second pixel driving circuit 221 can be located in the same row of the pixel array 100. It is understood that in the first pixel driving circuit 211 and the second pixel driving circuit 221, one is located in an odd-numbered row of the pixel array 100, and the other is located in an even-numbered row of the pixel array 100. For example, please refer to FIG1. In the embodiment shown in FIG1, the first pixel driving circuit 211 is located in an odd-numbered row, and the second pixel driving circuit 221 is located in an even-numbered row. For ease of understanding, this application uses the embodiment shown in FIG1 as an example to further explain the structure of the display circuit.
[0070] It is understood that the control circuit 300 described above can be electrically connected to the input terminal of any one of the plurality of second pixel driving circuits 221. For example, when the control circuit 300 is electrically connected to the first second pixel driving circuit 221 among the plurality of second pixel driving circuits 221, the sequence number of the first second pixel driving circuit 221 is 1. Referring to Figure 1, when the second pixel circuit 120 is an even-numbered row pixel circuit of the pixel array 100, the first second pixel driving circuit 221 is the second row pixel driving circuit of the pixel array 100. Correspondingly, the sequence number of the next second pixel driving circuit 221 after the first second pixel driving circuit 221 is 4, that is, the sequence number of the fourth row pixel driving circuit of the pixel array 100 is 2, and so on, with the sequence number increasing as the row number progresses.
[0071] For example, when the control circuit 300 is electrically connected to the first second pixel driving circuit 221 among the plurality of second pixel driving circuits 221, the sequence number of the first second pixel driving circuit 221 is 1. When the second pixel circuit 120 is an odd-numbered row pixel circuit of the pixel array 100, the first second pixel driving circuit 221 is the first row pixel driving circuit of the pixel array 100. Correspondingly, the sequence number of the next second pixel driving circuit 221 after the first second pixel driving circuit 221 is 2, that is, the sequence number of the third row pixel driving circuit of the pixel array 100 is 2, and so on, with the sequence number increasing as the row number increases.
[0072] For example, when the control circuit 300 is electrically connected to the second second pixel driving circuit 221 among the plurality of second pixel driving circuits 221, the sequence number of the second second pixel driving circuit 221 is 1. Please refer to Figure 1. When the second pixel circuit 120 is an even-numbered row pixel circuit of the pixel array 100, the second second pixel driving circuit 221 is the fourth row pixel driving circuit of the pixel array 100. Correspondingly, the number of the sixth row pixel driving circuit is 2. If the sequence number of the last second pixel driving circuit 221 is a, then after completing the numbering of the last second pixel driving circuit 221, we return to the first second pixel driving circuit 221. Since the first second pixel driving circuit 221 has not yet been numbered, the sequence number of the first second pixel driving circuit 221 is set to a+1, until the numbering of all second pixel driving circuits 221 is completed.
[0073] It is understood that in the above embodiments, the numbering of the second pixel driving circuits 221 is performed in a top-to-bottom order according to the arrangement of the plurality of second pixel driving circuits 221. In fact, it can also be set to be numbered from bottom to top as needed. For example, when the control circuit 300 is electrically connected to the first second pixel driving circuit 221 among the plurality of second pixel driving circuits 221, the sequence number of the first second pixel driving circuit 221 is 1. Please refer to Figure 1. When the second pixel circuit 120 is an even-numbered row pixel circuit of the pixel array 100, the first second pixel driving circuit 221 can be the last even-numbered row pixel driving circuit in the pixel array 100, and the sequence number of the second-to-last even-numbered row pixel driving circuit in the pixel array 100 is 2, and so on, with the sequence number being larger as the row number comes earlier.
[0074] It is understood that, since the second pixel driving circuit 221 with the largest sequence number does not have a subsequent second pixel driving circuit 221, the output terminal of the second pixel driving circuit 221 with the largest sequence number is only electrically connected to the corresponding second pixel circuit 120. That is, the value of j is less than s2, where s2 is the number of second pixel driving circuits 221 included in the second driving unit 220.
[0075] Please refer to Figure 1. In this embodiment, the second pixel circuit 120 is an even-numbered row pixel circuit of the pixel array 100, and the control circuit 300 is electrically connected to the first second pixel driving circuit 221 among the plurality of second pixel driving circuits 221, to further explain the driving principle of the display circuit. Referring to Figure 1, in some embodiments of this application, during the operation of the display circuit, the control circuit 300 can send a display signal to the input terminal of the first row second pixel driving circuit 221. The output terminal of the first row second pixel driving circuit 221 can output a corresponding control signal to the corresponding second pixel circuit 120. Simultaneously, this control signal can be cascaded to the next second pixel driving circuit 221, that is, cascaded to the input terminal of the fourth row pixel driving circuit. Thus, cascading is performed sequentially in the first driving unit 210 according to the row number to control the display process of all second pixel circuits 120.
[0076] It should be noted that the first pixel driving circuit 211 and the second pixel driving circuit 221 described above can be various types of GOA circuits. For example, referring to Figure 2, in some embodiments of this application, the GOA circuit includes nine P-type metal-oxide-semiconductor field-effect transistors (PMOS) and a storage capacitor Cst. The pixel circuit includes a light-emitting diode (LED), which includes a cathode, an anode, and an organic light-emitting layer. The GOA circuit and the LED together form a complete pixel.
[0077] In this embodiment, the second driving unit 220 includes a plurality of second pixel driving circuits 221 corresponding one-to-one with the multi-row second pixel circuits 120. The output terminal of the second pixel driving circuit 221 is electrically connected to the input terminal of the corresponding second pixel driving circuit 221. The control circuit 300 is electrically connected to the input terminal of one of the plurality of second pixel driving circuits 221. In the plurality of second pixel driving circuits 221, the output terminal of the second pixel driving circuit 221 with the sequence number j is electrically connected to the input terminal of the second pixel driving circuit 221 with the sequence number j+1. In this way, the various second pixel driving circuits 221 are connected sequentially, so that the relevant control signal received by the second pixel driving circuit 221 with the sequence number 1 can be transmitted to each second pixel driving circuit 221 sequentially according to the sequence number. Therefore, the control circuit 300 can control the connected second pixel driving circuits 221 to achieve unified control of all second pixel driving circuits 221.
[0078] Optionally, during the operation of the display circuit, the working period of any row of pixel circuits in the pixel array 100 includes multiple display periods, and in the multiple display periods, any two adjacent display periods are separated by a reset period;
[0079] In any two adjacent rows of pixel circuits, the midpoint of the i-th display period of one row of pixel circuits matches the midpoint of the i-th reset period of the other row of pixel circuits, where i is an integer greater than or equal to 1.
[0080] The matching of the midpoint of the i-th display period of one row of pixel circuits with the midpoint of the i-th reset period of another row of pixel circuits can mean that the midpoint of the i-th display period of one row of pixel circuits is the same as or close to the midpoint of the i-th reset period of another row of pixel circuits. For ease of understanding, in this embodiment, matching the midpoint of the i-th display period of one row of pixel circuits with the midpoint of the i-th reset period of another row of pixel circuits means that the midpoint of the i-th display period of one row of pixel circuits is the same as the midpoint of the i-th reset period of another row of pixel circuits. One pixel circuit is referred to as pixel circuit a, and the other as pixel circuit b. The display circuit provided in this embodiment will be further explained below.
[0081] It should be noted that during the operation of the pixel driving circuit, the pixel driving circuit will periodically reset. Therefore, referring to Figure 8, the reset period of pixel circuit b can be set to the middle position of the display period of pixel circuit a. In this way, after plotting the brightness waveforms of two adjacent pixel rows onto the same waveform diagram, it is equivalent to doubling the frequency, as shown in Figure 10, which shows the brightness waveforms before and after the improvement.
[0082] In the embodiment shown in Figure 8, by increasing the time-staggered distance between the first and second groups of GOAs, not only can the brightness drop ratio be reduced, but the frequency of screen brightness changes can also be doubled, thereby further optimizing flicker. As shown in Figures 11 and 12, the human eye perceives different frequencies of brightness changes differently. When the frequency of brightness changes is relatively low (0~20Hz), the human eye can easily perceive them, and the coefficient used in the Flicker calculation is 1, resulting in a higher risk of glare. However, when the frequency of brightness changes is high (>30Hz), the human eye is less likely to perceive the screen brightness changes, so the coefficient used in the Flicker calculation is lower, resulting in a lower Flicker value and a lower risk of glare. As shown in Figure 10, the embodiment shown in Figure 8 increases the frequency of screen brightness changes from 120Hz to 240Hz, which can effectively improve screen flicker.
[0083] In this embodiment, by matching the midpoint of the i-th display period of one row of pixel circuits with the midpoint of the i-th reset period of the other row of pixel circuits in any two adjacent rows of pixel circuits, not only can the brightness drop ratio be reduced, but the frequency of screen brightness changes can also be doubled, thereby further optimizing the flicker.
[0084] Optionally, during the operation of the display circuit, the control circuit 300 is also used to control the multi-row first pixel circuit 110 to display sequentially, and to control the multi-row second pixel circuit 120 to display sequentially.
[0085] Referring to Figure 3 or Figure 8, in some embodiments of this application, since in the first group of GOAs, for any two adjacent first pixel circuits 110, the signal input of the next row of first pixel circuits 110 is the signal output of the previous row of first pixel circuits 110, the start display time of the next row of first pixel circuits 110 will be later than the start display time of the previous row of first pixel circuits 110, thereby causing all the first pixel circuits 110 in the multi-row first pixel circuits 110 to be displayed sequentially. Correspondingly, since in the second group of GOAs, for any two adjacent second pixel circuits 120, the signal input of the next row of second pixel circuits 120 is the signal output of the previous row of second pixel circuits 120, the start display time of the next row of second pixel circuits 120 will be later than the start display time of the previous row of second pixel circuits 120, thereby causing all the second pixel circuits 120 in the multi-row second pixel circuits 120 to be displayed sequentially.
[0086] In this embodiment, during the operation of the display circuit, the control circuit 300 is also used to control the multi-row first pixel circuit 110 to display sequentially and to control the multi-row second pixel circuit 120 to display sequentially, thereby enabling the display circuit to display normally.
[0087] This application also provides a display screen, including the display circuit described in the above embodiments.
[0088] In this embodiment, since the display screen includes the display circuit described in the above embodiments, the display screen can implement each process of the display circuit in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.
[0089] Optionally, the display screen includes a first metal layer 410 and a second metal layer 420 arranged at intervals along the thickness direction of the display screen;
[0090] In the case where the first driving unit 210 includes a plurality of first pixel driving circuits 211 corresponding one-to-one with the plurality of rows of first pixel circuits 110, and the second driving unit 220 includes a plurality of second pixel driving circuits 221 corresponding one-to-one with the plurality of rows of second pixel circuits 120, the plurality of first pixel driving circuits 211 are arranged on the first metal layer 410, and the plurality of second pixel driving circuits 221 are arranged on the second metal layer 420.
[0091] The aforementioned arrangement of the multi-row first pixel driving circuit 211 on the first metal layer 410 can refer to the aforementioned first group of GOAs being arranged on the first metal layer 410. Correspondingly, the aforementioned arrangement of the multi-row second pixel driving circuit 221 on the second metal layer 420 can refer to the aforementioned second group of GOAs being arranged on the second metal layer 420. That is, the two groups of GOA traces are implemented through different metal layers, so that the two groups of GOA traces will not affect the black border of the display screen. Please refer to Figure 13, which is a schematic diagram of the two groups of GOAs located on different metal layers. As can be seen from Figure 13, by placing the two groups of GOAs on different metal layers, it is beneficial to effectively reduce the impact of setting the two groups of GOAs on the black border size, thereby reducing the area of the black border region of the display screen.
[0092] In this embodiment, by making the display screen include a first metal layer 410 and a second metal layer 420 arranged at intervals along the thickness direction of the display screen; when the first driving unit 210 includes a plurality of first pixel driving circuits 211 corresponding one-to-one with the multiple rows of first pixel circuits 110, and the second driving unit 220 includes a plurality of second pixel driving circuits 221 corresponding one-to-one with the multiple rows of second pixel circuits 120, the plurality of first pixel driving circuits 211 are arranged on the first metal layer 410 and the plurality of second pixel driving circuits 221 are arranged on the second metal layer 420, thus reducing the area of the black border region of the display screen.
[0093] This application also provides an electronic device, including the display screen described in the above embodiments.
[0094] In this embodiment, since the electronic device includes the display screen described in the above embodiments, the electronic device can implement all the processes of the display screen in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.
[0095] Please refer to Figure 14. This application embodiment also provides a display method applied to the electronic device described in the above embodiments. The method includes:
[0096] Step 1401: During the operation of the display screen, the control circuit 300 controls the reset time period of any two adjacent rows of pixel circuits in the pixel array 100 to be greater than a preset duration. The two adjacent rows of pixel circuits include a first pixel circuit 110 and a second pixel circuit 120. The preset duration is related to the total duration of the reset time period.
[0097] Optionally, during the operation of the display circuit, the working period of any row of pixel circuits in the pixel array 100 includes multiple display periods, and in the multiple display periods, any two adjacent display periods are separated by a reset period;
[0098] In any two adjacent rows of pixel circuits, the midpoint of the i-th display period of one row of pixel circuits matches the midpoint of the i-th reset period of the other row of pixel circuits, where i is an integer greater than or equal to 1.
[0099] Optionally, the method further includes:
[0100] During the operation of the display circuit, the control circuit 300 controls the multi-row first pixel circuit 110 to display sequentially, and controls the multi-row second pixel circuit 120 to display sequentially.
[0101] This implementation method is the same as the above-described embodiments. Its specific implementation process is the same as the above-described embodiments, and it has the same beneficial effects. To avoid repetition, it will not be described again here.
[0102] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A display circuit, characterized in that, include: The system comprises a pixel array, a first driving unit, a second driving unit, and a control circuit. The pixel array includes multiple rows of first pixel circuits and multiple rows of second pixel circuits, which are arranged alternately along the column direction of the pixel array. The control circuit is electrically connected to the multiple rows of first pixel circuits through the first driving unit, and the control circuit is also electrically connected to the multiple rows of second pixel circuits through the second driving unit. During the operation of the display circuit, the control circuit is used to control the time difference of the reset period corresponding to any two adjacent rows of pixel circuits in the pixel array to be greater than a preset duration. The two adjacent rows of pixel circuits include a first row of pixel circuits and a second row of pixel circuits. The preset duration is related to the total duration of the reset period.
2. The display circuit according to claim 1, characterized in that, The first driving unit includes a plurality of first pixel driving circuits corresponding one-to-one with the multiple rows of first pixel circuits. The output terminal of the first pixel driving circuit is electrically connected to the input terminal of the corresponding first pixel driving circuit. The control circuit is electrically connected to the input terminal of one of the plurality of first pixel driving circuits. In the plurality of first pixel driving circuits, the output terminal of the first pixel driving circuit with the sequence number p is electrically connected to the input terminal of the first pixel driving circuit with the sequence number p+1, where p is an integer greater than or equal to 1. The sequence number of the first pixel driving circuit is obtained by numbering the plurality of first pixel driving circuits according to the arrangement order, starting from the position of the first pixel driving circuit connected to the control circuit.
3. The display circuit according to claim 1, characterized in that, The second driving unit includes a plurality of second pixel driving circuits corresponding one-to-one with the multiple rows of second pixel circuits. The output terminal of the second pixel driving circuit is electrically connected to the input terminal of the corresponding second pixel driving circuit. The control circuit is electrically connected to the input terminal of one of the plurality of second pixel driving circuits. In the plurality of second pixel driving circuits, the output terminal of the second pixel driving circuit with the sequence number j is electrically connected to the input terminal of the second pixel driving circuit with the sequence number j+1, where j is an integer greater than or equal to 1. The sequence number of the second pixel driving circuit is obtained by numbering the plurality of second pixel driving circuits according to the arrangement order, starting from the position of the second pixel driving circuit connected to the control circuit.
4. The display circuit according to claim 1, characterized in that, During the operation of the display circuit, the working period of any row of pixel circuits in the pixel array includes multiple display periods. Among the multiple display periods, any two adjacent display periods are separated by a reset period. In any two adjacent rows of pixel circuits, the midpoint of the i-th display period of one row of pixel circuits matches the midpoint of the i-th reset period of the other row of pixel circuits, where i is an integer greater than or equal to 1.
5. The display circuit according to claim 1, characterized in that, During the operation of the display circuit, the control circuit is also used to control the sequential display of the multi-row first pixel circuit and the sequential display of the multi-row second pixel circuit.
6. A display screen, characterized in that, Includes the display circuit described in any one of claims 1 to 5.
7. The display screen according to claim 6, characterized in that, The display screen includes a first metal layer and a second metal layer arranged at intervals along the thickness direction of the display screen; when the first driving unit includes a plurality of first pixel driving circuits corresponding one-to-one with the plurality of rows of first pixel circuits, and the second driving unit includes a plurality of second pixel driving circuits corresponding one-to-one with the plurality of rows of second pixel circuits, the plurality of first pixel driving circuits are arranged on the first metal layer, and the plurality of second pixel driving circuits are arranged on the second metal layer.
8. An electronic device, characterized in that, Includes the display screen as described in claim 6 or 7.
9. A display method, characterized in that, Applied to the electronic device of claim 8, the method includes: during the operation of the display screen, based on the control circuit, controlling the time difference of the reset period corresponding to any two adjacent rows of pixel circuits in the pixel array to be greater than a preset duration, wherein the two adjacent rows of pixel circuits include a first row of pixel circuits and a second row of pixel circuits, and the preset duration is associated with the total duration of the reset period.
10. The method according to claim 9, characterized in that, During the operation of the display circuit, the working period of any row of pixel circuits in the pixel array includes multiple display periods. Among the multiple display periods, any two adjacent display periods are separated by a reset period. In any two adjacent rows of pixel circuits, the midpoint of the i-th display period of one row of pixel circuits matches the midpoint of the i-th reset period of the other row of pixel circuits, where i is an integer greater than or equal to 1.
11. The method according to claim 9, characterized in that, The method further includes: during the operation of the display circuit, controlling the multi-row first pixel circuit to display sequentially based on the control circuit, and controlling the multi-row second pixel circuit to display sequentially.