Display circuit, display panel, display screen and electronic equipment

Abstract

The embodiment of the invention provides a display circuit, a display panel, a display screen and electronic equipment, and relates to the technical field of terminals. The display circuit comprises a multi-stage driving circuit and a plurality of groups of pixel circuits, the multi-stage driving circuits are connected with the multiple groups of pixel circuits in a one-to-one correspondence manner; in the driving circuits corresponding to the continuous B groups of pixel circuits, the absolute value of the difference value between the stages of the driving circuits corresponding to the two groups of pixel circuits is greater than or equal to C, B is an integer greater than 1, and B is an integer smaller than C; c is the ratio of the duration of the first signal output by the driving circuit at the first level to the time delay between the first signals output by two adjacent stages of driving circuits; when the first signal is the first level, the pixel circuit does not emit light, and when the first signal is the second level, the pixel circuit emits light. Therefore, the situation that the first signals output by the driving circuits corresponding to the continuous multi-row pixel circuits are the first level at the same time is reduced, the situation that the continuous multi-row pixel circuits do not emit light is reduced, and the area of a black area is reduced.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to display circuits, display panels, displays and electronic devices. Background Technology

[0002] The display screen in mobile phones and other electronic devices typically includes components such as a display panel, a bezel, a backlight module, and a backplate. The display panel usually incorporates multi-level gate-on-array (GOA) circuits to enable the scanning and driving function of the display panel.

[0003] Specifically, each level of GOA circuit corresponds to one level of horizontal scan line, meaning that each level of GOA circuit is responsible for driving a group of pixel circuits.

[0004] However, during the process of refreshing the pixel circuits in the display panel by driving the GOA circuit, a large area of ​​black (also known as black bars) may appear on the display panel, which is not good for human eye health. Summary of the Invention

[0005] This application provides a display circuit, display panel, display screen, and electronic device, applicable to the field of terminal technology. It is used to reduce black areas on the display panel during the refresh display process.

[0006] In a first aspect, embodiments of this application propose a display circuit. The display circuit includes: a multi-level driving circuit and multiple sets of pixel circuits; the multi-level driving circuit and the multiple sets of pixel circuits are connected in a one-to-one correspondence; among the driving circuits corresponding to B consecutive sets of pixel circuits, the absolute value of the difference between the levels of two sets of pixel circuits is greater than or equal to C, where B is an integer greater than 1, B is an integer less than C, and C is the ratio between the duration of the first signal output by the driving circuit at a first level and the time delay between the first signals output by two adjacent driving circuits; when the first signal is at a first level, the pixel circuit does not emit light, and when the first signal is at a second level, the pixel circuit emits light.

[0007] Taking row driving as an example, a group of pixel circuits may include one or more rows of pixel circuits; the first signal may correspond to the scan signal Scan1 in the following text, the first level may correspond to the high level in the following text, and the second level may correspond to the low level in the following text.

[0008] This reduces the number of consecutive B-group pixel circuits that fail to emit light simultaneously, thereby reducing the width of the black bars caused by the pixel circuits not emitting light and improving the user experience.

[0009] In one possible implementation, multiple sets of pixel circuits belong to multiple pixel units; any pixel unit includes at least two consecutive sets of pixel circuits; the absolute value of the difference between the stages of the driving circuits corresponding to two adjacent sets of pixel circuits in a pixel unit is C.

[0010] In this way, the delay of the driving circuits corresponding to two adjacent sets of pixel circuits in the same pixel unit is the duration of the first signal at the first level. The driving circuits corresponding to two adjacent sets of pixel circuits will not be in a non-light-emitting state at the same time, reducing the width of the black bar caused by the pixel circuit not emitting light and improving the user experience.

[0011] In one possible implementation,

[0012] Where GOA(n) is the number of stages of the driving circuit, N is the number of rows of the pixel circuit, E is the total number of rows of multiple groups of pixel circuits, G is the number of rows of pixel circuits included in each group of pixel circuits, F is the time delay of the first signal corresponding to two adjacent driving circuit stages, and M is the duration of the first signal at the first level.

[0013] In this way, the number of driving circuit stages and rows in the same pixel unit are arranged in a forward direction, which makes it convenient for electronic devices to store the relationship between the number of driving circuit stages and rows, and to write the data corresponding to each row of pixel circuits.

[0014] In one possible implementation, the display circuit further includes: a connecting line for connecting the output terminal of the i-th stage driving circuit to the input terminal of the (i+1)-th stage driving circuit, where i is an integer greater than zero; the connecting line passes through the gaps between the pixel circuits in the multiple sets of pixel circuits.

[0015] By having the connecting lines pass through the gaps between pixel circuits, the occupancy of the connecting lines in the peripheral area PA can be reduced, thus reducing the area of ​​the peripheral area PA and the bezel width of the electronic device.

[0016] In one possible implementation, any set of pixel circuits includes: two consecutive rows of pixel circuits; any first-level driving circuit includes: a light emission control signal unit, a first reset signal unit, a second scan signal unit, a third scan signal unit, a first scan signal unit, and a second reset signal unit; the light emission control signal unit, the first reset signal unit, the second scan signal unit, the first scan signal unit, and the second reset signal unit are all connected to the first pixel circuit; the light emission control signal unit, the first reset signal unit, the second scan signal unit, the first scan signal unit, and the second reset signal unit are all connected to the second pixel circuit; the second scan signal unit is connected to the first pixel circuit, and the third scan signal unit is connected to the second pixel circuit, the number of rows corresponding to the first pixel circuit and the number of rows corresponding to the second pixel circuit are different; wherein, the light emission control signal unit is used to output a first signal; the first reset signal unit is used to output a second signal; the second reset signal unit is used to output a third signal, the second signal and the third signal are used to control the pixel circuit to reset; the second scan signal unit and the third scan signal unit are used to output a fourth signal; the fourth signal is used to control the pixel circuit to write data; the first scan signal unit is used to output a fifth signal; the fifth signal is used to lock the data of the pixel circuit.

[0017] The first signal can correspond to scan signal Scan1 (hereinafter referred to as Scan1), the second signal can correspond to scan signal Scan4 (hereinafter referred to as Scan4), the third signal can correspond to scan signal Scan3 (hereinafter referred to as Scan3), the fourth signal can correspond to scan signal Scan5 (hereinafter referred to as Scan5), and the fifth signal can correspond to scan signal Scan2 (hereinafter referred to as Scan2). In this way, the two rows of pixel circuits share some signals (e.g., scan signals Scan1, Scan3, Scan4, and Scan5), which reduces the number of devices outputting these signals in the display circuit and reduces the area of ​​the display circuit.

[0018] Secondly, embodiments of this application provide a display method, which includes: acquiring a first image, the first image being an image obtained by capturing a first display screen in a bright state, the first display screen including: a display circuit described in the first aspect or any possible implementation of the first aspect; displaying the first image; wherein the first display screen in the first image includes: one or more first regions; a first ratio is less than a second ratio, the first ratio being the ratio of the length of each first region in a first direction to the first display screen in the first image, the second ratio being the ratio of the length of C consecutive groups of pixel circuits in the first direction to the length of the first display screen in the first direction, and C being the ratio between the duration of the first signal output by the driving circuit at a first level and the time delay between the first signals output by two adjacent driving circuits; when the first signal is at a first level, the pixel circuit does not emit light, and when the first signal is at a second level, the pixel circuit emits light.

[0019] The first area can correspond to the black area in the following text.

[0020] In this way, the black area on the first display screen is smaller in the captured image.

[0021] In one possible implementation, the first ratio is less than or equal to the third ratio, the third ratio is less than the second ratio, and the third ratio is the ratio of the length of two adjacent sets of pixel circuits in the first direction to the length of the first display screen in the first direction.

[0022] Thirdly, embodiments of this application provide a display method, which includes: acquiring a first image, wherein the first image is an image obtained by capturing images of a first display screen in a screen-on state and a second display screen in a screen-on state, the first display screen including: the display circuit described in the first aspect or any possible implementation of the first aspect; the second display screen not including the display circuit described in the first aspect or any possible implementation of the first aspect;

[0023] The specifications of the first display screen are the same as those of the second display screen; the first display screen in the first image includes one or more first regions; the second display screen in the first image includes one or more second regions; the length of the first region in the first direction is less than the maximum length of the second region in the first direction.

[0024] Both the first and second regions can correspond to the black areas mentioned below.

[0025] Thus, in the image captured, the black area on the first display screen is smaller than the black area on the second display screen.

[0026] Fourthly, embodiments of this application provide a display panel, including: the display circuit described in the first aspect or any possible implementation of the first aspect.

[0027] Fifthly, embodiments of this application provide a display screen, including: a display panel described in the third aspect or any possible implementation of the third aspect.

[0028] Sixthly, embodiments of this application provide an electronic device, including: a display screen described in the fourth aspect or any possible implementation of the fourth aspect.

[0029] It should be understood that the second to sixth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0030] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0032] Figure 3 A timing diagram for a pixel circuit refresh display provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram illustrating the correspondence between the series order and the row order in a possible design.

[0034] Figure 5 The timing diagram shows the output drive signals of each stage of the drive circuit in a possible design.

[0035] Figure 6 This is a schematic diagram of a display circuit provided in an embodiment of this application;

[0036] Figure 7 A timing diagram of the driving signal output by a driving circuit provided in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of a display circuit provided in an embodiment of this application;

[0038] Figure 9 Timing diagrams of the drive signals output by each stage of the drive circuit provided in the embodiments of this application;

[0039] Figure 10 This is a schematic diagram of another display circuit provided in an embodiment of this application;

[0040] Figure 11 This is a schematic diagram of a display circuit provided in an embodiment of this application;

[0041] Figure 12A This is a schematic diagram of a driving circuit provided in an embodiment of this application;

[0042] Figure 12B This is a schematic diagram of the structure of an EM signal unit provided in an embodiment of this application;

[0043] Figure 13 This application provides a schematic diagram of a cascaded drive circuit structure.

[0044] Figure 14 This is a schematic diagram of another display circuit provided in an embodiment of this application;

[0045] Figure 15 A schematic diagram of the structure of a display screen provided in an embodiment of this application;

[0046] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0047] Figure 17 This is a schematic diagram of a first image provided for an embodiment of this application. Detailed Implementation

[0048] To facilitate a clear description of the technical solutions in the embodiments of this application, some terms and technologies involved in the embodiments of this application will be briefly introduced below:

[0049] 1. Persistence of vision

[0050] The persistence of vision is a characteristic of the human visual system that enables the perception of continuous motion and images. Specifically, it can be understood as the phenomenon where, when light enters the eye and stimulates photoreceptors on the retina, the retina transmits this information to the brain. However, this information does not disappear immediately but remains on the retina for a period of time (e.g., tens of milliseconds).

[0051] It is understandable that the refresh rate of a display screen is closely related to the persistence of vision effect. The refresh rate can affect the utilization of the persistence of vision effect, thereby affecting the user's viewing experience.

[0052] Specifically, when a display has a low refresh rate, the brief dark periods between each refresh can be perceived by the human eye, leading to visual discomfort and fatigue. Furthermore, at a low refresh rate, fast-moving images may appear blurry or ghosted.

[0053] When a display has a high refresh rate, the persistence of vision fills in the short time intervals between each image frame, making the image appear smoother and more stable, thus reducing flicker and improving visual comfort. Furthermore, a higher refresh rate provides more image frames, making fast-moving images appear smoother and clearer. The persistence of vision works even better at high refresh rates, reducing ghosting and blurring, achieving smooth image transitions, and improving visual comfort.

[0054] 2. On and off states.

[0055] A transistor is considered to be in a conducting state when its source and drain are electrically connected. A transistor is considered to be in a cut-off state when its source and drain are electrically disconnected.

[0056] It is understandable that leakage current can still exist when a transistor is turned off. If the transistor is an N-type transistor (e.g., an oxide transistor), the turn-on condition is: Vgs > Vth. If the transistor is a P-type transistor (e.g., an LTPO transistor), the turn-on condition is: Vgs < Vth. Vgs is the voltage difference between the gate and source of the transistor; Vth is the threshold voltage. The threshold voltage can also be called the turn-on voltage, or simply the turn-on voltage.

[0057] In the embodiments of this application, the high level can satisfy the conduction condition of an N-type transistor, and the low level can satisfy the conduction condition of a P-type transistor. Transistor conduction can be referred to as transistor enabling. Transistor non-conducting or being in a cutoff state can be referred to as transistor disabling.

[0058] 3. Other terms

[0059] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with substantially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order of execution. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0060] It should be noted that, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0061] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, and c can be single or multiple.

[0062] 4. Electronic equipment

[0063] The electronic devices in this application embodiment may include handheld devices with display functions, vehicle-mounted devices, etc. For example, some electronic devices include: mobile phones, tablet computers, PDAs, laptops, mobile internet devices (MIDs), wearable devices (e.g., smartwatches, smart glasses, smart bracelets, or smart jewelry), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, and personal digital assistants (PDAs). The embodiments of this application do not limit this to personal assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, vehicle-mounted devices, terminal devices in 5G networks or terminal devices in future evolved public land mobile networks (PLMNs).

[0064] The electronic devices in the embodiments of this application may also be referred to as: terminal equipment, user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device, etc.

[0065] In this embodiment, the electronic device or various network devices include a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as Linux, Unix, Android, iOS, or Windows. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0066] Mobile phones, computers, and other electronic devices are equipped with display panels to display images. In some embodiments, the pixel circuits in the display panel are refreshed by controlling the line-by-line scanning method, thereby achieving image refresh display.

[0067] However, during the image refresh process, the display panel may experience situations where multiple rows of pixel circuits fail to emit light, resulting in larger black bars on the display panel (or wider black bars), which affects the comfort of the human eye.

[0068] For ease of understanding, the following will be combined with Figures 1 to 3 The structure of the display panel, the pixel circuit, and the refresh display process of the pixel circuit are explained.

[0069] For example, Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 1 As shown, the display panel may include a display area DA and a peripheral area PA. The peripheral area PA is located outside the display area DA and at least partially surrounds the display area DA.

[0070] The peripheral area PA is used to generate drive signals (e.g., scan signals Scan1 to Scan5, etc.) to drive the display area DA to display the image. Specifically, the peripheral area PA can transmit the drive signals to each pixel circuit in the display area DA via leads to control whether the light-emitting elements in the pixel circuits emit light.

[0071] The display area DA is used to display images. For example, the display area DA includes multiple pixel circuits and wiring capable of applying drive signals to the multiple pixel circuits. The structure of the pixel circuits and the control process of the drive signals on the pixel circuits can be referred to below. Figure 2 or Figure 3 The embodiments shown are not described in detail here.

[0072] In some embodiments, the display panel further includes a display driver chip (not shown). The display driver chip can control the generation of drive signals.

[0073] In this embodiment, the peripheral area PA is provided with multiple levels of row driving circuits, and the display area DA is provided with multiple sets of pixel circuits. The multiple levels of row driving circuits are connected one-to-one with the multiple sets of pixel circuits. Each set of pixel circuits includes one or more rows of pixel circuits.

[0074] The row drive circuit is used to generate drive signals to control whether the light-emitting elements in a group of pixel circuits connected to the row drive circuit emit light or not.

[0075] It is understandable that multi-level row drive circuits are cascaded. Specifically, the input terminal of any level row drive circuit is used to input the drive signal output by the row drive circuit of the previous level; the drive signal output by the output terminal of any level row drive circuit is the drive signal input to the input terminal of the next level row drive circuit.

[0076] The following is combined with Figure 2 and Figure 3 The pixel circuit and its refresh display are explained.

[0077] For example, Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 2 As shown, the pixel circuit includes: a light-emitting element 201, a storage capacitor Cst, and multiple thin film transistors (TFTs).

[0078] The light-emitting element 201 may include an organic light-emitting diode (OLED). No specific limitation is made to the light-emitting element. Multiple thin-film transistors may include transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, and transistor T8.

[0079] like Figure 2 As shown, transistor T1, connected to node N1, is used to apply an initialization voltage Vref1 to node N1 in response to the scan signal Scan4. The scan signal Scan4 can also be called the ResetN signal.

[0080] Capacitor Cst is connected at one end to node N1 and at the other end to the positive terminal VDD of the power supply. Node N1 can also be called node N1 or point N1.

[0081] Transistor T5, connected to the positive terminal VDD and node N2, is used to apply the first power supply voltage from the positive terminal VDD to node N2 in response to the scan signal Scan1. The scan signal Scan1 can also be called the light emission control signal, EM signal, etc. Node N2 can also be called node N2 or point N2.

[0082] Transistor T3 connects nodes N1, N2, and N3, and is used to output current to node N3 under the control of node N1. Node N3 can also be called node N3 or point N3.

[0083] Transistor T2, connecting nodes N1 and N3, is used to turn on nodes N3 and N1 in response to the scan signal Scan2. The scan signal Scan2 can also be called the GateN signal.

[0084] Transistor T6 connects nodes N3 and N4, and is used to turn on nodes N3 and N4 in response to the scan signal Scan1. Node N4 can also be called node N4 or point N4.

[0085] The light-emitting element 201 is connected to node N4 at one end and to the negative terminal of the power supply VSS at the other end to load the initial voltage Vref2 of the negative terminal of the power supply VSS.

[0086] Transistor T7, connected to the fourth node N4, is used to apply an initialization voltage Vref2 to node N4 in response to the scan signal Scan3. The scan signal Scan3 can also be called the ResetP signal.

[0087] Transistor T4, connected to node N2, is used to apply the data voltage Vdata to node N2 in response to the scan signal Scan5. The scan signal Scan5 can also be called the GateP signal.

[0088] Transistor T8, connected to node N2, is used to apply an initialization voltage Vref3 to node N2 in response to the scan signal Scan3.

[0089] In this embodiment, transistor T3 is a driving thin-film transistor (DTFT) that drives the light-emitting element to emit light. Transistor T2 is a compensation transistor that controls the charging of capacitor Cst and the conduction of transistor T3. Transistors T1 and T2 may include oxide transistors. Other transistors (transistors T3 to T8) may include transistors using low-temperature poly-silicon (LTPS) technology.

[0090] It is understandable that the above Figure 2In the pixel circuit shown, any transistor can be replaced with a field-effect transistor. This field-effect transistor may include multiple transistors in parallel, or a chip with corresponding functions, etc. The specific replacement structure for the transistors is not limited here. Figure 2 The pixel circuit shown includes 8 transistors and 1 capacitor, therefore it can be called an 8T1C pixel circuit. Besides the 8T1C structure, the pixel circuit can also be a 7T1C (including 7 transistors and 1 capacitor), 10T1C (including 10 transistors and 1 capacitor), 6T2C (including 6 transistors and 2 capacitors), or 2T1C structure, etc. This application does not limit the specific structure of the pixel circuit in its embodiments.

[0091] It should be noted that during the refresh process of each frame of the image, each row of pixel circuits needs to undergo processes such as reset, compensation, data writing, and light emission display. During the reset, compensation, and data writing processes, the pixel circuits do not emit light.

[0092] For example, Figure 2 Provided for the embodiments of this application Figure 1 The diagram shows the timing sequence of the driving signals corresponding to the pixel circuit. Taking the example that the pixel circuit can include a reset phase, a write phase, a light-emitting wait phase, and a light-emitting phase each time the electronic device refreshes an image frame.

[0093] The reset phase is as follows:

[0094] The scan signal Scan1 is high. Transistors T5 and T6 are in the off state.

[0095] The scan signal Scan4 changes from low to high. The high level of the scan signal Scan4 turns on transistor T1.

[0096] The scan signal Scan3 changes from high to low and then back to high. The low-level start time of Scan3 is earlier than the high-level start time of Scan4. The low level of Scan3 turns on transistors T8 and T7.

[0097] The scan signal Scan2 changes from low to high. The high level of scan signal Scan2 starts earlier than the high level of scan signal Scan4. The high level of scan signal Scan2 turns on transistor T2, which in turn turns on nodes N1 and N3.

[0098] In some embodiments, during the reset phase, the scan signal Scan2 may also change from high to low and then from low to high. The start and end times of the low level both fall within the high-level period of the scan signal Scan4.

[0099] The scan signal Scan5 is high. Transistor T4 is in the off state.

[0100] The conducting transistor T1 applies an initialization voltage Vref1 to node N1, resetting node N1 and clearing the potential written in the previous frame. This also applies the initialization voltage Vref1 to capacitor Cst. The conducting transistor T2 also applies the initialization voltage Vref1 to node N3, resetting node N3 and clearing any residual signals that may have existed in the previous stage.

[0101] The conducting transistor T8 applies the initialization voltage Vref3 to node N2, writing the initialization voltage Vref3 to node N2. At this time, the gate-source voltage difference Vgs of transistor T3 is the voltage difference between nodes N1 and N2, that is, Vgs is the voltage difference between the initialization voltages Vref1 and Vref3. Since Vgs is greater than the threshold voltage Vth of transistor T3, transistor T3 is not conducting.

[0102] The conducting transistor T7 applies the initialization voltage Vref2 to node N4, writing the initialization voltage Vref2 to node N4.

[0103] The writing phase is as follows:

[0104] The scan signal Scan1 remains high. Transistors T5 and T6 are in the off state.

[0105] The scan signal Scan4 changes from high level to low level, causing transistor T1 to be in the off state.

[0106] The scan signal Scan3 remains high. Transistors T8 and T7 are both in the off state.

[0107] The scan signal Scan2 remains high. The high level of the scan signal Scan2 turns on transistor T2, which in turn turns on N1 and N3.

[0108] The scan signal Scan5 changes from high to low and then back to high. The low level of Scan5 turns on transistor T4. The turned-on transistor T4 applies the data voltage Vdata to node N2. Since capacitor Cst can discharge to transistor T3, transistor T3 is turned on. Therefore, the turned-on transistor T4 feeds the data voltage Vdata back to node N1 through transistors T3 and T2, and charges capacitor Cst. The voltage at node N1 is Vdata + Vth, where Vth is the threshold voltage of transistor T3. When transistor T4 is on, the voltage at node N2 is Vdata.

[0109] The luminescence waiting phase is as follows:

[0110] The scan signal Scan1 remains high. Transistors T5 and T6 are in the off state.

[0111] The scan signal Scan4 remains low, and transistor T1 is in the off state.

[0112] The scan signal Scan3 changes from high to low and then back to high. A low level in Scan3 turns on transistors T8 and T7. A high level in Scan3 turns both transistors T8 and T7 off.

[0113] When the scan signal Scan2 is low, transistor T2 is in the off state.

[0114] The scan signal Scan5 remains high. Transistor T4 is in the off state.

[0115] The conducting transistor T8 applies the initialization voltage Vref3 to node N2, writing the initial state voltage Vref3 to node N2.

[0116] The conducting transistor T7 applies the initialization voltage Vref2 to node N4, writing the initial state voltage Vref2 to node N4. This allows the light-emitting element to be reset before it emits light, thereby reducing the impact of any residual signals from the previous stage on the light-emitting element's emission.

[0117] Capacitor Cst can discharge transistor T3. When the gate-source voltage difference of transistor T3 is greater than the threshold voltage Vth of transistor T3, transistor T3 will not conduct.

[0118] The luminescence stages are as follows:

[0119] Capacitor Cst can maintain the N1 voltage of transistor T3.

[0120] The scan signal Scan1 changes from high to low. The low level of the scan signal Scan1 turns on transistors T5 and T6. The voltage at the positive terminal of the power supply (VDD) is written to node N2, and transistor T3 turns on because Vgs < Vth.

[0121] The scan signal Scan4 remains low. Transistor T1 is in the off state.

[0122] The scan signal Scan3 remains high. Transistors T7 and T8 are in the off state.

[0123] The scan signal Scan2 remains low. Transistor T2 is in the off state.

[0124] The scan signal Scan5 remains high. Transistor T4 is in the off state.

[0125] Transistor T5, which is conducting, applies the voltage from the positive terminal of the power supply to node N2. Transistor T3 is also conducting. Transistor T6, which is conducting, connects N3 and node N4. The voltage from the negative terminal of the power supply is applied to one end of the light-emitting element. The light-emitting element begins to emit light.

[0126] When the light-emitting element 201 emits light, the transistor T3 divides the voltage, so the brightness of the light-emitting element 201 is controlled by the transistor T3. The voltage division of the transistor T3 is affected by the gate voltage of the transistor T3, i.e., the N1 voltage. For example, the greater the gate-source voltage difference of the transistor T3, the smaller the current flowing through the transistor T3. Since the light-emitting element 201 is connected in series with the transistor T3, the current flowing through the light-emitting element 201 is also smaller, and thus the brightness of the light-emitting element 201 is lower.

[0127] From the above Figure 3 As shown in the timing diagram, when the scan signal Scan1 is high, the light-emitting element 201 does not emit light; when the scan signal Scan1 is low, the light-emitting element 201 emits light. Therefore, the state of the scan signal Scan1 can be used to confirm whether the light-emitting element 201 emits light or not.

[0128] In a possible design, the number of stages in the row drive circuit in the peripheral area PA corresponds sequentially to the number of rows of the pixel circuit in the display area DA. Alternatively, it can be understood that the number of stages in the drive circuit in the peripheral area PA is positively or negatively correlated with the number of rows of the pixel circuit in the corresponding display area DA.

[0129] For example, Figure 4 This is a schematic diagram illustrating the correspondence between the level order and the row order in a possible design. Taking a single-level driver circuit driving two rows of pixel circuits as an example, as follows... Figure 4 As shown, the A-th level driving circuit corresponds to the pixel circuits in rows 2A-1 and 2A. A is a positive integer.

[0130] Specifically, Figure 4 In this diagram, the first-level driving circuit corresponds to the pixel circuits in rows 1 and 2; the second-level driving circuit corresponds to the pixel circuits in rows 3 and 4; the third-level driving circuit corresponds to the pixel circuits in rows 5 and 6; the tenth-level driving circuit corresponds to the pixel circuits in rows 79 and 80; the forty-first-level driving circuit corresponds to the pixel circuits in rows 81 and 82; the forty-second-level driving circuit corresponds to the pixel circuits in rows 83 and 84; the forty-first-level driving circuit corresponds to the pixel circuits in rows 159 and 160; and the eighty-first-level driving circuit corresponds to the pixel circuits in rows 161 and 162.

[0131] For example, Figure 5 This is a timing diagram of the drive signals output by each stage of the drive circuit in a possible design.

[0132] like Figure 5 As shown, at time T1, the scan signal Scan1 output by the first-stage driving circuit switches from low to high, and the pixel circuits in rows 1 and 2 do not emit light. At time T2, the scan signal Scan1 output by the second-stage driving circuit switches from low to high, and the pixel circuits in rows 3 and 4 do not emit light. At time T3, the scan signal Scan1 output by the third-stage driving circuit switches from low to high, and the pixel circuits in rows 5 and 6 do not emit light.

[0133] At time T4, the scan signal Scan1 output by the first-stage driver circuit switches from high to low, and the pixel circuits in rows 1 and 2 illuminate. At time T5, the scan signal Scan1 output by the second-stage driver circuit switches from high to low, and the pixel circuits in rows 3 and 4 illuminate. At time T6, the scan signal Scan1 output by the third-stage driver circuit switches from high to low, and the pixel circuits in rows 5 and 6 illuminate.

[0134] from Figure 5 As shown in the timing diagram, from time T3 to time T4, since the Scan1 signal output by the first to third stage driving circuits is at a high level, the pixel circuits in rows 1 to 6 do not emit light, and the areas corresponding to the pixel circuits in rows 1 to 6 are black areas.

[0135] It is understandable that the area of ​​the black region is related to the area of ​​the non-light-emitting pixel circuit, and whether the pixel circuit emits light or not is controlled by the scan signal Scan1 output by its corresponding drive signal.

[0136] In some embodiments, assuming a display refresh rate of 120Hz, the duration (also known as the width of the scan signal Scan1) of the high level is typically 72 clock cycles (or 72H); and the scan signal Scan1 output by each driving circuit typically has a two-clock-cycle delay with the scan signal Scan1 output by the driving circuit above it. When each driving circuit drives two rows of pixel circuits, it is possible for 36 consecutive driving circuits to simultaneously output a high-level scan signal Scan1, which could result in 72 consecutive rows of pixel circuits remaining unlit, creating a black area.

[0137] A clock cycle can be understood as the time it takes for each row of pixel circuits to refresh during a single refresh of the display panel. For example, taking a display panel with a refresh rate of 120Hz and 2880 rows of pixel circuits as an example, one clock cycle is... Taking a display panel with a refresh rate of 60Hz and a 1440-line pixel circuit as an example, one clock cycle is...

[0138] In view of this, embodiments of this application provide a display circuit, a display panel, a display screen, and an electronic device. By adjusting the correspondence between the number of stages of the driving circuit and the number of rows of the pixel circuit, the number of stages of the driving circuit and the number of rows of the pixel circuit are not sequentially corresponding, thereby reducing the number of cases where the scan signal Scan1 output by the driving circuit corresponding to multiple consecutive rows of pixel circuits is simultaneously at level A, reducing the number of cases where multiple consecutive rows of pixel circuits do not emit light, and reducing the area of ​​the black region.

[0139] For example, Figure 6 This is a schematic diagram of a display circuit provided in an embodiment of this application. Figure 6 As shown, the display circuit includes a peripheral area PA and a display area DA. The peripheral area PA includes a multi-level driving circuit; the display area DA includes multiple sets of pixel circuits. Each multi-level driving circuit corresponds one-to-one with each set of pixel circuits, and each set of pixel circuits may include one or more consecutive rows of pixel circuits.

[0140] In this embodiment, among the driving circuits corresponding to two consecutive groups of pixel circuits, there exists a difference between the number of stages of the driving circuits corresponding to two groups of pixel circuits that is greater than or equal to the difference C. B is an integer greater than 1, B is an integer less than C, and the difference C is the ratio of the duration of the high level of the scan signal Scan1 within one cycle to the delay of each stage of the driving circuit.

[0141] In this way, in the continuous B-group pixel circuits, there are two groups of pixel circuits whose corresponding driving circuits have a delay greater than or equal to the duration of the scanning signal Scan1 being at a high level (the width of the scanning signal Scan1). The driving circuits corresponding to these two groups of pixel circuits will not be at a high level at the same time, thereby reducing the situation where the continuous B-group pixel circuits do not emit light at the same time, reducing the width of the black bar caused by the pixel circuits not emitting light, and improving the user experience.

[0142] For example, assuming the scan signal Scan1 is high for 72 hours, each pixel circuit group can include 2 rows of pixel circuits, resulting in 2880 rows of pixel circuits, with N being 1 and the delay of each driving circuit stage being 2 hours, the difference C is 36 and B is 36. Therefore, in the driving circuits corresponding to 36 consecutive pixel circuit groups, there exists a difference in the number of stages between two sets of pixel circuit groups that is greater than or equal to 36.

[0143] like Figure 6 As shown, if the difference between the number of stages of the driving circuits corresponding to the first and fifth pixel circuits is 36, and the number of stages of the driving circuits corresponding to the first pixel circuit is 1, then the first stage driving circuit corresponds to the first and second row pixel circuits; the 37th stage driving circuit corresponds to the 9th and 10th row pixel circuits.

[0144] For example, Figure 7 This is a timing diagram of the drive signal output by a drive circuit provided in an embodiment of this application. For example... Figure 7 As shown, at time T1, the scan signal Scan1 output by the first-stage driving circuit switches from low to high, and the pixel circuits in the first and second rows do not emit light. The scan signal Scan1 output by the 37th-stage driving circuit is low, and the pixel circuits in the third and fourth rows emit light.

[0145] At time T2, the Scan1 signal output by the first-stage driving circuit switches from high level to low level, and the pixel circuits of the first and second rows emit light; the Scan1 signal output by the 37th-stage driving circuit switches from low level to high level, and the pixel circuits of the third and fourth rows do not emit light.

[0146] In this way, when the first group of pixel circuits does not emit light, the fifth group of pixel circuits emits light, which can reduce the situation where multiple consecutive groups of pixel circuits do not emit light, reduce the black bar area caused by the pixel circuits not emitting light, and improve the user experience.

[0147] In some embodiments, multiple sets of pixel circuits are divided into multiple pixel units according to group number order. Each pixel unit includes at least two consecutive sets of pixel circuits. The difference between the stages of the driving circuits corresponding to two adjacent sets of pixel circuits in any pixel unit is equal to the difference C. C is the ratio of the duration of the high level of the scan signal Scan1 within one cycle to the delay of each stage of the driving circuit.

[0148] In this way, the delay of the driving circuit corresponding to two adjacent groups of pixel circuits in the same pixel unit is the duration of the scanning signal Scan1 being at a high level (the width of the scanning signal Scan1). The driving circuits corresponding to two adjacent groups of pixel circuits will not be at a high level at the same time, thereby reducing the situation where two adjacent groups of pixel circuits do not emit light at the same time, reducing the width of the black bar caused by the pixel circuit not emitting light, and improving the user experience.

[0149] For example, Figure 8 This is a schematic diagram of a display circuit provided in an embodiment of this application. Taking the duration of the scan signal Scan1 being at a high level as 72H, each group of pixel circuits may include 2 rows of pixel circuits, 2880 rows of pixel circuits, N is 1, and the delay of each driving circuit stage is 2H as an example, the delay of the driving circuits corresponding to two adjacent groups of pixel circuits is 2H.

[0150] like Figure 8As shown, the first-level driving circuit corresponds to the pixel circuits in rows 1 and 2; the 37th-level driving circuit corresponds to the pixel circuits in rows 3 and 4; the 73rd-level driving circuit corresponds to the pixel circuits in rows 5 and 6; the 1405th-level driving circuit corresponds to the pixel circuits in rows 79 and 80; the second-level driving circuit corresponds to the pixel circuits in rows 81 and 82; the 38th-level driving circuit corresponds to the pixel circuits in rows 83 and 84; the 1406th-level driving circuit corresponds to the pixel circuits in rows 159 and 160; and the third-level driving circuit corresponds to the pixel circuits in rows 161 and 162.

[0151] For example, Figure 9 Timing diagrams of the drive signals output by each stage of the drive circuit provided in the embodiments of this application.

[0152] like Figure 9 As shown, at time T1, the scan signal Scan1 output by the first-stage driving circuit switches from low to high, and the pixel circuits in the first and second rows do not emit light. The scan signal Scan1 output by the 37th-stage driving circuit is low, and the pixel circuits in the third and fourth rows emit light.

[0153] At time T2, the scan signal Scan1 output by the first-stage driver circuit switches from high to low, and the pixel circuits in rows 1 and 2 illuminate. The scan signal Scan1 output by the third-stage driver circuit switches from low to high, and the pixel circuits in rows 3 and 4 do not illuminate. The scan signal Scan1 output by the seventh-stage driver circuit is low, and the pixel circuits in rows 5 and 6 do not illuminate.

[0154] At time T3, the Scan1 signal output by the 37th stage driving circuit switches from high level to low level, and the pixel circuits in the 3rd and 4th rows illuminate; the Scan1 signal output by the 73rd stage driving circuit switches from low level to high level, and the pixel circuits in the 5th and 6th rows illuminate.

[0155] from Figure 9 As shown in the timing diagram, the delay of the driving circuits corresponding to two adjacent sets of pixel circuits is equal to the duration of the scan signal Scan1 at level A. This ensures that when one set of pixel circuits is not emitting light, the adjacent set emits light, reducing the likelihood of multiple consecutive sets of pixel circuits not emitting light, minimizing the black bar area caused by non-emitting pixel circuits, and improving the user experience.

[0156] In some embodiments, each pixel unit includes D groups of pixel circuits. D is an integer greater than 1.

[0157] The above Figure 8The illustrated embodiment is based on the example of each pixel unit comprising 40 groups of pixel circuits. A pixel unit may also include more or fewer groups of pixel circuits, for example, 30, 20, 2, etc. No specific limitation is made here. The number of groups of pixel circuits included in each pixel unit may be the same or different. No specific limitation is made here.

[0158] For example, taking a pixel unit comprising 30 sets of pixel circuits as an example, Figure 10 This is a schematic diagram of another display circuit provided in an embodiment of this application. Figure 10 As shown, the first-level driving circuit corresponds to the pixel circuits in rows 1 and 2; the 37th-level driving circuit corresponds to the pixel circuits in rows 3 and 4; the 73rd-level driving circuit corresponds to the pixel circuits in rows 5 and 6; the 1045th-level driving circuit corresponds to the pixel circuits in rows 59 and 60; the second-level driving circuit corresponds to the pixel circuits in rows 61 and 62; the 38th-level driving circuit corresponds to the pixel circuits in rows 63 and 64; the 1046th-level driving circuit corresponds to the pixel circuits in rows 119 and 120; and the third-level driving circuit corresponds to the pixel circuits in rows 121 and 122.

[0159] It is understood that the above embodiments are illustrated by assuming that the driving circuits are arranged in a forward order when the conditions are met. However, the driving circuits may not be arranged in a forward order when the conditions are met. No specific limitation is made here.

[0160] In some embodiments, multiple pixel circuits are divided into C pixel units. C is the ratio of the duration of the high level of the scan signal Scan1 within one cycle to the delay of each driving circuit stage. This minimizes the number of pixel units, reducing the possibility of adjacent pixel circuits in different pixel units being at a high level simultaneously, and reducing the phenomenon of large black areas caused by pixel circuits at the edges of different pixel units not emitting light, thus improving the user experience.

[0161] In some embodiments, the correspondence between the number of stages of the driving circuit and the number of rows is as follows: Where GOA(n) is the number of stages of the driving circuit, N is the number of rows of pixel circuits, E is the total number of rows of pixel circuits in the display area DA, G is the number of rows of pixel circuits included in each group of pixel circuits, F is the time delay of the scan signal Scan1 corresponding to two adjacent stages of the driving circuit, and M is the duration of the scan signal Scan1 at level A. When the scan signal Scan1 is at level A, the pixel circuit corresponding to the driving circuit does not emit light.

[0162] In this way, the number of driving circuit stages and rows in the same pixel unit are arranged in a forward direction, which makes it convenient for electronic devices to store the relationship between the number of driving circuit stages and rows, and to write the data corresponding to each row of pixel circuits.

[0163] It should be noted that when the actual number of pixel circuits in the display panel is an integer multiple of the first value, the total number of pixel circuits in the display area DA is the actual number of pixel circuits in the display panel. The first value is the ratio between the duration during which the scan signal Scan1 indicates no light emission (e.g., the duration of being at a high level) and the clock cycle. It can also be understood as the ratio between E and M mentioned above.

[0164] The actual number of rows of pixel circuits in the display panel may not be an integer multiple of the first value. The total number of rows of pixel circuits in the display area DA is the sum of the actual number of rows of pixel circuits in the display panel and the number of rows of supplementary pixel circuits. Specifically, when calculating the clock cycle, some supplementary rows may be added to make the total number of rows of pixel circuits in the display panel an integer multiple of the first value. For example, taking a display panel with a refresh rate of 120Hz, 2840 rows of pixel circuits, and the Scan signal Scan1 being high for 72 hours, since 2840 is not an integer multiple of 72, 40 rows of supplementary pixel circuits are added for clock cycle calculation, E becomes 2880, and the clock cycle is...

[0165] In some embodiments, if M is 72H, the correspondence between the number of stages and the number of rows in the driving circuit is as follows: The meanings of GOA(n), N, E, G, and F can be found in the above explanations, and will not be repeated here.

[0166] It is understandable that the duration of the high level of the scan signal Scan1 is usually 72 clock cycles. If the duration of the high level of the scan signal Scan1 is less than 72 clock cycles, the reset, compensation, and data writing processes of the pixel circuit will be shorter. The transistors in the pixel circuit may have insufficient reset time, compensation time, and data reset time, resulting in poor display effect.

[0167] It's important to note that the reset time is used to reset the transistors in the pixel circuit. Insufficient reset time can lead to ghosting, decreased image contrast, color distortion, and display instability. Specifically, insufficient reset time may result in incomplete clearing of image information from the previous frame, leaving residue in the pixel circuit. When displaying a new image, the ghosting from the previous frame may be superimposed on the new image, causing blurring or ghosting. Furthermore, insufficient reset time prevents the pixel circuit from fully returning to its initial state, affecting its responsiveness. The brightness and color of the pixel circuit cannot be accurately displayed, leading to color distortion, decreased contrast, and an image that appears unclear and dull. Insufficient reset time can also cause instability in the pixel circuit during display (e.g., flickering, noise, or other unstable phenomena).

[0168] It's important to note that the reset time is used to write image data. Insufficient write time can lead to image blurring, decreased contrast, color distortion, and flickering. Specifically, insufficient write time may cause the pixel circuitry to fail to fully receive image data. The image displayed by the pixel circuitry may be incomplete or inaccurate, resulting in blurring or distortion. Furthermore, insufficient write time reduces the accuracy of color data received by the pixel circuitry, leading to color distortion, decreased contrast, and poor image quality. Insufficient write time can also cause the pixel circuitry to be unable to display data stably during the refresh process, resulting in flickering and other unstable phenomena.

[0169] It should be noted that compensation time is typically used to correct various non-ideal effects in pixel circuits, such as voltage drift, temperature variations, and aging effects. Insufficient compensation time may lead to…

[0170] It is understandable that the above Figures 6 to 10 The embodiment shown is illustrated with an example of each group of pixel circuits including two rows of pixel circuits. Each group of pixel circuits may also include more or fewer rows of pixel circuits, which is not specifically limited here.

[0171] The above Figures 8 to 10 In the embodiment shown, the difference between the levels corresponding to two adjacent sets of pixel circuits is used as an example to illustrate the ratio of the width of the scan signal Scan1 to the delay of each driving circuit.

[0172] In some embodiments, multiple groups of pixel circuits are divided into two pixel units according to their group numbers. The difference between the levels corresponding to two adjacent groups of pixel circuits in any pixel unit can also be an integer greater than 1.

[0173] For example, multiple pixel circuits are divided into pixel unit A and pixel unit B. The nth pixel circuit in pixel unit A corresponds to the 2n-1th stage driving circuit; the n-720th pixel circuit in pixel unit B corresponds to the 2n-1440th stage driving circuit.

[0174] For example, Figure 11 This is a schematic diagram of a display circuit provided in an embodiment of this application. Taking D as 2, each group of pixel circuits includes two rows of pixel circuits, and taking 2880 rows of pixel circuits as an example, multiple groups of pixel circuits can be divided into pixel unit A and pixel unit B. Pixel unit A includes pixel circuits from group 1 to group 720, and pixel unit B includes pixel circuits from group 721 to group 1440.

[0175] like Figure 11 As shown, the first-level driving circuit corresponds to the first group of pixel circuits (the first and second rows of pixel circuits); the third-level driving circuit corresponds to the second group of pixel circuits (the third and fifth rows of pixel circuits); and the fifth-level driving circuit corresponds to the third group of pixel circuits (the fifth and sixth rows of pixel circuits).

[0176] The second-level driving circuit corresponds to the 721st group of pixel circuits (rows 1441 and 1442); the fourth-level driving circuit corresponds to the 722nd group of pixel circuits (rows 1443 and 1444); and the sixth-level driving circuit corresponds to the 723rd group of pixel circuits (rows 1445 and 1446).

[0177] Understandably, if the Scan signal Scan1 is high for 72 hours, and the delay between adjacent drive circuits is 2 hours, then... Figure 11 In the circuit shown, there may be a situation where 18 consecutive driving circuits simultaneously output a high-level scan signal Scan1, which may result in 36 consecutive rows of pixel circuits not emitting light at the same time, and the area corresponding to the 36 consecutive rows of pixel circuits is a black area.

[0178] Thus, compared to the above Figure 4 The display circuit shown is Figure 11 The circuit shown reduces the black areas appearing on the display panel during pixel refresh.

[0179] The above Figure 11 This explanation uses two pixel units as an example, but it can also be divided into three or more pixel units; no specific limitation is made here.

[0180] It is understood that the above embodiments are illustrated with the example of each group of pixel circuits including two rows of pixel circuits. Each group of pixel circuits may also include more or fewer rows of pixel circuits, and no specific limitation is made here.

[0181] The time delay between the scan signals Scan1 corresponding to two adjacent pixel circuits is taken as the duration of Scan signal Scan1 being at a high level. In some embodiments, the maximum time delay between the scan signals output by the driving circuits corresponding to adjacent D pixel circuits is the scan signal...

[0182] For example, Figure 12A This is a schematic diagram of the structure of a first-stage driving circuit provided in an embodiment of this application. Figure 12A As shown, the driving circuit includes: EM signal unit, ResetN signal unit, GateP signal unit (GateP1 signal and GateP2 signal), GateN signal unit, and ResetP signal unit.

[0183] The EM signal unit, ResetN signal unit, GateP signal unit (GateP1 signal and GateP2 signal), GateN signal unit, and ResetP signal unit are all connected to the pixel circuit.

[0184] The EM signal unit is used to output the scan signal Scan1; the ResetN signal unit is used to output the scan signal Scan4; the GateP unit is used to output the scan signal Scan5; the GateN signal unit is used to output the scan signal Scan2; and the ResetP signal unit is used to output the scan signal Scan3.

[0185] Scan signals Scan3 and Scan4 are used to control the pixel circuit reset; Scan signal Scan5 is used to control the pixel circuit to write data; Scan signal Scan2 is used to lock the data in the pixel circuit. The specific implementation of Scan signals Scan1 to Scan5 in the pixel circuit's reset, writing, light emission waiting, and light emission processes can be found above. Figure 3 The description in the text will not be repeated here.

[0186] In this embodiment of the application, the EM signal unit can be a 16T3C structure (such as...). Figure 12B The circuit shown includes 16 transistors and 3 capacitors, 13T2C (including 13 transistors and 2 capacitors), 10T2C, or other arbitrary structures; no specific limitation is made here. The ResetN signal unit, GateP signal unit (GateP1 and GateP2 signals), GateN signal unit, and ResetP signal unit can be of 16T3C structure (e.g., ...). Figure 12BThe circuit shown includes 16 transistors and 3 capacitors, 13T2C (including 13 transistors and 2 capacitors), 10T2C or other arbitrary structures, without specific limitations.

[0187] If a set of pixel circuits includes two rows of pixel circuits, then the GateP unit may include a GateP1 signal unit and a GateP2 signal unit. The GateP1 signal unit is connected to one row of pixel circuits; the GateP2 signal unit is connected to the other row of pixel circuits.

[0188] The GateP1 signal unit is used to output Scan5 for one row of pixel circuits; the GateP2 signal unit is used to output Scan5 for the other row of pixel circuits. In this way, the two rows of pixel circuits share some signals, reducing the number of signal units in the display circuit and thus reducing the area of ​​the display circuit.

[0189] For example, Figure 13 This is a schematic diagram of a cascaded drive circuit structure provided in an embodiment of this application. Figure 13 As shown, adjacent driving circuits transmit signals through cascaded signals, and the output of the (x-1)th driving circuit is the input of the xth driving circuit.

[0190] Specifically, the driving signals include: scan signals Scan1 to Scan5; Scan1, the scan signal output by the EM signal unit in the (x-1)th group of driving circuits, is the input signal of the EM signal unit in the x-th group of driving circuits; Scan2, the scan signal output by the GateN signal unit in the (x-1)th group of driving circuits, is the input signal of the GateN signal unit in the x-th group of driving circuits; Scan5, the scan signal output by the GateP unit in the (x-1)th group of driving circuits, is the input signal of the GateP unit in the x-th group of driving circuits; Scan4, the scan signal output by the ResetN signal unit in the (x-1)th group of driving circuits, is the input signal of the ResetN signal unit in the x-th group of driving circuits; and Scan3, the scan signal output by the ResetP signal unit in the (x-1)th group of driving circuits, is the input signal of the ResetP signal unit in the x-th group of driving circuits.

[0191] It is understood that adjacent driving circuits are connected by connecting lines. In this embodiment, the connecting lines can be located in the peripheral area PA or in the display area DA.

[0192] When the connecting line is located within the display area DA, it can pass through the gaps between pixel circuits. This reduces the area occupied by the connecting line in the peripheral area PA, thereby reducing the size of the peripheral area PA and the bezel width of the electronic device.

[0193] It is understood that the above embodiments are illustrated using row-driven pixel circuits as an example. In some embodiments, pixel circuits may also be driven column-wise. The correspondence between the number of stages in the column driving circuit and the number of columns in the pixel circuit is similar to the correspondence between the number of stages in the row driving circuit and the number of rows in the pixel circuit, and will not be elaborated here.

[0194] For example, Figure 14 This is a schematic diagram of another display circuit provided in an embodiment of this application. Figure 14 As shown, the display circuit includes: a pixel circuit 1401, a driving circuit 1402, and a connecting line 1403. The connection relationship, function, and structure of the pixel circuit 1401 and the driving circuit 1402 can be referred to the above. Figures 5 to 13 The explanation will not be repeated here.

[0195] The connecting line 1403 includes: a first part connecting line 1403-1, a second part connecting line 1403-2, and a third part connecting line 1403-3. The first part connecting line 1403-1, the second part connecting line 1403-2, and the third part connecting line 1403-3 are connected to each other.

[0196] The first part of the connecting line 1403-1 extends along the row direction and passes through the gap between the pixel circuits 1401 to connect to the second part of the connecting line 1403-2; the second part of the connecting line 1403-2 extends along the column direction and passes through the gap between the pixel circuits 1401 to connect to the third part of the connecting line 1403-3; the third part of the connecting line 1403-3 extends along the row direction and passes through the gap between the pixel circuits 1401.

[0197] In the above embodiments, the first, second, and third connecting lines extend linearly and connect at right angles. Alternatively, they can extend in a curved shape and / or connect with rounded corners. The first, second, and third connecting lines can be arranged in a "Z," "V," "Zigzag," or stepped pattern between the pixel circuits 1401. This application does not limit the specific arrangement shape of the first, second, and third connecting lines in its embodiments.

[0198] In this embodiment, the connecting line 1403 can be located in a conductive film layer such as Gate 1 (metal layer, such as molybdenum (Mo) metal), Gate 2 (metal layer, such as molybdenum (Mo) metal), Gate 3 (metal layer, such as molybdenum (Mo) metal), ITO film layer, or SD (metal layer, Metal layer, Ti / Al / Ti titanium / aluminum / titanium). No limitation is made here.

[0199] In some embodiments, the connecting line 1403 can be a trace with low resistance, such as a titanium aluminum titanium (TiAlTi) structure.

[0200] Understandably, low-resistance cables generate less power consumption when transmitting signals, thus reducing power consumption. In addition, low-resistance cables cause less signal attenuation, which can better maintain the amplitude and shape of the signal and improve the quality of signal transmission.

[0201] It is understood that the above embodiments are illustrated by taking the example that the group number of the pixel circuit in each pixel unit is positively correlated with the number of stages of the driving circuit, while the group number of the pixel circuit in each pixel unit is negatively correlated with the number of stages of the driving circuit. No specific limitations are made here.

[0202] It is understood that the above embodiment is illustrated by taking the scanning signal Scan1 at a high level as an example of indicating refresh display. The scanning signal Scan1 can also indicate refresh display at a low level. The implementation principle of the specific circuit is similar to that of the scanning signal Scan1 at a high level indicating refresh display, and will not be described in detail here.

[0203] This application embodiment also provides a display screen, which includes the aforementioned display panel, and the display panel is used to display images. For example, as shown... Figure 15 As shown, the display screen includes, but is not limited to, a protective cover 1501, a polarizer 1502, a display panel 1503, a heat dissipation layer 1504, and a protective layer 1505.

[0204] The polarizer 1502 is fixed to the protective cover 1501. The protective cover 1501 can be a transparent glass cover or a cover made of organic materials such as polyimide, to provide protection while minimizing the impact on the display effect. The polarizer 1502 can be a circular polarizer to prevent anode reflection. The heat dissipation layer 1504 can be made of heat-dissipating copper foil, and the protective layer 1505 can be protective foam. The various layers of the display screen can be bonded together using optically transparent adhesive or non-transparent pressure-sensitive adhesive. Furthermore, since moisture and oxygen in the air significantly affect the lifespan of the light-emitting devices in the display panel 1503, the light-emitting devices of the display panel need to be strictly sealed to prevent moisture and oxygen from entering the display.

[0205] In this embodiment, the display screen can be a flexible display screen or a rigid display screen. For example, the display screen can be an OLED display screen, a quantum dot light emitting diode (QLED) flexible display screen, a rollable screen, a foldable screen, etc.

[0206] This application also provides an electronic device, which includes the aforementioned display screen for displaying images. For example, as shown... Figure 16 As shown, the electronic device includes, but is not limited to, a display screen 1601, a mid-frame 1602, a rear cover 1603, and a printed circuit board (PCB) 1604. The mid-frame 1602 can be used to support the PCB and the display screen 1601, with the display screen 1601 and the PCB located on opposite sides of the mid-frame 1602. The rear cover 1603 is located on the side of the PCB away from the mid-frame 1602. Additionally, the display device may also include components 1605 disposed on the PCB 1604, which may, but are not limited to, be disposed on the side of the PCB 1604 facing the mid-frame 1602.

[0207] It should be noted that the module names involved in the embodiments of this application can all be defined as other names, as long as they can achieve the function of each module, and no specific restrictions are placed on the module names.

[0208] This application provides a display method, which includes: acquiring a first image, the first image being an image obtained by capturing a first display screen in a bright state, the first display screen including: the display circuit described in the above embodiments; displaying the first image; wherein the first display screen in the first image includes: one or more first regions; a first ratio is less than a second ratio, the first ratio being the ratio of the length of each first region in a first direction to the first display screen in the first image, the second ratio being the ratio of the length of C consecutive groups of pixel circuits in the first direction to the length of the first display screen in the first direction, and C being the ratio between the duration of the first signal output by the driving circuit at a first level and the time delay between the first signals output by two adjacent driving circuits; when the first signal is at a first level, the pixel circuit does not emit light, and when the first signal is at a second level, the pixel circuit emits light.

[0209] The first region can correspond to the black region mentioned above. In this way, the black region on the first display screen is smaller in the captured image.

[0210] In one possible implementation, the first ratio is less than or equal to the third ratio, the third ratio is less than the second ratio, and the third ratio is the ratio of the length of two adjacent sets of pixel circuits in the first direction to the length of the first display screen in the first direction.

[0211] This application provides a display method, which includes: acquiring a first image, wherein the first image is an image obtained by capturing images of a first display screen in a bright state and a second display screen in a bright state, the first display screen including: the display circuit described in the above embodiments; and the second display screen including the display circuit described in the above possible design.

[0212] The specifications of the first display screen are the same as those of the second display screen; the first display screen in the first image includes one or more first regions; the second display screen in the first image includes one or more second regions; the length of the first region in the first direction is less than the maximum length of the second region in the first direction.

[0213] Both the first and second regions can correspond to the black areas mentioned above. The first display screen may include: the areas mentioned above. Figures 6 to 14 Any of the display circuits described above; the second display screen may include: Figure 4 The described display circuit.

[0214] For example, Figure 17 This is a schematic diagram of a first image provided in an embodiment of this application. Taking the first direction as the vertical direction as an example, as... Figure 17 As shown, the length of the first region in the vertical direction in the first display screen is less than the length of the second region in the vertical direction in the second display screen.

[0215] Thus, in the image captured, the black area on the first display screen is smaller than the black area on the second display screen.

[0216] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0217] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display circuit, characterized in that, include: Multi-level driving circuit, and multiple sets of pixel circuits; The multi-level driving circuit is connected to the multi-group pixel circuit in a one-to-one correspondence; In the driving circuits corresponding to B consecutive pixel circuits, there exists a difference between the absolute values ​​of the stages of the driving circuits corresponding to two pixel circuits that is greater than or equal to C, where B is an integer greater than 1, B is an integer less than C, and C is the ratio between the duration of the first signal output by the driving circuit at the first level and the time delay between the first signals output by two adjacent driving circuit stages. When the first signal is at a first level, the pixel circuit does not emit light; when the first signal is at a second level, the pixel circuit emits light.

2. The display circuit according to claim 1, characterized in that, The multiple sets of pixel circuits belong to multiple pixel units; each pixel unit includes at least two consecutive sets of pixel circuits. The absolute value of the difference between the stages of the driving circuits corresponding to two adjacent groups of pixel circuits in the pixel unit is C.

3. The display circuit according to claim 2, characterized in that, Wherein, GOA(n) is the number of stages of the driving circuit, N is the number of rows of the pixel circuit, E is the total number of rows of the multiple groups of pixel circuits, G is the number of rows of pixel circuits included in each group of pixel circuits, F is the time delay of the first signal corresponding to two adjacent driving circuit stages, and M is the duration of the first signal at the first level.

4. The display circuit according to any one of claims 1-3, characterized in that, The display circuit further includes: a connecting line, which is used to connect the output terminal of the i-th stage driving circuit to the input terminal of the (i+1)-th stage driving circuit, where i is an integer greater than zero; The connecting line passes through the gaps between the pixel circuits in the plurality of pixel circuits.

5. The display circuit according to any one of claims 1-4, characterized in that, Any group of pixel circuits includes: two consecutive rows of pixel circuits; any level of driving circuit includes: a light emission control signal unit, a first reset signal unit, a second scan signal unit, a third scan signal unit, a first scan signal unit, and a second reset signal unit; The light emission control signal unit, the first reset signal unit, the second scan signal unit, the first scan signal unit, and the second reset signal unit are all connected to the first pixel circuit; The light emission control signal unit, the first reset signal unit, the second scan signal unit, the first scan signal unit, and the second reset signal unit are all connected to the second pixel circuit; The second scanning signal unit is connected to the first pixel circuit, and the third scanning signal unit is connected to the second pixel circuit. The number of rows corresponding to the first pixel circuit and the number of rows corresponding to the second pixel circuit are different. The light emission control signal unit is used to output the first signal; The first reset signal unit is used to output a second signal; the second reset signal unit is used to output a third signal, and the second signal and the third signal are used to control the pixel circuit to reset; The second scanning signal unit and the third scanning signal unit are used to output a fourth signal; the fourth signal is used to control the pixel circuit to write data. The first scanning signal unit is used to output a fifth signal; the fifth signal is used to lock the data of the pixel circuit.

6. A display method, characterized in that, The method includes: Acquire a first image, wherein the first image is an image obtained by capturing a first display screen in a bright state, and the first display screen includes: the display circuit according to any one of claims 1-5; Display the first image; Wherein, the first display screen in the first image includes: one or more first regions; The first ratio is less than the second ratio. The first ratio is the ratio of the length of each of the first regions in the first direction to the length of the first display screen in the first image. The second ratio is the ratio of the length of the C consecutive groups of pixel circuits in the first direction to the length of the first display screen in the first direction. C is the ratio between the duration of the first signal output by the driving circuit at the first level and the time delay between the first signals output by two adjacent driving circuits. When the first signal is at a first level, the pixel circuit does not emit light; when the first signal is at a second level, the pixel circuit emits light.

7. The display method according to claim 6, characterized in that, The first ratio is less than or equal to the third ratio, the third ratio is less than the second ratio, and the third ratio is the ratio of the length of two adjacent sets of pixel circuits in the first direction to the length of the first display screen in the first direction.

8. A display panel, characterized in that, include: The display circuit according to any one of claims 1-5.

9. A display screen, characterized in that, include: The display panel as claimed in claim 8.

10. An electronic device, characterized in that, include: The display screen according to claim 9.

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