Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a relay circuit and a plurality of row pixel driving circuits. The relay circuit is arranged on a source driving signal line in front of a target row pixel driving circuit in the row pixel driving circuits; the relay circuit is used for amplifying the data current of the source electrode driving signal line and then outputting the data current to the far-end row pixel driving circuit; the far-end row pixel driving circuit comprises a target row pixel driving circuit and a pixel driving circuit behind the target row pixel driving circuit. According to the display panel, the data current of the source electrode driving signal line can be amplified through the relay circuit and then output to the far-end row pixel driving circuit, so that the charging time of a pixel capacitor in the far-end row pixel driving circuit can be shortened, the pixel capacitor in the far-end row pixel driving circuit can be quickly charged, and the charging efficiency is improved. The data current which is not amplified is still adopted in the near-end row pixel driving circuit, so that the signal delay at the far end of the large-size display panel is reduced, and the display effect of the display panel is improved.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology and the increasing demand in the consumer display market, large-size Organic Light-Emitting Diodes (OLEDs) have come into the public eye. OLEDs are gradually becoming thinner and lighter. Thinner OLED displays mean thinner source traces, but also higher impedance. At the same time, due to the reliability requirements of large-size OLEDs, there are often thicker encapsulation layers and more photocoupled structures, which will increase the resistance and parasitic capacitance on the data signal transmission path. When data is transmitted over long distances along the source trace, the signal delay at the far end will be higher than the signal delay at the near end of the driver IC. Figure 1 illustrates the far-end signal delay, where the horizontal axis represents time. If a voltage reaching 90% of the target voltage is considered a valid signal, then the near-end gate can reach 90% of the target voltage within approximately 0.1 widths after the falling edge trigger, while the far end may take 0.5 widths to reach 90% of the target voltage. Therefore, there is a signal delay at the far end. This signal delay will increase the charging rise time of the far-end pixel capacitor, causing incorrect charging.

[0003] To address this issue, some related technologies integrate an OE (output enable) signal at the Gate Driver on Array (GOA) terminal on the array substrate, causing the gate to turn off prematurely and ensuring correct data writing. However, this approach reduces the charging rate and causes a decrease in brightness (IR-Drop). Therefore, reducing signal delay at distant points has become a pressing problem for large-size display panels. Summary of the Invention

[0004] This application provides a display panel and display device to solve the technical problem of how to reduce signal delay at the far end of a large-size display panel.

[0005] In a first aspect, this application provides a display panel, the display panel including a relay circuit and a plurality of row pixel driving circuits; the relay circuit is disposed on a source driving signal line before a target row pixel driving circuit in the row pixel driving circuit; the relay circuit is used to amplify the data current of the source driving signal line and output it to a remote row pixel driving circuit; the remote row pixel driving circuit includes the target row pixel driving circuit and a pixel driving circuit after the target row pixel driving circuit.

[0006] Optionally, the relay circuit includes a first switch, a first resistor, and a second resistor; a first terminal of the first switch is connected to a first terminal of the first resistor, the input terminal of the target row pixel driving circuit, and the source driving signal line; a second terminal of the first resistor is connected to a first negative power supply; a second terminal of the first switch is connected to a first positive power supply and a first terminal of the second resistor; a second terminal of the second resistor is connected to a third terminal of the first switch and the source driving circuit; the third terminal of the first switch amplifies the current output from the source of the first switch under the action of the source driving circuit.

[0007] Optionally, the display panel further includes a feedback compensation circuit; the feedback compensation circuit is used to calibrate the gate voltage of the distal row pixel driving circuit so that the gate voltage of the distal row pixel driving circuit is consistent with the gate voltage of the proximal row pixel driving circuit; wherein, the proximal row pixel driving circuit is the row pixel driving circuit preceding the target row pixel driving circuit.

[0008] Optionally, the feedback compensation circuit is located in the driver chip where the source drive circuit is located.

[0009] Optionally, the relay circuit in each column of source drive signal lines corresponds to one of the feedback compensation circuits.

[0010] Optionally, when the relay circuits in the source drive signal lines of different columns are all in different target row pixel drive circuits, the multiple relay circuits correspond to one feedback compensation circuit.

[0011] Optionally, the feedback compensation circuit includes a second switch, a first capacitor, a first transistor, and an error amplifier; the third terminal of the second switch is connected to the transmit control signal of the source drive signal line, the first terminal of the second switch is connected to the first terminal of the first capacitor and the second input terminal of the error amplifier; the second terminal of the first capacitor is grounded; the first input terminal of the error amplifier is connected to the first terminal of the first switch; the output terminal of the error amplifier is connected to the base of the first transistor, the emitter of the first transistor is connected to the third terminal of the first switch, and the collector of the first transistor is connected to the second terminal of the second switch and the source drive signal line.

[0012] Optionally, the first switch is an NMOS transistor; the first terminal of the first switch is the source of the NMOS transistor, the second terminal of the first switch is the drain of the NMOS transistor, and the third terminal of the first switch is the gate of the NMOS transistor.

[0013] Optionally, the second switch is an NMOS transistor; the first terminal of the second switch is the source of the NMOS transistor, the second terminal of the second switch is the drain of the NMOS transistor, and the third terminal of the second switch is the gate of the NMOS transistor.

[0014] Secondly, this application provides a display device, the display device including a driving circuit and a display panel as described in any one of the first aspects, the display panel displaying under the drive of the driving circuit.

[0015] Compared with the prior art, the technical solution provided in this application has the following advantages: The display panel provided in this application includes a relay circuit and multiple row pixel driving circuits; the relay circuit is disposed on the source driving signal line before the target row pixel driving circuit in the row pixel driving circuit; the relay circuit is used to amplify the data current of the source driving signal line and output it to the far-end row pixel driving circuit; the far-end row pixel driving circuit includes the target row pixel driving circuit and the pixel driving circuit after the target row pixel driving circuit. This display panel can amplify the data current of the source driving signal line through the relay circuit and output it to the far-end row pixel driving circuit, which includes the target row pixel driving circuit and the far-end row pixel driving circuit after the target row pixel driving circuit. This reduces the charging time of the pixel capacitors in the far-end row pixel driving circuit, allowing the pixel capacitors in the far-end row pixel driving circuit to charge quickly, while the near-end row pixel driving circuit still uses the unamplified data current, thereby reducing the signal delay at the far end of the large-size display panel and improving the display effect of the display panel. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 is a schematic diagram of a remote signal delay; Figure 2 is a schematic diagram of a display device provided in one embodiment of this application; Figure 3 is a schematic diagram of the position of a relay circuit in a display panel provided in one embodiment of this application; Figure 4 is a schematic diagram of a display device provided in another embodiment of this application; Figure 5 is a schematic diagram of a display device provided in a specific embodiment of this application; Figure 6 is a timing diagram of a display device provided in one embodiment of this application.

[0020] The reference numerals are as follows: S1 - First switch transistor; S2 - Second switch transistor; M1 - First MOSFET; M2 - Second MOSFET; R1 - First resistor; R2 - Second resistor; VEE1 - First negative power supply; VCC1 - First positive power supply; T1 - First thin-film transistor; T2 - Second thin-film transistor; T3 - Third thin-film transistor; T4 - Fourth thin-film transistor; T5 - Fifth thin-film transistor; T6 - Sixth thin-film transistor; T7 - ​​Seventh thin-film transistor; Cst - Pixel capacitor; C1 - First capacitor; Q1 - First transistor; IC1 - Error amplifier. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0023] With the development of display technology and the increasing demand in the consumer display market, large-size OLEDs are gaining popularity. OLEDs are gradually becoming thinner and lighter. Thinner OLED displays mean thinner source traces, but also higher impedance. Meanwhile, due to the reliability requirements of large-size OLEDs, thicker encapsulation layers and more complex optical coupling structures are often used. These increase the resistance and parasitic capacitance along the data signal transmission path. When data is transmitted over long distances along the source trace, the signal delay at the far end will be higher than the signal delay at the near end of the driver chip IC. Figure 1 illustrates the far-end signal delay, where the horizontal axis represents time. If a voltage reaching 90% of the target voltage is considered a valid signal, then the near-end gate can reach 90% of the target voltage within approximately 0.1 widths after the falling edge trigger, while the far end may take about 0.5 widths to reach 90%. Therefore, there is a signal delay at the far end. This signal delay increases the charging rise time of the far-end pixel capacitor, causing incorrect charging. To address this issue, some technologies add an OE (output enable) signal at the GOA (Gate of Access) to prematurely shut down the gate, ensuring correct data writing. However, this approach reduces the charging rate and causes a decrease in brightness (IR-Drop). Therefore, reducing signal latency at the far end has become a pressing problem for large-size display panels.

[0024] To address the technical problem of reducing signal delay at the far end of large-size display devices in the prior art, this application provides a display panel and display device that can amplify the data current of the source drive signal line through a relay circuit and output it to the far-end row pixel drive circuit. This reduces the charging time of the pixel capacitors in the far-end row pixel drive circuit, enabling them to charge quickly. Meanwhile, the near-end row pixel drive circuit still uses the unamplified data current, thereby reducing the signal delay at the far end of the large-size display panel and improving the display effect of the display panel.

[0025] The first embodiment of this application provides a display panel, as shown in FIG2. The display panel includes a relay circuit and multiple row pixel driving circuits.

[0026] The relay circuit is located on the source drive signal line before the target row pixel drive circuit in the row pixel drive circuit. The relay circuit is used to amplify the data current of the source drive signal line and output it to the far-end row pixel drive circuit. The far-end row pixel drive circuit includes the target row pixel drive circuit and the pixel drive circuit after the target row pixel drive circuit. The row pixel drive circuit before the target row pixel drive circuit can be called the near-end row pixel drive circuit.

[0027] This display panel can amplify the data current of the source drive signal line through a relay circuit and output it to the far-end row pixel drive circuit. This reduces the charging time of the pixel capacitors in the far-end row pixel drive circuit, allowing them to charge quickly. Meanwhile, the near-end row pixel drive circuit still uses the unamplified data current, thereby reducing the signal delay at the far end of the large-size display panel and improving the display effect.

[0028] It should be understood that in the display panel, each row of pixel driving circuits includes multiple columns, and a relay circuit can be set in each column, as shown in Figure 3, which is a schematic diagram of the position of the relay circuit in the display panel.

[0029] In one embodiment, as shown in FIG4, the relay circuit includes a first switch S1, a first resistor R1, and a second resistor R2.

[0030] The connection is as follows: the first terminal of the first switch S1 is connected to the first terminal of the first resistor R1, the input terminal of the target row pixel driving circuit, and the source driving signal line; the second terminal of the first resistor R1 is connected to the first negative power supply VEE1; the second terminal of the first switch S1 is connected to the first positive power supply VCC1 and the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the third terminal of the first switch S1 and the source driving circuit; under the action of the source driving circuit, the third terminal of the first switch S1 amplifies the current output from the source of the first switch S1.

[0031] In this embodiment, the row pixel driving circuit can be composed of seven thin-film transistors (TFTs): a first TFT T1, a second TFT T2, a third TFT T3, a fourth TFT T4, a fifth TFT T5, a sixth TFT T6, and a seventh TFT T7, a pixel capacitor Cst, and an OLED pixel. Specifically, the first switching transistor S1 can be a MOS transistor, such as an NMOS or PMOS transistor. It should be understood that each row pixel driving circuit includes the above structure, and the target row pixel driving circuit with the relay circuit is similarly configured.

[0032] In a specific embodiment, taking the first switching transistor S1 as the first MOS transistor M1 as an example, the first terminal of the first switching transistor S1 is the source of the first MOS transistor M1, the second terminal of the first switching transistor S1 is the drain of the first MOS transistor M1, and the third terminal of the first switching transistor S1 is the gate of the first MOS transistor M1, as shown in Figure 5. The relay circuit includes the first MOS transistor M1, the first resistor R1, and the second resistor R2. The connection relationship is as follows: the source of the first MOS transistor M1 is connected to the first terminal of the first resistor R1, the input terminal of the target row pixel driving circuit, and the source line (i.e., the signal line for transmitting data); the second terminal of the first resistor R1 is connected to the first negative power supply VEE1; the drain of the first MOS transistor M1 is connected to the first positive power supply VCC1 and the first terminal of the second resistor R2; the second terminal of the second resistor R2 is connected to the gate of the first MOS transistor M1 and the source driving circuit; under the action of the source driving circuit, the gate of the first MOS transistor M1 amplifies the current output from the source of the first MOS transistor M1.

[0033] In this embodiment, the first MOS transistor M1 can be operated in the amplification region. By adjusting the gate voltage of the first MOS transistor M1, the current flowing inside the first MOS transistor M1 can be changed, thereby amplifying the current output from the source of the first MOS transistor M1.

[0034] In one embodiment, the display panel further includes a feedback compensation circuit.

[0035] The feedback compensation circuit is used to calibrate the gate voltage of the far-end row pixel driving circuit so that the gate voltage of the far-end row pixel driving circuit is consistent with the gate voltage of the near-end row pixel driving circuit; wherein, the near-end row pixel driving circuit is the row pixel driving circuit before the target row pixel driving circuit.

[0036] In this embodiment, the display panel also includes a feedback compensation circuit. The feedback compensation circuit can calibrate the gate voltage of the far-end row pixel driving circuit so that the gate voltage of the far-end row pixel driving circuit is consistent with the gate voltage of the near-end row pixel driving circuit, avoiding voltage drop caused by the resistance of the transmission line, thereby ensuring that the gate of the first MOS transistor amplifies the current output from the source of the first MOS transistor under the action of the source driving circuit.

[0037] Specifically, the first MOSFET can be an NMOS transistor, and the resistance values ​​of the first resistor R1 and the second resistor R2 can be 10kΩ.

[0038] In one embodiment, the feedback compensation circuit is located in the driver chip where the source drive circuit is located.

[0039] In this embodiment, the feedback compensation circuit can be set in the driver IC where the source drive circuit is located, that is, the feedback compensation circuit is set inside the driver IC.

[0040] In one embodiment, the relay circuit in each column of source drive signal lines corresponds to a feedback compensation circuit.

[0041] In this embodiment, each relay circuit can correspond to a feedback compensation circuit. As shown in the schematic diagram of the relay circuit position in the display panel in Figure 3, the source drive signal line of each relay circuit can be connected to a feedback compensation circuit.

[0042] In one embodiment, when the relay circuits in the source drive signal lines of different columns are all in different target row pixel drive circuits, multiple relay circuits correspond to one feedback compensation circuit.

[0043] In this embodiment, when the relay circuits in the source drive signal lines of different columns are located in different rows, for example, the relay circuit of source drive signal line 1 is located before the pixel drive circuit in row A, the relay circuit of source drive signal line 2 is located before the pixel drive circuit in row A+1, and the relay circuit of source drive signal line 3 is located before the pixel drive circuit in row A+2, then the three relay circuits of source drive signal line 1, source drive signal line 2, and source drive signal line 3 can share the same feedback compensation circuit, thereby saving the design space of the driver chip IC. In this embodiment, the relay circuits in different columns can be set to a staggered structure to reasonably allocate the pixel circuit layout space.

[0044] In one embodiment, as shown in FIG4, the feedback compensation circuit includes a second switch S2, a first capacitor C1, a first transistor Q1, and an error amplifier IC1.

[0045] The connections are as follows: the third terminal of the second switch S2 is connected to the transmit control signal of the source drive signal line; the first terminal of the second switch S2 is connected to the first terminal of the first capacitor C1 and the second input terminal of the error amplifier IC1; the second terminal of the first capacitor C1 is grounded; the first input terminal of the error amplifier IC1 is connected to the first terminal of the first switch S1; the output terminal of the error amplifier IC1 is connected to the base of the first transistor Q1; the emitter of the first transistor Q1 is connected to the third terminal of the first switch S1; and the collector of the first transistor Q1 is connected to the second terminal of the second switch S2 and the source drive signal line.

[0046] In this embodiment, the second switch S2 can specifically be a MOS transistor, such as an NMOS transistor or a PMOS transistor. The initial data voltage Vdata can be acquired through the transmit control signal Data_SYNC from the source drive signal line and the first capacitor C1, and compared with the voltage value output by the relay circuit. The resistance value of the first transistor Q1 is adjusted, thereby adjusting the voltage at the third terminal of the first switch. Since the relay circuit does not have voltage amplification gain, the output of the first switch is adjusted.

[0047] In a specific embodiment, taking the second switch S2 as an example, specifically the second MOS transistor M2, the first terminal of the second switch S2 is the source of the second MOS transistor M2, the second terminal of the second switch S2 is the drain of the second MOS transistor M2, and the third terminal of the second switch S2 is the gate of the second MOS transistor M2, as shown in Figure 5. The feedback compensation circuit includes the second MOS transistor M2, the first capacitor C1, the first transistor Q1, and the error amplifier IC1. The connection relationship is as follows: the gate of the second MOS transistor M2 is connected to the transmit control signal Data_SYNC of the source drive signal line; the source of the second MOS transistor M2 is connected to the first terminal of the first capacitor C1 and the second input terminal of the error amplifier IC1; the second terminal of the first capacitor C1 is grounded; the first input terminal of the error amplifier IC1 is connected to the source of the first MOS transistor M1; the output terminal of the error amplifier IC1 is connected to the base of the first transistor Q1; the emitter of the first transistor Q1 is connected to the gate of the first MOS transistor M1; and the collector of the first transistor Q1 is connected to the drain of the second MOS transistor M2 and the source drive signal line.

[0048] In this embodiment, the initial data voltage Vdata can be acquired through the transmit control signal Data_SYNC of the source drive signal line and the first capacitor C1. This data is then compared with the voltage value output by the relay circuit. The resistance value of the first transistor Q1 is adjusted, thereby adjusting the gate voltage of the first MOSFET M1. Since the relay circuit does not have voltage amplification gain, the output of the first MOSFET is adjusted. Specifically, the second MOSFET M2 can be an NMOS transistor.

[0049] It should be noted that, based on this structure, the data voltage Vdata requires a gain voltage after the source drive signal line transmit control signal Data_SYNC is sampled. This gain ratio can be reflected in the timing design. The specific gain value is not limited and can be determined according to the parameters.

[0050] It should be understood that, depending on the type of VCC2 and the source drive signal line's transmit control signal Data_SYNC, the first MOS transistor M1 and the second MOS transistor M2 can also be PMOS transistors. Data_SYNC can be a low-potential pulse at a normal high potential. The types of the first MOS transistor M1, the second MOS transistor M2, and the source drive signal line's transmit control signal Data_SYNC in the above embodiment are merely illustrative examples and do not represent limitations. The first resistor R1 and the second resistor R2 can be 10KΩ, or other components can be set according to actual needs without restriction.

[0051] In one specific embodiment, Figure 6 is a timing diagram of a display device. The source output position of the first MOS transistor M1 is defined as the Q point. When Data_SYNC is pulled high, the second MOS transistor M2 is turned on, Vdata is written to the first capacitor C1, and the gate voltage of the first MOS transistor M1 is also Vdata. At this time, the current at the Q point is... .

[0052] Where W represents the channel width of the TFT; L represents the channel length of the TFT; μ n The carrier migration rate is generally determined by the TFT material; C ox The capacitance per unit area of ​​the gate oxide layer is usually determined by the design structure; VDD here is the first positive power supply VCC1.

[0053] When the first capacitor C1 finishes sampling, Data_SYNC enters a low potential, the second MOSFET M2 is turned off, and the first capacitor C1 maintains the original Data voltage. At this time, the Data voltage from the driver chip is applied to the gate of the first MOSFET M1 after amplification. Since the first MOSFET M1 has a low on-state voltage drop Vth, the Q-point voltage will be slightly lower than Vdata in the initial and sampling stages, approximately Vdata-Vth. At this time, the driver chip outputs the amplified Data voltage and samples the voltage from the Q-point. The sampled voltage is compared with the voltage before amplification stored in the first capacitor C1 to control the conduction level of the first transistor Q1. When the sampled voltage is lower than the stored reference voltage Data, the voltage output of the error amplifier IC1 rises, the conduction level of the first transistor Q1 increases, and the gate input of the first MOSFET M1 rises. According to the emitter follower characteristics, the Q-point voltage rises until the sampled Q-point voltage equals the voltage before amplification, Vdata.

[0054] In this embodiment, in the row where the relay circuit is located, counting in the refresh direction, the Data voltage of the previous row (i.e., the far end of the driver chip) will be output twice. The first output is Data, stored in the first capacitor C1 for standard reference. The second output is Data_OD, which is slightly higher than Data, used to provide the base voltage. The error amplifier compares the Q-point voltage with the voltage in the first capacitor C1 and corrects the output until they are equal. As can be seen from the timing diagram of the Q-point voltage in Figure 6, without a feedback compensation circuit, the Q-point voltage will remain at the voltage after the first rising edge. By adding a feedback compensation voltage and setting a Data_OD slightly higher than Data, the Q-point voltage can be increased to a voltage value comparable to the voltage level of the first capacitor C1. In this embodiment, the relay circuit amplifies the current, enabling the far end to charge quickly. The feedback compensation circuit calibrates the voltage, keeping the gate voltage of the far end consistent with that of the near end, thereby ensuring the output of the first MOS transistor M1, avoiding the problem of insufficient charging rate at the far end of large-size OLED panels, and improving the display effect.

[0055] In one embodiment, the row pixel driving circuit is an OLED row pixel driving circuit, that is, the display panel is an OLED display panel.

[0056] In this OLED display panel, the source of the first MOS transistor M1 is connected to the first terminal of the first resistor R1, the input terminal of the target row pixel driving circuit, and the source driving signal line (i.e., the signal line for transmitting data); the second terminal of the first resistor R1 is connected to the first negative power supply VEE1; the drain of the first MOS transistor M1 is connected to the first positive power supply VCC1 and the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the gate of the first MOS transistor M1 and the source driving circuit; under the action of the source driving circuit, the gate of the first MOS transistor M1 amplifies the current output from the source of the first MOS transistor M1.

[0057] In this OLED display panel, the first MOSFET M1 can be operated in the amplification region. By adjusting the gate voltage of the first MOSFET M1, the current flowing inside the first MOSFET M1 can be changed, thereby amplifying the current output from the source of the first MOSFET M1.

[0058] Specifically, the OLED display panel also includes a feedback compensation circuit.

[0059] The feedback compensation circuit is used to calibrate the gate voltage of the far-end row pixel driving circuit so that the gate voltage of the far-end row pixel driving circuit is consistent with the gate voltage of the near-end row pixel driving circuit; wherein, the near-end row pixel driving circuit is the row pixel driving circuit before the target row pixel driving circuit.

[0060] In this embodiment, the OLED display panel further includes a feedback compensation circuit. The feedback compensation circuit can calibrate the gate voltage of the far-end row pixel driving circuit so that the gate voltage of the far-end row pixel driving circuit is consistent with the gate voltage of the near-end row pixel driving circuit, avoiding voltage drop caused by the resistance of the transmission line, thereby ensuring that the gate of the first MOS transistor amplifies the current output from the source of the first MOS transistor under the action of the source driving circuit.

[0061] Specifically, the first MOSFET can be an NMOS transistor, and the resistance values ​​of the first resistor R1 and the second resistor R2 can be 10kΩ.

[0062] In one embodiment, the feedback compensation circuit is located in the driver chip where the source drive circuit is located.

[0063] In this OLED display panel, the feedback compensation circuit can be set in the driver IC where the source driving circuit is located, that is, the feedback compensation circuit is set inside the driver IC.

[0064] In this OLED display panel, the feedback compensation circuit may include a second MOSFET M2, a first capacitor C1, a first transistor Q1, and an error amplifier IC1.

[0065] The gate of the second MOSFET M2 is connected to the transmit control signal (Data_SYNC) of the source drive signal line. The source of the second MOSFET M2 is connected to the first terminal of the first capacitor C1 and the second input terminal of the error amplifier IC1. The second terminal of the first capacitor C1 is grounded. The first input terminal of the error amplifier IC1 is connected to the source of the first MOSFET M1. The output terminal of the error amplifier IC1 is connected to the base of the first transistor Q1. The emitter of the first transistor Q1 is connected to the gate of the first MOSFET M1. The collector of the first transistor Q1 is connected to the drain of the second MOSFET M2 and the source drive signal line.

[0066] In this OLED display panel, the initial data voltage Vdata can be acquired through Data_SYNC and the first capacitor C1, compared with the voltage value output by the relay circuit, and the resistance value of the first transistor Q1 is adjusted, thereby adjusting the gate voltage of the first MOSFET M1. Since the relay circuit does not have voltage amplification gain, the output of the first MOSFET M1 is adjusted. Specifically, the second MOSFET can be an NMOS transistor.

[0067] It should be noted that Vdata based on this structure requires a gain voltage after Data_SYNC sampling. This gain ratio can be reflected in the timing design. The specific gain value is not limited and can be determined according to the parameters.

[0068] It should be understood that, depending on the types of VCC2 and Data_SYNC, the first MOSFET M1 and the second MOSFET M2 can also be PMOS transistors, and Data_SYNC can be a low-potential pulse that is normally at a high potential. The first MOSFET M1, the second MOSFET M2, and the Data_SYNC signal type in the above embodiment are only illustrative examples and do not represent any limitation. The resistance values ​​of the first resistor R1 and the second resistor R2 can be selected as 10KΩ, or other values ​​can be set according to actual needs without restriction.

[0069] Based on the same technical concept, the second embodiment of this application provides a display device, which includes a driving circuit and a display panel as described in any one of the first embodiments, and the display panel displays under the drive of the driving circuit.

[0070] In this display device, the display panel can amplify the data current of the source drive signal line through a relay circuit and output it to the far-end row pixel drive circuit after the target row pixel drive circuit. This can reduce the charging time of the pixel capacitor in the far-end row pixel drive circuit, enabling the pixel capacitor in the far-end row pixel drive circuit to charge quickly. The near-end row pixel drive circuit still uses the unamplified data current, thereby reducing the signal delay at the far end of the large-size display panel and improving the display effect of the display device.

[0071] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0072] It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. In the description, suffixes such as "module," "part," or "unit" used to denote elements are used solely for illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0073] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display panel, characterized in that, The display panel includes a relay circuit and multiple row pixel driving circuits; the relay circuit is disposed on the source driving signal line before the target row pixel driving circuit in the row pixel driving circuit; the relay circuit is used to amplify the data current of the source driving signal line and output it to the far-end row pixel driving circuit; wherein, the far-end row pixel driving circuit includes the target row pixel driving circuit and the pixel driving circuit after the target row pixel driving circuit.

2. The display panel according to claim 1, characterized in that, The relay circuit includes a first switch, a first resistor, and a second resistor; the first terminal of the first switch is connected to the first terminal of the first resistor, the input terminal of the target row pixel driving circuit, and the source driving signal line; the second terminal of the first resistor is connected to a first negative power supply; the second terminal of the first switch is connected to a first positive power supply and the first terminal of the second resistor, and the second terminal of the second resistor is connected to the third terminal of the first switch and the source driving circuit; the third terminal of the first switch amplifies the current output from the source of the first switch under the action of the source driving circuit.

3. The display panel according to claim 2, characterized in that, The display panel further includes a feedback compensation circuit; the feedback compensation circuit is used to calibrate the gate voltage of the distal row pixel driving circuit so that the gate voltage of the distal row pixel driving circuit is consistent with the gate voltage of the proximal row pixel driving circuit; wherein, the proximal row pixel driving circuit is the row pixel driving circuit preceding the target row pixel driving circuit.

4. The display panel according to claim 3, characterized in that, The feedback compensation circuit is located in the driver chip where the source drive circuit is located.

5. The display panel according to claim 3, characterized in that, Each relay circuit in the source drive signal line of each column corresponds to one of the feedback compensation circuits.

6. The display panel according to claim 3, characterized in that, When the relay circuits in the source drive signal lines of different columns are all in different target row pixel drive circuits, multiple relay circuits correspond to one feedback compensation circuit.

7. The display panel according to claim 3, characterized in that, The feedback compensation circuit includes a second switch, a first capacitor, a first transistor, and an error amplifier. The third terminal of the second switch is connected to the transmit control signal of the source drive signal line, and the first terminal of the second switch is connected to the first terminal of the first capacitor and the second input terminal of the error amplifier. The second terminal of the first capacitor is grounded. The first input terminal of the error amplifier is connected to the first terminal of the first switch. The output terminal of the error amplifier is connected to the base of the first transistor, the emitter of the first transistor is connected to the third terminal of the first switch, and the collector of the first transistor is connected to the second terminal of the second switch and the source drive signal line.

8. The display panel according to claim 2, characterized in that, The first switching transistor is an NMOS transistor; the first terminal of the first switching transistor is the source of the NMOS transistor, the second terminal of the first switching transistor is the drain of the NMOS transistor, and the third terminal of the first switching transistor is the gate of the NMOS transistor.

9. The display panel according to claim 7, characterized in that, The second switch is an NMOS transistor; the first terminal of the second switch is the source of the NMOS transistor, the second terminal of the second switch is the drain of the NMOS transistor, and the third terminal of the second switch is the gate of the NMOS transistor.

10. A display device, characterized in that, The display device includes a driving circuit and a display panel as described in any one of claims 1-9, wherein the display panel displays under the drive of the driving circuit.

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