Control circuit structure for column memory, chip, image sensor and equipment

Abstract

The invention provides a control circuit structure for a column memory, a chip, an image sensor and an imaging device. The column memory comprises 2N memory banks which are sequentially arranged along the column direction of the column memory, and each memory bank comprises M column memory units; the control circuit structure comprises a logic control circuit and at least one shifting register circuit which are electrically connected, each shifting register circuit corresponds to one or more column storage units, and the projection of the logic control circuit on the plane where the column storage is located is located in the area where the column storage is located; and the logic control circuit can drive the shift register circuit to shift and read the data to be read out from the corresponding column storage unit according to a received reading instruction in a manner of one bit in each clock period, and meanwhile, the subsequent data to be read out is moved by one bit in the reading direction so as to output the data to be read out. According to the invention, the data reading time can be greatly reduced, so that the data reading efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to a control circuit structure, chip, image sensor, and imaging device for column memory. Background Technology

[0002] Please see Figure 1 , Figure 1 A block diagram schematically illustrates the control circuitry used in columnar memory in related technologies. From Figure 1 As can be seen, the control circuit for the column memory 101 in the related technology mainly includes a logic control circuit 102 and a readout circuit 103 on the side of the column memory 101. The working principle of the control circuit for the column memory in the related technology is roughly as follows: Under the control of the logic control circuit 102, the readout circuit 103 reads data from the column memory 101 column by column for subsequent processing by relevant modules (e.g., sending the read image data to an image processor for face recognition, object recognition, etc.).

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a control circuit structure, chip, image sensor, and imaging device for columnar memory. This invention can significantly reduce data readout time, thereby improving data readout efficiency.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a control circuit structure for a column memory, wherein the column memory comprises 2N memory banks arranged sequentially along the column direction of the column memory, each memory bank comprising M column memory cells; the control circuit structure comprises an electrically connected logic control circuit and at least one shift register circuit, each shift register circuit corresponding to one or more of the column memory cells, and the projection of the logic control circuit onto the plane of the column memory is located within the region of the column memory;

[0006] The logic control circuit is configured to drive the shift register circuit to shift and read the data to be read from the corresponding column storage unit in a manner of one bit per clock cycle according to the received read instruction, while the subsequent data to be read is shifted one bit in the read direction, so as to output the data to be read.

[0007] Optionally, the column memory is used for an image sensor, the image sensor having a bit depth of n, where n < M.

[0008] Optionally, the logic control circuit is configured to drive the shift register circuit to simultaneously read the data to be read from all the memory banks according to the received read instruction.

[0009] Optionally, the control circuit structure further includes a first multiplexer, and the logic control circuit is configured to drive the first multiplexer to select the memory bank in a time-division multiplexing manner according to the received read instruction, and drive the shift register circuit to read the data to be read from the selected memory bank.

[0010] Optionally, the control circuit structure further includes a second multiplexer, and the logic control circuit is configured to drive the second multiplexer to select one or more of the column storage cells in a time-division multiplexing manner according to the received read instruction, and drive the shift register circuit to read the data to be read from the selected column storage cells.

[0011] Optionally, there are N column storage units that are selected, and these N column storage units that are selected simultaneously are located in N storage bodies respectively.

[0012] Optionally, the shift register circuit includes an input interface, a shift register, an output interface, and a readout clock, all electrically connected. The shift register is configured to receive the corresponding bit of the data to be read from the column storage unit through the input interface, and to shift and read the data to be read out through the output interface according to the clock signal of the readout clock, one bit per clock cycle.

[0013] To achieve the above objectives, the present invention also provides a chip, wherein the chip integrates the control circuit structure for column memory described in any of the above claims.

[0014] To achieve the above objectives, the present invention also provides an image sensor, which includes the control circuit structure for column memory described in any of the above claims or the chip described above.

[0015] To achieve the above objectives, the present invention also provides an imaging device, which includes the control circuit structure for column memory described in any of the above claims, or the chip described above, or the image sensor described above.

[0016] Compared with the prior art, the control circuit structure, chip, image sensor, and imaging device for column memory provided by the present invention have the following advantages: The control circuit structure for column memory provided by the present invention, by adopting a design in which the projection of the logic control circuit onto the plane of the column memory is located within the region of the column memory, can significantly reduce the load on the control line, thereby effectively reducing the data readout time; furthermore, the logic control circuit can drive the shift register circuit to shift and read the data to be read from the corresponding column memory cell by one bit per clock cycle, while the subsequent data to be read is shifted one bit in the readout direction, which can greatly reduce the data readout time, thereby improving the data readout efficiency.

[0017] Since the chip, image sensor, and imaging device provided by this invention belong to the same inventive concept as the control circuit structure for column memory provided by this invention, the chip, image sensor, and imaging device provided by this invention have at least all the advantages of the control circuit structure for column memory provided by this invention. For details on the beneficial effects of the chip, image sensor, and imaging device provided by this invention, please refer to the above description of the beneficial effects of the control circuit structure for column memory provided by this invention, which will not be repeated here. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the control circuit structure used in columnar memory in the prior art.

[0019] Figure 2 This is a schematic diagram illustrating the working principle of a control circuit structure for a columnar memory provided in one embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the shift register circuit for the control circuit structure of a column memory provided by the present invention.

[0021] Figure 4 The working principle of the control circuit structure for a columnar memory provided in another embodiment of the present invention is shown in the figure.

[0022] Figure 5 The diagram illustrates the working principle of a control circuit structure for a columnar memory provided in another embodiment of the present invention.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] Column memory - 101, 100; memory bank - 110; column memory cell - 111; logic control circuit - 102, 210; shift register circuit - 220; input interface - 221; shift register - 221; output interface - 223; read clock - 224; read circuit - 103; first multiplexer - 230; second multiplexer - 250. Detailed Implementation

[0025] The control circuit structure, chip, image sensor, and imaging device for column memory proposed in this invention will be further described in detail below with reference to the accompanying drawings. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, if they are the same as or similar to the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be discussed further in subsequent figures. Furthermore, if the methods described herein involve a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or other steps not described herein may be added to the method.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms "a," "an," and "the" include plural objects; the term "or" is generally used to include "and / or"; the term "several" is generally used to include "at least one"; the term "at least two" is generally used to include "two or more"; and the term "multiple" is generally used to include "at least two." Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. They may also include elements inherent to such a process, method, article, or apparatus.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0028] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0029] The core idea of ​​this invention is to provide a control circuit structure, chip, image sensor and imaging device for column memory. This invention can significantly reduce data readout time, thereby improving data readout efficiency.

[0030] It should be noted that the control circuit structure and chip for column memory provided by this invention can be applied to the image sensor and imaging device provided by this invention. The image sensor provided by this invention can be applied to the imaging device provided by this invention. It should be understood that the term "imaging device" or "imaging equipment" or other similar terms as used herein includes general imaging devices, such as, but not limited to, cameras, camcorders, mobile phones, tablets, educational devices, and medical imaging devices with image sensors.

[0031] To achieve the above-mentioned ideas, one embodiment of the present invention provides a control circuit structure for a columnar memory. For an example, please refer to... Figure 2 , Figure 2 This is a block diagram illustrating the control circuit structure for a columnar memory provided in this embodiment. Figure 2 It can be seen that the column memory 100 includes columns along the column direction of the column memory 100 ( Figure 2 The control circuit structure includes an electrically connected logic control circuit 210 and at least one shift register circuit 220. Each shift register circuit 220 corresponds to one or more of the column storage cells 111. The projection of the logic control circuit 210 onto the plane of the column storage 100 is located within the area of ​​the column storage 100. The logic control circuit 210 is configured to drive the shift register circuit 220 to shift and read the data to be read from the corresponding column storage cell 111 at a rate of one bit per clock cycle according to the received read instruction. At the same time, the subsequent data to be read is shifted one bit in the read direction to output the data to be read.

[0032] Therefore, the control circuit structure for the column memory 100 provided by the present invention, by adopting a design in which the projection of the logic control circuit 210 onto the plane where the column memory 100 is located is situated within the region where the column memory 100 is located, can significantly reduce the load on the control line (by comparison). Figure 1 and Figure 2 It can be known that: Figure 1 The length of the load line is equal to the column width of the entire column memory, while Figure 2The length of the load line is only half the width of the entire column memory, thus effectively reducing the data read time. Furthermore, the logic control circuit 210 can drive the shift register circuit 220 to shift the data to be read from the corresponding column memory cell 111 in a manner of one bit per clock cycle, while the subsequent data to be read is moved one bit in the read direction, which can greatly reduce the data read time and thus improve the data read efficiency.

[0033] It should be noted that the present invention does not limit the specific implementation of each shift register circuit 220 corresponding to one or more column storage units 111. For example, in some embodiments, each shift register circuit 220 corresponds to multiple column storage units 111, and the number of column storage units 111 corresponding to each shift register circuit 220 may be the same or different. In other embodiments, some shift register circuits 220 may correspond to one column storage unit 111, and other shift register circuits 220 may correspond to multiple column storage units 111. In other embodiments, each shift register circuit 220 may correspond to one column storage unit 111. For ease of understanding and explanation, this document uses an example of having multiple shift register circuits 220 and a one-to-one correspondence between the shift register circuits 220 and the column storage units 111.

[0034] It should also be noted that the present invention does not limit the description of the column storage units 111 of each storage bank 110, and each storage bank 110 may have one or more column storage units 111.

[0035] For example, such as Figure 2 As shown, in this example, the column memory 100 has 2N memory banks 110, namely memory banks 0, 1, ..., and N-1 located to the left of the control input (control IN), and memory banks N, N+1, ..., and 2N-1 located to the right of the control input. Each memory bank 110 includes M column storage cells 111. Taking memory bank 0 as an example, memory bank 0 includes column storage cells 0, 1, ..., and M-1. It should be understood that although... Figure 2 For clarity, the memory bank 0, memory bank 1, ..., memory bank 2N-1 are all represented by column storage units 0, column storage units 1, ..., and column storage unit M-1. However, it is clear that the column storage units 110 in memory bank 0, memory bank 1, ..., memory bank 2N-1 are all independent and different column storage units.

[0036] It should be noted that, although Figure 2 In the example shown, there are two logic control circuits 210 symmetrically distributed on both sides of the column memory 100. However, it is obvious that the present invention does not impose too much limitation on the number of logic control circuits 210. In other embodiments, the number of logic control circuits 210 can also be 4, 8, etc.

[0037] For example, please see Figure 3 , Figure 3 This is a schematic diagram of the shift register circuit 220, which is part of the control circuit structure for the column memory 100 provided in this embodiment. Figure 3 As can be seen, the shift register circuit 220 includes an input interface 221, a shift register 222, an output interface 223, and a readout clock 224 that are electrically connected. The shift register 222 is configured to receive the corresponding bit of the data to be read from the column storage unit 111 through the input interface 221, and shift and read the data to be read through the output interface 223 according to the clock signal of the readout clock 224 in a manner of one bit per clock cycle.

[0038] Therefore, the control circuit structure for the column memory 100 provided by the present invention, wherein the shift register circuit 220 adopts the design of input interface 221, shift register 222, output interface 223 and read clock 224, can effectively realize the shifting and reading of the data to be read from the corresponding column storage unit 111 in a manner of one bit per clock cycle, and the subsequent data to be read is shifted one bit in the reading direction, thereby laying a good foundation for improving data reading efficiency.

[0039] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the number of shift registers 222. For example, taking the column memory 100 as an example of an image sensor (such as a CIS, CMOS Image Sensor), the number of shift registers 222 can be consistent with the bit depth of the image sensor. Figure 3 Taking n shift registers 222 as an example, correspondingly, the shift register circuit 220 has n input interfaces 221 to receive the bits D of the read data from the corresponding column storage unit 111. <n>D<n-1> D<n-2>, ..., D <2> D <1> .

[0040] Exemplary examples, in some exemplary embodiments, the column memory 100 is used for an image sensor with a bit depth of n, where n < M (M is the number of column memory cells 111 in each memory bank 110). Preferably, n is much smaller than M; for example, in one example, n is 11 and M is 2048. Because n is much smaller than M, data readout efficiency can be further improved. It should be noted that those skilled in the art should understand that the present invention does not limit the specific values ​​of N, M, and n.

[0041] It should be noted that although this article uses the control circuit structure for use in the column memory of an image sensor as an example, it is obvious that the present invention does not limit the application scenarios of the column memory 100. For more detailed information, please refer to the relevant content on the application scenarios of column memory known to those skilled in the art.

[0042] To better understand the present invention, the working principle of the control circuit structure for column memory provided by the present invention will be explained by way of example using the first embodiment, the second embodiment, and the third embodiment.

[0043] <First Implementation Method>

[0044] For example, please continue to see Figure 3 ,like Figure 3 As shown, in this embodiment, the logic control circuit 210 is configured to drive the shift register circuit 220 to simultaneously read out the data to be read from all the memory banks 110 according to the received read instruction.

[0045] The control circuit structure for columnar memory provided in this embodiment, by employing the logic control circuit 210 to drive the shift register circuit 220 to simultaneously output the data to be read corresponding to all the memory banks 110, can significantly reduce the data read time (for example, if each memory bank 110 has M columnar storage units 111, the read time becomes 1 / M of the original time), thereby effectively improving data read efficiency. For example, as... Figure 2 As shown, in this embodiment, the data to be read from memory bank 0, memory bank 1, ..., and memory bank 2N-1 are output simultaneously.

[0046] This embodiment provides yet another control circuit structure for a columnar memory. The difference between this control circuit structure and the first embodiment is that the control circuit structure for a columnar memory provided in this embodiment further includes a first multiplexer. For example, please refer to... Figure 4 , Figure 4 This is a schematic diagram illustrating the working principle of the control circuit structure for a columnar memory provided in this embodiment. For example... Figure 4 As shown, the logic control circuit 210 is configured to drive the first multiplexer 230 to select the memory bank 110 in a time-division manner according to the received read instruction, and drive the shift register circuit 220 to read the data to be read from the selected memory bank 110.

[0047] Therefore, the control circuit structure for the column memory provided in this embodiment, by employing the logic control circuit 210 to drive the first multiplexer 230 to select the memory bank 110 in a time-division multiplexing manner, and driving the shift register circuit 220 to read the data to be read from the selected memory bank 110, can not only significantly reduce the data read time (taking each memory bank 110 having M column memory cells 111 as an example, the read time becomes n / M of the original), thereby improving the data read efficiency; moreover, compared with the first embodiment, it can also avoid the instantaneous large current caused by reading the data in all the memory banks 110 at the same time, thereby reducing the requirements for power supply wiring and having better adaptability; furthermore, it can also reduce the risk of subsequent layout changes of related data processing modules that may be caused by outputting the data in all the memory banks 110 at the same time.

[0048] For example, such as Figure 4 As shown, at a certain moment, the first multiplexer 230 selects the data to be read from memory bank 0, and the shift register circuit 220 corresponding to memory bank 0 ( Figure 4 (Using red dashed boxes as an illustration) The data to be read from all the column storage units 0, 1, ..., M-1 in storage bank 0 is read out. At this moment, the shift register circuits 220 corresponding to the other storage banks 1, ..., 2N-1 (…) are also read out. Figure 4 (Illustrated by the blue dashed box) It is not working. Similarly, at another moment, if the first multiplexer 230 selects to read the data to be read from memory bank 1, the shift register circuit 220 corresponding to memory bank 1 will read the data to be read from all the column storage cells 0, column storage cells 1, ..., column storage cells M-1 in memory bank 0. At this moment, the shift register circuits 220 corresponding to the other memory banks 0, ..., memory bank 2N-1 are not working.

[0049] <Third Implementation Method>

[0050] This embodiment provides yet another control circuit structure for a columnar memory. The difference between this control circuit structure and the first embodiment is that the control circuit structure for a columnar memory provided in this embodiment further includes a second multiplexer. For example, please refer to... Figure 5 , Figure 5 This is a schematic diagram illustrating the working principle of the control circuit structure for a columnar memory provided in this embodiment. For example... Figure 5 As shown, the control circuit structure further includes a second multiplexer 240. The logic control circuit 210 is configured to drive the second multiplexer 240 to select one or more of the column storage units 111 in a time-division manner according to the received read instruction, and drive the shift register circuit 220 to read the data to be read from the selected column storage unit 111.

[0051] Therefore, the control circuit structure for the column memory provided in this embodiment, by employing the logic control circuit 210 to drive the second multiplexer 240 to select one or more of the column memory cells 111 in a time-division multiplexing manner, and driving the shift register circuit 220 to read the data to be read from the selected column memory cells 111, can not only significantly reduce the data read time (taking M column memory cells 111 in each memory bank 110 as an example, the read time becomes n / 2qM of the original, where q is the number of selected column memory cells 111), thereby improving the data read efficiency; but also further optimizes the current distribution during data read, thereby significantly improving the circuit performance during data read.

[0052] For example, please continue to see Figure 5 ,like Figure 5 As shown, in some exemplary embodiments, N column storage cells 111 are selected, and these N simultaneously selected column storage cells 111 are located in N memory banks 110 respectively. This not only significantly reduces data readout time and improves data readout efficiency, but also results in a more balanced current distribution during data readout, thereby significantly improving circuit performance during data readout.

[0053] For example, such as Figure 5 As shown, at a certain moment, the second multiplexer 240 selects to read the data to be read from N column storage cells 111. These N column storage cells 111 are column storage cells 1 in memory bank 0, column storage cells 1 in memory bank 1, ..., and column storage cells 1 in memory bank 2N-1. The shift register circuit 220 corresponding to these column storage cells 111 ( Figure 5 (Using red dashed boxes as illustrations) The data to be read from column storage cell 1 in memory bank 0, column storage cell 1, ..., column storage cell 1 in memory bank 1, and column storage cell 1 in memory bank 2N-1 are read out. At this moment, the shift register circuit 220 corresponding to the other column storage cells 0, ..., column storage cell M-1 in memory bank 0 (excluding column storage cell 1), the other column storage cells 0, ..., column storage cell M-1 in memory bank 1 (excluding column storage cell 1), ..., and the other column storage cells 0, ..., column storage cell M-1 in memory bank 2N-1 (excluding column storage cell 1) is also read out. Figure 5 (The blue dashed box indicates that none of them work.) Similarly, at another moment, if the second multiplexer 240 selects to read the data to be read from N column storage units 111, these N column storage units 111 are column storage unit i in storage bank 0, column storage unit j in storage bank 1, ..., and column storage unit k in storage bank 2N-1, the shift register circuit 220 corresponding to these column storage units 111 will read the data to be read from column storage unit i in storage bank 0, column storage unit j in storage bank 1, ..., and column storage unit k in storage bank 2N-1. At this moment, the shift register circuit 220 corresponding to the other column storage units 0, ..., M-1 in storage bank 0 (excluding column storage unit i), the other column storage units 0, ..., M-1 in storage bank 1 (excluding column storage unit j), ..., and the other column storage units 0, ..., M-1 in storage bank 2N-1 (excluding column storage unit k) are all not working; i, j, and k can be the same or different. In addition, the number of selected column storage units 111 in each of the storage banks 110 can be the same or different.

[0054] For example, an image sensor employing the control circuit structure for column memory provided by the present invention significantly shortens the total data readout time of the column memory, making it easier for the image sensor to avoid the overlap between the counting time interval and the data readout time interval, thereby reducing the performance interference between the counting interval and the readout interval, and thus enabling the image sensor to have higher performance.

[0055] It should be noted that, based on the description herein, those skilled in the art should understand that the logic control circuit 210 for the control circuit structure of the column memory provided by the present invention does not limit the read mode set by the read instruction. For example, as exemplified in the first embodiment, the read mode can be to simultaneously read all the data to be read from the memory banks 110 to maximize read efficiency; or as exemplified in the second embodiment, the read mode can be to time-divisionally select the memory banks 110 to balance read efficiency and instantaneous power during read; or as exemplified in the third embodiment, the read mode can be to time-divisionally select one or more of the column memory cells 111 to better balance instantaneous power with read efficiency as needed.

[0056] It should also be noted that the present invention does not impose excessive limitations on the specific implementation of the first multiplexer 230 and the second multiplexer 240. Due to space limitations, this article will not elaborate on the first multiplexer 230 and the second multiplexer 240. For more detailed information on the first multiplexer 230 and the second multiplexer 240, please refer to the relevant technical adaptations known to those skilled in the art.

[0057] Another embodiment of the present invention provides a chip on which a control circuit structure for a column memory is integrated, wherein the control circuit structure for the column memory is the control circuit structure for a column memory provided in any of the embodiments herein.

[0058] This invention does not limit the manufacturing process or application field of the chip. For example, the chip may be, but is not limited to, a 7nm chip, a 14nm chip, and a 28nm chip; the chip may be, but is not limited to, automotive chips, consumer electronics chips, and medical chips, etc.

[0059] Another embodiment of the present invention provides an image sensor, in some exemplary embodiments of which the image sensor includes a control circuit structure for a column memory provided in any of the embodiments herein; in other exemplary embodiments, the image sensor includes a chip provided in the above embodiments.

[0060] Furthermore, the image sensor provided in this embodiment may further include an image processor. The image processor is used to extract and optimize image information from the data read from the control circuit structure for the column memory (raw image data acquired by the image sensor (e.g., a CMOS or CCD sensor), and output the image to an application for display, storage, or further processing. The optimized image information includes, but is not limited to, noise reduction, other processing (e.g., white balance), mosaic rearrangement, and color adjustment. For more detailed information about image sensors, please refer to the relevant technical adaptations known to those skilled in the art; due to space limitations, this document will not elaborate further.

[0061] Another embodiment of the present invention also provides an imaging device, in some exemplary embodiments of which the imaging device includes a control circuit structure for a column memory provided in any of the embodiments herein; in other exemplary embodiments of which the imaging device includes a chip provided in the above embodiments; and in still other exemplary embodiments of which the imaging device includes an image sensor provided in the above embodiments.

[0062] More specifically, the imaging device provided in this embodiment, in addition to at least a processor, may further include a display component, a communication component, a sensor component, a power supply component, a multimedia component, and an input / output interface, depending on actual needs. The display component, the control circuit structure for the column memory, the communication component, the sensor component, the power supply component, the multimedia component, and the input / output interface are all connected to the processor. The processor may be a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.

[0063] Since the chip, image sensor, and imaging device provided by this invention belong to the same inventive concept as the control circuit structure for column memory provided by this invention, the chip, image sensor, and imaging device provided by this invention have at least all the advantages of the control circuit structure for column memory provided by this invention. For details on the beneficial effects of the chip, image sensor, and imaging device provided by this invention, please refer to the above description of the beneficial effects of the control circuit structure for column memory provided by this invention, which will not be repeated here.

[0064] Compared with the prior art, the control circuit structure, chip, image sensor, and imaging device for column memory provided by the present invention have the following advantages: The control circuit structure for column memory provided by the present invention, by adopting a design in which the projection of the logic control circuit onto the plane of the column memory is located within the region of the column memory, can significantly reduce the load on the control line, thereby effectively reducing the data readout time; furthermore, the logic control circuit can drive the shift register circuit to shift and read the data to be read from the corresponding column memory cell by one bit per clock cycle, while the subsequent data to be read is shifted one bit in the readout direction, which can greatly reduce the data readout time, thereby improving the data readout efficiency.

[0065] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0066] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0067] The above description is merely a description of preferred embodiments of the control circuit structure, chip, image sensor, and imaging device for columnar memory provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.< / n>

Claims

1. A control circuit structure for a columnar memory, characterized in that, The column memory includes 2N memory banks arranged sequentially along the column direction of the column memory, and each memory bank includes M column memory cells; the control circuit structure includes an electrically connected logic control circuit and at least one shift register circuit, each shift register circuit corresponds to one or more of the column memory cells, and the projection of the logic control circuit on the plane where the column memory is located is located within the region where the column memory is located; The logic control circuit is configured to drive the shift register circuit to shift and read the data to be read from the corresponding column storage unit in a manner of one bit per clock cycle according to the received read instruction, while the subsequent data to be read is shifted one bit in the read direction, so as to output the data to be read.

2. The control circuit structure according to claim 1, characterized in that, The column memory is used for an image sensor, the image sensor having a bit depth of n, where n < M.

3. The control circuit structure according to claim 1, characterized in that, The logic control circuit is configured to drive the shift register circuit to simultaneously read the data to be read from all the memory banks according to the received read instruction.

4. The control circuit structure according to claim 1, characterized in that, The control circuit structure further includes a first multiplexer. The logic control circuit is configured to drive the first multiplexer to select the memory bank in a time-division multiplexing manner according to the received read instruction, and drive the shift register circuit to read the data to be read from the selected memory bank.

5. The control circuit structure according to claim 1, characterized in that, The control circuit structure further includes a second multiplexer. The logic control circuit is configured to drive the second multiplexer to select one or more of the column storage cells in a time-division manner according to the received read instruction, and drive the shift register circuit to read the data to be read from the selected column storage cells.

6. The control circuit structure according to claim 5, characterized in that, There are N column storage units that are selected, and these N column storage units that are selected simultaneously are located in N storage bodies respectively.

7. The control circuit structure according to any one of claims 1 to 6, characterized in that, The shift register circuit includes an input interface, a shift register, an output interface, and a readout clock that are electrically connected. The shift register is configured to receive the corresponding bits of the data to be read from the column storage unit through the input interface, and to shift and read the data to be read out through the output interface according to the clock signal of the readout clock, one bit per clock cycle.

8. A chip, characterized in that, It integrates a control circuit structure for columnar memory as described in any one of claims 1 to 7.

9. An image sensor, characterized in that, Includes a control circuit structure for a columnar memory as described in any one of claims 1 to 7 or a chip as described in claim 8.

10. An imaging device, characterized in that, Includes a control circuit structure for a columnar memory as described in any one of claims 1 to 7, or a chip as described in claim 9.

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