On-chip integrated light amplification device and preparation method thereof

Abstract

The invention relates to the technical field of optical amplification devices, and particularly discloses an on-chip integrated optical amplification device and a preparation method thereof, the device comprises a micro-ring resonant cavity based on an SOI wafer, a gain medium, an electric pumping structure, an optical coupling structure and a temperature control module; all the functional units are integrated on the same SOI wafer, so that miniaturization and high-density integration of the device structure are realized. The preparation method is based on a standard silicon process, and comprises the steps of manufacturing the resonant cavity and the heavily doped region on the top silicon, depositing the insulating layer, integrating the gain medium, finally forming metal electrode interconnection and the like. The micro-ring resonant cavity is used for enhancing the effect of light and the gain medium, the gain medium is efficiently pumped through the alternating electric field to achieve light amplification, stable performance is maintained by means of the built-in closed-loop temperature control system, and the micro-ring resonant cavity pump has the advantages of being compact in structure, high in integration level, high in pumping efficiency, low in power consumption, stable in work, good in compatibility with the CMOS technology and the like. The method is suitable for high-speed optical communication and photoelectric integrated systems.

Description

An on-chip integrated optical amplification device and its fabrication method Technical Field

[0001] This invention relates to the field of optical amplification technology, and in particular to an on-chip integrated optical amplification device and its fabrication method. Background Technology

[0002] In the fields of optical communication and optical interconnection, to ensure the power and quality of optical signals after long-distance, large-scale system transmission, it is necessary to periodically amplify signals that have attenuated during transmission due to various reasons (such as optical coupling, waveguide absorption and scattering, and inherent device losses). On-chip integrated optical amplifiers are the core devices for achieving this function. Their goal is to efficiently and stably enhance optical signals on a tiny chip to meet the needs of modern high-density, high-bandwidth optoelectronic integrated systems.

[0003] Several on-chip optical amplification schemes already exist in the prior art. For example, Chinese patent document CN103219646A discloses an optical amplifier, which includes a substrate, a waveguide located on the substrate, and a gain layer covering the amplification part of the waveguide. This scheme uses shapes such as wraparound or circular shapes to increase the length of the light path through the amplifier, thereby increasing the amplification effect of the optical signal. This patent represents the traditional technical approach of using a combination of waveguides and gain materials to achieve optical amplification.

[0004] However, the aforementioned and similar traditional waveguide amplification schemes have some inherent drawbacks. First, the directional, spiral structure generally refers to a spiral loop, not a continuous loop, and does not imply reflection or back-transmission; it is designed to increase path length and reduce area to some extent. Second, to achieve sufficient interaction length between light and the gain material, the waveguide structure (including the directional portion) typically requires a large physical size, resulting in a large overall chip area and low integration density. Finally, efficient and reliable electrical pumping (i.e., electrical excitation) of the gain medium (i.e., the gain layer) is difficult, often requiring complex electrode designs and connection structures, increasing process complexity and instability. Furthermore, the energy efficiency (power consumption) and stability to environmental changes (especially temperature) of these schemes still need improvement. Therefore, how to achieve miniaturization, high integration, simple and reliable electrical pumping, and low-power stable operation while maintaining high performance is a key technical challenge for the development of on-chip integrated optical amplifiers. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide an on-chip integrated optical amplification device and its fabrication method to solve the above problems.

[0006] An on-chip integrated optical amplification device includes an SOI wafer, the SOI wafer including a top silicon layer, and further including: a microring resonator integrated within the top silicon layer; a gain medium disposed above and insulated from the microring resonator; an electric pump structure corresponding to the positions of the microring resonator and the gain medium, for generating an alternating electric field in the gain medium region to excite stimulated emission of the gain medium; an optical coupling structure integrated on the top silicon layer for coupling optical signals into or out of the microring resonator; and a temperature control module integrated on the top silicon layer for adjusting its local operating temperature based on feedback from the output optical power of the optical amplification device.

[0007] Specifically, the electric pump structure includes: an inner heavily doped region and an outer heavily doped region, respectively formed in the top silicon layer by ion implantation and located on the inner and outer sides of the micro-ring resonant cavity; a first metal electrode electrically connected to the inner heavily doped region; and two second metal electrodes electrically connected to the two ends of the outer heavily doped region, respectively. An alternating voltage is applied between the first metal electrode and either of the second metal electrodes to form an alternating electric field passing through the gain medium between the inner heavily doped region and the outer heavily doped region.

[0008] Specifically, the inner heavily doped region is an N-type heavily doped region and the outer heavily doped region is a P-type heavily doped region, or the inner heavily doped region is a P-type heavily doped region and the outer heavily doped region is an N-type heavily doped region.

[0009] Specifically, the gain medium is disposed in the form of a thin film above the microring resonant cavity.

[0010] Specifically, a first insulating layer is provided between the gain medium and the micro-ring resonant cavity.

[0011] Specifically, the gain medium is covered on the top and sides with a second insulating layer.

[0012] Specifically, the materials of the first insulating layer and the second insulating layer include silicon dioxide or hexagonal boron nitride.

[0013] Specifically, the gain medium is a direct bandgap semiconductor thin film, and its material is selected from III-V group semiconductor materials or two-dimensional van der Waals semiconductor materials.

[0014] Specifically, the temperature control module includes: a beam splitter, disposed in the output optical path of the optical coupling structure; a photodetector, used to receive a portion of the output light split by the beam splitter and convert it into an electrical signal; and an external control circuit, electrically connected to the photodetector and the two second metal electrodes. The external control circuit adjusts the DC voltage applied between the two second metal electrodes according to the electrical signal output by the photodetector, thereby adjusting the temperature of the optical amplification device through the resistive heating effect of the outer heavily doped region.

[0015] Specifically, the optical coupling structure includes: a coupling waveguide, fabricated in the top silicon layer and disposed adjacent to the microring resonant cavity, for coupling optical signals into and out of the microring resonant cavity; and a coupler, connected to the coupling waveguide, for realizing optical signal coupling between the optical fiber and the coupling waveguide.

[0016] A method for fabricating an optical amplification device includes the following steps: S1: On the top silicon layer of an SOI wafer, a micro-ring resonator, a coupling waveguide, a beam splitter, and inner and outer pre-doped regions are fabricated using photolithography and etching processes; S2: Using photoresist as a mask, inner heavily doped regions and outer heavily doped regions with opposite conductivity types are formed on the inner and outer pre-doped regions respectively using ion implantation processes; S3: A first insulating layer material is deposited and chemically mechanically polished; S4: A gain dielectric film is integrated on the first insulating layer using bonding or transfer processes; S5: A second insulating layer material is deposited and chemically mechanically polished to encapsulate the gain dielectric film therein; S6: At positions corresponding to the inner and outer heavily doped regions, the second insulating layer and the first insulating layer are photolithographically etched and etched to form vias exposing the inner and outer heavily doped regions; S7: Metal material is deposited and patterned within the vias to form a first metal electrode connected to the inner heavily doped region and two second metal electrodes respectively connected to both ends of the outer heavily doped region.

[0017] Specifically, in step S1, when fabricating the beam splitter, germanium material is epitaxially grown on the silicon waveguide structure of the beam splitter and subsequent fabrication processes are carried out simultaneously to form a photodetector made of germanium material.

[0018] The beneficial effects of this invention are as follows: 1. This invention integrates the micro-ring resonator, gain medium, electric pump structure, optical coupling structure, and temperature control module all on the top silicon layer and the area above it of the same SOI wafer. The micro-ring resonator serves as the core of optical feedback, with the gain medium adjacent to it in the form of an insulating thin film, achieving efficient, short-range interaction between light and the gain material. The electric pump structure utilizes heavily doped regions formed at specific locations in the top silicon layer and their corresponding metal electrodes to apply an alternating electric field, thereby efficiently exciting the gain medium in a non-contact manner. This integrated design eliminates the redundant waveguides and complex electrical interconnect structures required by traditional waveguide amplifiers, significantly reducing the size of the entire optical amplifier from the millimeter level to the tens of micrometer level, achieving a highly compact structure. Simultaneously, this solution is entirely based on mature silicon-based micro / nano fabrication technology, fully compatible with CMOS technology platforms, paving the way for large-scale, low-cost, and highly consistent on-chip optoelectronic system integration; 2. Addressing the inherent problems of temperature sensitivity and performance susceptibility to environmental interference in on-chip optical devices, this invention integrates a closed-loop feedback temperature control module on-chip. This module monitors minute changes in the amplified output optical power in real time using a photodetector and converts the optical signal into an electrical signal. Based on this signal, the external control circuit precisely adjusts the DC voltage applied to specific heating electrodes, using the Joule heating effect of the heating resistor to achieve localized and precise temperature control of the device's operating area. This closed-loop feedback system automatically compensates for the micro-ring resonant wavelength drift caused by changes in ambient temperature, locking the amplifier in its optimal operating state. This not only significantly improves the long-term operational stability and reliability of the optical amplifier but also reduces reliance on high-precision, high-cost external temperature control equipment, enhancing its practicality. Attached Figure Description

[0019] Figure 1 is a top view of the optical amplification device of Embodiment 1; Figure 2 is a cross-sectional view of the optical amplification device of Embodiment 1; Figure 3 is a structural diagram of steps S1-S3 of Embodiment 1; Figure 4 is a structural diagram of steps S4-S7 of Embodiment 1; Figure 5 is a cross-sectional view of the optical amplification device of Embodiment 2; Figure 6 is a structural diagram of step S61 of Embodiment 2.

[0020] The attached figures are labeled as follows: SOI wafer 10, top silicon layer 11, silicon dioxide insulating layer 12, silicon substrate 13, micro-ring resonator 20, gain medium 30, electric pump structure 40, inner heavily doped region 41, outer heavily doped region 42, first metal electrode 43, second metal electrode 44, optical coupling structure 50, coupling waveguide 51, coupler 52, temperature control module 60, beam splitter 61, photodetector 62, first insulating layer 70, second insulating layer 80, through hole 90, third insulating layer 100. Detailed Implementation

[0021] This invention provides an on-chip integrated optical amplification device and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0022] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] Please refer to Figures 1-2: This embodiment discloses an on-chip integrated optical amplification device, including an SOI wafer 10. The SOI wafer 10 includes a top silicon layer 11, a silicon dioxide insulating layer 12, and a silicon substrate 13, arranged sequentially from top to bottom. The top silicon layer 11 has a thickness of approximately 220 nm and serves as the optical transmission layer of the SOI wafer 10. The silicon dioxide insulating layer 12, located below the top silicon layer 11, has a thickness of approximately 3 micrometers. Its function is to provide lower refractive index confinement for the waveguides above (such as the micro-ring resonator 20 and the coupling waveguide 51), confining the light field to propagate within the top silicon layer 11 to achieve low-loss optical waveguides. It also serves as an electrical insulating layer to isolate the active region from the silicon substrate 13. The silicon substrate 13 is the mechanical support substrate of the SOI wafer, providing physical support for the entire device and being compatible with mature CMOS process platforms. The operating wavelength of this device is typically a standard wavelength for optical communication, such as 1550 nm.

[0024] Furthermore, the optical amplification device in this embodiment also includes a micro-ring resonator 20, a gain medium 30, an electric pump structure 40, an optical coupling structure 50, and a temperature control module 60. The micro-ring resonator 20 is fabricated within the top silicon layer 11, and its radius can be selected within the range of 10-50 micrometers according to design requirements, with a width of approximately 400 nm. The size of the micro-ring resonator 20 and the thickness of the top silicon layer 11 together determine its optical mode and resonance characteristics, exhibiting a high quality factor and significantly enhancing the interaction between light and the gain medium 30. The gain medium 30 is disposed above the micro-ring resonator 20, the electric pump structure 40 corresponds to the positions of the micro-ring resonator 20 and the gain medium 30, the optical coupling structure 50 is fabricated on the top silicon layer 11, and the temperature control module 60 is integrated on the top silicon layer 11.

[0025] This application achieves compact and high-density device integration by integrating the microring resonator 20, gain dielectric 30, electric pump structure 40, optical coupling structure 50, and temperature control module 60 onto the top silicon 11 of the same SOI wafer 10. The typical size is on the order of tens of micrometers, far smaller than traditional waveguide amplifier structures that are on the order of millimeters. This highly integrated architecture fully leverages the compatibility of the SOI platform with CMOS processes, facilitating large-scale, low-cost optoelectronic integration.

[0026] Furthermore, in this embodiment, the gain medium 30 is insulated from the micro-ring resonator 20; the electric pump structure 40 is used to form an alternating electric field in the region of the gain medium 30 to excite the gain medium 30 to generate stimulated emission; and the optical coupling structure 50 is used to couple optical signals into or out of the micro-ring resonator 20.

[0027] The optical amplification principle of this application is as follows: A weak optical signal enters the optical amplification device through the optical coupling structure 50 and is coupled into the micro-ring resonator 20. The resonant and enhanced optical field within the micro-ring resonator 20 interacts with the gain medium 30 above. Simultaneously, the electric pump structure 40 applies a high-intensity alternating electric field parallel to the thin film plane of the gain medium 30 in the region of the gain medium 30. This electric field accelerates the free charges in the gain medium 30, generating a large number of electron-hole pairs through a collisional ionization process. When the population inversion state is reached, the gain medium 30 is in a stimulated emission state. At this time, the photons resonating in the micro-ring resonator 20 "stimulate" these high-energy electron-hole pairs to recombine, releasing new photons with the same frequency and phase, thereby continuously amplifying the optical signal as it circulates within the resonator. The amplified light is finally coupled back to the output waveguide. This structure, combining a high-Q micro-ring resonator 20 and an efficient electric field pump, is beneficial for achieving low-energy-consumption, high-gain signal amplification.

[0028] Furthermore, this application incorporates a temperature control module 60, which adjusts the local operating temperature of the optical amplifier based on feedback from the output optical power. The principle of temperature control is as follows: a very small portion (e.g., 1%) of the amplified output light is separated by the beam splitter 61 in the temperature control module 60 and fed into the photodetector 62. The photodetector 62 (e.g., an epitaxial germanium detector) converts this optical power signal into a corresponding electrical signal (current or voltage) and sends it to the external control circuit. Since the resonant wavelength of the micro-ring resonant cavity 20 drifts with temperature, causing changes in output optical power, the external control circuit monitors this electrical signal in real time to determine whether the device is operating in its optimal state (e.g., at the maximum output power point). If a power deviation is detected, the external control circuit dynamically adjusts the DC voltage applied between the two second metal electrodes 44. Because the outer heavily doped region 42 itself has resistance, the DC current flowing through it generates heat due to the Joule heating effect, thereby achieving precise heating of a localized area of ​​the entire device. This closed-loop feedback control can stabilize the device's operating temperature near the set value, with an adjustment range of tens of degrees Celsius and an accuracy on the order of 0.01℃. This effectively suppresses the interference of ambient temperature fluctuations on amplifier performance and ensures its long-term stable operation.

[0029] Furthermore, the electric pump structure 40 includes an inner heavily doped region 41, an outer heavily doped region 42, a first metal electrode 43, and two second metal electrodes 44. The inner heavily doped region 41 and the outer heavily doped region 42 are formed in the top silicon layer 11 by ion implantation and are located on the inner and outer sides of the microring resonator 20, respectively. The outer heavily doped region 42 is designed as a notched ring structure with a difference in inner and outer diameter of approximately 5-20 micrometers to provide a suitable heating resistance and electric field distribution area. The spacing between the inner and outer heavily doped regions 41 and 42 and the edge of the microring resonator 20 is designed to be 0.2-1 micrometer. This spacing is a key design parameter: it needs to ensure that the electric field applied to the gain medium 30 has sufficient strength while effectively avoiding the absorption loss of the fine optical modes in the microring resonator 20 by the heavily doped material, thereby ensuring the high quality factor of the microring. The first metal electrode 43 is electrically connected to the inner heavily doped region 41; the two second metal electrodes 44 are electrically connected to the two ends of the outer heavily doped region 42, respectively.

[0030] When an alternating voltage is applied between the first metal electrode 43 and any of the second metal electrodes 44, an alternating electric field passing through the gain medium 30 is formed between the inner heavily doped region 41 and the outer heavily doped region 42. The principle of energization is as follows: When a high-frequency alternating voltage is applied between the first metal electrode 43 (connecting the N-type inner heavily doped region 41) and a second metal electrode 44 (connecting the P-type outer heavily doped region 42), a high-intensity parallel alternating electric field is formed in the semiconductor region between them (including the location of the gain medium 30 above) due to the excellent conductivity of the inner and outer heavily doped regions 41 and 42. The frequency of this electric field is typically on the order of GHz to match the excitation dynamics of charge carriers in the gain medium; the voltage amplitude is typically between a few volts and tens of volts, depending on the spacing between the heavily doped regions and the characteristics of the dielectric material. The electrode structure does not form an ohmic contact directly with the gain medium 30. Instead, it acts on the thin film of the gain medium 30 through an electric field, which accelerates the free charges in the film and gives them energy. Through the collision ionization process, a large number of electron-hole pairs are generated, thereby achieving efficient "electric pumping" and exciting the generation of a population inversion state for optical amplification.

[0031] In a preferred embodiment, the first metal electrode 43 and the two second metal electrodes 44 can be made of highly conductive metal materials such as aluminum, copper, or gold, and fabricated through physical vapor deposition (e.g., sputtering) and subsequent photolithography and etching processes. Their thickness ranges from several hundred nanometers to several micrometers, and their size is generally greater than 20 micrometers to ensure reliable electrical connection. The via shape is similar to the shape of the heavily doped region it connects to, but the area is slightly smaller than the heavily doped region. Applying high-frequency alternating current to the first metal electrode 43 and one second metal electrode 44 creates an alternating electric field in the gain medium 30 region, which is used for electric pumping to excite the gain. Applying direct current to the two second metal electrodes 44 allows current to flow through the annular outer heavily doped region 42, generating Joule heating through its resistance, thereby achieving active temperature control. This separate design of the three electrodes allows the AC pumping and DC heating functions to be performed independently and without interference.

[0032] In a preferred embodiment, the inner heavily doped region 41 is an N-type heavily doped region, and the outer heavily doped region 42 is a P-type heavily doped region. The N-type heavily doped region is typically formed by implanting donor impurities such as phosphorus ions, while the P-type heavily doped region is formed by implanting acceptor impurities such as boron ions. The doping concentration of both is not less than 1 × 10⁻⁶. 19 cm -3To ensure good metallic contact and conductivity, the pre-doped regions are defined in the top silicon layer 11 by photolithography. Using photoresist as a mask, ion implantation is then used to implant the corresponding impurities into the predetermined regions. A high-temperature annealing process then activates the impurities and repairs lattice damage, forming the desired heavily doped regions. After doping, the N-type and P-type heavily doped regions will exhibit good conductivity, and when an AC voltage is applied, a strong electric field can be established more effectively in the region near the gaps.

[0033] Of course, in other embodiments, the inner heavily doped region 41 can be a P-type heavily doped region and the outer heavily doped region 42 can be an N-type heavily doped region. The ion doping types of the inner heavily doped region 41 and the outer heavily doped region 42 can be interchanged to achieve similar effects.

[0034] In a preferred embodiment, the gain medium 30 is disposed above the microring resonator 20 in the form of a thin film. The gain medium 30 is a direct bandgap semiconductor thin film, and its material is selected from III-V group semiconductor materials or two-dimensional van der Waals semiconductor materials. The thickness of the thin film is in the range of several nanometers to tens of nanometers. Specific examples of III-V group semiconductor materials include InGaAsP, AlGaInAs, InGaAs / GaAs quantum wells, etc., which have efficient light-emitting characteristics in the communication band. Two-dimensional van der Waals semiconductor materials include monolayer thin films of transition metal chalcogenides, such as WS2, WSe2, MoS2, and MoSe2, which have atomically flat interfaces and unique band structures, and are easy to integrate with silicon-based waveguides through transfer processes. The doping concentration of the gain medium 30 can be designed as needed, typically in the range of 10. 16 cm -3 Magnitude.

[0035] Furthermore, a first insulating layer 70 is disposed between the gain dielectric 30 and the microring resonator 20. The material of the first insulating layer 70 includes silicon dioxide or hexagonal boron nitride. The thickness of the first insulating layer 70 can be adjusted as needed within the process allowance. Its main function is to achieve physical and electrical insulation between the gain dielectric 30 and the underlying silicon-based microring resonator 20. Silicon dioxide is a commonly used insulating material in standard CMOS processes, while hexagonal boron nitride is a high-performance two-dimensional insulating material with an atomically smooth surface and good thermal conductivity. This layer is formed by thin film deposition processes such as chemical vapor deposition and is chemically mechanically polished to obtain a flat surface, providing an ideal substrate for the subsequent integration of the gain dielectric 30.

[0036] Furthermore, a second insulating layer 80 is applied above and to the sides of the gain dielectric 30. The material of the second insulating layer 80 includes silicon dioxide or hexagonal boron nitride. The thickness of the second insulating layer 80 is approximately a few micrometers. Its function is to completely encapsulate and protect the thin film of the gain dielectric 30, isolating it from subsequently formed structures such as metal electrodes to prevent short circuits and contamination. Similar to the first insulating layer 70, it is also fabricated through deposition and chemical mechanical polishing processes to ultimately form a flat dielectric layer surface, facilitating the upper metal interconnect processes.

[0037] Furthermore, the temperature control module 60 includes a beam splitter 61, a photodetector 62, and an external control circuit.

[0038] The beam splitter 61 is located in the output optical path of the optical coupling structure 50. The beam splitter 61 is a passive optical device fabricated in the top silicon layer 11, such as a Y-branch or a multimode interference coupler, which splits a small portion (e.g., 1%) of the light in the main output optical path into the monitoring branch. The photodetector 62 is used to receive a portion of the output light split by the beam splitter 61 and convert it into an electrical signal.

[0039] The photodetector 62 is preferably a germanium detector grown on the silicon waveguide at the output of the beam splitter 61 using an epitaxial process. Germanium material has high absorption efficiency for light in the 1550 nm communication band. The external control circuit is electrically connected to the photodetector 62 and the two second metal electrodes 44.

[0040] The external control circuit can adjust the DC voltage applied between the two second metal electrodes 44 according to the electrical signal output by the photodetector 62, and adjust the temperature of the optical amplification device through the resistance heating effect of the outer heavily doped region 42.

[0041] The specific control logic is a closed-loop feedback process: for example, when the ambient temperature decreases, causing a blue shift in the resonant wavelength of the micro-ring resonator 20, resulting in a decrease in the output optical power at the operating wavelength, the photocurrent detected by the photodetector 62 decreases accordingly. Upon receiving this signal, the external control circuit increases the DC voltage applied between the two second metal electrodes 44 according to a predetermined algorithm (such as proportional-integral-derivative control). The increased DC current flows through the outer heavily doped region 42, generating more Joule heat, raising the local temperature of the device, thereby "pulling" the resonant wavelength of the micro-ring back to the operating wavelength and restoring maximum output power. This integrated temperature control scheme significantly improves the amplifier's robustness to changes in the external environment.

[0042] Furthermore, the optical coupling structure 50 includes a coupling waveguide 51 and a coupler 52. The coupling waveguide 51 is fabricated in the top silicon layer 11 and is adjacent to the micro-ring resonator 20, used to couple optical signals into and out of the micro-ring resonator 20. The gap between the coupling waveguide 51 and the micro-ring resonator 20 is carefully designed (typically on the order of hundreds of nanometers) to achieve a critical coupling state and optimize the efficiency of optical power entering and leaving the resonator. The coupler 52 is connected to the coupling waveguide 51 and is used to couple optical signals between the optical fiber and the coupling waveguide 51. The coupler 52 can be a grating coupler (a periodic grating structure etched on the waveguide surface) or an end-face coupler (the chip end face formed by precision polishing is aligned with the lens fiber). Its function is to efficiently guide or export light from the external optical fiber into or out of the coupling waveguide 51 on the chip, and it is a key interface for connecting the chip to the external optical path.

[0043] As shown in Figures 3 and 4, this application also discloses a method for fabricating an optical amplification device, comprising the following steps: S1: On the top silicon 11 of an SOI wafer 10, a micro-ring resonator 20, a coupling waveguide 51, a beam splitter 61, and inner and outer pre-doped regions are fabricated using photolithography and etching processes; this step is based on standard CMOS micro / nano fabrication technology. First, photoresist is spin-coated onto the top silicon 11. Using a deep ultraviolet or electron beam lithography machine, a mask pattern containing the micro-ring resonator 20, the coupling waveguide 51, the beam splitter 61, and the heavily doped region pattern is transferred onto the photoresist. Subsequently, the top silicon 11 not protected by the photoresist is etched away using a dry etching process such as reactive ion etching, thereby forming a three-dimensional structure of these components on the silicon layer. The etching depth is equal to the thickness of the top silicon 11 (approximately 220 nm) to ensure the formation of the waveguide structure.

[0044] S11: During the fabrication of beam splitter 61, germanium material is epitaxially grown on the silicon waveguide structure of beam splitter 61 to form a germanium-silicon photodiode with a pin structure, i.e., a photodetector 62 made of germanium material. Other fabrication processes involved in photodetector 62 can be completed synchronously with subsequent process steps, requiring virtually no additional independent steps. In a specific silicon waveguide region at the output end of beam splitter 61, a single-crystal germanium thin film is deposited using a selective epitaxial growth process. The thickness and area of ​​the germanium layer are designed to optimize the absorption efficiency and response speed for 1550 nm wavelength light, thereby forming a high-performance on-chip photodetector 62.

[0045] S2: Using photoresist as a mask, an inner heavily doped region 41 and an outer heavily doped region 42 with opposite conductivity types are formed in the inner and outer pre-doped regions respectively through ion implantation. This step uses another photomask to define the regions to be doped. Then, in an ion implanter, a high dose of phosphorus ions (for forming N-type heavy doping) is implanted into the inner pre-doped region, and a high dose of boron ions (for forming P-type heavy doping) is implanted into the outer pre-doped region. The implantation energy and dose are precisely controlled to ensure that the doping concentration is not less than 1 × 10⁻⁶. 19 cm -3 After implantation, rapid thermal annealing is performed to activate impurity ions and repair lattice damage.

[0046] S3: Deposit the first insulating layer 70 material and perform chemical mechanical polishing; a layer of silicon dioxide or hexagonal boron nitride is uniformly deposited on the entire wafer surface using a chemical vapor deposition process to form the first insulating layer 70. Then, chemical mechanical polishing is used to grind the surface of the deposited layer to atomic level flatness, providing a perfect bonding interface for the subsequent bonding or transfer of the gain medium 30.

[0047] S4: Integrate the gain dielectric 30 thin film on the first insulating layer 70 using bonding or transfer processes. Using wafer bonding or precise transfer technology, a high-quality III-V group semiconductor quantum well film or two-dimensional van der Waals semiconductor film pre-prepared on another substrate is completely transferred and bonded to the polished surface of the first insulating layer 70. The bonding interface requires extremely low defect density to ensure good optical and electrical performance. Then, the central region of the gain dielectric 30 and surrounding excess areas are etched to expose the central region of the gain dielectric 30, forming a ring-shaped gain dielectric 30.

[0048] S5: Deposit the second insulating layer 80 material and chemically mechanically polish it to encapsulate the gain dielectric 30 film; then use chemical vapor deposition again to cover it with a thicker layer of silicon dioxide or hexagonal boron nitride to form the second insulating layer 80, completely encapsulating the gain dielectric 30 film. A second chemical mechanical polishing is then performed to further planarize the surface.

[0049] S6: At positions corresponding to the inner heavily doped region 41 and the outer heavily doped region 42, the second insulating layer 80 and the first insulating layer 70 are photolithographically etched to form vias 90 exposing the inner heavily doped region 41 and the outer heavily doped region 42. The pattern of the vias 90 is defined on the second insulating layer 80 using photolithography, and then reactive ion etching is used to sequentially etch through the second insulating layer 80 and the first insulating layer 70 until the surfaces of the inner heavily doped region 41 and the outer heavily doped region 42 in the underlying top silicon 11 are exposed. The etching process requires good anisotropy to form vias with steep sidewalls.

[0050] S7: Deposit and pattern metal material within the via 90 to form a first metal electrode 43 connected to the inner heavily doped region 41, and two second metal electrodes 44 connected to both ends of the outer heavily doped region 42. Then, deposit a thick layer of metal (such as aluminum or copper) across the entire surface using physical vapor deposition (e.g., sputtering). Finally, remove unwanted metal portions through another photolithography and etching process, retaining only the designed first metal electrode 43, second metal electrode 44, and possible interconnect patterns, thus completing the fabrication of the entire device.

[0051] As shown in Figure 5, the optical amplification device in Embodiment 2 differs from Embodiment 1 in that a third insulating layer 100 is provided on the sidewall of the via 90. The material of the third insulating layer 100 is typically silicon dioxide, with a thickness of several nanometers to tens of nanometers. Its key function is to provide strict electrical isolation between the metal electrodes (first metal electrode 43 and second metal electrode 44) subsequently filled into the via 90 and the sidewall of the via 90, especially the edge of the gain dielectric 30 film that may be exposed. This structure effectively prevents short circuits or leakage between the metal electrodes and the gain dielectric 30, improving the reliability and yield of the device. It is an important optimized design to ensure the independent and stable operation of the electric pump structure 40 and the gain dielectric 30.

[0052] As shown in Figure 6, the fabrication method of the optical amplification device in this embodiment differs from that in Embodiment 1 in that step S4 does not require etching the middle region and surrounding redundant regions of the gain medium 30. Step S6 further includes: S61: Depositing a third insulating layer 100 on the sidewall of the via 90. This step is performed after etching the via 90 in step S6 and before metal deposition in step S7. Specifically, a process with excellent step coverage, such as atomic layer deposition, is used to conformally and uniformly deposit a high-quality third insulating layer 100 film on the inner sidewall of the via 90 (including the potentially exposed first insulating layer 70, second insulating layer 80, and sidewall of the gain medium 30). Subsequently, anisotropic etching or etch-back processes can be used to selectively remove the third insulating layer 100 at the bottom of the via 90, retaining only the insulating layer on the sidewall, thereby ensuring good contact between the metal electrode and the heavily doped region at the bottom while achieving complete insulation on the sidewall. While this process step increases the complexity, it significantly improves the electrical isolation performance and long-term reliability of the device.

[0053] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. An on-chip integrated optical amplification device, comprising an SOI wafer (10), said SOI wafer (10) comprising a top silicon layer (11), characterized in that, Also includes: A microring resonator (20) integrated within the top silicon layer (11); a gain medium (30) disposed above and insulated from the microring resonator (20); an electric pump structure (40) corresponding to the positions of the microring resonator (20) and the gain medium (30), used to form an alternating electric field in the region of the gain medium (30) to excite stimulated emission of the gain medium (30); an optical coupling structure (50) integrated on the top silicon layer (11), used to couple optical signals into or out of the microring resonator (20); and a temperature control module (60) integrated on the top silicon layer (11), used to adjust the local operating temperature of the optical amplifier based on the output optical power feedback.

2. The on-chip integrated optical amplification device according to claim 1, characterized in that, The electric pump structure (40) includes: an inner heavily doped region (41) and an outer heavily doped region (42), which are formed in the top silicon layer (11) by ion implantation and located on the inner and outer sides of the micro-ring resonant cavity (20); a first metal electrode (43) electrically connected to the inner heavily doped region (41); and two second metal electrodes (44) electrically connected to the two ends of the outer heavily doped region (42), respectively. When an alternating voltage is applied between the first metal electrode (43) and any of the second metal electrodes (44), an alternating electric field passing through the gain medium (30) can be formed between the inner heavily doped region (41) and the outer heavily doped region (42).

3. The on-chip integrated optical amplification device according to claim 2, characterized in that, The inner heavily doped region (41) is an N-type heavily doped region, and the outer heavily doped region (42) is a P-type heavily doped region, or the inner heavily doped region (41) is a P-type heavily doped region, and the outer heavily doped region (42) is an N-type heavily doped region.

4. The on-chip integrated optical amplification device according to claim 2, characterized in that: The gain medium (30) is disposed in the form of a thin film above the micro-ring resonator (20); a first insulating layer (70) is disposed between the gain medium (30) and the micro-ring resonator (20); a second insulating layer (80) is covered above and to the side of the gain medium (30).

5. The on-chip integrated optical amplification device according to claim 4, characterized in that, The materials of the first insulating layer (70) and the second insulating layer (80) include silicon dioxide or hexagonal boron nitride.

6. The on-chip integrated optical amplification device according to claim 1, characterized in that, The gain medium (30) is a direct bandgap semiconductor thin film, and its material is selected from III-V group semiconductor materials or two-dimensional van der Waals semiconductor materials.

7. The on-chip integrated optical amplification device according to claim 2, characterized in that, The temperature control module (60) includes: a beam splitter (61) disposed in the output optical path of the optical coupling structure (50); a photodetector (62) for receiving a portion of the output light split by the beam splitter (61) and converting it into an electrical signal; and an external control circuit electrically connected to the photodetector (62) and the two second metal electrodes (44). The external control circuit adjusts the DC voltage applied between the two second metal electrodes (44) according to the electrical signal output by the photodetector (62), and adjusts the temperature of the optical amplification device by the resistance heating effect of the outer heavily doped region (42).

8. The on-chip integrated optical amplification device according to claim 1, characterized in that, The optical coupling structure (50) includes: a coupling waveguide (51), which is fabricated in the top silicon layer (11) and disposed adjacent to the micro-ring resonator (20) for coupling optical signals into and out of the micro-ring resonator (20); and a coupler (52), which is connected to the coupling waveguide (51) for realizing optical signal coupling between the optical fiber and the coupling waveguide (51).

9. A method for fabricating an on-chip integrated optical amplification device as described in any one of claims 1-8, characterized in that, Includes the following steps: S1: On the top silicon (11) of the SOI wafer (10), a micro-ring resonator (20), a coupling waveguide (51), a beam splitter (61), and an inner pre-doped region and an outer pre-doped region are fabricated by photolithography and etching processes. S2: Using photoresist as a mask, an inner heavily doped region (41) and an outer heavily doped region (42) with opposite conductivity types are formed in the inner pre-doped region and the outer pre-doped region, respectively, by ion implantation process; S3: Deposit the first insulating layer (70) material and chemically mechanically polish it; S4: Integrate the gain dielectric (30) film on the first insulating layer (70) by bonding or transfer process; S5: Deposit the second insulating layer (80) material and chemically mechanically polish it, and encapsulate the gain dielectric (30) film therein; S6: At a position corresponding to the inner heavily doped region (41) and the outer heavily doped region (42), the second insulating layer (80) and the first insulating layer (70) are photolithographically etched to form a via (90) exposing the inner heavily doped region (41) and the outer heavily doped region (42); S7: Metal material is deposited and patterned in the via (90) to form a first metal electrode (43) connected to the inner heavily doped region (41) and two second metal electrodes (44) respectively connected to both ends of the outer heavily doped region (42).

10. The preparation method according to claim 9, characterized in that: In step S1, when fabricating the beam splitter (61), germanium material is epitaxially grown on the silicon waveguide structure of the beam splitter (61) and subsequent fabrication processes are carried out simultaneously to form a photodetector (62) made of germanium material.

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