Dynamic dead time control in wireless transmission functionality

Abstract

Embodiments described herein provide a wireless power transmitter that dynamically adjusts dead time to reduce power loss. Specifically, a wireless power transmitter includes a transistor circuit for switching a first voltage at a first node and a second voltage at a second node, and an LC circuit coupled between the first node and the second node. The wireless power transmitter also includes a controller coupled to the transistor circuit. The controller is configured to determine whether any one of the first voltage and the second voltage is negative during a dead time of the switching. The controller is configured to increment or decrement the dead time by an adjustment amount depending on whether the negative voltage is detected.

Description

Dynamic dead time control in wireless transmission function Divisional Application Instructions

[0001] This application is a divisional application of Chinese patent application No. 201911269583.7, filed on December 11, 2019, entitled "Dynamic Dead Time Control in Wireless Transmission Function". Cross-referencing

[0002] This application claims the benefit of co-pending and co-owned U.S. Provisional Application No. 62 / 783,064, filed December 20, 2018, under 35 USC §119(e), which is hereby expressly incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to the wireless transmission of electricity, and particularly to controlling the dead time in a wireless power transmitter. Background Technology

[0004] Mobile devices (such as smartphones, tablets, wearables, and other devices) are increasingly using wireless power charging systems. Generally, wireless power transmission involves a transmitter and a receiver. The transmitter drives a transmitter coil, and the receiver has a receiver coil placed near the transmitter coil. The receiver coil receives the wireless power generated by the transmitter coil and uses the received power to power a load, such as a battery charger.

[0005] Several different currently used standards exist for wireless power transmission. More common standards for wireless power transmission include the Wireless Power Consortium (A4WP) standard and the Wireless Power Consortium (WPC) standard, as well as the Qi standard. Under the WPC specification, inductive coupling systems are used to charge a single device with receiver coil circuitry. In the Qi standard, the receiver coil is placed very close to the transmitter coil, while in the A4WP standard, the receiver coil is placed near the transmitter coil (possibly along with other receiver coils belonging to other charging devices).

[0006] Typically, a wireless power system includes a transmitter coil and a receiver coil. The transmitter coil is driven by an alternating current to generate a time-varying magnetic field, and the receiver coil can be part of a device (such as a cellular phone, PDA, computer, or other device) positioned relative to the transmitter coil to receive power transmitted in the time-varying magnetic field. Power transmission losses can often occur during power transfer from the transmitter coil to the receiver coil, which reduces the efficiency of the wireless power charging system.

[0007] Therefore, there is a need to improve the efficiency of wireless power transmission. Summary of the Invention

[0008] In view of the power transmission efficiency problems attributable to dead-time configuration, the embodiments described herein provide a wireless power transmitter that dynamically adjusts the dead time to reduce power loss. Specifically, the wireless power transmitter includes transistor circuitry for switching a first voltage at a first node and a second voltage at a second node, and an LC circuitry coupled between the first and second nodes. The wireless power transmitter also includes a controller coupled to the transistor circuitry. The controller is configured to determine whether either the first or second voltage is negative during the switching dead time (due to body diode conduction of the MOSFET). When neither the first nor the second voltage is negative during the switching dead time, the controller is configured to increment the dead time by an adjustment amount. When one of the first or second voltages is negative during the switching dead time, the controller is configured to decrement the dead time by an adjustment amount.

[0009] These and other embodiments will be discussed below with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 illustrates a wireless power system with a controller for dead-time control according to some embodiments.

[0011] Figure 2 illustrates an example circuit structure of the wireless power transmitter shown in Figure 1 according to some embodiments.

[0012] Figure 3 illustrates example waveforms of voltages generated according to some embodiments to drive the LC circuitry within the wireless power transmitter shown in Figure 2.

[0013] Figure 4 illustrates an example data plot according to some embodiments, which represents the power loss as a function of dead time in the wireless power transmitter shown in Figure 2.

[0014] Figures 5-7 illustrate example waveforms of voltages according to some embodiments, which are generated using different dead-time settings to drive the LC circuitry within the wireless power transmitter shown in Figure 2.

[0015] Figure 8 illustrates an example logic flowchart according to some embodiments, which shows the process of dynamically controlling the dead time to reduce power loss at the wireless transmitter shown in Figure 2.

[0016] These and other aspects of embodiments of the invention are further discussed below. Detailed Implementation

[0017] In the following description, specific details describing some embodiments of the invention are set forth. However, it will be apparent to those skilled in the art that some embodiments may be practiced without some or all of these specific details. The specific embodiments disclosed herein are intended to be illustrative and not restrictive. Other elements, though not specifically described herein, can be implemented by those skilled in the art within the scope and spirit of this disclosure.

[0018] This description illustrates various aspects of the invention, and the embodiments should not be considered limiting—the claims define the protected invention. Various changes may be made without departing from the spirit and scope of this description and the claims. In some instances, well-known structures and techniques have not been shown or described in detail so as not to obscure the invention.

[0019] Figure 1 illustrates a wireless power system 100 according to some embodiments of the present invention. As illustrated in Figure 1, a transmitting device 102 transmits wireless power to a receiving device 104.

[0020] Transmitter 102 is powered by a direct current (DC) input 105 (e.g., from 5V to 19V), which can be obtained from a Universal Serial Bus (USB) bus or an AC / DC power adapter. Transmitter 102 includes a switching transistor array 110 coupled to the DC input source 105 and a transmitter coil 106. The transistor array 110 generates an alternating current that is fed to the transmitter coil 106, which in turn generates a time-varying electromagnetic field. In this way, the transmitter coil 106 supplies power to the receiver coil 108 coupled to the receiver 104 via electromagnetic induction.

[0021] The receiver coil 108 is coupled to a rectifier circuit within the receiving device 104, which receives and rectifies the wireless power received at the receiver coil 108, and then provides an output voltage for battery charging.

[0022] Specifically, transistor array 110 is controlled by controller 115 at transmitter 102. For example, controller 115 is configured to control transistor array 110 to adjust the dead time in the alternating voltage output from transistor array 110 to reduce power loss. Further details regarding the structure and operation of transistor array 110 and controller 115 for dynamic dead time control are discussed below with reference to Figures 2-8.

[0023] Figure 2 illustrates an example circuit structure of the wireless power transmitter 102 shown in Figure 1 according to some embodiments. The wireless transmitter 102 includes an LC circuit comprising a transmitter coil inductor 205 and a capacitor 208 coupled in series. The LC circuit of inductor 205 and capacitor 208 is coupled between node AC1 201 and node AC2 202.

[0024] The LC circuit is driven by an inverter circuit, which is formed by transistor switches 211 (Q1), 212 (Q2), 213 (Q3), and 214 (Q4). Specifically, transistor switches 211 (Q1) and 213 (Q3) are coupled in series to control the output voltage V. DC A transistor bridge is formed between the DC voltage input 105 and ground. Node AC1 201 couples transistor switches 211 (Q1) and 213 (Q3). Similarly, transistor switches 212 (Q2) and 214 (Q4) are coupled in series to connect the voltage input V. DC Another transistor bridge is formed between 105 and ground, and is connected in parallel with the bridge of transistor switches 211 (Q1) and 213 (Q3). Node AC2 202 couples transistor switches 212 (Q2) and 214 (Q4).

[0025] In some embodiments, each of transistor switches 211 (Q1), 212 (Q2), 213 (Q3) and 214 (Q4) includes a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes a body diode connected in parallel or a diode connected in parallel with the transistor.

[0026] The controller 115 is configured to control transistor switches 211 (Q1), 212 (Q2), 213 (Q3), and 214 (Q4) by applying gate voltages to the transistors in Q1-Q4. Specifically, in order to provide AC current through the transmission coil of inductor 205, the gates of transistors 211 (Q1), 212 (Q2), 213 (Q3), and 214 (Q4) are controlled such that during a portion of a time period (e.g., the first half of the duty cycle), transistor switches 211 (Q1) and 214 (Q4) are turned on, while transistor switches 212 (Q2) and 213 (Q3) are turned off, and during a second portion of the time period (e.g., the second half of the duty cycle), transistor switches 212 (Q2) and 213 (Q3) are turned on, while transistor switches 211 (Q1) and 214 (Q4) are turned off. For example, controller 115 is configured to apply gate voltages to transistor switches 211 (Q1) and 214 (Q4), and to apply the inverse gate voltages to transistor switches 212 (Q2) and 213 (Q3), such that transistor switches 211 (Q1) and 214 (Q4), and transistor switches 212 (Q2) and 213 (Q3), are alternately turned on or off. Therefore, the voltage at node 201 of AC1 is V DC The voltage at node 202 of AC2 alternates with the voltage at node 202 of AC1 between 0 (when transistor switches 211 (Q1) and 214 (Q4) are on and transistor switches 212 (Q2) and 213 (Q3) are off) and 0 (when transistor switches 211 (Q1) and 214 (Q4) are off and transistor switches 212 (Q2) and 213 (Q3) are on). Furthermore, the voltage at node 202 of AC2 alternates with the voltage at node 213 of AC1 between 0 (when transistor switches 211 (Q1) and 214 (Q4) are on and 212 (Q2) and 213 (Q3) are off) and V. DC (When transistor switches 211 (Q1) and 214 (Q4) are off and transistor switches 211 (Q2) and 213 (Q3) are on) switch between.

[0027] In some embodiments, the controller is configured to monitor alternating voltages from AC1 node 201 and AC2 node 202, and then adjust the timing of the gate voltages for transistor switches 211 (Q1) and 214 (Q4) or transistor switches 212 (Q2) and 213 (Q3), respectively.

[0028] Figure 3 illustrates example waveforms of voltages generated according to some embodiments to drive an LC circuit of capacitor 208 and inductor 205 within the wireless power transmitter 102 shown in Figure 2. As illustrated in Figures 301 and 302 of Figure 3, during the first portion of the cycle, when Q1 and Q4 are on and Q2 and Q3 are off, node 201 of AC1 is held at V.DC (Shown at segment 303), while AC2 node 202 is held ground (shown at segment 304). During the second part of the cycle, when Q2 and Q3 are on and Q1 and Q4 are off, AC1 node 201 is held ground (shown at segment 305), while AC2 node 202 is held at V. DC (Shown at segment 306).

[0029] The switching time between the first and second parts is called the dead time, where the voltage at node 201 of AC1 changes from V... DC The voltage at AC2 node 202 changes from ground to V. DC For example, dead time is the time interval between the conduction of high-side transistor switches 211 (Q1) and 212 (Q2) on the same half-bridge and the conduction of low-side transistor switches 213 (Q3) and 214 (Q4). Dead time prevents the simultaneous conduction of both high-side and low-side transistors on the same half-bridge. A long dead time will cause the switching transient at the AC1 / AC2 node to complete before the dead time ends. In this case, the MOSFET body diode turns on when the switching transition is completed before the dead time ends. As illustrated in segment 307 or segment 308, when the dead time is too long, overshoot during the transition (e.g., the voltage drops below zero when transitioning from high to low) may occur. A short dead time causes the switching transition at the AC1 / AC2 node to not be completed when the MOSFET is turned on. In this case, a hard switch will occur.

[0030] The switching transient time is determined by the coil current, load conditions, supply voltage, and AC1 / AC2 capacitance, which may vary. Dead time is a parameter that can be set by firmware or hardware to accommodate any switching transient time. In some embodiments, controller 115 is configured to set the dead time for transistor array 110.

[0031] Figure 4 illustrates the power loss versus dead time for an example wireless transmitter circuit 102, such as that shown in Figure 2. As discussed above, a short dead time results in hard switching. Therefore, the energy stored in the AC1 / AC2 capacitors is then dissipated through the transistors and parasitic resistance, leading to energy loss. Conversely, a long dead time results in operation in diode mode, where the body diodes of transistor switches 211-214 (Q1-Q4) are turned on. The power loss during a long dead time is then attributed to the current flowing through the forward voltage of the body diode. The optimized dead time, shown at data point 402, which produces minimal power loss, can lead to the avoidance of hard switching or diode mode.

[0032] Figures 5-7 illustrate example waveforms of voltages according to some embodiments, generated using different dead-time settings to drive the LC circuitry within the wireless power transmitter shown in Figure 2. Figure 5 illustrates a dead-time 501 of 50 ns, which causes a hard switch after the dead-time. Figure 6 illustrates a dead-time 602 of 260 ns, as illustrated in Figure 4, which is substantially close to the optimized dead-time, during which the high-to-low transition is completed precisely as the dead-time ends. Figure 7 illustrates operation using a dead-time 702 of 377 ns, which is in diode mode range when the high-to-low transition is completed before the dead-time ends. Figure 7 also illustrates overshoot with a significant negative voltage at nodes AC1 or AC2 during switching. For example, when the AC1 node voltage changes from high to low, the voltage may overshoot to the negative voltage shown at segment 704. Simultaneously, when the AC2 node voltage changes from low to high, the voltage may overshoot to the larger positive voltage shown at segment 706 during switching.

[0033] Therefore, according to some embodiments, controller 115 is configured to perform a dynamic dead-time optimization function. In some embodiments, controller 115 may include a zero-crossing detection circuit block that can detect, as illustrated in FIG. 7, when AC1 or AC2 transitions to a negative voltage, indicating operation in diode mode. Therefore, if a negative voltage is detected, indicating that the voltage transition from high to low has been completed before the end of the dead time, the dead time can be decreased. If no negative voltage is detected, indicating that the voltage transition from high to low may not have been completed before the end of the dead time, the dead time can be increased. Thus, regardless of the initial value of the dead time, the final dead time will converge to the optimal dead time.

[0034] Figure 8 illustrates an example logic flowchart according to some embodiments, showing a process 800 of dynamically controlling the dead time to reduce power loss at the wireless transmitter shown in Figure 2. At step 802, the switching voltages at nodes AC1 and AC2 in transistor array 110 are generated using the switching dead time. At step 804, the LC circuits (205 and 208) are driven by the switching voltage. At step 806, zero crossings are monitored to detect negative voltages on nodes AC1 and / or AC2 during the dead time. At step 808, the controller determines whether the voltage at either node AC1 or AC2 is negative during the switching dead time. At step 812, when a negative voltage is detected, the dead time is decremented by an adjustment value. At step 810, when no negative voltage is detected, the dead time is incremented by an adjustment value. The adjustment value can be predetermined, for example, 5 ns, 10 ns, 15 ns, etc.

[0035] The above detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the invention. The invention is set forth in the following claims.

Claims

1. A wireless power transmitter, comprising: A transistor circuit for switching a first voltage at a first node and a second voltage at a second node, the transistor circuit including a first transistor bridge and a second transistor bridge connected in parallel with the first transistor bridge, the first transistor bridge including a first transistor switch and a second transistor switch connected through the first node, and the second transistor bridge including a third transistor switch and a fourth transistor switch connected through the second node; an LC circuit coupled between the first node and the second node; The controller, coupled to the transistor circuit, includes a zero-crossing detection circuit configured to detect when the first node or the second node transitions to a negative voltage, and the controller is configured to: determine whether either the first voltage or the second voltage is negative during a switching dead time, the switching dead time representing the time to complete the switching; increment the dead time by an adjustment amount when neither the first voltage nor the second voltage is negative during the switching dead time, or decrement the dead time by the adjustment amount when one of the first voltage and the second voltage is negative during the switching dead time; and repeat the following operations: determine whether either the first voltage or the second voltage is negative during an increased or decreased dead time, and increment the dead time by an adjustment amount when neither the first voltage nor the second voltage is negative during the increased or decreased dead time, or decrement the dead time by the adjustment amount when one of the first voltage and the second voltage is negative during the increased or decreased dead time.

2. The wireless power transmitter of claim 1, wherein the controller applies a first gate voltage to the first transistor switch and the fourth transistor switch, and applies an inversion of the first gate voltage to the second transistor switch and the third transistor switch, such that the first transistor switch and the fourth transistor switch, and the second transistor switch and the third transistor switch, are alternately turned on or off.

3. The wireless power transmitter of claim 1, wherein the first voltage is fed as a first gate voltage to the first transistor switch and the fourth transistor switch, and the second voltage is fed as a second gate voltage to the second transistor switch and the third transistor switch.

4. The wireless power transmitter of claim 2, wherein the first voltage at the first node switches between a value equal to the input voltage and zero with a switching first dead time, and the second voltage at the second node switches opposite to the first voltage between zero and the value equal to the input voltage with a switching second dead time.

5. The wireless power transmitter of claim 1, wherein the controller is further configured to: set the dead time via firmware or hardware using an incrementing or decrementing adjustment amount; and operate the transistor circuit with the dead time having the incrementing or decrementing adjustment amount.

6. A method for dynamically controlling the dead time of voltage switching in a wireless power transmitter, comprising: A switching voltage is generated at a first node and a second node of a transistor circuit with a dead time. The transistor circuit includes a first transistor bridge and a second transistor bridge connected in parallel with the first transistor bridge. The first transistor bridge includes a first transistor switch and a second transistor switch connected through the first node, and the second transistor bridge includes a third transistor switch and a fourth transistor switch connected through the second node. The switching voltage drives an LC circuit coupled between the first node and the second node. Zero-crossing detection detects when the first node or the second node transitions to a negative voltage, and determines whether either the first voltage or the second voltage is negative during the dead time of the switching, wherein the dead time of the switching represents the time to complete the switching; When neither the first voltage nor the second voltage is negative during the switching dead time, the dead time is increased by a first adjustment amount, or when one of the first voltage and the second voltage is negative during the switching dead time, the dead time is decreased by a second adjustment amount, and the following operations are repeated: determining whether either the first voltage or the second voltage is negative during the increased or decreased dead time, and increasing the dead time by an adjustment amount when neither the first voltage nor the second voltage is negative during the increased or decreased dead time, or decreasing the dead time by an adjustment amount when one of the first voltage and the second voltage is negative during the increased or decreased dead time.

7. The method of claim 6, further comprising receiving an input voltage at the transistor circuit.

8. The method of claim 7, wherein generating switching voltages at the first and second nodes of the transistor circuit with a dead time comprises: The first transistor switch and the fourth transistor switch, as well as the second transistor switch and the third transistor switch, are alternately turned on or off by applying a first gate voltage to the first transistor switch and the fourth transistor switch, and applying an inverted version of the first gate voltage to the second transistor switch and the third transistor switch.

9. The method according to claim 7, further comprising: The first voltage is fed as the first gate voltage to the first transistor switch and the fourth transistor switch; And the second voltage is fed as a second gate voltage to the second transistor switch and the third transistor switch.

10. The method of claim 8, further comprising: The first voltage at the first node switches between a value equal to the input voltage and zero with a first dead time, and the second voltage at the second node switches between zero and the value equal to the input voltage with a second dead time, opposite to the first voltage.

11. The method of claim 6, further comprising: The dead time is set by increasing or decreasing the adjustment amount via firmware or hardware. The transistor circuit is operated with a dead time having an increasing or decreasing adjustment amount.

12. A system for dynamically controlling the dead time of voltage switching in a wireless power transmitter, comprising: A component for generating switching voltages at a first node and a second node of a transistor circuit with a dead time, the transistor circuit including a first transistor bridge and a second transistor bridge connected in parallel with the first transistor bridge, the first transistor bridge including a first transistor switch and a second transistor switch connected through the first node, and the second transistor bridge including a third transistor switch and a fourth transistor switch connected through the second node. Components for driving an LC circuit coupled between the first node and the second node by means of the switching voltage; zero-crossing detection for detecting when the first node or the second node transitions to a negative voltage; and components for determining whether either the first voltage or the second voltage is negative during the dead time of the switching, wherein the dead time of the switching represents the time to complete the switching. A component for increasing the dead time by a first adjustment amount when neither the first voltage nor the second voltage is negative during the switching dead time, or a component for decreasing the dead time by a second adjustment amount when one of the first voltage and the second voltage is negative during the switching dead time, and repeating the following operations: determining whether either the first voltage or the second voltage is negative during the increased or decreased dead time, and increasing the dead time by an adjustment amount when neither the first voltage nor the second voltage is negative during the increased or decreased dead time, or decreasing the dead time by an adjustment amount when one of the first voltage and the second voltage is negative during the increased or decreased dead time.

13. The system of claim 12 further includes a component for receiving an input voltage at the transistor circuit.

14. The system of claim 13, wherein the component for generating switching voltages at the first and second nodes of the transistor circuit with a dead time comprises: A component for alternately turning the first transistor switch and the fourth transistor switch, and the second transistor switch and the third transistor switch on or off by means of: a component for applying a first gate voltage to the first transistor switch and the fourth transistor switch, and applying an inversion of the first gate voltage to the second transistor switch and the third transistor switch.

15. The system of claim 13, further comprising: Components for feeding the first voltage as a first gate voltage to the first transistor switch and the fourth transistor switch; And components for feeding the second voltage as a second gate voltage to the second transistor switch and the third transistor switch.

16. The system of claim 14, further comprising: The components are for causing the first voltage at the first node to switch between a value equal to the input voltage and zero with a switching first dead time, and for causing the second voltage at the second node to switch opposite to the first voltage with a switching second dead time between zero and the value equal to the input voltage.

17. The system of claim 12, further comprising: A component for setting the dead time by incrementing or decrementing the adjustment amount via firmware or hardware; And components for operating the transistor circuit with the dead time having an increasing or decreasing adjustment amount.

18. The system of claim 12, further comprising: A component for feeding the first voltage or the second voltage to a transmitter coil, which transmits power through electromagnetic induction.

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