Wide-delay reverse-connection-prevention slow start circuit with pre-charging function

Abstract

The invention discloses a wide-delay reverse-connection-prevention slow start circuit with a pre-charging function, and belongs to the technical field of power management. The circuit comprises an input end, an output end, an anti-reverse-connection switch unit, a time delay unit and a control unit, the input end is connected with a direct-current power supply, the output end is connected with a load, and the anti-reverse-connection switch unit is connected between the input end and the output end and used for being turned off when the direct-current power supply is reversely connected; the delay unit is connected between the output end and the reference ground and is used for pre-charging the output end and generating a delay electric signal from hundreds of milliseconds to seconds; and the control unit is used for receiving the delay electric signal and controlling the anti-reverse connection switch unit to be switched on stably according to the delay electric signal. The back-to-back PMOS tubes are adopted to form the reverse connection prevention switch unit, and the reverse connection prevention switch unit is matched with the second-order RC delay unit and the NPN triode control unit, so that reliable reverse connection prevention, wide-delay slow start from hundreds of milliseconds to seconds, low impedance during forward conduction and low static power consumption are realized, and the reverse connection prevention circuit is particularly suitable for vehicle-mounted, unmanned aerial vehicle, missile-borne and other direct-current power supply systems.

Description

A wide-delay reverse connection protection soft-start circuit with pre-charge function Technical Field

[0001] This invention relates to the field of power management technology, and more specifically to a long-delay reverse connection protection slow-start circuit with pre-charge function for DC power supply systems. Background Technology

[0002] In DC power supply systems for drones, missile-borne devices, and automotive electronics, two major problems are prone to occur during power connection: First, reverse connection, where the positive and negative terminals are reversed due to incorrect wiring, improper plugging or unplugging, or damaged connectors. This can cause sensitive chips and power components in the circuit to be subjected to reverse voltage and suffer permanent damage. Second, the instantaneous current surge when the power is turned on. Direct power-on can cause large surge currents in internal capacitors, voltage regulators, or MCU power-on reset circuits, which cannot change voltage at their ends. This can lead to voltage drops, overcurrent, noise fluctuations, and even chip mis-starting or locking. In addition, mechanical bounce during actual wiring can cause multiple electrical shocks. Therefore, a long-delay soft-start circuit is required.

[0003] In existing technologies, reverse connection protection circuits are mostly implemented using unidirectional diodes, transient voltage suppressor diodes (TVS), or single PMOS transistors, while soft-start circuits often use RC time constants, dedicated counting units, or soft-start ICs. However, these solutions have the following drawbacks: short delay time, making it difficult to achieve a wide delay of more than 100 milliseconds; large power consumption due to diode and RC on-state voltage drop, resulting in low energy efficiency in high-current scenarios; high cost of dedicated soft-start ICs; and large instantaneous current after soft-start, which can easily damage the device. Moreover, existing solutions cannot simultaneously meet the comprehensive requirements of reverse connection protection, wide-delay soft-start, and low power consumption.

[0004] Therefore, there is an urgent need to design a circuit that combines reliable reverse connection protection, wide delay start-up at the millisecond to second level, low power consumption, and low cost to meet the application requirements of DC power supply systems such as drones, missiles, and vehicles. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of large surge current during power-on and difficulty in simultaneously achieving reverse connection protection and wide-delay soft-start function in the prior art, and to provide a wide-delay reverse connection protection soft-start circuit with pre-charge function.

[0006] According to one aspect of the present invention, a wide-delay reverse connection protection soft-start circuit with pre-charge function includes: an input terminal for connecting to a DC power supply; an output terminal configured with an energy storage element for connecting to a load; a reverse connection protection switch unit coupled between the input terminal and the output terminal, including at least one switching element for turning off when the DC power supply is reverse connected; a delay unit coupled between the output terminal and a reference ground for pre-charging the energy storage element and generating a delay electrical signal of a preset duration after the DC power supply is turned on; and a control unit connected to the delay unit and the reverse connection protection switch unit respectively, and configured to: receive the delay electrical signal, and control the reverse connection protection switch unit to switch from a turned-off state to a turned-on state according to the delay electrical signal.

[0007] More specifically, according to the above, the reverse connection protection switch unit includes: a first switching element connected between the input terminal and the first node A; a second switching element connected between the first node A and the output terminal; the first switching element and the second switching element are connected in reverse series and each has a control terminal; the delay unit includes: a pre-charge branch connected between the first node A and the output terminal; the pre-charge branch includes a first current limiting element connected between the first node A and the output terminal and a first energy storage element connected between the output terminal and a reference ground, the first energy storage element constituting the energy storage element of the output terminal. A delay signal generation module, connected between the output terminal and a reference ground, is configured to generate the delay electrical signal based on the voltage at the output terminal. The control unit includes: a third switching element having a control terminal connected to the output terminal of the delay signal generation module; and a third current limiting element connected between the first node A and the third node C. The third node C is also connected to the control terminals of the first switching element and the second switching element. The control unit is configured to control the first switching element and the second switching element to conduct synchronously when the third switching element conducts in response to the delay electrical signal.

[0008] More specifically, according to the above, the delay signal generation module includes: a second current limiting element connected between the output terminal and the second node B; and a second energy storage element connected between the second node B and a reference ground; wherein the second node B constitutes the output terminal of the delay signal generation module.

[0009] More specifically, according to the above, the first switching element is a PMOS transistor Q1, the second switching element is a PMOS transistor Q2, and the third switching element is an NPN transistor Q3; the first current limiting element is a resistor R1, the second current limiting element is a resistor R2, and the third current limiting element is a resistor R4; the first energy storage element is a capacitor C1, and the second energy storage element is a capacitor C2, wherein the drain of the PMOS transistor Q1 is connected to the input terminal, the source is connected to the source of the PMOS transistor Q2 and forms the first node A at the connection point, and the gate serves as a control terminal and is connected to the third node C; the drain of the PMOS transistor Q2... The output terminal is connected to the gate, which serves as the control terminal and is connected to the third node C; the resistor R1 is connected between the first node A and the output terminal; the resistor R2 is connected between the output terminal and the second node B; the resistor R4 is connected between the first node A and the third node C; the capacitor C1 is connected between the output terminal and the reference ground; the capacitor C2 is connected between the second node B and the reference ground; the base of the NPN transistor Q3 serves as the control terminal and is connected to the second node B, the emitter is connected to the reference ground, and the collector is connected to one end of the resistor R4, forming the third node C at the connection point.

[0010] In accordance with the above, more specifically, the resistance value of resistor R1 is not greater than 1kΩ, the resistance value of resistor R2 is not less than 100kΩ, the resistance value of resistor R4 is between 10kΩ and 100kΩ, the capacitance value of capacitor C1 is not less than 100μF, and the capacitance value of capacitor C2 is between 10μF and 100μF.

[0011] In accordance with the above, the wide-delay reverse connection protection soft-start circuit with pre-charge function further includes a Zener diode D1, which is connected between the first node A and the third node C, and the Zener diode D1 has a Zener voltage of 12V.

[0012] In accordance with the above, the wide-delay reverse connection protection soft-start circuit with pre-charge function further includes a resistor R3, which is connected between the collector of the NPN transistor Q3 and the third node C, and the resistance of the resistor R3 is 10kΩ to 100kΩ.

[0013] Based on the above aspects, as a prominent substantive feature of the present invention, the preset duration delay electrical signal is a delay electrical signal on the order of hundreds of milliseconds to seconds.

[0014] According to another aspect of the present invention, a power module is provided, which includes the wide-delay reverse connection protection soft-start circuit with pre-charge function described above.

[0015] According to another aspect of the present invention, an electronic device is provided, which includes a DC power supply and a load, and further includes the wide-delay reverse connection protection soft-start circuit with pre-charge function described above.

[0016] The beneficial effects of the present invention are as follows: According to the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention, by configuring an energy storage element at the output end, the energy storage element is pre-charged after the delay unit is powered on. In the initial stage of power-on, when the anti-reverse connection switch unit is not turned on, a small current is used to gradually replenish the energy storage element at the output end, and the voltage difference between the two ends of the energy storage element is leveled in advance. When the pre-charge process reaches a certain duration, that is, when the voltage level of the delay signal reaches the preset threshold (i.e., the conduction threshold voltage of the third switch element), the anti-reverse connection switch unit is turned on. At this time, there is no sudden change in voltage difference at the moment the switch is turned on, which completely eliminates the large surge current, and at the same time protects the load sensitive device and internal circuit components, solving the problem of large surge current when powered on. In addition, the reverse polarity protection switch unit is dedicated to shutting off the power supply when the polarity is reversed, blocking the reverse current path, and is unaffected by delay or pre-charge operations; the delay unit can directly generate a wide delay electrical signal in the range of hundreds of milliseconds to seconds that is related to the pre-charge duration, without the need for an additional external timing module, and is suitable for scenarios such as power supply plugging and unplugging, and mechanical bouncing of wiring; the control unit only controls the switch to conduct after receiving the delay electrical signal. Therefore, this invention simultaneously achieves three core functions: surge current suppression, reverse polarity protection, and wide delay soft start. It has a high degree of integration, a simple structure, and is suitable for various scenarios such as drones, missiles, and automotive electronics.

[0017] This invention uses back-to-back PMOS transistors Q1 and Q2 to form a reverse connection protection switching unit. When the DC power supply is reversed, Q1 and Q2 are reliably turned off, cutting off the reverse current loop. When the PMOS transistor is forward-biased, the on-resistance is low and there is almost no on-resistance voltage drop, which greatly reduces the on-resistance power consumption and solves the problem of high power consumption of existing diode reverse connection protection.

[0018] The circuit of this invention uses common PMOS transistors, NPN transistors, resistors, capacitors, and Zener diodes, eliminating the need for a dedicated soft-start IC, resulting in low material costs; it also has no additional power-consuming components, low static power consumption, and is compatible with high-efficiency and energy-saving DC power supply systems.

[0019] The core components used in this invention are all general-purpose surface mount devices. The circuit topology is simple, without complex control logic, and is easy to manufacture and miniaturize, meeting the requirements of drones, missiles, automotive electronics and other devices for miniaturization and lightweighting. Attached Figure Description

[0020] Figure 1 is a circuit diagram of an embodiment of the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention.

[0021] Figure 2 is a schematic diagram of an embodiment of the anti-reverse connection soft-start circuit with pre-charge function of the present invention when the power supply is reversed.

[0022] Figure 3 is a schematic diagram of an embodiment of the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention to realize the pre-charge function when powered on.

[0023] Figure 4 is a schematic diagram of the conduction principle of an embodiment of the wide-delay anti-reverse connection slow-start circuit with pre-charge function of the present invention under the control of the control unit.

[0024] Figure 5 is an equivalent circuit diagram of an embodiment of the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention at the moment of power-on.

[0025] Figure 6 is a simulation model diagram of an embodiment of the wide-delay anti-reverse connection slow-start circuit with pre-charge function of the present invention adapted to a 24V DC power supply.

[0026] Figure 7 shows the time-voltage waveform corresponding to the simulation model in Figure 6.

[0027] Figure 8 is a simulation model diagram of an embodiment of the wide-delay reverse connection protection soft-start circuit with pre-charge function of the present invention adapted to a 12V DC power supply.

[0028] Figure 9 shows the time-voltage waveform corresponding to the simulation model in Figure 8.

[0029] Figure 10 is a simulation model diagram of an embodiment of the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention adapted to a 48V DC power supply.

[0030] Figure 11 shows the time-voltage waveform corresponding to the simulation model in Figure 10. Detailed Implementation

[0031] The following detailed description of the wide-delay anti-reverse connection soft-start circuit with pre-charge function of the present invention is provided in conjunction with specific embodiments. The scope of protection of the present invention is not limited to the following embodiments. All equivalent transformations made based on the technical solutions of the present invention fall within the scope of protection of the present invention.

[0032] As shown in Figure 1, according to an embodiment of the present invention, a wide-delay reverse-connection soft-start circuit with pre-charge function includes: an input terminal for connecting to a DC power supply; an output terminal configured with an energy storage element for connecting to a load, wherein in this embodiment, the energy storage element is a capacitor C1; a reverse-connection switch unit coupled between the input terminal and the output terminal, including at least one switch element for turning off when the DC power supply is reverse-connected, preferably, the reverse-connection switch unit includes a first switch element and a second switch element connected in reverse series, both having control terminals, wherein in this embodiment, the first switch element is a PMOS transistor Q1 and the second switch element is a PMOS transistor Q2; and a delay unit coupled between the output terminal and a reference ground (in this embodiment, the negative terminal of the DC power supply, but not limited thereto), for pre-charging the energy storage element and generating a delay signal of a preset duration after the DC power supply is turned on, specifically, the delay unit includes a pre-charge branch configured to pre-charge the energy storage element and generate a delay signal of a preset duration after the DC power supply is turned on. After the circuit is turned on, the energy storage element is charged with a current-limited circuit. The pre-charge branch includes a first current-limiting element and a first energy storage element. The first energy storage element constitutes the energy storage element of the output terminal, namely, capacitor C1. In this embodiment, the first current-limiting element is resistor R1. In addition, the delay unit also includes a delay signal generation module, which is configured to generate a delay electrical signal according to the voltage of the output terminal. The delay signal generation module includes a second current-limiting element and a second energy storage element. In this embodiment, the second current-limiting element is resistor R2 and the second energy storage element is capacitor C2. The unit is also connected to the delay unit and the reverse connection protection switch unit, and is configured to receive the delay electrical signal and control the reverse connection protection switch unit to switch from the off state to the on state according to the delay electrical signal. Specifically, the control unit includes a third switching element with a control terminal and a third current-limiting element. In this embodiment, the third switching element is NPN transistor Q3 and the third current-limiting element is resistor R4.

[0033] This embodiment uses a PMOS transistor as a reverse connection protection switch. It has low on-resistance and low power consumption, and its driving logic is simple (low-level conduction) in high-side switching applications. Furthermore, it utilizes the parasitic body diode inside the PMOS transistor to achieve the natural formation of the pre-charge path: when the power supply is connected in the forward direction, the body diode of Q2 is forward-biased, providing an initial charging path for C1; when the power supply is connected in the reverse direction, the body diodes of both Q1 and Q2 are reverse-biased, automatically cutting off the current path and achieving reverse connection protection.

[0034] This embodiment uses an NPN transistor Q3 as the control switch, which is low in cost, fast in response, and has a clear conduction threshold and excellent switching characteristics. Its base-emitter junction voltage (approximately 0.7V) provides a stable trigger threshold for the delay circuit.

[0035] It is worth mentioning that the input voltage of the circuit in this invention must be greater than the absolute value of the gate-source threshold voltage of the PMOS transistor. Specifically, when the power supply voltage is higher than the gate-source threshold voltage of the PMOS transistor, under the action of the control unit, the gate voltages of Q1 and Q2 are pulled down to near ground potential, and the source voltage is the power supply voltage. Therefore, Vgs ≈ -Vin, which is far greater than the threshold voltage, allowing the PMOS transistor to be fully turned on. The on-resistance is reduced to the milliohm level, thereby minimizing the conduction loss and achieving high-efficiency power transfer. This condition also ensures that after pre-charging, the main power path can provide sufficient current drive capability to meet the normal operating requirements of the load.

[0036] Referring again to Figure 1, the connection relationships of the components in the circuit according to the above embodiment are as follows: the drain of PMOS transistor Q1 is connected to the input terminal, the source is connected to the source of PMOS transistor Q2 and forms a first node A at the connection point, and the gate serves as the control terminal and is connected to the third node C; the drain of PMOS transistor Q2 is connected to the output terminal, and the gate serves as the control terminal and is connected to the third node C; resistor R1 is connected between the first node A and the output terminal; resistor R2 is connected between the output terminal and the second node B; resistor R4 is connected between the first node A and the third node C; capacitor C1 is connected between the output terminal and the reference ground; capacitor C2 is connected between the second node B and the reference ground; the base of NPN transistor Q3 serves as the control terminal and is connected to the second node B, the emitter is connected to the reference ground, and the collector is connected to one end of resistor R4, forming the third node C at the connection point. It should be noted that the second node B is the output terminal of the delay unit of this invention, and the voltage signal at the second node B is the delay electrical signal of this invention.

[0037] Preferably, the circuit further includes a Zener diode D1 connected between the first node A and the third node C. Zener diode D1 limits the gate-source voltage of PMOS transistors Q1 and Q2, preventing gate overvoltage damage and protecting the PMOS transistors. The Zener diode D1 has a Zener voltage of 12V. Under normal operating conditions, the gate-source voltage Vgs of Q1 is -Vin (e.g., -48V), while the gate-source withstand voltage of a typical power PMOS transistor is ±20V to ±30V, thus far exceeding the safe range. D1 clamps the gate-source voltage to its Zener value (e.g., 12V), ensuring that the gate voltages of Q1 and Q2 are always within a safe range, preventing permanent device damage caused by gate oxide breakdown. Simultaneously, the introduction of the Zener diode allows the control unit to provide only a small gate drive current (limited by R4), reducing control power consumption. A 12V regulated voltage is a typical safe voltage for power MOSFET gate drives. It is significantly higher than the threshold voltage of a PMOS transistor (typically -2V to -4V), ensuring full device conduction, while also providing sufficient safety margin (generally less than 50% of the maximum rated gate-source voltage). The 12V regulated voltage is compatible with standard logic levels and drive circuits, facilitating interfacing with subsequent control circuits. Furthermore, 12V Zener diodes are commonly available in the market, offering low cost and easy procurement.

[0038] Preferably, the circuit further includes a resistor R3, which is connected between the collector of the NPN transistor Q3 and the third node C. R3 is used to limit and divide the gate drive current of the PMOS transistor, ensuring gate voltage stability and improving the reliability of the control unit drive. The resistance of R3 is between 10kΩ and 100kΩ. R3, together with the gate input capacitances of Q1 and Q2, forms an RC network, which slows down the rate of gate voltage decrease, thereby controlling the turn-on speed (dV / dt) of the PMOS transistor and achieving a soft-start effect. The value range of R3 (10kΩ~100kΩ) allows for a trade-off between switching speed and conduction losses: a smaller R3 value speeds up the turn-on speed and reduces switching losses; a larger R3 value prolongs the conduction time and further suppresses current surges. This resistor also provides some current-limiting protection for Q3, preventing excessive gate capacitor discharge current from damaging the transistor.

[0039] In various embodiments of the present invention, the resistance value of resistor R1 is not greater than 1kΩ, the resistance value of resistor R2 is not less than 100kΩ, the resistance value of resistor R4 is 10kΩ to 100kΩ, the capacitance value of capacitor C1 is not less than 100μF, and the capacitance value of capacitor C2 is 10μF to 100μF.

[0040] In detail, the resistance of resistor R1 is no greater than 1kΩ to ensure that the pre-charge current is large enough to charge the large-capacity capacitor C1 (≥100μF) to near the power supply voltage within seconds, while limiting the inrush current to a safe range (for example, for a 48V power supply, R1=100Ω can limit the pre-charge current to within 480mA); the resistance of resistor R2 is no less than 100kΩ, which, together with C2 (10μF~100μF), can generate a delay time constant τ = R2×C2 = 1 second to 10 seconds, ensuring that the main switch is triggered to turn on only after C1 is fully charged; the resistance of resistor R4 is 10kΩ to 100kΩ, which can provide a suitable collector load for Q3, ensuring that when Q3 is turned on, the gate voltages of Q1 and Q2 can be pulled down to below the threshold, while limiting the gate discharge current and avoiding EMI problems.

[0041] The working principle of the wide-delay anti-reverse connection slow-start circuit with pre-charge function according to the above embodiments of the present invention is described below.

[0042] As shown in Figure 2, when the power supply is reversed, since there is no current at the base of NPN transistor Q3, NPN transistor Q3 is turned off. Therefore, the gate-source GS voltage of PMOS transistors Q1 and Q2 is 0V, and PMOS transistors Q1 and Q2 are turned off. The anti-parallel diode of PMOS transistor Q1 cuts off the current loop, thereby playing a role in preventing reverse connection.

[0043] As shown in Figure 3, power is applied at time T0. At this time, the base voltage of NPN transistor Q3 is less than 0.7V, so NPN transistor Q3 is turned off. Therefore, the gate-source voltage (GS) of PMOS transistors Q1 and Q2 is 0V, and PMOS transistors Q1 and Q2 are also turned off. The DC power supply charges capacitor C1 through the anti-parallel diode of PMOS transistor Q1 and R1, achieving the pre-charge function. Then, it charges C2 through R2. Thus, the voltage signal at the second node B, i.e., the delayed signal, rises from 0. Before the voltage level of the delayed signal reaches the conduction threshold of transistor Q3, transistor Q3 is turned off, so PMOS transistors Q1 and Q2 remain turned off.

[0044] As shown in Figure 4, when the pre-charge process reaches time T1, the voltage level of the delayed electrical signal has risen to the PN junction voltage of transistor Q3, approximately 0.7V. NPN transistor Q3 begins to conduct, causing the GS voltage of PMOS transistors Q1 and Q2 to become negative. PMOS transistors Q1 and Q2 then conduct, allowing the input DC power supply to be connected to the load terminal with low impedance.

[0045] The following describes the calculation of the slow-start time of the wide-delay reverse-connection slow-start circuit with pre-charge function according to the above embodiment of the present invention.

[0046] At the moment of power-on, the circuit is equivalent to the circuit diagram shown in Figure 5.

[0047] This circuit is a second-order RC charging circuit. The initial conditions are defined as follows: the voltage at the upper node of C1 is... The voltage across C2 is Initial conditions: The capacitor has no stored energy before power is applied; at t=0+, (0)=0, (0) = 0 (the capacitor voltage cannot change abruptly).

[0048] Based on Kirchhoff's Current Law (KCL) and the current-voltage characteristic of a capacitor, the core equation is: the total current flowing through R1. for

[0049] C1 charging current for

[0050] The current flowing through R2 and charging C2 for Derived from KCL

[0051] simultaneous elimination , obtained only about Second-order linear nonhomogeneous differential equation with constant coefficients:

[0052] Solving differential equations The time-domain expression is as follows: The complete solution of the second-order differential equation = steady-state particular solution + transient homogeneous solution.

[0053] Find the steady-state particular solution: Under DC steady-state conditions, the capacitor is equivalent to an open circuit. , Substituting into the equation, we obtain the steady-state value: (∞) = U1, meaning that after being fully charged, the voltage of C2 is equal to the power supply voltage U1.

[0054] Find the homogeneous solution and characteristic roots: The homogeneous equation is:

[0055] This is a standard quadratic equation in one variable, denoted as... , , Discriminant .

[0056] An RC circuit has no inductance, Δ>0, and is overdamped. The two unequal negative real roots are as follows:

[0057]

[0058] The homogeneous solution has the following form: , where A and B are undetermined coefficients.

[0059] By determining the coefficients, we obtain the complete solution of the time-domain expression:

[0060] Substituting the initial conditions to solve for the coefficients: at t=0,

[0061] At t=0, Therefore

[0062] Solving the system of equations simultaneously, we get: Finally, the voltage of C2 is obtained. The time-domain formula:

[0063] according to Calculated

[0064] For the first use case of adapting to a 24V DC power supply in the above embodiments, the expected pre-charge voltage is 23V and the soft start time is 0.39s.

[0065] Figure 6 shows a simulation model of the circuit of the present invention for a first application scenario. The parameter settings of each component in this first application scenario are as follows: DC power supply voltage U1 is 24V; resistor R1 is 1kΩ; R2 is 100kΩ; capacitor C1 is 100μF; C2 is 100μF; R3 and R4 are both 10kΩ. Figure 7 shows the time-voltage waveforms of the four nodes VF1, VF2, VF3 and VF4 of the simulation model for the first application scenario.

[0066] Substitute the parameters of each component into the above formula to calculate.

[0067]

[0068]

[0069]

[0070]

[0071]

[0072] Therefore, the calculated delay time is t = 0.3983s.

[0073] The soft-start time of 0.3983s is basically consistent with the expected soft-start time of 0.39s, and the expected pre-charge voltage value is also consistent. Comparison with simulation results Basically the same.

[0074] As shown in Figure 7, the input voltage VF1 remains at a constant DC level, representing a 24V DC input power supply. VF2, generated by the voltage divider of Zener diode Z1 (1N2813) and resistor R3, serves as the circuit's stable reference voltage, slightly lower than the input voltage VF1. VF3 rapidly builds up during startup, following VF2, and then remains stable. Around 350ms, a step pull-down occurs, transitioning from a high level close to the input voltage to a lower level. This is the circuit's protection / current limiting action, reducing the power transistor's conduction level and limiting the output current by lowering the gate voltage of T2 (PMOS transistor Q2). VF4 exhibits a typical RC charging rise curve during startup, with its rise rate determined by the output capacitor C1 and the load / sampling resistor R2. It eventually approaches the target regulated voltage, briefly fluctuates after 350ms following the action of VF3, and finally stabilizes at the regulated output level of VF1.

[0075] For the second use case of adapting to a 12V DC power supply in the above embodiments, the expected pre-charge voltage is 11V and the soft start time is 0.4s.

[0076] Figure 8 shows the simulation model of the circuit of the present invention for the second application scenario. The parameter settings of each component in the second application scenario are as follows: DC power supply voltage U1 is 12V; resistor R1 is 1kΩ; R2 is 100kΩ; capacitor C1 is 100μF; C2 is 50μF; R3 is 1kΩ; and R4 is 10kΩ. In this application scenario, a smaller filter capacitor C2 is used. A smaller filter capacitor C2 will speed up the feedback loop response, which is suitable for the fast voltage regulation requirements under lower voltages such as 12V; while a larger C2 enhances the filtering effect, which is suitable for the stability under high voltage scenarios of 24V / 48V. Figure 9 shows the time-voltage waveforms of the four nodes VF1, VF2, VF3, and VF4 of the simulation model for the second application scenario.

[0077] For the third usage scenario of adapting to a 48V DC power supply in the above embodiments, the expected pre-charge voltage is 46V and the soft start time is 0.37s.

[0078] Figure 10 shows the simulation model of the circuit of the present invention for a third application scenario. The parameter settings for each component in the third application scenario are as follows: DC power supply voltage U1 is 48V; resistor R1 is 1kΩ; R2 is 200kΩ; capacitor C1 is 100μF; C2 is 100μF; R3 is 20kΩ; and R4 is 10kΩ. In this application scenario, a larger sampling resistor R2 is used. A larger sampling resistor R2 can reduce the sampling current and adapt to the power consumption control requirements under higher input voltages. Figure 11 shows the time-voltage waveforms of the four nodes VF1, VF2, VF3, and VF4 in the simulation model for the third application scenario.

[0079] The above three application scenarios are designed for 24V, 12V, and 48V DC input respectively, proving that the voltage regulation control requirements under different input voltages can be adapted by adjusting the parameters of feedback resistor R3, sampling resistor R2, and filter capacitor C2, thus ensuring stable output voltage.

[0080] The wide-delay reverse-connection soft-start circuit with pre-charge function of the present invention achieves five major technical effects—pre-charge, wide-range delay, low voltage drop, low power consumption, and low cost—through a combination of a pair of back-to-back PMOSFETs, pre-charge, RC delay, and NPN transistor threshold control. It effectively solves the shortcomings of existing technologies, such as the incompatibility between reverse-connection protection and soft-start, low delay, high power consumption, and high cost. The circuit structure of the present invention is simple and inexpensive, suitable for various scenarios such as UAVs, missile-borne systems, automotive electronics, industrial control, and communication base station power supplies, possessing significant market promotion and patent protection value.

[0081] The present application and its embodiments have been described above illustratively. This description is not restrictive, and the accompanying drawings are only one embodiment of the present application. The actual structure is not limited to this. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present application, such designs should fall within the protection scope of the present application.

Claims

1. A wide-delay reverse connection protection soft-start circuit with pre-charge function, characterized in that, include: The input terminal is used to connect to a DC power supply. The output terminal is equipped with an energy storage element for connecting a load; the reverse connection protection switch unit is coupled between the input terminal and the output terminal and includes at least one switching element for shutting off when the DC power supply is reversed. The delay unit, coupled between the output terminal and the reference ground, is used to precharge the energy storage element and generate a delay electrical signal of a preset duration after the DC power supply is turned on. The control unit is connected to the delay unit and the reverse connection protection switch unit respectively, and is configured to: receive the delay electrical signal, and control the reverse connection protection switch unit to switch from the off state to the on state according to the delay electrical signal.

2. The wide-delay reverse connection protection soft-start circuit with pre-charge function according to claim 1, characterized in that, The reverse connection protection switch unit includes: a first switch element connected between the input terminal and the first node A; a second switch element connected between the first node A and the output terminal; the first switch element and the second switch element are connected in reverse series and each has a control terminal; the delay unit includes: a pre-charge branch connected between the first node A and the output terminal, configured to perform current-limited charging of the energy storage element after the DC power supply is turned on; the pre-charge branch includes a first current-limiting element connected between the first node A and the output terminal and a first energy storage element connected between the output terminal and the reference ground, the first energy storage element constituting the output terminal. The control unit includes: an energy storage element at the output terminal; a delay signal generation module connected between the output terminal and a reference ground, configured to generate the delay electrical signal based on the voltage at the output terminal; a third switching element having a control terminal connected to the output terminal of the delay signal generation module; and a third current limiting element connected between the first node A and the third node C; wherein the third node C is also connected to the control terminals of the first switching element and the second switching element; the control unit is configured to: control the first switching element and the second switching element to conduct synchronously when the third switching element conducts in response to the delay electrical signal.

3. The wide-delay anti-reverse connection soft-start circuit with pre-charge function according to claim 2, characterized in that, The delay signal generation module includes: a second current limiting element connected between the output terminal and the second node B; and a second energy storage element connected between the second node B and a reference ground; wherein the second node B constitutes the output terminal of the delay signal generation module.

4. The wide-delay anti-reverse connection soft-start circuit with pre-charge function according to claim 3, characterized in that, The first switching element is a PMOS transistor Q1, the second switching element is a PMOS transistor Q2, and the third switching element is an NPN transistor Q3; the first current limiting element is a resistor R1, the second current limiting element is a resistor R2, and the third current limiting element is a resistor R4; the first energy storage element is a capacitor C1, and the second energy storage element is a capacitor C2. The drain of the PMOS transistor Q1 is connected to the input terminal, its source is connected to the source of the PMOS transistor Q2, forming the first node A at the connection point, and its gate serves as a control terminal and is connected to the third node C; the drain of the PMOS transistor Q2 is connected to the input terminal. The output terminal has its gate as a control terminal and connected to the third node C; resistor R1 is connected between the first node A and the output terminal; resistor R2 is connected between the output terminal and the second node B; resistor R4 is connected between the first node A and the third node C; capacitor C1 is connected between the output terminal and the reference ground; capacitor C2 is connected between the second node B and the reference ground; the base of the NPN transistor Q3 is connected to the second node B as a control terminal, the emitter is connected to the reference ground, and the collector is connected to one end of resistor R4, forming the third node C at the connection point.

5. The wide-delay reverse connection protection soft-start circuit with pre-charge function according to claim 4, characterized in that, The resistance value of resistor R1 is not greater than 1kΩ, the resistance value of resistor R2 is not less than 100kΩ, the resistance value of resistor R4 is between 10kΩ and 100kΩ, the capacitance value of capacitor C1 is not less than 100μF, and the capacitance value of capacitor C2 is between 10μF and 100μF.

6. The wide-delay reverse connection protection soft-start circuit with pre-charge function according to claim 4, characterized in that, It also includes a Zener diode D1, which is connected between the first node A and the third node C, and the Zener diode D1 has a Zener voltage of 12V.

7. The wide-delay reverse connection protection soft-start circuit with pre-charge function according to claim 4, characterized in that, It also includes a resistor R3, which is connected between the collector of the NPN transistor Q3 and the third node C, and the resistance of the resistor R3 is from 10kΩ to 100kΩ.

8. The wide-delay reverse connection protection soft-start circuit with pre-charge function according to any one of claims 1 to 7, characterized in that, The preset duration of the delay signal is a delay signal in the range of hundreds of milliseconds to seconds.

9. A power supply module, characterized in that, Includes the wide-delay reverse connection protection soft-start circuit with pre-charge function as described in any one of claims 1 to 8.

10. An electronic device comprising a DC power supply and a load, characterized in that, It also includes the wide-delay reverse connection protection soft-start circuit with pre-charge function as described in any one of claims 1 to 8.

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