Laminated electronic component

Abstract

This laminated electronic component is provided with a laminated body including a plurality of dielectric layers and a plurality of conductors that are laminated. The laminated body includes: a plurality of first inductors each including at least one first conductor layer and wound around an axis passing through a space surrounded by the at least one first conductor layer; and at least one second inductor, each of which includes a second conductor layer and a plurality of through-holes, and which is wound around an axis passing through a space surrounded by the second conductor layer and the plurality of through-holes. The number of the plurality of first inductors is greater than the number of the at least one second inductor.

Description

Stacked electronic components

[0001] This application was filed on [date]. January 27, 2022 Application number is 202210100730.3 The invention is named Layered type Electronic components A divisional application of the patent application. Technical Field

[0002] This invention relates to a stacked electronic component comprising two inductors. Background Technology

[0003] The following structure is widely used in small mobile communication devices: an antenna is set up that is used in the system and in multiple applications with different frequency bands, and the antenna uses a demultiplexer to separate multiple signals to be transmitted and received.

[0004] Typically, a wavelength division multiplexing (WDM) that separates a first signal at a frequency within a first frequency band and a second signal at a frequency within a second frequency band higher than the first frequency band includes: a common port, a first signal port, a second signal port, a first filter disposed on a first signal path from the common port to the first signal port, and a second filter disposed on a second signal path from the common port to the second signal port. For example, an LC resonator constructed using an inductor and a capacitor is used as the first and second filters.

[0005] As a wavelength division multiplexing (WDM), a WDM using a laminate comprising multiple dielectric layers, as disclosed in Chinese Patent Application Publication No. 107408932A, is known. Additionally, as an inductor for an LC resonator, an inductor constructed using inductor electrodes extending along the short side direction of the laminate and two through-hole conductors extending along the lamination direction of the laminate, as disclosed in Chinese Patent Application Publication No. 107408932A, is known.

[0006] In recent years, the market has demanded miniaturization and space-saving design of small mobile communication devices, which in turn requires miniaturization of the demultiplexers used in these devices. When the LC resonator constituting the filter contains two inductors, miniaturization of the demultiplexer sometimes results in excessively strong electromagnetic coupling between the two inductors. Consequently, the desired characteristics may not always be achieved.

[0007] Chinese Patent Application Publication No. 107408932A discloses a method in which two inductors, each consisting of inductor electrodes and two via-hole conductors, are offset along the long side of the upper surface of a duplexer to reduce electromagnetic coupling between the two inductors. However, if the demultiplexer is miniaturized, the space for offsetting the two inductors also decreases. Therefore, in the method described in Chinese Patent Application Publication No. 107408932A, there is a problem that the electromagnetic coupling between the two inductors cannot be sufficiently reduced in a miniaturized demultiplexer.

[0008] The aforementioned problems are not limited to wave demultiplexers, but are applicable to all stacked electronic components containing two inductors that can be electromagnetically coupled. Summary of the Invention

[0009] The object of the present invention is to provide a stacked electronic component capable of suppressing electromagnetic field coupling between two inductors and achieving desired characteristics.

[0010] The stacked electronic component of the present invention includes: a first port; a second port through which a signal input to the first port passes; a first inductor and a second inductor disposed between the first port and the second port in a circuit structure; and a stack comprising a plurality of stacked dielectric layers and a plurality of conductors for integrating the first port, the second port, the first inductor, and the second inductor. The first inductor has: a first end closest to the first port in the circuit structure, and a second end that is the opposite side to the first end. The second end of the first inductor is connected to one end of the second inductor.

[0011] The laminate includes a first inductor conductor constituting a first inductor and a second inductor conductor constituting a second inductor. The first inductor conductor is wound around an axis extending along a first direction. The second inductor conductor is wound around an axis extending along a second direction intersecting the first direction.

[0012] In the stacked electronic component of the present invention, the first direction and the second direction may be orthogonal to each other. In this case, one of the first direction and the second direction may be parallel to the stacking direction of the plurality of dielectric layers.

[0013] Alternatively, in the stacked electronic component of the present invention, the first inductor and the second inductor may be connected in series on the path connecting the first port and the second port.

[0014] Alternatively, the stacked electronic component of the present invention may further include: a first resonator disposed between the first port and the second port in the circuit structure. Alternatively, a first inductor and a second inductor may be included within the first resonator. In this case, the stacked electronic component may also include: a third port; and a second resonator disposed between the first port and the third port in the circuit structure.

[0015] Furthermore, when the stacked electronic component of the present invention includes a third port, one of the second port and the third port may also be a first signal port that selectively allows a first signal with a frequency within a first passband to pass through, and the other of the second port and the third port may also be a second signal port that selectively allows a second signal with a frequency within a second passband lower than the first passband to pass through. Additionally, the second port may also be a first signal port, and the third port may also be a second signal port.

[0016] Alternatively, in the case where the stacked electronic component of the present invention includes a second resonator, the stack may further include a second resonator conductor constituting the second resonator. In this case, one of the first inductor conductor and the second inductor conductor may be a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers, and the other of the first inductor conductor and the second inductor conductor may be a vertical inductor conductor wound around an axis extending in a direction orthogonal to the stacking direction of the plurality of dielectric layers. The vertical inductor conductor may also be positioned further away from the second resonator conductor than the horizontal inductor conductor.

[0017] Alternatively, in the case where the stacked electronic component of the present invention includes a second resonator, the stack may have: a bottom surface and a top surface located at both ends of the stacking direction of the plurality of dielectric layers, and four side surfaces connecting the bottom surface and the top surface. The shape of each of the bottom surface and the top surface may also be a rectangular shape that is elongated in one direction. The four side surfaces may also include: a first side surface and a second side surface located at both ends of the long side direction of the rectangular shape. In this case, one of the first inductor conductor and the second inductor conductor may be a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers, and the other of the first inductor conductor and the second inductor conductor may be a vertical inductor conductor wound around an axis extending in a direction orthogonal to the stacking direction of the plurality of dielectric layers. The vertical inductor conductor may also be positioned closer to the first side surface than the second side surface. The distance from the vertical inductor conductor to the first side surface may also be less than the distance from the horizontal inductor conductor to the first side surface.

[0018] In the stacked electronic component of the present invention, the first inductor conductor constituting the first inductor is wound around an axis extending along a first direction, and the second inductor conductor constituting the second inductor is wound around an axis extending along a second direction intersecting the first direction. Thus, according to the present invention, a stacked electronic component can be realized that can suppress electromagnetic field coupling between the first and second inductors and achieve desired characteristics.

[0019] Other objects, features and benefits of the present invention will become quite clear from the following description. Attached Figure Description

[0020] Figure 1 is a circuit diagram showing the circuit structure of a stacked electronic component according to an embodiment of the present invention.

[0021] Figure 2 is a perspective view showing the appearance of a stacked electronic component according to an embodiment of the present invention.

[0022] Figures 3A to 3C are explanatory diagrams showing the pattern formation surfaces of the first to third dielectric layers in a laminate of a laminated electronic component according to an embodiment of the present invention.

[0023] Figures 4A to 4C are explanatory diagrams showing the pattern formation surfaces of the fourth to sixth dielectric layers in a laminated electronic component according to an embodiment of the present invention.

[0024] Figures 5A to 5C are explanatory diagrams showing the pattern formation surfaces of the seventh to tenth dielectric layers in a laminated electronic component according to an embodiment of the present invention.

[0025] Figures 6A to 6C are explanatory diagrams showing the pattern formation surfaces of the eleventh to thirteenth dielectric layers in a stack of a stacked electronic component according to an embodiment of the present invention.

[0026] Figures 7A to 7C are explanatory diagrams showing the pattern formation surfaces of the fourteenth to sixteenth dielectric layers in a laminated electronic component according to an embodiment of the present invention.

[0027] Figures 8A to 8C are explanatory diagrams showing the pattern formation surfaces of the seventeenth to twentieth dielectric layers in a stack of a stacked electronic component according to an embodiment of the present invention.

[0028] Figures 9A to 9C are explanatory diagrams showing the pattern formation surfaces of the twenty-first to twenty-third dielectric layers in a stack of a stacked electronic component according to an embodiment of the present invention.

[0029] Figures 10A to 10C are explanatory diagrams showing the pattern formation surfaces of the twenty-fourth to twenty-sixth dielectric layers in a laminated electronic component according to an embodiment of the present invention.

[0030] Figures 11A to 11C are explanatory diagrams showing the pattern formation surfaces of the twenty-seventh to twenty-ninth dielectric layers in a stack of a stacked electronic component according to an embodiment of the present invention.

[0031] Figures 12A and 12B are explanatory diagrams showing the pattern formation surfaces of the thirtieth and thirty-first dielectric layers in a stack of a stacked electronic component according to an embodiment of the present invention.

[0032] Figure 13 is a perspective view showing the interior of a stack of stacked electronic components according to an embodiment of the present invention.

[0033] Figure 14 is a cross-sectional view showing a portion of the interior of the laminate shown in Figure 13.

[0034] Figure 15 is a characteristic diagram illustrating an example of the transmission attenuation characteristics and reflection attenuation characteristics of a stacked electronic component according to an embodiment of the present invention.

[0035] Figure 16 is a characteristic diagram showing the insertion loss of a first filter according to an embodiment of the present invention.

[0036] Figure 17 is a characteristic diagram showing the reflection loss of a first filter according to an embodiment of the present invention. Detailed Implementation

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, referring to FIG1, a general description of the structure of a stacked electronic component (hereinafter simply referred to as electronic component) 1 according to an embodiment of the present invention will be given. The electronic component 1 of this embodiment includes at least: a first port, a second port, a first inductor, and a second inductor. The second port is a port through which a signal input to the first port passes. The first and second inductors are disposed between the first port and the second port in the circuit structure. Furthermore, in this application, the expression "in the circuit structure" does not refer to the configuration in the physical structure, but rather to the configuration in the circuit diagram.

[0038] Figure 1 shows an example of a demultiplexer (duplexer) as an electronic component 1 comprising a first port, a second port, a first inductor, and a second inductor. The demultiplexer includes: a first filter that selectively allows a first signal with a frequency within a first passband to pass through, and a second filter that selectively allows a second signal with a frequency within a second passband lower than the first passband to pass through.

[0039] Electronic component 1 also includes a third port. One of the second and third ports is a first signal port that selectively allows a first signal with a frequency within a first passband to pass through, and the other of the second and third ports is a second signal port that selectively allows a second signal with a frequency within a second passband to pass through. In this embodiment, specifically, electronic component 1 includes: a common port 2 serving as the first port, a signal port 4 serving as the second port, and a signal port 3 serving as the third port. Signal port 4 corresponds to the first signal port. Signal port 3 corresponds to the second signal port.

[0040] The electronic component 1 also includes: a resonator 10 disposed in the circuit structure between the common port 2 and the signal port 3, and a resonator 20 disposed in the circuit structure between the common port 2 and the signal port 4.

[0041] Next, referring to FIG1, an example of the structure of resonators 10 and 20 will be described. Resonator 10 includes: a port 11 connected to a common port 2, a port 12 connected to a signal port 3, a path 13 connecting port 11 and port 12, inductors L11, L12, and L13, and capacitors C11, C12, and C13. Inductors L11 and L12 are connected in series on path 13. Path 13 is part of the path connecting the common port 2 and the signal port 3.

[0042] One end of inductor L11 is connected to port 11. One end of inductor L12 is connected to the other end of inductor L11. The other end of inductor L12 is connected to port 12.

[0043] One end of capacitor C11 is connected to one end of inductor L12. One end of capacitor C12 is connected to the other end of inductor L12. Inductor L13 connects the other ends of capacitors C11 and C12 to ground. Capacitor C13 and inductor L12 are connected in parallel.

[0044] The resonator 20 includes: a port 21 connected to a common port 2, a port 22 connected to a signal port 4, a path 23 connecting the port 21 and the port 22, and LC circuits 24, 25, and 26 disposed between the port 21 and the port 22 in the circuit structure.

[0045] LC circuit 24 includes inductor L21 and capacitors C21 and C22. One end of inductor L21 is connected to port 21. Capacitor C21 is connected in parallel with inductor L21. One end of capacitor C22 is connected to the other end of inductor L21. The other end of capacitor C22 is connected to ground.

[0046] LC circuit 25 includes inductors L22 and L23, and capacitors C23, C24, C25, C26, C27, C28, C29, and C30. One end of capacitor C23 is connected to the other end of inductor L21 in LC circuit 24. One end of capacitor C24 is connected to the other end of capacitor C23. One end of capacitor C25 is connected to the other end of capacitor C24. One end of capacitor C26 is connected to the other end of capacitor C25.

[0047] One end of capacitor C27 is connected to one end of capacitor C23. One end of capacitor C28 is connected to the other end of capacitor C27. The other end of capacitor C28 is connected to the other end of capacitor C26.

[0048] One end of capacitor C29 is connected to the junction of capacitors C23 and C24. The other end of capacitor C29 is connected to the junction of capacitors C26 and C28. One end of inductor L22 is connected to the junction of capacitors C23 and C24. The other end of inductor L22 is connected to ground.

[0049] One end of capacitor C30 is connected to the junction of capacitors C23 and C27. The other end of capacitor C30 is connected to the junction of capacitors C25 and C26. One end of inductor L23 is connected to the junction of capacitors C25 and C26. The other end of inductor L23 is connected to ground.

[0050] LC circuit 26 includes inductors L24 and L25 and capacitors C31, C32, C33, and C34. Inductors L24 and L25 are connected in series on path 23. Path 23 is part of the path connecting common port 2 and signal port 4.

[0051] One end of inductor L24 is connected to the other end of capacitor C26 in LC circuit 25. One end of inductor L25 is connected to the other end of inductor L24. The other end of inductor L25 is connected to port 22.

[0052] One end of capacitor C31 is connected to one end of inductor L24. One end of capacitor C32 is connected to one end of inductor L25. The other ends of capacitors C31 and C32 are connected to ground. Capacitor C33 is connected in parallel with inductor L24. Capacitor C34 is connected in parallel with inductor L25.

[0053] A first signal at a frequency within the first passband selectively passes through path 23 of resonator 20. A second signal at a frequency within the second passband selectively passes through path 13 of resonator 10. Thus, electronic component 1 separates the first and second signals.

[0054] Next, referring to Figure 2, the other structures of electronic component 1 will be described. Figure 2 is a perspective view showing the appearance of electronic component 1.

[0055] Electronic component 1 further includes a laminate 50 comprising multiple dielectric layers and multiple conductors. The laminate 50 is used to integrate a first port, a second port, a third port, a first inductor, and a second inductor. In this embodiment, in particular, the laminate 50 integrates a common port 2, signal ports 3 and 4, and resonators 10 and 20. Resonators 10 and 20 are constructed using multiple conductors.

[0056] The laminate 50 has a bottom surface 50A and a top surface 50B located at both ends of the lamination direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. Side surfaces 50C and 50D face opposite sides to each other, and side surfaces 50E and 50F also face opposite sides to each other. Side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0057] Here, as shown in Figure 2, the X, Y, and Z directions are defined. The X, Y, and Z directions are orthogonal to each other. In this embodiment, the direction parallel to the stacking direction T is designated as the Z direction. Furthermore, the direction opposite to the X direction is designated as the -X direction, the direction opposite to the Y direction as the -Y direction, and the direction opposite to the Z direction as the -Z direction.

[0058] As shown in Figure 2, the bottom surface 50A is located at one end of the laminate 50 in the -Z direction. The top surface 50B is located at one end of the laminate 50 in the Z direction. Both the bottom surface 50A and the top surface 50B are rectangular shapes that are longer in the X direction. The side surface 50C is located at one end of the laminate 50 in the -X direction. The side surface 50D is located at one end of the laminate 50 in the X direction. The side surface 50E is located at one end of the laminate 50 in the -Y direction. The side surface 50F is located at one end of the laminate 50 in the Y direction.

[0059] Electronic component 1 further includes terminals 111, 112, 113, 114, 115, and 116 disposed on the bottom surface 50A of the laminate 50. Terminals 114, 111, and 113 are arranged sequentially along the X direction at a position closer to side surface 50E than side surface 50F. Terminals 116, 112, and 115 are arranged sequentially along the X direction at a position closer to side surface 50F than side surface 50E.

[0060] Terminal 112 corresponds to common port 2, terminal 113 corresponds to signal port 3, and terminal 114 corresponds to signal port 4. Therefore, common port 2 and signal ports 3 and 4 are located on the bottom surface 50A of the laminate 50. Terminals 111, 115, and 116 are connected to ground respectively.

[0061] Next, referring to Figures 3A to 13, an example of the plurality of dielectric layers and the plurality of conductors constituting the laminate 50 will be described. In this example, the laminate 50 has thirty-one dielectric layers stacked together. Hereinafter, these thirty-one dielectric layers will be referred to as the first layer to the thirty-first layer from bottom to top. In addition, the first layer to the thirty-first layer will be represented by the symbols 51 to 81.

[0062] In Figures 3A to 11C, multiple circles represent multiple through holes. Multiple through holes are formed in each of the dielectric layers 51 to 79. Each through hole is formed by filling a conductive paste into its cavity. Each through hole is connected to a conductive layer or other through holes.

[0063] Figure 3A shows the patterned surface of the first dielectric layer 51. Terminals 111 to 116 are formed on the patterned surface of the dielectric layer 51.

[0064] Figure 3B shows the patterning surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the patterning surface of the dielectric layer 52.

[0065] Figure 3C shows the patterning surface of the third dielectric layer 53. Conductor layers 531, 532, 533, and 534 are formed on the patterning surface of the dielectric layer 53.

[0066] Figure 4A shows the patterning surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, and 546 are formed on the patterning surface of the dielectric layer 54. Conductor layer 545 is connected to conductor layer 544.

[0067] Figure 4B shows the patterning surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, 554, 555, 556, and 557 are formed on the patterning surface of the dielectric layer 55. Conductor layer 553 is connected to conductor layer 552. Conductor layers 555 and 556 are connected to conductor layer 554.

[0068] Figure 4C shows the patterning surface of the sixth dielectric layer 56. Conductor layers 561, 562, 563, 564, and 565 are formed on the patterning surface of the dielectric layer 56.

[0069] Figure 5A shows the patterning surface of the seventh dielectric layer 57. Conductor layers 571, 572, 573, 574, 575, and 576 are formed on the patterning surface of the dielectric layer 57. Conductor layer 574 is connected to conductor layer 573. Conductor layer 576 is connected to conductor layer 575.

[0070] Figure 5B shows the patterning surfaces of the eighth and ninth dielectric layers 58 and 59. No conductor layers are formed on the patterning surfaces of dielectric layers 58 and 59.

[0071] Figure 5C shows the patterning surface of the tenth dielectric layer 60. Conductor layers 601 and 602 are formed on the patterning surface of the dielectric layer 60. In addition, in Figure 5C, the symbols 60T1, 60T2, 60T3, and 60T4 represent through-holes for inductors formed in the dielectric layer 60.

[0072] Figure 6A shows the patterned surface of the eleventh dielectric layer 61. Conductor layers 611 and 612 are formed on the patterned surface of the dielectric layer 61. In addition, in Figure 6A, the symbols 61T1, 61T2, 61T3, and 61T4 represent through-holes for inductors formed in the dielectric layer 61.

[0073] Figure 6B shows the patterning surface of the twelfth dielectric layer 62. Conductor layers 621 and 622 are formed on the patterning surface of the dielectric layer 62. In addition, in Figure 6B, the symbols 62T1, 62T2, 62T3, and 62T4 represent through-holes for inductors formed in the dielectric layer 62.

[0074] Figure 6C shows the patterning surface of the thirteenth dielectric layer 63. Conductor layers 631, 632, and 633 are formed on the patterning surface of the dielectric layer 63. In addition, in Figure 6C, the symbols 63T1, 63T2, 63T3, and 63T4 represent inductor vias formed in the dielectric layer 63.

[0075] Figure 7A shows the patterning surface of the fourteenth dielectric layer 64. Conductor layers 641, 642, and 643 are formed on the patterning surface of the dielectric layer 64. In addition, in Figure 7A, the symbols 64T1, 64T2, 64T3, and 64T4 represent through-holes for inductors formed in the dielectric layer 64.

[0076] Figure 7B shows the patterning surface of the fifteenth dielectric layer 65. Conductor layers 651, 652, and 653 are formed on the patterning surface of the dielectric layer 65. In addition, in Figure 7B, the symbols 65T1, 65T2, 65T3, and 65T4 represent through-holes for inductors formed in the dielectric layer 65.

[0077] Figure 7C shows the patterning surface of the sixteenth dielectric layer 66. Conductor layers 661, 662, and 663 are formed on the patterning surface of the dielectric layer 66. In addition, in Figure 7C, the symbols 66T1, 66T2, 66T3, and 66T4 represent through-holes for inductors formed in the dielectric layer 66.

[0078] Figure 8A shows the patterning surface of the seventeenth dielectric layer 67. Conductor layers 671, 672, and 673 are formed on the patterning surface of the dielectric layer 67. In addition, in Figure 8A, the symbols 67T1, 67T2, 67T3, and 67T4 represent inductor vias formed in the dielectric layer 67.

[0079] Figure 8B shows the patterning surface of the eighteenth dielectric layer 68. Conductor layers 681, 682, and 683 are formed on the patterning surface of the dielectric layer 68. In addition, in Figure 8B, the symbols 68T1, 68T2, 68T3, and 68T4 represent through-holes for inductors formed in the dielectric layer 68.

[0080] Figure 8C shows the patterning surfaces of the nineteenth and twentieth dielectric layers 69 and 70. No conductor layers are formed on the patterning surfaces of dielectric layers 69 and 70. Additionally, in Figure 8C, symbols 69T1, 69T2, 69T3, and 69T4 denote vias for inductors formed in dielectric layers 69 and 70.

[0081] Figure 9A shows the patterning surface of the twenty-first dielectric layer 71. Conductor layers 711 and 712 are formed on the patterning surface of the dielectric layer 71.

[0082] Figure 9B shows the patterning surface of the twenty-second dielectric layer 72. No conductor layer is formed on the patterning surface of the dielectric layer 72.

[0083] Figure 9C shows the patterning surface of the twenty-third dielectric layer 73. Conductor layers 731, 732, 733, and 734 are formed on the patterning surface of the dielectric layer 73.

[0084] Figure 10A shows the patterning surface of the twenty-fourth dielectric layer 74. Conductor layers 741, 742, 743, and 744 are formed on the patterning surface of the dielectric layer 74.

[0085] Figure 10B shows the patterning surface of the twenty-fifth dielectric layer 75. Conductor layers 751, 752, and 753 are formed on the patterning surface of the dielectric layer 75.

[0086] Figure 10C shows the patterning surface of the twenty-sixth dielectric layer 76. Conductor layers 761, 762, and 763 are formed on the patterning surface of the dielectric layer 76.

[0087] Figure 11A shows the patterning surface of the twenty-seventh dielectric layer 77. Conductor layers 771, 772, and 773 are formed on the patterning surface of the dielectric layer 77.

[0088] Figure 11B shows the patterning surface of the twenty-eighth dielectric layer 78. Conductor layers 781, 782, and 783 are formed on the patterning surface of the dielectric layer 78.

[0089] Figure 11C shows the patterning surface of the twenty-ninth dielectric layer 79. Conductor layers 791, 792, and 793 are formed on the patterning surface of the dielectric layer 79.

[0090] Figure 12A shows the patterning surface of the thirtieth dielectric layer 80. Conductor layers 801, 802, and 803 are formed on the patterning surface of the dielectric layer 80.

[0091] Figure 12B shows the patterning surface of the thirty-first dielectric layer 81. Marks 811, composed of conductor layers, are formed on the patterning surface of the dielectric layer 81.

[0092] The laminate 50 shown in Figure 2 is constructed by stacking the first to the thirty-first dielectric layers 51 to 81 in such a way that the pattern-forming surface of the first dielectric layer 51 becomes the bottom surface 50A of the laminate 50, and the surface opposite to the pattern-forming surface of the thirty-first dielectric layer 81 becomes the upper surface 50B of the laminate 50.

[0093] Each of the vias shown in Figures 3A to 11C is connected to a conductor layer or other vias overlapping in the stacking direction T when the first to twenty-ninth dielectric layers 51 to 79 are stacked. Additionally, vias located within terminals or conductor layers shown in Figures 3A to 11C are connected to those terminals or conductor layers.

[0094] Figure 13 shows the interior of a laminate 50 constructed by stacking the first to thirty-first dielectric layers 51 to 81. As shown in Figure 13, multiple conductor layers and multiple vias, as shown in Figures 3A to 12B, are stacked inside the laminate 50. Furthermore, the designation 811 is omitted in Figure 13. Additionally, for ease of understanding, the dimensions of the laminate 50 in the stacking direction T are drawn larger than they actually are in Figure 13.

[0095] The following describes the correspondence between the circuit components of the electronic component 1 shown in FIG1 and the internal components of the laminate 50 shown in FIG3A to FIG12B. First, the components of the resonator 10 will be described. The inductor L11 is composed of conductor layers 731, 741, 751, 761, 771, 781, 791, and 801 shown in FIG9C to FIG12A and a plurality of through holes connected to these conductor layers.

[0096] The inductor L12 is composed of conductor layers 611, 621, 631, 641, 651, 661, 671, and 681 as shown in Figures 6A to 8B, and multiple through holes connected to these conductor layers.

[0097] The inductor L13 is composed of the conductor layer 521 shown in Figure 3B.

[0098] The capacitor C11 is composed of conductor layers 531, 541, 551, and 561 as shown in Figures 3C to 4C, and dielectric layers 53 to 55 between these conductor layers.

[0099] The capacitor C12 is composed of conductor layers 531, 542, and 551 as shown in Figures 3C to 4B, and dielectric layers 53 and 54 between these conductor layers.

[0100] The capacitor C13 is composed of conductor layers 561 and 571 as shown in Figures 4C and 5A, and a dielectric layer 56 between these conductor layers.

[0101] Next, the constituent elements of the LC circuit 24 of the resonator 20 will be explained. The inductor L21 is composed of conductor layers 612, 622, 632, 642, 652, 662, 672, and 682 as shown in Figures 6A to 8B, and a plurality of through holes connected to these conductor layers.

[0102] The capacitor C21 is composed of terminal 112 and conductor layer 543 as shown in Figures 3A and 4A, and dielectric layers 51 to 53 between terminal 112 and conductor layer 543.

[0103] The capacitor C22 is composed of terminal 116 and conductor layer 532 as shown in Figures 3A and 3C, and dielectric layers 51 and 52 between terminal 116 and conductor layer 532.

[0104] Next, the constituent elements of the LC circuit 25 of the resonator 20 will be explained. The inductor L22 is composed of conductor layers 732, 742, 752, 762, 772, 782, 792, and 802 as shown in Figures 9C to 12A, and a plurality of through holes connected to these conductor layers.

[0105] The inductor L23 is composed of conductor layers 733, 743, 753, 763, 773, 783, 793, and 803 as shown in Figures 9C to 12A, and multiple through holes connected to these conductor layers.

[0106] The capacitor C23 is composed of conductor layers 543, 552, and 562 as shown in Figures 4A to 4C, and dielectric layers 54 and 55 between these conductor layers.

[0107] The capacitor C24 is composed of conductor layers 553 and 563 as shown in Figures 4B and 4C, and a dielectric layer 55 between these conductor layers.

[0108] The capacitor C25 is composed of conductor layers 554 and 563 as shown in Figures 4B and 4C, and a dielectric layer 55 between these conductor layers.

[0109] The capacitor C26 is composed of conductor layers 544, 555, and 564 as shown in Figures 4A to 4C, and dielectric layers 54 and 55 between these conductor layers.

[0110] The capacitor C27 is composed of conductor layers 562 and 573 as shown in Figures 4C and 5A, and a dielectric layer 56 between these conductor layers.

[0111] The capacitor C28 is composed of conductor layers 564 and 574 as shown in Figures 4C and 5A, and a dielectric layer 56 between these conductor layers.

[0112] The capacitor C29 is composed of conductor layers 545 and 553 as shown in Figures 4A and 4B, and a dielectric layer 54 between these conductor layers.

[0113] The capacitor C30 is composed of conductor layers 532 and 556 as shown in Figures 3C and 4B, and dielectric layers 53 and 54 between these conductor layers.

[0114] Next, the constituent elements of the LC circuit 26 of the resonator 20 will be described. The inductor L24 is composed of conductor layers 633, 643, 653, 663, 673, and 683 as shown in Figures 6C to 8B, and a plurality of through holes connected to these conductor layers.

[0115] The inductor L25 is composed of conductor layers 601, 711, and 712 as shown in Figures 5C and 9A, and through holes 60T1-60T4, 61T1-61T4, 62T1-62T4, 63T1-63T4, 64T1-64T4, 65T1-65T4, 66T1-66T4, 67T1-67T4, 68T1-68T4, and 69T1-69T4 as shown in Figures 5C to 9A.

[0116] Through holes 60T1, 61T1, 62T1, 63T1, 64T1, 65T1, 66T1, 67T1, 68T1, and 69T1 are connected in series. Through holes 60T2, 61T2, 62T2, 63T2, 64T2, 65T2, 66T2, 67T2, 68T2, and 69T2 are connected in series. Through holes 60T3, 61T3, 62T3, 63T3, 64T3, 65T3, 66T3, 67T3, 68T3, and 69T3 are connected in series. Through holes 60T4, 61T4, 62T4, 63T4, 64T4, 65T4, 66T4, 67T4, 68T4, and 69T4 are connected in series.

[0117] A via 69T1 formed in dielectric layer 70 is connected to a portion near one end of conductor layer 711. A via 69T2 formed in dielectric layer 70 is connected to a portion near the other end of conductor layer 711. A via 60T2 formed in dielectric layer 60 is connected to a portion near one end of conductor layer 601. A via 60T3 formed in dielectric layer 60 is connected to a portion near the other end of conductor layer 601. A via 69T3 formed in dielectric layer 70 is connected to a portion near one end of conductor layer 712. A via 69T4 formed in dielectric layer 70 is connected to a portion near the other end of conductor layer 712.

[0118] The capacitor C31 is composed of conductor layers 533 and 544 as shown in Figures 3C and 4A, and a dielectric layer 53 between these conductor layers.

[0119] The capacitor C32 is composed of conductor layers 522 and 534 as shown in Figures 3B and 3C, and a dielectric layer 52 between these conductor layers.

[0120] The capacitor C33 is composed of conductor layers 564 and 575 as shown in Figures 4C and 5A, and a dielectric layer 56 between these conductor layers.

[0121] The capacitor C34 is composed of conductor layers 534, 546, 557, 565, and 576 as shown in Figures 3C to 5A, and dielectric layers 53 to 56 between these conductor layers.

[0122] Next, referring to FIGS. 1, 13, and 14, the structural features of the electronic component 1 of this embodiment will be described. FIG. 14 is a cross-sectional view showing a portion of the interior of the laminate 50 shown in FIG. 13. In this embodiment, the inductor L24 of the LC circuit 26 of the resonator 20 corresponds to the first inductor, and the inductor L25 of the LC circuit 26 of the resonator 20 corresponds to the second inductor.

[0123] Hereinafter, inductor L24 will be referred to as the first inductor L24, and inductor L25 will be referred to as the second inductor L25. As shown in Figure 1, the first inductor L24 and the second inductor L25 are included in resonator 20 and are connected in series on path 23 of resonator 20. Path 23 is part of the path connecting common port 2 (first port) and signal port 4 (second port). The first inductor L24 has a first end that is closest to common port 2 (first port) in the circuit structure, and a second end that is opposite to the first end. The second end of the first inductor L24 is connected to one end of the second inductor L25.

[0124] The laminate 50 includes a first inductor conductor L24c constituting a first inductor L24 and a second inductor conductor L25c constituting a second inductor L25. The first inductor conductor L24c is a conductor structure composed of conductor layers 633, 643, 653, 663, 673, 683 and a plurality of through-holes connected to these conductor layers. The second inductor conductor L25c is a conductor structure composed of conductor layers 601, 711, 712 and through-holes 60T1–60T4, 61T1–61T4, 62T1–62T4, 63T1–63T4, 64T1–64T4, 65T1–65T4, 66T1–66T4, 67T1–67T4, 68T1–68T4, and 69T1–69T4. In Figure 14, solid and dashed lines are used to represent the first and second inductor conductors L24c and L25c.

[0125] In Figure 14, symbol A1 represents an axis passing through the space surrounded by conductor layers 633, 643, 653, 663, 673, and 683. The first inductor conductor L24c is wound around axis A1, which extends along a first direction.

[0126] In Figure 14, symbol A2 represents the axis passing through the space surrounded by conductor layers 601, 711, 712, and through-holes 60T1–60T4, 61T1–61T4, 62T1–62T4, 63T1–63T4, 64T1–64T4, 65T1–65T4, 66T1–66T4, 67T1–67T4, 68T1–68T4, and 69T1–69T4. The second inductor conductor L25c is wound around axis A2, which extends along a second direction intersecting the first direction.

[0127] In this embodiment, the first direction and the second direction are orthogonal to each other. Furthermore, one of the first and second directions is parallel to the stacking direction T. In this embodiment, the first direction is parallel to the Z-direction and also parallel to the stacking direction T. Axis A1 extends in a direction parallel to the stacking direction T. The second direction is parallel to the X-direction. Axis A2 extends in a direction orthogonal to the stacking direction T.

[0128] Here, the inductor conductor wound around an axis extending parallel to the stacking direction T is referred to as a horizontal inductor conductor, and the inductor conductor wound around an axis extending orthogonally to the stacking direction T is referred to as a vertical inductor conductor. In this embodiment, the first inductor conductor L24c is a horizontal inductor conductor, and the second inductor conductor L25c is a vertical inductor conductor.

[0129] As described above, the bottom surface 50A and the top surface 50B of the laminate 50 are each rectangular in shape, elongated in the X direction. Of the four sides 50C, 50D, 50E, and 50F of the laminate 50, sides 50C and 50D are located at both ends of the long side of the aforementioned rectangular shape. As shown in FIG14, the second inductor conductor L25c, which is a vertical inductor conductor, is positioned closer to side 50C than side 50D. The distance from the second inductor conductor L25c to side 50C is less than the distance from the first inductor conductor L24c, which is a horizontal inductor conductor, to side 50C.

[0130] The laminate 50 further includes a resonator conductor constituting the resonator 10. The resonator conductor is a conductor structure consisting of multiple conductor layers constituting each of the inductors L11-L13 and capacitors C11-C13, and multiple through-holes connected to these conductor layers. In FIG14, the multiple conductor layers constituting the inductors L11-L13 in the resonator conductor are indicated by dashed lines. The resonator conductor is positioned closer to the side surface 50D than the side surface 50C. Therefore, the second inductor conductor L25c, which is a vertical inductor conductor, is positioned further away from the resonator conductor than the first inductor conductor L24c, which is a horizontal inductor conductor. Furthermore, the second inductor conductor L25c is positioned further away from the multiple conductor layers constituting the inductors L11-L13 than the first inductor conductor L24c.

[0131] Next, an example of the characteristics of the electronic component 1 in this embodiment is shown. FIG15 is a characteristic diagram showing an example of the transmission attenuation characteristics and reflection attenuation characteristics of the electronic component 1. In FIG15, the curve marked with symbol 91 represents the transmission attenuation characteristics of the second filter composed of the resonator 10 disposed between the common port 2 and the signal port 3. In addition, the curve marked with symbol 92 represents the transmission attenuation characteristics of the first filter composed of the resonator 20 disposed between the common port 2 and the signal port 4. In addition, the curve marked with symbol 93 represents the reflection attenuation characteristics of the common port 2.

[0132] Figure 16 is a characteristic plot showing the insertion loss of the first filter. Figure 17 is a characteristic plot showing the reflection loss of the first filter. In Figure 16, the horizontal axis represents frequency, and the vertical axis represents insertion loss. In Figure 17, the horizontal axis represents frequency, and the vertical axis represents reflection loss.

[0133] Next, the function and effects of the electronic component 1 in this embodiment will be explained. As described above, in this embodiment, the second end of the first inductor L24 is connected to one end of the second inductor L25. If the electronic component 1 is miniaturized, the distance between two inductors, such as the first and second inductors L24 and L25, which are close in circuit structure, becomes smaller, and the electromagnetic field coupling between the two inductors becomes stronger. In particular, when the two inductors, as described in Chinese Patent Application Publication No. 107408932A, are arranged such that the two inductor conductors constituting the two inductors are both wound around an axis extending in the same direction, and one of the two inductor conductors overlaps the other when viewed from the axial direction, the electromagnetic field coupling between the two inductors tends to become stronger.

[0134] In contrast, in this embodiment, the first inductor conductor L24c constituting the first inductor L24 is wound around an axis A1 extending along a first direction, and the second inductor conductor L25c constituting the second inductor L25 is wound around an axis A2 extending along a second direction intersecting the first direction. Therefore, according to this embodiment, electromagnetic field coupling between the first inductor L24 and the second inductor L25 can be suppressed compared to the case described above. Thus, according to this embodiment, the electronic component 1 can be miniaturized, and the desired characteristics can be achieved. Specifically, as shown in FIG15, the pass-through attenuation in frequency bands higher than the first passband (approximately 3 GHz to approximately 8 GHz) can be increased.

[0135] Furthermore, in this embodiment, the first direction and the second direction are orthogonal to each other. Therefore, according to this embodiment, electromagnetic field coupling between the first inductor L24 and the second inductor L25 can be further suppressed.

[0136] However, compared to horizontal inductor conductors, vertical inductor conductors are more prone to electromagnetic field coupling with other conductors arranged in a direction orthogonal to the stacking direction T. In this embodiment, the first inductor conductor L24c is a horizontal inductor conductor, and the second inductor conductor L25c is a vertical inductor conductor. The first and second inductor conductors L24c and L25c are arranged relative to the side surface 50C in the positional relationship described above. Therefore, according to this embodiment, compared to the case where the distance from the second inductor conductor L25c to the side surface 50C is greater than the distance from the first inductor conductor L24c to the side surface 50C, the distance from other conductors arranged on the side surface 50D can be increased. As a result, according to this embodiment, electromagnetic field coupling between the second inductor conductor L25c and other conductors arranged on the side surface 50D can be suppressed.

[0137] Furthermore, the electronic component 1 in this embodiment is a demultiplexer (duplexer) comprising a resonator 10 disposed between the common port 2 and the signal port 3, and a resonator 20 disposed between the common port 2 and the signal port 4. First and second inductors L24 and L25 are included in the resonator 20. The first and second inductor conductors L24c and L25c are arranged relative to the resonator conductor constituting the resonator 10 in the aforementioned positional relationship. Therefore, according to this embodiment, it is possible to prevent the deterioration of the isolation characteristics between the signal port 3 and the signal port 4 due to electromagnetic field coupling between the second inductor conductor L25c included in the resonator 20 and the resonator conductor constituting the resonator 10.

[0138] Furthermore, the present invention is not limited to the above-described embodiments and various modifications are possible. For example, the electronic component of the present invention may be an electronic component that only includes the resonator 20 as a circuit element, or it may be an electronic component that only includes the LC circuit 26 as a circuit element. The electronic component that only includes the resonator 20 functions as a bandpass filter. The electronic component that only includes the LC circuit 26 functions as a low-pass filter.

[0139] Furthermore, the first and second inductor conductors of the present invention can also be applied to two inductors other than inductors L24 and L25, provided that the second terminal of the first inductor is connected to one terminal of the second inductor. Specifically, the first and second inductor conductors of the present invention can also be applied to inductors L11 and L12 of resonator 10 or inductors L22 and L23 of LC circuit 25 of resonator 20. The groups of inductors L11 and L12 and the groups of inductors L22 and L23 both satisfy the requirement that the second terminal of the first inductor is connected to one terminal of the second inductor.

[0140] In addition, the second end of the first inductor and one end of the second inductor can be directly connected or indirectly connected.

[0141] Alternatively, contrary to the implementation method, the first inductor conductor constituting the first inductor L24 may also be a vertical inductor conductor, and the second inductor conductor constituting the second inductor L25 may also be a horizontal inductor conductor.

[0142] Based on the above description, it is obvious that various modes or variations of the present invention can be implemented. Therefore, within the equivalent scope of the claims, the present invention can also be implemented in ways other than the preferred mode described above.

Claims

1. A stacked electronic component, wherein, The device comprises: a laminate including a plurality of stacked dielectric layers and a plurality of conductors, the laminate including: a plurality of first inductors, each including at least one first conductor layer and wound around an axis centered on a space surrounded by the at least one first conductor layer; and at least one second inductor, each including a second conductor layer and a plurality of through holes and wound around an axis centered on a space surrounded by the second conductor layer and the plurality of through holes, wherein the number of the plurality of first inductors is greater than the number of the at least one second inductor.

2. The stacked electronic component according to claim 1, wherein, It also includes: a first port; and a second port through which a signal input to the first port passes, the plurality of first inductors including: a plurality of specific first inductors connected in series between the first port and the second port in the circuit structure, and the at least one second inductor including: a specific second inductor connected in series between the first port and the second port in the circuit structure and in number less than the plurality of specific first inductors.

3. The stacked electronic component according to claim 2, wherein, It also has a third port, wherein one of the second port and the third port is a first signal port that selectively allows a first signal with a frequency within a first passband to pass through, and the other of the second port and the third port is a second signal port that selectively allows a second signal with a frequency within a second passband that is lower than the first passband to pass through.

4. The stacked electronic component according to claim 1, wherein, It also features: a first port; and a second port through which the signal input to the first port passes, the plurality of first inductors including: a plurality of specific first inductors disposed in the circuit structure between the first port and the second port, and the at least one second inductor including: a specific second inductor disposed in the circuit structure between the first port and the second port, the number of which is less than the plurality of specific first inductors.

5. The stacked electronic component according to claim 4, wherein, It also includes: a circuit disposed between the first port and the second port, and comprising the plurality of specific first inductors and the specific second inductors.

6. The stacked electronic component according to claim 4, wherein, It also has a third port, wherein one of the second port and the third port is a first signal port that selectively allows a first signal with a frequency within a first passband to pass through, and the other of the second port and the third port is a second signal port that selectively allows a second signal with a frequency within a second passband that is lower than the first passband to pass through.

7. The stacked electronic component according to claim 5, wherein, The second port is the first signal port, and the third port is the second signal port.

8. The stacked electronic component according to claim 1, wherein, The at least one first conductor layer is a plurality of conductor layers including two conductor layers. The two conductor layers are two conductor layers that are spaced apart and adjacent to each other in the stacking direction of the plurality of dielectric layers, with one end connected to each other through a first through hole and the other end connected to each other through a second through hole.

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