A variable Q double second-order filter based on resistance feedback

Abstract

This invention provides a variable Q-value dual second-order filter based on resistive feedback, belonging to the field of radio frequency receiver technology. The invention employs a differential source follower to construct the second-order filter unit and introduces a cross-coupled resistor network between the differential signal nodes, providing a novel method for adjusting the filter's quality factor. Through the equivalent feedback path formed by the cross-coupled resistors in differential operation, the filter's quality factor Q can be adjusted independently. Furthermore, a parasitic zero-point cancellation method is proposed, achieving negative capacitance by cross-coupling two capacitors between the differential input and output nodes, thereby improving stopband rejection performance. This structure achieves variable Q-value and high linearity without increasing filter power consumption, making it suitable for radio frequency receiver systems and showing promising engineering application prospects.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency receiver technology, and mainly relates to a variable Q-value dual second-order filter based on resistor feedback. Background Technology

[0002] With the increasing demands for high-speed data transmission and multi-service concurrency support in portable wireless communication terminals, the requirement for RF receiver front-ends to simultaneously achieve high linearity and configurable filtering characteristics under low power consumption conditions is becoming increasingly prominent. Especially in complex interference environments, to ensure the integrity of the received signal and system stability, active filters not only need to possess good linearity, but their quality factor Q must also be flexibly configurable according to different channel bandwidths and application scenarios. Therefore, achieving independent adjustment of the filter's Q value without sacrificing linearity has become an important goal in receiver analog front-end design.

[0003] In existing RF receivers, continuous-time active filters are typically implemented using a transconductance capacitor (Gm-C) structure, where the filter's quality factor Q is primarily determined by the capacitor parameters. To meet the requirement of adjustable Q, current technologies often achieve this by changing the capacitor ratio. However, this method usually requires the introduction of a capacitor array, resulting in a significant increase in capacitor area and a larger chip footprint, thus limiting the circuit's applicability in high-integration and low-cost applications.

[0004] Furthermore, under high-frequency operating conditions, the zeros introduced by the parasitic parameters of the transconductance unit in the Gm-C filter will gradually enter the high-frequency response region, causing non-ideal fluctuations in the amplitude-frequency characteristics, thereby weakening the filter's roll-off characteristics and limiting its lag band suppression capability.

[0005] Therefore, how to achieve independent adjustment of the quality factor Q without increasing the area while maintaining the high linearity of the filter circuit, and suppress the adverse effects of high-frequency zeros on frequency response and hysteresis band performance, remains a technical problem that urgently needs to be solved in the design of active filter circuits. Summary of the Invention

[0006] In order to overcome the shortcomings of the existing technology, solve the problem of increased device area caused by capacitor array, suppress the frequency response of high frequency zero point, and improve the hysteresis band suppression capability, this invention provides a variable Q-value dual second-order filter based on resistor feedback.

[0007] The technical solution adopted by the present invention to solve its technical problem is a Q-value variable dual second-order filter based on resistance feedback, including an NMOS input differential pair, an NMOS output differential pair, a PMOS zero-point cancellation capacitor, a bias transistor, a first variable resistor R1, a second variable resistor R2, a first capacitor C1, and a second capacitor C2.

[0008] The inputs of the NMOS input differential pair include a first input differential input terminal, a second input differential input terminal, a first voltage working terminal, and a second voltage working terminal; the outputs of the NMOS input differential pair include a first node VS+ and a second node VS-.

[0009] The first differential input terminal is connected to the positive voltage input terminal VIN+; the first working voltage terminal is connected to the power supply VDD; the second differential input terminal is connected to the negative voltage input terminal VIN-; the second working voltage terminal is connected to the power supply VDD.

[0010] The inputs of the NMOS output differential pair include a first output differential input terminal, a second output differential input terminal, a third output differential input terminal, and a fourth output differential input terminal;

[0011] The output of the NMOS output differential pair includes a differential voltage positive output terminal VO+ and a differential voltage negative output terminal VO-.

[0012] The third output differential input terminal is connected to the second node VS-; the first output differential input terminal is connected to the first node VS+; and the second output differential input terminal is connected to one end of the second variable resistor R2.

[0013] The inputs of the PMOS zero-point cancellation capacitor are the first cancellation input terminal and the second cancellation input terminal; the outputs of the PMOS zero-point cancellation capacitor are the first cancellation output terminal and the second cancellation output terminal.

[0014] The first cancellation input is connected to the first node VS+; the second cancellation input is connected to the second node VS-; the first cancellation output is connected to the fourth output differential input; the second cancellation output is connected to the second output differential input.

[0015] The inputs of the bias transistor include a first bias input terminal, a second bias input terminal, a first bias voltage terminal, and a second bias voltage terminal; the outputs of the bias transistor are a first reference voltage terminal and a second reference voltage terminal.

[0016] The first reference voltage terminal is connected to ground (GND); the first bias voltage terminal is connected to the bias voltage (VB); the first bias input terminal is connected to the differential voltage positive output terminal (VO+).

[0017] The second reference voltage terminal is connected to ground (GND); the second bias voltage terminal is connected to the bias voltage (VB); the second bias input terminal is connected to the differential voltage negative output terminal (VO-).

[0018] The positive voltage input terminal VIN+ and the negative voltage input terminal VIN- are 180° out of phase;

[0019] The upper-level board of the first capacitor C1 is connected to the first node VS+; the lower-level board of the first capacitor C1 is connected to the second node VS-.

[0020] The upper stage of the second capacitor C1 is connected to the positive output terminal VO+ of the differential voltage; the lower stage of the second capacitor C2 is connected to the negative output terminal VO- of the differential voltage.

[0021] One end of the first variable resistor R1 is connected to the first node VS+; the other end of the first variable resistor R1 is connected to the fourth output differential input terminal.

[0022] One end of the second variable resistor R2 is connected to the second node VS-; the other end of the second variable resistor R2 is connected to the second output differential input terminal.

[0023] The NMOS input differential pair is responsible for receiving the positive voltage input terminal VIN+ and the negative voltage input terminal VIN-. The first stage of signal transmission is achieved by using the NMOS input differential pair with a source follower structure, providing high linearity performance for the Q-value variable dual second-order filter.

[0024] The NMOS output differential pair and the NMOS input differential pair are cascaded together to achieve the dual second-order low-pass filter function and generate the required poles;

[0025] The PMOS zero-point cancellation capacitor utilizes the parasitic capacitance characteristics of the MOS transistor to cancel high-frequency parasitic zeros, thereby enhancing the circuit's hysteresis band suppression capability and improving the overall frequency selectivity of the Q-value variable dual second-order filter.

[0026] The bias transistor provides a stable bias current to the circuit, ensuring that the circuit operates in the appropriate saturation region, and also serves as an active load for the NMOS output differential pair.

[0027] The first variable resistor R1 and the second variable resistor R2 form a cross-coupled resistor feedback network, which allows the filter quality factor Q to be independently adjustable by adjusting the resistance value; the cross-coupled resistor feedback network saves more chip area than the capacitor array.

[0028] The first capacitor C1, the second capacitor C2, the first variable resistor R1, the second variable resistor R2, the NMOS input differential pair, the NMOS output differential pair, and the PMOS zero-point cancellation capacitor together determine the low-pass cutoff frequency and transfer function characteristics of the Q-value variable dual second-order filter.

[0029] Furthermore, the NMOS input differential pair includes a first NMOS transistor M1 and a second NMOS transistor M2;

[0030] The gate of the first NMOS transistor M1 is connected to the first differential input terminal; the source of the first NMOS transistor M1 is connected to the first node VS+; the drain of the first NMOS transistor M1 is connected to the first voltage operating terminal.

[0031] The gate of the second NMOS transistor M2 is connected to the second differential input terminal; the source of the second NMOS transistor M2 is connected to the second node VS-; and the drain of the second NMOS transistor M2 is connected to the second voltage operating terminal.

[0032] Furthermore, the NMOS output differential pair includes a third NMOS transistor M3 and a fourth NMOS transistor M4;

[0033] The drain of the third NMOS transistor M3 is connected to the first output differential input terminal; the source of the third NMOS transistor M3 is connected to the differential voltage positive output terminal VO+; and the gate of the third NMOS transistor M3 is connected to the second output differential input terminal.

[0034] The drain of the fourth NMOS transistor M4 is connected to the third output differential input terminal; the source of the fourth NMOS transistor M4 is connected to the differential voltage negative output terminal VO-; and the gate of the fourth NMOS transistor M4 is connected to the fourth output differential input terminal.

[0035] Furthermore, the PMOS zero-point cancellation capacitor includes a seventh PMOS transistor M7 and an eighth PMOS transistor M8; the source and drain of the seventh PMOS transistor M7 are both connected to the first cancellation input terminal; the source and drain of the eighth PMOS transistor M8 are both connected to the second cancellation input terminal; the gate of the seventh PMOS transistor M7 is connected to the first cancellation output terminal; and the gate of the eighth PMOS transistor M8 is connected to the second cancellation output terminal.

[0036] Furthermore, the bias transistor includes a fifth NMOS transistor M5 and a sixth NMOS transistor M6; the drain of the fifth NMOS transistor M5 is connected to the first bias input terminal; the gate of the fifth NMOS transistor M5 is connected to the first bias voltage terminal; the source of the fifth NMOS transistor M5 is connected to the first reference voltage terminal; the drain of the sixth NMOS transistor M6 is connected to the second bias input terminal; the gate of the sixth NMOS transistor M6 is connected to the second bias voltage terminal; and the source of the sixth NMOS transistor M6 is connected to the second reference voltage terminal.

[0037] Furthermore, the low-pass cutoff frequency of the Q-value variable dual second-order filter... for:

[0038] ;

[0039] in, This is the transconductance value of the fourth NMOS transistor M4; This is the capacitance value of the second capacitor C2; The gate-drain parasitic capacitance values ​​for the third NMOS transistor M3 and the fourth NMOS transistor M4; The gate-source parasitic capacitance values ​​are for the third NMOS transistor M3 and the fourth NMOS transistor M4; Let R1 be the resistance value of the first variable resistor and R2 be the resistance value of the second variable resistor.

[0040] Furthermore, the quality factor of the Q-value variable bi-second-order filter... for:

[0041] ;

[0042] in The capacitance value is for the PMOS zero-point cancellation capacitor.

[0043] The beneficial effects of this invention are as follows: This invention achieves a dual second-order low-pass filter function by employing a source follower structure, exhibiting high linearity performance and a third-order input cutoff point (IIP3) of 27.3 dBm. Furthermore, this invention provides a novel method for adjusting the filter's quality factor through a cross-coupled resistor network, reducing the area by approximately 30%. It further introduces capacitors to cancel high-frequency parasitic zeros, enhancing hysteresis band suppression and improving the overall frequency selectivity of the filter. Moreover, the Q-value-variable dual second-order filter based on resistor feedback proposed in this invention can be used in the baseband receiver of 5G / 6G mobile terminals, demonstrating a wide range of applications. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a variable Q-value dual second-order filter structure based on resistance feedback provided in an embodiment of the present invention;

[0045] Figure 2 These are the simulation results of the frequency response of a variable Q-value dual second-order filter based on resistance feedback provided in the embodiments of the present invention;

[0046] Figure 3 These are the simulation results of the linearity of the Q-value variable double second-order filter based on resistance feedback provided in the embodiments of the present invention;

[0047] In the diagram, M1 is the first NMOS transistor; M2 is the second NMOS transistor; M3 is the third NMOS transistor; M4 is the fourth NMOS transistor; M5 is the fifth NMOS transistor; M6 is the sixth NMOS transistor; M7 is the seventh PMOS transistor; M8 is the eighth PMOS transistor; C1 is the first capacitor; C2 is the second capacitor; R1 is the first variable resistor; R2 is the second variable resistor; VS+ is the first node; VS- is the second node; VIN+ is the positive input terminal; VIN- is the negative input terminal; VO+ is the positive output terminal of the differential voltage; VO- is the negative output terminal of the differential voltage; GND is ground; VDD is the power supply. Detailed Implementation

[0048] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0049] A variable Q-value dual second-order filter based on resistor feedback includes an NMOS input differential pair, an NMOS output differential pair, a PMOS zero-point cancellation capacitor, a bias transistor, a first variable resistor R1, a second variable resistor R2, a first capacitor C1, and a second capacitor C2.

[0050] The NMOS input differential pair is responsible for receiving the positive voltage input terminal VIN+ and the negative voltage input terminal VIN-, and realizes the first stage of signal transmission through the source follower structure, providing high linearity performance for the Q-value variable dual second-order filter.

[0051] The NMOS output differential pair and the NMOS input differential pair are cascaded together to achieve the dual second-order low-pass filter function and generate the required poles;

[0052] The PMOS zero-point cancellation capacitor utilizes the parasitic capacitance characteristics of the MOS transistor to cancel high-frequency parasitic zeros, thereby enhancing the circuit's hysteresis band suppression capability and improving the overall frequency selectivity of the Q-value variable dual second-order filter.

[0053] The bias transistor provides a stable bias current to the circuit, ensuring that the circuit operates in the appropriate saturation region, and also serves as an active load for the NMOS output differential pair.

[0054] The first variable resistor R1 and the second variable resistor R2 form a cross-coupled resistor feedback network, which allows the filter quality factor Q to be independently adjustable by adjusting the resistance value; the cross-coupled resistor feedback network saves more chip area than the capacitor array.

[0055] The first capacitor C1, the second capacitor C2, the first variable resistor R1, the second variable resistor R2, the NMOS input differential pair, the NMOS output differential pair, and the PMOS zero-point cancellation capacitor together determine the low-pass cutoff frequency and transfer function characteristics of the Q-value variable dual second-order filter.

[0056] The inputs of the NMOS input differential pair include a first input differential input terminal, a second input differential input terminal, a first voltage working terminal, and a second voltage working terminal; the outputs of the NMOS input differential pair include a first node VS+ and a second node VS-.

[0057] The NMOS input differential pair includes a first NMOS transistor M1 and a second NMOS transistor M2;

[0058] The gate of the first NMOS transistor M1 is connected to the first differential input terminal; the source of the first NMOS transistor M1 is connected to the first node VS+; the drain of the first NMOS transistor M1 is connected to the first voltage operating terminal.

[0059] The gate of the second NMOS transistor M2 is connected to the second differential input terminal; the source of the second NMOS transistor M2 is connected to the second node VS-; the drain of the second NMOS transistor M2 is connected to the second voltage operating terminal.

[0060] The first differential input terminal is connected to the positive voltage input terminal VIN+; the first working voltage terminal is connected to the power supply VDD; the second differential input terminal is connected to the negative voltage input terminal VIN-; the second working voltage terminal is connected to the power supply VDD.

[0061] The inputs of the NMOS output differential pair include a first output differential input terminal, a second output differential input terminal, a third output differential input terminal, and a fourth output differential input terminal;

[0062] The output of the NMOS output differential pair includes a differential voltage positive output terminal VO+ and a differential voltage negative output terminal VO-.

[0063] The NMOS output differential pair includes a third NMOS transistor M3 and a fourth NMOS transistor M4;

[0064] The drain of the third NMOS transistor M3 is connected to the first output differential input terminal; the source of the third NMOS transistor M3 is connected to the differential voltage positive output terminal VO+; and the gate of the third NMOS transistor M3 is connected to the second output differential input terminal.

[0065] The drain of the fourth NMOS transistor M4 is connected to the third output differential input terminal; the source of the fourth NMOS transistor M4 is connected to the differential voltage negative output terminal VO-; the gate of the fourth NMOS transistor M4 is connected to the fourth output differential input terminal.

[0066] The third output differential input terminal is connected to the second node VS-;

[0067] The first output differential input terminal is connected to the first node VS+; the second output differential input terminal is connected to one end of the second variable resistor R2.

[0068] The inputs of the PMOS zero-point cancellation capacitor are the first cancellation input terminal and the second cancellation input terminal; the outputs of the PMOS zero-point cancellation capacitor are the first cancellation output terminal and the second cancellation output terminal.

[0069] The PMOS zero-point cancellation capacitor includes a seventh PMOS transistor M7 and an eighth PMOS transistor M8; the source and drain of the seventh PMOS transistor M7 are both connected to the first cancellation input terminal; the source and drain of the eighth PMOS transistor M8 are both connected to the second cancellation input terminal; the gate of the seventh PMOS transistor M7 is connected to the first cancellation output terminal; and the gate of the eighth PMOS transistor M8 is connected to the second cancellation output terminal.

[0070] The first cancellation input is connected to the first node VS+; the second cancellation input is connected to the second node VS-; the first cancellation output is connected to the fourth output differential input; the second cancellation output is connected to the second output differential input.

[0071] The inputs of the bias transistor include a first bias input terminal, a second bias input terminal, a first bias voltage terminal, and a second bias voltage terminal; the outputs of the bias transistor are a first reference voltage terminal and a second reference voltage terminal.

[0072] The bias transistors include a fifth NMOS transistor M5 and a sixth NMOS transistor M6; the drain of the fifth NMOS transistor M5 is connected to the first bias input terminal; the gate of the fifth NMOS transistor M5 is connected to the first bias voltage terminal; and the source of the fifth NMOS transistor M5 is connected to the first reference voltage terminal.

[0073] The first reference voltage terminal is connected to ground (GND); the first bias voltage terminal is connected to the bias voltage (VB); the first bias input terminal is connected to the differential voltage positive output terminal (VO+).

[0074] The second reference voltage terminal is connected to ground (GND); the second bias voltage terminal is connected to the bias voltage (VB); the second bias input terminal is connected to the differential voltage negative output terminal (VO-).

[0075] The positive voltage input terminal VIN+ and the negative voltage input terminal VIN- are 180° out of phase;

[0076] The upper-level board of the first capacitor C1 is connected to the first node VS+; the lower-level board of the first capacitor C1 is connected to the second node VS-.

[0077] The upper stage of the second capacitor C1 is connected to the positive output terminal VO+ of the differential voltage; the lower stage of the second capacitor C2 is connected to the negative output terminal VO- of the differential voltage.

[0078] One end of the first variable resistor R1 is connected to the first node VS+; the other end of the first variable resistor R1 is connected to the fourth output differential input terminal.

[0079] One end of the second variable resistor R2 is connected to the second node VS-; the other end of the second variable resistor R2 is connected to the second output differential input terminal.

[0080] The low-pass cutoff frequency of the Q-value variable second-order filter for:

[0081] ;

[0082] in, This is the transconductance value of the fourth NMOS transistor M4; This is the capacitance value of the second capacitor C2; The gate-drain parasitic capacitance values ​​for the third NMOS transistor M3 and the fourth NMOS transistor M4; The gate-source parasitic capacitance values ​​are for the third NMOS transistor M3 and the fourth NMOS transistor M4; Let R1 be the resistance value of the first variable resistor and R2 be the resistance value of the second variable resistor.

[0083] The quality factor of the Q-value variable second-order filter for:

[0084] ;

[0085] in The capacitance value is for the PMOS zero-point cancellation capacitor.

[0086] Please see Figure 1 , Figure 1 This is a schematic diagram of a variable Q-value dual second-order filter structure based on resistor feedback provided in an embodiment of the present invention. It is characterized by including an NMOS input differential pair, an NMOS output differential pair, a PMOS zero-point cancellation capacitor, a bias transistor, a first variable resistor R1, a second variable resistor R2, a first capacitor C1, and a second capacitor C2.

[0087] In this embodiment, the NMOS input differential pair includes a first NMOS transistor M1 and a second NMOS transistor M2, and the NMOS output differential pair includes a third NMOS transistor M3 and a fourth NMOS transistor M4. The gate of the first NMOS transistor M1 is connected to the positive input terminal VIN+, and the gate of the second NMOS transistor M2 is connected to the negative input terminal VIN-. The phase of the positive input terminal VIN+ is 180° out of phase with the phase of the negative input terminal VIN-. The drains of the first NMOS transistor M1 and the second NMOS transistor M2 are both connected to the power supply VDD. The source of the first NMOS transistor M1 and the drain of the third NMOS transistor M3 are connected to the upper plate of the first capacitor C1, and the source of the second NMOS transistor M2 and the drain of the fourth NMOS transistor M4 are connected to... The lower plate of the first capacitor C1; one end of the first variable resistor R1 is connected to the upper plate of the first capacitor C1, and the other end is connected to the gate of the fourth NMOS transistor M4; one end of the second variable resistor R2 is connected to the lower plate of the first capacitor C1, and the other end is connected to the gate of the third NMOS transistor M3; the source of the third NMOS transistor M3, the drain of the fifth NMOS transistor M5, and the upper plate of the second capacitor C2 are connected to the positive output terminal VO+ of the differential voltage; the source of the fourth NMOS transistor M4, the drain of the sixth NMOS transistor M6, and the lower plate of the second capacitor C2 are connected to the negative output terminal VO- of the differential voltage; the gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both connected to the bias voltage VB, and the sources of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both connected to ground GND.

[0088] In this embodiment, the PMOS zero-point cancellation capacitor includes a seventh PMOS transistor M7 and an eighth PMOS transistor M8. The source and drain of the seventh PMOS transistor M7 are connected to the first node VS+, and the gate of the seventh PMOS transistor M7 is connected to the gate of the fourth NMOS transistor M4. The source and drain of the eighth PMOS transistor M8 are connected to the second node VS-, and the gate of the eighth PMOS transistor M8 is connected to the gate of the third NMOS transistor M3.

[0089] The potential of the power supply VDD is 1.8V, and the potential of the ground GND is 0V.

[0090] In this embodiment, the transconductance value of the third NMOS transistor M3 is The transconductance value of the fourth NMOS transistor M4 is The gate-source parasitic capacitance values ​​of the third NMOS transistor M3 and the fourth NMOS transistor M4 are... The gate-drain parasitic capacitance values ​​of the third NMOS transistor M3 and the fourth NMOS transistor M4 are... The capacitance of the second capacitor C2 is The resistance values ​​of the first variable resistor R1 and the second variable resistor R2 are both The capacitance of the PMOS zero-point cancellation capacitor is Without considering the first variable resistor R1, the second variable resistor R2, and the PMOS zero-point cancellation capacitor, the transfer function from the first node VS+ to the differential voltage positive output terminal VO+ is... for:

[0091] ;

[0092] s It is a complex frequency variable in the Laplace domain, reflecting the exponential decay and oscillatory characteristics of the signal as it changes over time.

[0093] This generates a left half-plane pole, with a gain slope change of -20 dB / dec.

[0094] Considering the first variable resistor R1 and the second variable resistor R2, and neglecting the PMOS zero-point cancellation capacitor, the transfer function from the first node VS+ to the differential voltage positive output terminal VO+ is... for:

[0095]

[0096] The system now becomes second-order, generating two poles in the left half-plane and one zero in the left half-plane: The gain slope changes by +20 dB / dec. This produces a right-half-plane zero. The gain slope changes by +20 dB / dec. The zero point... much smaller , It plays a major role.

[0097] Considering the first variable resistor R1 and the second variable resistor R2, and the PMOS zero-point cancellation capacitor, the transfer function from the first node VS+ to the differential voltage positive output terminal VO+ is... for:

[0098]

[0099] According to the transfer function, the circuit generates a left-half-plane zero: The gain slope changes by +20 dB / dec, and a right half-plane zero is generated simultaneously. The gain slope changes by +20 dB / dec, depending on the capacitance value. Increase, zero point Pushing to the right enhances the circuit's resistance band suppression capability.

[0100] The low-pass cutoff frequency and quality factor of the Q-variable dual second-order filter are as follows:

[0101]

[0102] It is the low-pass cutoff frequency of the Q-value variable bisecond-order filter, and defines the bandwidth range of the Q-value variable bisecond-order filter. The quality factor of a variable Q-value bisecond-order filter reflects its peak response characteristics at the cutoff frequency. By changing the resistance r of the first variable resistor R1 and the second variable resistor R2, the quality factor can be adjusted without significantly increasing the chip area. Flexible configuration of values.

[0103] Figure 2 This is a simulation result of the frequency response of a variable Q-value dual second-order filter based on resistor feedback provided in an embodiment of the present invention. The Q-value is adjustable when the resistance r of the first variable resistor R1 and the second variable resistor R2 increases.

[0104] Figure 3 The figure shows the simulation results of the linearity of the Q-value variable dual second-order filter based on resistance feedback provided in the embodiment of the present invention. The third-order input cutoff point (IIP3) is 27.3dBm, which is an improvement of about 165%.

[0105] In summary, this invention provides a variable Q-value dual second-order filter based on resistive feedback. By employing a source follower structure, it achieves dual second-order low-pass filtering, exhibiting high linearity and a third-order input cutoff point (IIP3) of 27.3 dBm. Furthermore, this invention introduces a cross-coupled resistor network, providing a novel method for adjusting the filter's quality factor, reducing the area by approximately 30%. A capacitor is further introduced to cancel high-frequency parasitic zeros, enhancing hysteresis band suppression and improving the overall frequency selectivity of the filter. Moreover, the variable Q-value dual second-order filter based on resistive feedback proposed in this invention can be used in baseband receivers of 5G / 6G mobile terminals, demonstrating broad applicability.

Claims

1. A Q-value variable second-order filter based on resistive feedback, characterized in that, It includes an NMOS input differential pair, an NMOS output differential pair, a PMOS zero-point cancellation capacitor, a bias transistor, a first variable resistor, a second variable resistor, a first capacitor, and a second capacitor; The NMOS input differential pair has the following inputs: a first differential input terminal, a second differential input terminal, a first voltage working terminal, and a second voltage working terminal. The NMOS input differential pair also has the following outputs: a first node and a second node. The first differential input terminal is connected to the positive voltage input terminal; the first voltage working terminal is connected to the power supply; the second differential input terminal is connected to the negative voltage input terminal; and the second voltage working terminal is also connected to the power supply. The NMOS output differential pair has the following inputs: a first differential output terminal, a second differential output terminal, a third differential output terminal, and a fourth differential output terminal. The NMOS output differential pair also has the following outputs: a positive differential voltage output terminal and a negative differential voltage output terminal. The third differential output terminal is connected to the second node. The first differential output terminal is connected to the first node. The second differential output terminal is connected to one end of a second variable resistor. The PMOS zero-point cancellation capacitor has the following inputs: a first cancellation input terminal and a second cancellation input terminal. The PMOS zero-point cancellation capacitor also has the following outputs: a first cancellation output terminal and a second cancellation output terminal. The first cancellation input terminal is connected to the first node. The second cancellation input is connected to the second node; the first cancellation output is connected to the fourth output differential input. The second cancellation output terminal is connected to the second output differential input terminal; the input of the bias tube includes a first bias input terminal, a second bias input terminal, a first bias voltage terminal, and a second bias voltage terminal; The output of the bias transistor is a first reference voltage terminal and a second reference voltage terminal; The first reference voltage terminal is connected to ground; The first bias voltage terminal is connected to the bias voltage; The first bias input terminal is connected to the positive output terminal of the differential voltage; The second reference voltage terminal is connected to ground; The second bias voltage terminal is connected to the bias voltage. The second bias input terminal is connected to the negative output terminal of the differential voltage; the positive and negative input terminals are 180° out of phase; the upper stage of the first capacitor is connected to the first node; the lower stage of the first capacitor is connected to the second node; the upper stage of the second capacitor is connected to the positive output terminal of the differential voltage; the lower stage of the second capacitor is connected to the negative output terminal of the differential voltage; one end of the first variable resistor is connected to the first node; the other end of the first variable resistor is connected to the fourth output differential input terminal; one end of the second variable resistor is connected to the second node; the other end of the second variable resistor is connected to the second output differential input terminal. The NMOS input differential pair is responsible for receiving the positive and negative voltage input terminals. The first stage of signal transmission is achieved by using the NMOS input differential pair with a source follower structure, providing high linearity performance for the Q-value variable double second-order filter. The NMOS output differential pair is cascaded with the NMOS input differential pair to jointly realize the double second-order low-pass filter function and generate the required poles. The PMOS zero-point cancellation capacitor utilizes the parasitic capacitance characteristics of the MOS transistor to cancel high-frequency parasitic zeros, thereby enhancing the circuit's hysteresis band suppression capability and improving the overall frequency selectivity of the Q-value variable dual second-order filter. The bias transistor provides a stable bias current to the circuit, ensuring that the circuit operates in the saturation region, and also serves as an active load for the NMOS output differential pair. The first and second variable resistors form a cross-coupled resistor feedback network, and the filter quality factor Q can be independently adjusted by adjusting the resistance value. The first capacitor, the second capacitor, the first variable resistor, the second variable resistor, the NMOS input differential pair, the NMOS output differential pair, and the PMOS zero-canceling capacitor together determine the low-pass cutoff frequency and transfer function characteristics of the Q-value variable dual second-order filter.

2. The Q-value variable second-order filter based on resistive feedback according to claim 1, characterized in that: The NMOS input differential pair includes a first NMOS transistor and a second NMOS transistor; the gate of the first NMOS transistor is connected to the first input differential input terminal; the source of the first NMOS transistor is connected to the first node; the drain of the first NMOS transistor is connected to the first voltage operating terminal; and the gate of the second NMOS transistor is connected to the second input differential input terminal. The source of the second NMOS transistor is connected to the second node; the drain of the second NMOS transistor is connected to the second voltage operating terminal.

3. The Q-value variable second-order filter based on resistive feedback according to claim 1, characterized in that: The NMOS output differential pair includes a third NMOS transistor and a fourth NMOS transistor; the drain of the third NMOS transistor is connected to the first output differential input terminal; the source of the third NMOS transistor is connected to the positive output terminal of the differential voltage; the gate of the third NMOS transistor is connected to the second output differential input terminal; the drain of the fourth NMOS transistor is connected to the third output differential input terminal; the source of the fourth NMOS transistor is connected to the negative output terminal of the differential voltage; and the gate of the fourth NMOS transistor is connected to the fourth output differential input terminal.

4. The Q-value variable second-order filter based on resistance feedback according to claim 1, characterized in that: The PMOS zero-point cancellation capacitor includes a seventh PMOS transistor and an eighth PMOS transistor; the source and drain of the seventh PMOS transistor are both connected to the first cancellation input terminal; the source and drain of the eighth PMOS transistor are both connected to the second cancellation input terminal; the gate of the seventh PMOS transistor is connected to the first cancellation output terminal; and the gate of the eighth PMOS transistor is connected to the second cancellation output terminal.

5. A variable Q-value dual second-order filter based on resistance feedback according to claim 1, characterized in that: The bias transistors include a fifth NMOS transistor and a sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to a first bias input terminal; the gate of the fifth NMOS transistor is connected to a first bias voltage terminal; the source of the fifth NMOS transistor is connected to a first reference voltage terminal; the drain of the sixth NMOS transistor is connected to a second bias input terminal; the gate of the sixth NMOS transistor is connected to a second bias voltage terminal; and the source of the sixth NMOS transistor is connected to a second reference voltage terminal.

6. A variable Q-value dual second-order filter based on resistance feedback according to claim 3, characterized in that: The low-pass cutoff frequency of the Q-value variable second-order filter for: ； in, This is the transconductance value of the fourth NMOS transistor; This is the capacitance value of the second capacitor; The gate-drain parasitic capacitance values ​​for the third and fourth NMOS transistors; The values ​​of the gate-source parasitic capacitances of the third and fourth NMOS transistors; Here are the resistance values ​​of the first variable resistor and the second variable resistor.

7. A variable Q-value dual second-order filter based on resistance feedback according to claim 3, characterized in that: The quality factor of the Q-value variable second-order filter for: ； in The capacitance value of the PMOS zero-point cancellation capacitor; This is the transconductance value of the fourth NMOS transistor; This is the capacitance value of the second capacitor; The gate-drain parasitic capacitance values ​​for the third and fourth NMOS transistors; The values ​​of the gate-source parasitic capacitances of the third and fourth NMOS transistors; Here are the resistance values ​​of the first variable resistor and the second variable resistor.

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