A transimpedance amplifier integrating automatic reset and fast burst response

Abstract

The application relates to a trans-impedance amplifier integrated with automatic reset and fast burst response, which comprises a trans-impedance amplifier front-end circuit, a reset signal automatic generation circuit in communication with the trans-impedance amplifier front-end circuit and an adjustable low-pass filter circuit; the adjustable low-pass filter circuit is in communication with an output signal of the trans-impedance amplifier front-end circuit and in communication with reset signals RST and inverse reset signals RSTB generated by the reset signal automatic generation circuit; the adjustable low-pass filter circuit is used for controlling MOS variable resistors and MOS switches arranged in the adjustable low-pass filter circuit according to the reset signals RST and the inverse reset signals RSTB and forming a low-pass filter with adjustable cut-off frequency, and a signal output by the low-pass filter with adjustable cut-off frequency conforms to a mean interval of a voltage signal output by the trans-impedance amplifier front-end circuit. An external RESET signal provided by an MCU is no longer needed to complete fast burst response of chips such as a trans-impedance amplifier, a limiting amplifier and a CDR.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor integrated circuit technology and optical communication, and particularly to a transimpedance amplifier that integrates automatic reset and fast burst response. Background Technology

[0002] In optical access networks, downlink service data (service data sent from the OLT to the ONU) is transmitted in broadcast form, while uplink service data (service data sent from the ONU to the OLT) is transmitted in time-division multiplexing burst mode. To increase the effective data volume in uplink burst packets, the burst response time of the OLT-side optical receiving component typically needs to be reduced to several hundred ns. However, current commercial transimpedance amplifiers (TIAs), operating independently without external control signals, cannot meet the burst response time requirements, easily leading to mutual interference between uplink signals from different ONUs and data transmission failures. To address this issue, the relevant technology employs a solution where the internal MCU provides a RESET signal to the transimpedance amplifier inside the burst-mode optical receiving component, as well as the burst-mode limiting amplifier and CDR (Clock and Data Recoverer) on the OLT optical module PCB. Before each burst signal data packet arrives, a RESET signal is sent to allow the transimpedance amplifier to quickly complete the reset operation. However, this solution increases the complexity of the OLT optical module's operation to some extent.

[0003] To reduce the complexity and cost of system implementation, some technologies employ time-division multiplexing burst mode for uplink service transmission. This means that uplink data from different ONUs is allocated to complementary overlapping time slots for transmission within the time domain. This requires the uplink signal receiving channel link (including optical receiver components, limiting amplifiers, and CDRs) within the OLT optical module to have rapid burst response capabilities and correctly receive uplink service data transmitted by different ONUs. In related technologies, the OLT optical module product generates a corresponding RESET signal through its internal MCU based on the time slot interval allocated to each of its subordinate ONUs. This RESET signal is then output to the various components and chips (including optical receiver components, limiting amplifiers, and CDRs) on the uplink signal receiving channel link, controlling these components and chips to quickly complete reset operations and respond rapidly to burst signals during the guard time intervals between ONU uplink data packets. However, this approach requires consideration of the difficulty and feasibility of existing transimpedance amplifiers, limiting amplifiers, and CDRs in achieving their own rapid burst response, which also increases the complexity and difficulty of OLT optical module operation to some extent. Summary of the Invention

[0004] This invention provides a transimpedance amplifier that integrates automatic reset and fast burst response, eliminating the need for an external RESET signal from the MCU to achieve fast burst response for chips such as the transimpedance amplifier, limiting amplifier, and CDR. This reduces the operational complexity and implementation difficulty of the OLT optical module.

[0005] On one hand, embodiments of the present invention provide a transimpedance amplifier integrating automatic reset and fast burst response, characterized in that it comprises:

[0006] The front-end circuit of the transimpedance amplifier is used to convert a single-ended input current signal into a single-ended output voltage signal.

[0007] An automatic reset signal generation circuit, which is connected to the front-end circuit of the transimpedance amplifier, is used to generate a delayed digital strength signal based on the voltage signal strength output by the front-end circuit of the transimpedance amplifier, and automatically generate a reset signal RST and an inverted reset signal RSTB through an XOR gate and an inverter.

[0008] An adjustable low-pass filter circuit is connected to the output signal of the transimpedance amplifier front-end circuit, and is also connected to the reset signal RST and the inverted reset signal RSTB generated by the automatic reset signal generation circuit.

[0009] The adjustable low-pass filter circuit is used to control the MOS variable resistor and MOS switch set therein according to the reset signal RST and the inverted reset signal RSTB to form a low-pass filter with an adjustable cutoff frequency, and the signal output by the low-pass filter with an adjustable cutoff frequency conforms to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

[0010] In some embodiments, the automatic reset signal generation circuit further includes:

[0011] A signal strength monitoring circuit is connected to the front-end circuit of the transimpedance amplifier and is used to output a corresponding analog strength signal based on the voltage signal strength output by the front-end circuit of the transimpedance amplifier.

[0012] A signal strength decision circuit is connected to the output terminal of the signal strength monitoring circuit, and is used to make a digital decision on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result.

[0013] A delay circuit is connected to the output terminal of the signal strength decision circuit, and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit;

[0014] An XOR gate, whose input terminals are connected to the output terminals of the signal strength decision circuit and the delay circuit respectively, is used to perform XOR processing on the received digital strength signal and digital strength delay signal to obtain a reset signal RST;

[0015] An inverter, the input of which is connected to the output of the XOR gate, is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

[0016] In some embodiments, the delay circuit includes:

[0017] A clock generation circuit, which is used to automatically generate and output a clock signal according to a preset frequency;

[0018] The D flip-flop has its input connected to the output of the signal strength decision circuit, and is used to generate a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit under the control of the clock signal.

[0019] In some embodiments, the signal strength monitoring circuit includes: NMOS transistors MN (30), MN (31), MN (32), MN (33), and MN (34), a current source Ibias, transistors Q (31), Q (32), Q (33), Q (34), and Q (35), resistors R (31), R (32), R (33), R (34), R (35), R (36), and R (37), capacitor C (31), and a differential-to-single-ended amplifier;

[0020] The first port of the current source Ibias is connected to the power supply VCC, and its second port is simultaneously connected to NMOS transistors MN (30), MN (31), MN (32), MN (33), and MN (34).

[0021] The source of the NMOS transistor MN(30) is grounded, and its drain and gate are both connected to the second port of the current source Ibias.

[0022] The source of the NMOS transistor MN (31) is grounded, and its drain is connected to the emitter of the transistor Q (31), the first port of the capacitor C (31) and the first port of the resistor R (33). The gate of the NMOS transistor MN (31) is connected to the second port of the current source Ibias.

[0023] The source of the NMOS transistor MN (32) is grounded, and its drain is connected to the emitter of the transistor Q (32), the second port of the capacitor C (31) and the second port of the resistor R (33). The gate of the NMOS transistor MN (32) is connected to the second port of the current source Ibias.

[0024] The source of the NMOS transistor MN(33) is grounded, and its gate is connected to the second port of the current source Ibias.

[0025] The source of the NMOS transistor MN(34) is grounded, and its gate is connected to the second port of the current source Ibias.

[0026] The base of the transistor Q (31) is connected to the input port INN, and its collector is simultaneously connected to the first port of the resistor R (31), the base of the transistor Q (33), and the first port of the resistor R (34).

[0027] The base of the transistor Q (32) is connected to the input port INP, and its collector is simultaneously connected to the first port of the resistor R (32), the base of the transistor Q (34), and the first port of the resistor R (35).

[0028] The collectors of transistors Q(33) and Q(34) are both connected to power supply VCC. The emitters of transistors Q(33) and Q(34) are shorted and then connected to the drain of NMOS transistor MN(33) and the first input port of the differential input pair of the differential-to-single-ended amplifier.

[0029] The collector of the transistor Q (35) is connected to the power supply VCC, and its emitter is connected to the first port of the resistor R (36).

[0030] The second ports of both resistor R(31) and resistor R(32) are connected to power supply VCC;

[0031] The second port of resistor R(34) and the second port of resistor R(35) are shorted and then connected to the base of transistor Q(35).

[0032] The second port of the resistor R (36) is simultaneously connected to the second input port of the differential input pair of the differential-to-single-ended amplifier, the drain of the NMOS transistor MN (34), and the first port of the resistor R (37).

[0033] The second port of the resistor R (37) is connected to the output of the differential-to-single-ended amplifier;

[0034] The output of the transimpedance amplifier front-end circuit is connected to one of the input ports of the signal strength decision circuit through resistor R (21), and the other port of the input port of the signal strength decision circuit is connected to a fixed reference voltage.

[0035] The output terminal of the differential-to-single-ended amplifier is used to output an analog intensity signal corresponding to the voltage signal intensity output by the front-end circuit of the transimpedance amplifier.

[0036] In some embodiments, the signal strength decision circuit includes: an NMOS transistor MN (41), a PMOS transistor MP (41), a PMOS transistor MP (42), a PMOS transistor MP (43), and an inverter (41);

[0037] The gate of the NMOS transistor MN (41) is connected to the output terminal of the signal strength monitoring circuit, the gate of the PMOS transistor MP (41) and the gate of the PMOS transistor MP (42), the source of the NMOS transistor MN (41) is grounded, and the drain of the NMOS transistor MN (41) is connected to the drain of the PMOS transistor MP (41), the gate of the PMOS transistor MP (43) and the input port of the inverter (41).

[0038] The source of the PMOS transistor MP (41) is connected to the drain of the PMOS transistor MP (42) and the source of the PMOS transistor MP (43);

[0039] The source of the PMOS transistor MP(42) is connected to the power supply VCC;

[0040] The drain of the PMOS transistor MP(43) is grounded;

[0041] The digital intensity signal is output from the output terminal of the inverter (41).

[0042] In some embodiments, the adjustable low-pass filter circuit includes:

[0043] Resistor R(21) and resistor R(22), the first port of resistor R(21) is connected to the output terminal of the transimpedance amplifier front-end circuit and its second port is connected to the source of MOS variable resistor M(22) and the first port of resistor R(22). Resistor R(21) is used to reduce the influence of the parasitic parameters of resistor R(22) on the bandwidth of the output terminal of the transimpedance amplifier front-end circuit.

[0044] The MOS variable resistor M(22) has its gate connected to the output terminal of the XOR gate and its drain connected to the second port of the resistor R(22). The MOS variable resistor M(22) is used to change the high or low resistance value according to the reset signal RST output by the XOR gate.

[0045] The source of the MOS switch M(21) is grounded, its gate is connected to the output terminal of the inverter and its drain is connected to the second port of the capacitor C(21). The MOS switch M(21) is used to change its on / off state according to the inverted reset signal RSTB output by the inverter.

[0046] The capacitor C(21) has its first port connected to the second port of the resistor R(22);

[0047] The capacitor C(22) has its first port connected to the second port of the resistor R(22), and its second port is grounded;

[0048] The resistor R (22), the MOS variable resistor M (22), the MOS switch M (21), the capacitor C (21), and the capacitor C (22) are used to form the low-pass filter with adjustable cutoff frequency according to the reset signal RST and the inverted reset signal RSTB, and make the output signal of the second port of the resistor R (22) conform to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

[0049] Secondly, a differential limiting amplifier circuit integrating automatic reset and fast burst response, characterized in that it comprises:

[0050] The automatic reset signal generation circuit has its input terminal connected to the output terminal of the differential limiting amplifier, and is used to generate a delayed digital strength signal based on the output voltage signal strength of the differential limiting amplifier, and automatically output the reset signal RST and the inverted reset signal RSTB through an XOR gate and an inverter.

[0051] An adjustable high-pass filter circuit is connected to input signals INP and INN, and is also connected to the reset signal RST and the inverted reset signal RSTB output by the automatic reset signal generation circuit.

[0052] The adjustable high-pass filter circuit is used to control the variable capacitor and MOS transistor installed therein according to the reset signal RST and the inverted reset signal RSTB to form a high-pass filter with an adjustable cutoff frequency, and the signal output by the high-pass filter with an adjustable cutoff frequency conforms to the signal rate characteristics and amplitude characteristics of the input signals INP and INN.

[0053] The input terminal of the differential limiting amplifier is connected to the output terminal of the high-pass filter circuit.

[0054] Thirdly, embodiments of the present invention also provide a differential limiting amplifier circuit integrating automatic reset and fast burst response, characterized in that,

[0055] The adjustable high-pass filter circuit includes a variable capacitor C (611), a capacitor C (612), a MOSFET M (61), a variable capacitor C (621), a capacitor C (622), a MOSFET M (62), and a resistor R (61).

[0056] The first port of the variable capacitor C (611) is connected to the input signal INN and the first port of the capacitor C (612). The second port of the variable capacitor C (611) is connected to the source of the MOS transistor M (61), the first port of the resistor R (61), and the first input terminal of the differential input pair of the differential limiting amplifier. The control terminal of the variable capacitor C (611) is connected to the reset signal RST.

[0057] The second port of the capacitor C (612) is connected to the drain of the MOS transistor M (61), and the gate of the MOS transistor M (61) is connected to the inverted reset signal RSTB.

[0058] The first port of the variable capacitor C (621) is connected to both the input signal INP and the first port of the capacitor C (622). The second port of the variable capacitor C (621) is connected to the source of the MOS transistor M (62), the second port of the resistor R (61), and the second input terminal of the differential input pair of the differential limiting amplifier. The control terminal of the variable capacitor C (621) is connected to the reset signal RST.

[0059] The second port of the capacitor C (622) is connected to the drain of the MOS transistor M (62), and the gate of the MOS transistor M (62) is connected to the inverted reset signal RSTB.

[0060] In some embodiments, the automatic reset signal generation circuit further includes:

[0061] A signal strength monitoring circuit, the input of which is connected to the output signal of the differential amplitude limiting amplifier, and which is used to output a corresponding analog strength signal according to the output signal strength of the differential amplitude limiting amplifier;

[0062] A signal strength decision circuit is connected to the output terminal of the signal strength monitoring circuit, and is used to make a digital decision on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result.

[0063] A delay circuit is connected to the output terminal of the signal strength decision circuit, and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit;

[0064] An XOR gate, whose input terminals are connected to the output terminals of the signal strength decision circuit and the delay circuit respectively, is used to perform XOR processing on the received digital strength signal and digital strength delay signal to obtain a reset signal RST;

[0065] An inverter, the input of which is connected to the output of the XOR gate, is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

[0066] In some embodiments, an output buffer stage is further connected between the output terminal of the differential limiting amplifier and the input terminal of the signal strength monitoring circuit, and a pair of differential output terminals of the differential limiting amplifier are connected to a pair of differential input terminals of the output buffer stage, and a pair of differential output terminals of the output buffer stage are connected to a pair of differential input terminals of the signal strength monitoring circuit.

[0067] This invention provides a transimpedance amplifier integrating automatic reset and fast burst response. It can generate a reset signal internally to achieve fast reset and rapid response to burst data signals, and can be applied to transimpedance amplifiers, limiting amplifiers, and CDRs within optical receiver components. Using the automatic reset and fast burst response circuit provided by this invention eliminates the need for an external RESET signal from the MCU to achieve fast burst response for transimpedance amplifiers, limiting amplifiers, and CDRs, thus reducing the operational complexity and implementation difficulty of OLT optical modules. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 A schematic diagram of the circuit structure of a transimpedance amplifier integrating automatic reset and fast burst response provided for an embodiment of the present invention;

[0070] Figure 2 The signal strength monitoring circuit provided in the embodiments of the present invention;

[0071] Figure 3 The signal strength decision circuit provided in the embodiments of the present invention;

[0072] Figure 4 A schematic diagram of a transimpedance amplifier structure integrating automatic reset and fast burst response is provided for an embodiment of the present invention;

[0073] Figure 5A schematic diagram of a delay circuit structure provided in an embodiment of the present invention;

[0074] Figure 6 A schematic diagram of a differential limiting amplifier circuit integrating automatic reset and fast burst response is provided in an embodiment of the present invention;

[0075] Figure 7 The simulation results of the transimpedance amplifier with integrated automatic reset and fast burst response provided in the embodiments of the present invention are shown in the figure. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0077] like Figure 1 As shown, this embodiment of the invention provides a transimpedance amplifier structure integrating automatic reset and fast burst response, which includes:

[0078] The front-end circuit of the transimpedance amplifier is used to convert a single-ended input current signal into a single-ended output voltage signal.

[0079] An automatic reset signal generation circuit, which is connected to the front-end circuit of the transimpedance amplifier, is used to generate a delayed digital strength signal based on the voltage signal strength output by the front-end circuit of the transimpedance amplifier, and automatically generate a reset signal RST and an inverted reset signal RSTB through an XOR gate and an inverter.

[0080] An adjustable low-pass filter circuit is connected to the output signal of the transimpedance amplifier front-end circuit, and is also connected to the reset signal RST and the inverted reset signal RSTB generated by the automatic reset signal generation circuit.

[0081] The adjustable low-pass filter circuit is used to control the MOS variable resistor and MOS switch set therein according to the reset signal RST and the inverted reset signal RSTB to form a low-pass filter with an adjustable cutoff frequency, and the signal output by the low-pass filter with an adjustable cutoff frequency conforms to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

[0082] It should be noted that, as Figure 1 As shown, the input port IN of the transimpedance amplifier front-end circuit, which is also the input port of the transimpedance amplifier, is connected to the output port of the external photodetector.

[0083] like Figure 1 As shown, the transimpedance amplifier with integrated automatic reset and fast burst response provided in this embodiment also includes a single-ended to differential amplifier, a differential amplifier, and an output buffer stage. The first input port of the differential input of the single-ended to differential amplifier is connected to the output of the transimpedance amplifier's front-end circuit, and can be used to convert the single-ended voltage signal output by the transimpedance amplifier into a differential voltage signal. A pair of inputs of the differential amplifier are connected to the output of the single-ended to differential amplifier, and a pair of outputs of the differential amplifier are connected to a pair of inputs of the output buffer stage. The differential amplifier is mainly used to amplify the differential voltage signal output by the single-ended to differential amplifier, while the output buffer stage is used to achieve output impedance matching and provide a certain output voltage signal amplitude.

[0084] It is understood that the automatic reset and fast burst response circuit provided in this embodiment of the invention can generate a reset signal internally to achieve fast reset and fast response to burst data signals, and can be applied to chips such as transimpedance amplifiers, limiting amplifiers, and CDRs in optical receiving components. This eliminates the need for the MCU to provide an external RESET signal to achieve fast burst response for chips such as transimpedance amplifiers, limiting amplifiers, and CDRs, thus reducing the operational complexity and implementation difficulty of the OLT optical module.

[0085] In some embodiments, the automatic reset signal generation circuit further includes:

[0086] A signal strength monitoring circuit is connected to the front-end circuit of the transimpedance amplifier and is used to output a corresponding analog strength signal based on the voltage signal strength output by the front-end circuit of the transimpedance amplifier.

[0087] The signal strength decision circuit is connected to the output of the signal strength monitoring circuit, and is used to make digital decisions on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result.

[0088] The delay circuit is connected to the output of the signal strength decision circuit and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit.

[0089] The XOR gate has its input terminals connected to the output terminals of the signal strength decision circuit and the delay circuit, respectively, and is used to perform XOR processing on the received digital strength signal and the digital strength delay signal to obtain the reset signal RST.

[0090] An inverter whose input is connected to the output of an XOR gate, and is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

[0091] It is understandable that, such as Figure 1As shown, the signal strength monitoring circuit can be used to monitor the output voltage signal OUT of the transimpedance amplifier front-end circuit. front1 The signal strength monitoring circuit measures the intensity (e.g., amplitude, power, peak-to-peak value) and outputs a corresponding analog strength signal SI. The signal strength decision circuit can be used to make digital decisions on the analog strength signal SI output by the signal strength monitoring circuit. When the strength signal SI is greater than or equal to a certain value, the output digital strength signal DSI is high; otherwise, it is low.

[0092] like Figure 1 As shown, in some embodiments, the delay circuit includes:

[0093] A clock generation circuit, which is used to automatically generate and output a clock signal according to a preset frequency;

[0094] The D flip-flop has its input connected to the output of the signal strength decision circuit, and is used to generate a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit under the control of the clock signal.

[0095] It should be noted that the clock generation circuit is used to automatically generate and output the clock signal CLK, the frequency of which can generally be selected from about 50 to 200MHz; the D flip-flop can generate a digital strength delay signal Q_DSI with a delay relative to the digital strength signal DSI under the control of the clock signal CLK.

[0096] like Figure 4 As shown, in some embodiments, the clock generation circuit and D flip-flop can be replaced with a delay unit. The output of the delay unit is the delayed digital strength signal Q_DSI, which is connected to one input of an XOR gate. The delay unit can have multiple digital input control ports to control the delay time generated by the delay unit, such as... Figure 5 As shown, K digital input control ports TD1, TD2...TDK can be set.

[0097] In a specific embodiment, such as Figure 5 The schematic diagram of the delay circuit shown is a multi-stage cascaded controllable delay circuit based on inverter delay units with digital switch control. NMOS transistors MN521, MN5211, and PMOS transistor MP521 form the first inverter delay unit; NMOS transistors MN522, MN5221, and PMOS transistor MP522 form the second inverter delay unit; and NMOS transistors MN52K, MN52K1, and PMOS transistor MP52K form the Kth inverter delay unit. The internal components and connections of these K inverter delay units are identical.

[0098] Taking the first inverter delay unit as an example, its internal components and connections are as follows: The gate of NMOS transistor MN521 is the input terminal, which is connected to the gate of PMOS transistor MP521 and the source of NMOS switch NM5211; the drain of NMOS transistor MN521 is the output terminal, which is connected to the drain of PMOS transistor MP521 and the drain of NMOS switch NM5211; the source of NMOS transistor MN521 is grounded; the source of PMOS transistor MP521 is connected to the power supply VCC; the gate of NMOS switch NM5211 is the delay control terminal TD1. If the delay control terminal TD1 is low, the NMOS switch NM5211 is turned off, and the inverter delay unit composed of NMOS transistor MN521 and PMOS transistor MP521 is in operation. The delay of the output signal of the inverter delay unit relative to its input signal is determined by the characteristics of the inverter. If the delay control terminal TD1 is high, the NMOS switch NM5211 is turned on, and the input signal of the inverter delay unit is directly transmitted to the output of the inverter delay unit through the turned-on NMOS switch NM5211. The input of the first inverter delay unit is the input of the multi-stage cascaded controllable delay unit, the output of the Kth inverter delay unit is the output of the multi-stage cascaded controllable delay unit, and the output of the (K-1)th inverter delay unit is connected to the input of the Kth inverter delay unit.

[0099] It should be noted that the NMOS switch NM5211 must be a high-speed switching unit. It can be a high-speed NMOS switch, which needs to meet the requirements of small size and fast response speed, and can quickly close and open according to the gate control voltage; it can also be a switch composed of high-speed NMOS and PMOS connected in parallel, or other high-speed switching circuits.

[0100] like Figure 2 As shown, in some embodiments, the signal strength monitoring circuit includes: NMOS transistors MN30, MN31, MN32, MN33, and MN34; a current source Ibias; transistors Q31, Q32, Q33, Q34, and Q35; resistors R31, R32, R33, R34, R35, R36, and R37; capacitor C31; and a differential-to-single-ended amplifier.

[0101] Among them, the first port of the current source Ibias is connected to the power supply VCC, and its second port is connected to NMOS transistors MN30, MN31, MN32, MN33 and MN34.

[0102] The source of NMOS transistor MN30 is grounded, and its drain and gate are both connected to the second port of current source Ibias.

[0103] The source of NMOS transistor MN31 is grounded, and its drain is connected to the emitter of transistor Q31, the first port of capacitor C31 and the first port of resistor R33. The gate of NMOS transistor MN31 is connected to the second port of current source Ibias.

[0104] The source of NMOS transistor MN32 is grounded, and its drain is connected to the emitter of transistor Q32, the second port of capacitor C31 and the second port of resistor R33. The gate of NMOS transistor MN32 is connected to the second port of current source Ibias.

[0105] The source of the NMOS transistor MN33 is grounded, and its gate is connected to the second port of the current source Ibias.

[0106] The source of the NMOS transistor MN34 is grounded, and its gate is connected to the second port of the current source Ibias.

[0107] The base of transistor Q31 is connected to the input port INN, and its collector is connected to the first port of resistor R31, the base of transistor Q33, and the first port of resistor R34.

[0108] The base of transistor Q32 is connected to the input port INP, and its collector is connected to the first port of resistor R32, the base of transistor Q34, and the first port of resistor R35.

[0109] The collectors of transistors Q33 and Q34 are both connected to the power supply VCC. The emitters of transistors Q33 and Q34 are shorted and then connected to the drain of NMOS transistor MN33 and the first input port of the differential input pair of the differential-to-single-ended amplifier.

[0110] The collector of transistor Q35 is connected to the power supply VCC, and its emitter is connected to the first port of resistor R36.

[0111] The second terminals of resistors R31 and R32 are both connected to the power supply VCC;

[0112] The second terminals of resistor R34 and resistor R35 are shorted and then connected to the base of transistor Q35.

[0113] The second port of resistor R36 is connected to the second input port of the differential input pair of the differential-to-single-ended amplifier, the drain of NMOS transistor MN34, and the first port of resistor R37.

[0114] The second port of resistor R37 is connected to the output of the differential-to-single-ended amplifier;

[0115] The output of the transimpedance amplifier front-end circuit is connected to one of the input ports of the signal strength decision circuit through a series resistor R21, and the other port of the input port of the signal strength decision circuit is connected to a fixed reference voltage.

[0116] The output of the differential-to-single-ended amplifier is used to output an analog signal that corresponds to the amplitude and rate of the voltage signal output by the front-end circuit of the transimpedance amplifier.

[0117] It is understood that in this embodiment, a differential amplifier with equalization compensation function is composed of NMOS transistors MN30, MN31, and MN32, current source Ibias, transistors Q31 and Q32, resistors R31, R32, and R33, and capacitor C31; and a signal power / peak monitoring circuit is composed of NMOS transistors MN33 and MN34, transistors Q33, Q34, and Q35, resistors R34, R35, R36, and R37, and a differential-to-single-ended amplifier.

[0118] like Figure 3 As shown, in some embodiments, the signal strength decision circuit includes: NMOS transistor MN41, PMOS transistor MP41, PMOS transistor MP42, PMOS transistor MP43 and inverter 41;

[0119] In this circuit, the gate of NMOS transistor MN41 is connected to the output terminal of the signal strength monitoring circuit, the gate of PMOS transistor MP41, and the gate of PMOS transistor MP42. The source of NMOS transistor MN41 is grounded, and the drain of NMOS transistor MN41 is simultaneously connected to the drain of PMOS transistor MP41, the gate of PMOS transistor MP43, and the input port of inverter 41. The source of PMOS transistor MP41 is connected to the drain of PMOS transistor MP42 and the source of PMOS transistor MP43. The source of PMOS transistor MP42 is connected to the power supply VCC. The drain of PMOS transistor MP43 is grounded. The output terminal of inverter 41 outputs a digital strength signal.

[0120] like Figure 1 As shown, in some embodiments, the adjustable low-pass filter circuit includes: resistor R21, resistor R22, MOS variable resistor M22, MOS switch M21, capacitor C21, and capacitor C22; wherein,

[0121] The first port of resistor R21 is connected to the output terminal of the transimpedance amplifier front-end circuit, and its second port, the source of the MOS variable resistor M22, is connected to the first port of resistor R22. It should be noted that resistor R21 is a low-resistance resistor, which can generally be taken as several hundred ohms to thousands of ohms, and can be used to reduce the influence of the parasitic parameters of resistor R22 on the bandwidth of the output terminal of the transimpedance amplifier front-end circuit.

[0122] Resistor R22 can be set to a high-resistance resistor, which, together with capacitors C21 and C22, forms a low-pass filter to obtain the output voltage signal OUT of the transimpedance amplifier front-end circuit. front The mean interval signal OUT front_avg ;

[0123] The gate of the MOS variable resistor M22 is connected to the output of the XOR gate and its drain is connected to the second port of the resistor R22. The MOS variable resistor M22 is used to change the high or low resistance value according to the reset signal RST output by the XOR gate.

[0124] The source of MOS switch M21 is grounded, its gate is connected to the output of the inverter, and its drain is connected to the second port of capacitor C21. MOS switch M21 is used to change its on / off state according to the inverted reset signal RSTB output by the inverter.

[0125] The first port of capacitor C21 is connected to the second port of resistor R22; the first port of capacitor C22 is connected to the second port of resistor R22, and its second port is grounded; it should be noted that C21 is a large-value capacitor, C22 is a small-value capacitor, and capacitors C21 and C22 can form a low-pass filter with high-value resistor R22.

[0126] Resistor R22, MOS variable resistor M22, MOS switch M21, capacitor C21 and capacitor C22 are used to form a low-pass filter with an adjustable cutoff frequency based on the reset signal RST and the inverted reset signal RSTB, and make the output signal of the second port of resistor R22 conform to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

[0127] like Figure 1 As shown, it can be understood that the MOS variable resistor M22 and the MOS switch M21 are controlled by the reset signal RST and the inverted reset signal RSTB. When RST is high, RSTB is low, M22 is in a low-resistance state, and the resistance of M22 in parallel with the high-resistance resistor R22 is low. At the same time, M21 is in the off state, and the path from the large capacitor C21 to ground is broken. At this time, M22, the high-resistance resistor R22, and the small-resistance capacitor C22 form a low-pass filter with a high cutoff frequency of 3dB (e.g., above 100MHz), and its output average signal OUT...front_avg The signal converges rapidly to the output voltage signal OUT of the transimpedance amplifier front-end circuit. front The average value is near the mean. When RST is low, RSTB is high, M22 is in a high-impedance off state, and the resistance of M22 in parallel with the high-resistance resistor R22 is in a high-resistance state. At the same time, M21 is in the on state, and the path from the large capacitor C21 to ground is open. At this time, M22, the high-resistance resistor R22, the large capacitor C21, and the small capacitor C22 form a low-pass filter with a low 3dB cutoff frequency (such as below 100KHz), and its output average signal OUT front_avg The convergence and stabilization of the output voltage signal OUT at the front end of the transimpedance amplifier circuit front It is near the mean.

[0128] In a specific embodiment, such as Figure 1 As shown, preferably, the input terminal of the signal strength monitoring circuit is connected to the second port of resistor R21, that is, the input terminal of the signal strength monitoring circuit is OUT. front1 Signal;

[0129] The output port SI of the signal strength monitoring circuit is connected to the input terminal of the signal strength decision circuit; the output port DSI of the signal strength decision circuit is connected to the input port D of the D flip-flop.

[0130] The output port CLK of the clock generation circuit is connected to the clock signal input port of the D flip-flop; the output port Q of the D flip-flop outputs the signal Q_DSI.

[0131] The output port DSI of the signal strength decision circuit is also connected to the first input port of the XOR gate, and the output signal Q_DSI of the D flip-flop is connected to the second input port of the XOR gate.

[0132] The output port signal of the XOR gate is RST, and it is simultaneously connected to the gate of the MOS variable resistor M22 and the input port of the inverter 21.

[0133] The output port signal of inverter 21 is RSTB, and it is connected to the gate of MOS variable resistor M21.

[0134] The second port of resistor R22 is connected to the drain of MOS variable resistor M22, the first port of capacitor C21, the first port of capacitor C22, and the second input port of the differential input of the single-ended to differential amplifier. The output signal of the second port of resistor R22 is OUT. front The mean signal OUT front_avg ;

[0135] The second port of capacitor C21 is connected to the drain of MOS variable resistor M21;

[0136] The source of the MOS variable resistor M21 is grounded; the second port of capacitor C22 is grounded.

[0137] A pair of differential output ports of a single-ended to differential amplifier are connected to a pair of differential input ports of a differential amplifier;

[0138] A pair of differential output ports of the differential amplifier are connected to a pair of differential input ports of the output buffer stage; the pair of differential output ports of the output buffer stage are OUTP and OUTN (i.e., the differential output ports of the transimpedance amplifier).

[0139] It should be noted that, considering the relatively large parasitic capacitance parameters of R22, M22, C1, C2, etc., directly connecting them to OUT is not recommended. front This will cause OUT front The node's bandwidth is severely degraded. Resistor R21 is used (OUT after resistor R21). front1 The purpose of the output to the signal strength monitoring circuit is to isolate OUT. front The node and the large parasitic capacitance behind it.

[0140] It is understandable that, such as Figure 1 and Figure 4 As shown, this embodiment provides an automatic reset and fast burst response circuit suitable for transimpedance amplifiers. An automatic reset signal generation circuit, consisting of a signal strength monitoring circuit, a signal strength decision circuit, a clock generation circuit, a D flip-flop, an XOR gate, and an inverter, or a similar circuit, rapidly generates a reset signal RST pulse signal and an inverted reset signal RSTB pulse signal with a certain time width (e.g., tens to hundreds of ns) after a burst signal arrives. RST and RSTB control a low-pass filter circuit with a 3dB cutoff frequency that is adjustable (high / low) and consists of a low-resistance resistor R21, a high-resistance resistor R22, a large-capacitance capacitor C21, a small-capacitance capacitor C22, a MOS variable resistor M22, and a MOS switch M21.

[0141] During the active pulse periods of the reset signal RST and the inverted reset signal RSTB, RST is high and RSTB is low. M22 is in a low-resistance state, and the resistance of M22 connected in parallel with the high-resistance resistor R22 is low. Simultaneously, M21 is off, the path from the large capacitor C21 to ground is broken, and the large capacitor C21 has no effect. At this time, M22, the high-resistance resistor R22, and the small-resistance capacitor C22 form a low-pass filter with a high 3dB cutoff frequency (e.g., above 100MHz). In this state, the average signal OUT output by the low-pass filter circuit network... front_avg It converges quickly to its input voltage signal OUT frontIt is near the mean.

[0142] During the invalid pulse periods of the reset signal RST and the inverted reset signal RSTB, RST is low, RSTB is high, M22 is in a high-impedance off state, and the resistance of M22 connected in parallel with the high-resistance resistor R22 is high. Simultaneously, M21 is in the on state, and the path from the large capacitor C21 to ground is open. At this time, M22, the high-resistance resistor R22, the large capacitor C21, and the small capacitor C22 form a low-pass filter with a low 3dB cutoff frequency (e.g., below 100kHz). In this state, the average signal OUT output by the low-pass filter circuit network... front_avg It converges and stabilizes at its input voltage signal OUT front It is near the mean.

[0143] This invention also provides a differential limiting amplifier circuit integrating automatic reset and fast burst response, comprising:

[0144] The automatic reset signal generation circuit has its input terminal connected to the output terminal of the differential limiting amplifier, and is used to generate a delayed digital strength signal based on the output voltage signal strength of the differential limiting amplifier, and automatically output the reset signal RST and the inverted reset signal RSTB through an XOR gate and an inverter.

[0145] An adjustable high-pass filter circuit is connected to input signals INP and INN, and is also connected to the reset signal RST and the inverted reset signal RSTB output by the automatic reset signal generation circuit.

[0146] The adjustable high-pass filter circuit is used to control the variable capacitor and MOS transistor installed therein according to the reset signal RST and the inverted reset signal RSTB to form a high-pass filter with an adjustable cutoff frequency, and the signal output by the adjustable high-pass filter conforms to the signal rate characteristics and amplitude characteristics of the input signals INP and INN.

[0147] The input terminal of the differential limiting amplifier is connected to the output terminal of the high-pass filter circuit.

[0148] Understandably, the function of a high-pass filter is to filter out the DC component in a signal. The rate characteristic refers to the signal rate, such as 10Gbps or 25Gbps, and the amplitude characteristic refers to the signal swing. After passing through a high-pass filter, both the signal rate and the signal swing must remain consistent.

[0149] like Figure 6 As shown, in some embodiments, the adjustable high-pass filter circuit includes a variable capacitor C611, a capacitor C612, a MOSFET M61, a variable capacitor C621, a capacitor C622, a MOSFET M62, and a resistor R61; wherein,

[0150] The first port of variable capacitor C611 is connected to the input signal INN and the first port of capacitor C612. The second port of variable capacitor C611 is connected to the source of MOSFET M61, the first port of resistor R61, and the first input terminal of the differential input pair of differential limiting amplifier. The control terminal of variable capacitor C611 is connected to the reset signal RST.

[0151] The second port of capacitor C612 is connected to the drain of MOSFET M61, and the gate of MOSFET M61 is connected to the inverted reset signal RSTB.

[0152] The first port of variable capacitor C621 is connected to both the input signal INP and the first port of capacitor C622. The second port of variable capacitor C621 is connected to the source of MOSFET M62, the second port of resistor R61, and the second input of the differential input pair of differential limiting amplifier. The control terminal of variable capacitor C621 is connected to the reset signal RST.

[0153] The second port of capacitor C622 is connected to the drain of MOSFET M62, and the gate of MOSFET M62 is connected to the inverted reset signal RSTB.

[0154] like Figure 6 As shown, in some embodiments, the automatic reset signal generation circuit further includes:

[0155] The signal strength monitoring circuit has its input terminal connected to the output signal of the differential limiting amplifier, and it is used to output a corresponding analog strength signal based on the output signal strength of the differential limiting amplifier.

[0156] The signal strength decision circuit is connected to the output of the signal strength monitoring circuit, and is used to make digital decisions on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result.

[0157] The delay circuit is connected to the output of the signal strength decision circuit and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit.

[0158] An XOR gate, whose input terminals are connected to the output terminals of the signal strength decision circuit and the delay circuit respectively, is used to perform XOR processing on the received digital strength signal and digital strength delay signal to obtain a reset signal RST.

[0159] An inverter whose input is connected to the output of an XOR gate, and is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

[0160] like Figure 6As shown, in some embodiments, an output buffer stage is also connected between the output terminal of the differential limiting amplifier and the input terminal of the signal strength monitoring circuit. A pair of differential output terminals of the differential limiting amplifier are connected to a pair of differential input terminals of the output buffer stage, and a pair of differential output terminals of the output buffer stage are connected to a pair of differential input terminals of the signal strength monitoring circuit. The output buffer stage is used to achieve output impedance matching and provide a certain output voltage signal amplitude.

[0161] like Figure 6 As shown, the output port DSI of the signal strength decision circuit is connected to the input port D of the D flip-flop; the output port CLK of the clock generation circuit is connected to the clock signal input port of the D flip-flop; the output port Q of the D flip-flop outputs the signal Q_DSI; the output port DSI of the signal strength decision circuit is also connected to the first input port of the XOR gate, and the output signal Q_DSI of the D flip-flop is connected to the second input port of the XOR gate; the output port signal of the XOR gate is RST, and it is simultaneously connected to the control terminal of the variable capacitor C611, the control terminal of the variable capacitor C621, and the input port of the inverter 61; the output port signal of the inverter 61 is RSTB, and it is simultaneously connected to the gate of the MOSFET M61 and the gate of the MOSFET M62.

[0162] It is understandable that, such as Figure 6 As shown, this embodiment provides a circuit structure for a differential limiting amplifier circuit that integrates automatic reset and fast burst response. Through an automatic reset signal generation circuit, a reset signal RST pulse signal and an inverted reset signal RSTB pulse signal with a certain time width (e.g., tens to hundreds of ns) are quickly generated after a burst signal arrives. The RST and RSTB signals control a high-pass filter circuit network with adjustable low-frequency cutoff frequency, consisting of variable capacitor C611, capacitor C612, MOSFET M61, variable capacitor C621, capacitor C622, MOSFET M62, and resistor R61.

[0163] During the effective pulse signal periods of the reset signal RST and the inverted reset signal RSTB, RST is high, RSTB is low, MOSFETs M61 and M62 are in a low-impedance state, and variable capacitors C611 and C621 are in a low-capacitance state. Capacitor C612 is connected in parallel with variable capacitor C611 in a low-capacitance state through the low-impedance MOSFET M61, and capacitor C622 is connected in parallel with variable capacitor C621 in a low-capacitance state through the low-impedance MOSFET M62. At this time, the circuit network composed of capacitor C612, MOSFET M61, and variable capacitor C611, as well as the circuit network composed of capacitor C622, MOSFET M62, and variable capacitor C621, can be equivalent to a low-capacitance capacitor, and together with resistor R61, they form a high-pass filter with a high low-frequency cutoff frequency (e.g., above 100MHz). In this state, the output signal of the high-pass filter circuit network will quickly converge to a state consistent with the input signal INP / INN.

[0164] During the invalid pulse periods of the reset signal RST and the inverted reset signal RSTB, RST is low, RSTB is high, MOSFETs M61 and M62 are in a high-impedance off state, and variable capacitors C611 and C621 are in a high-capacitance state. The parallel connection between capacitor C612 and variable capacitor C611 through MOSFET M61 is broken, and the parallel connection between capacitor C622 and variable capacitor C621 through MOSFET M62 is also broken. At this time, the circuit network composed of capacitor C612, MOSFET M61, and variable capacitor C611, as well as the circuit network composed of capacitor C622, MOSFET M62, and variable capacitor C621, can all be equivalent to a high-capacitance capacitor, and together with resistor R61, they form a high-pass filter with a low low-frequency cutoff frequency (such as below several hundred kHz). In this state, the output signal of the high-pass filter circuit network will converge and stabilize in a state consistent with the input signal INP / INN.

[0165] like Figure 7(a) shows the simulation results, where / R1 / PLUS is the input current signal of the transimpedance amplifier, which is a burst signal. There is no signal for a period of time at the beginning, followed by a period of random data signal, then another period of no signal, followed by another period of random data signal, and then another period of no signal; / OUTfront is the output port signal of the transimpedance amplifier front-end circuit; / OUTfrontavg is the average signal after low-pass filtering of the output port signal of the transimpedance amplifier front-end circuit; / CLK is the output port signal of the clock generation circuit; / SI is the output port signal of the signal strength monitoring circuit; / DSI is the output port signal of the signal strength decision circuit; / Q_DSI is the output signal after the / DSI signal is input to the D flip-flop and processed by the D flip-flop; / RST is the automatically generated reset signal; / RSTB is the inverted signal of the reset signal / RST; / OUTP and / OUTN are a pair of differential output port signals of the transimpedance amplifier.

[0166] Depend on Figure 7 (a) It can be seen that a reset pulse signal / RST will automatically appear approximately 100 ns after the random data signal appears and approximately tens of ns after the random data signal ends; during the period after the random data signal arrives and the reset pulse signal / RST is inactive (low), / OUTfrontavg changes very slowly toward the mean of the random data signal.

[0167] like Figure 7 As shown in (b), during the period after the arrival of the random data signal and while the reset pulse signal / RST is active (high), / OUTfrontavg can quickly reach the mean state of the random data signal from the initial voltage state. Figure 7 The response time of / OUTfrontavg is approximately 30ns. Simultaneously, the differential output ports / OUTP and / OUTN of the transimpedance amplifier rapidly transition from the signal setup state to the normal output signal state. Figure 7 In this context, the response time for / OUTP and / OUTN is approximately 30ns. During the period after the random data signal ends and the reset pulse signal / RST is active (high), / OUTfrontavg can quickly return from the mean state of the random data signal to the initial voltage state. At the same time, the differential output port signals / OUTP and / OUTN of the transimpedance amplifier also quickly return to their initial signal states.

[0168] This invention enables rapid reset and fast response to burst data signals by generating a reset signal internally within the chip. The OLT optical module no longer requires the MCU to provide external RESET signals to chips such as transimpedance amplifiers, limiting amplifiers, and CDRs for rapid burst response, effectively reducing the complexity and difficulty of achieving rapid signal response in the uplink burst link within the OLT optical module. Furthermore, it can also be applied to transimpedance amplifiers, limiting amplifiers, and CDRs within optical receiving components.

[0169] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0170] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0171] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A transimpedance amplifier integrating automatic reset and fast burst response, characterized in that, It includes: The front-end circuit of the transimpedance amplifier is used to convert a single-ended input current signal into a single-ended output voltage signal. The automatic reset signal generation circuit is connected to the front-end circuit of the transimpedance amplifier. It is used to generate a delayed digital strength signal based on the voltage signal strength output by the front-end circuit of the transimpedance amplifier, and automatically generate a reset signal RST through an XOR gate and an inverted reset signal RSTB through an inverter. The automatic reset signal generation circuit also includes a signal strength monitoring circuit, which includes: NMOS transistors MN30, MN31, MN32, MN33, and MN34; a current source Ibias; transistors Q31, Q32, Q33, Q34, and Q35; resistors R31, R32, R33, R34, R35, R36, and R37; capacitor C31; and a differential-to-single-ended amplifier. The first port of the current source Ibias is connected to the power supply VCC, and its second port is simultaneously connected to NMOS transistors MN30, MN31, MN32, MN33, and MN34. The source of the NMOS transistor MN30 is grounded, and its drain and gate are both connected to the second port of the current source Ibias. The source of the NMOS transistor MN31 is grounded, and its drain is connected to the emitter of the transistor Q31, the first port of the capacitor C31 and the first port of the resistor R33. The gate of the NMOS transistor MN31 is connected to the second port of the current source Ibias. The source of the NMOS transistor MN32 is grounded, and its drain is connected to the emitter of the transistor Q32, the second port of the capacitor C31 and the second port of the resistor R33. The gate of the NMOS transistor MN32 is connected to the second port of the current source Ibias. The source of the NMOS transistor MN33 is grounded, and its gate is connected to the second port of the current source Ibias. The source of the NMOS transistor MN34 is grounded, and its gate is connected to the second port of the current source Ibias. The base of transistor Q31 is connected to the input port INN, and its collector is simultaneously connected to the first port of resistor R31, the base of transistor Q33, and the first port of resistor R34. The base of transistor Q32 is connected to the input port INP, and its collector is simultaneously connected to the first port of resistor R32, the base of transistor Q34, and the first port of resistor R35. The collectors of transistors Q33 and Q34 are both connected to power supply VCC. The emitters of transistors Q33 and Q34 are shorted and then connected to the drain of NMOS transistor MN33 and the first input port of the differential input pair of the differential-to-single-ended amplifier. The collector of the transistor Q35 is connected to the power supply VCC, and its emitter is connected to the first port of the resistor R36. The second ports of both resistors R31 and R32 are connected to the power supply VCC. The second port of resistor R34 and the second port of resistor R35 are shorted and then connected to the base of transistor Q35. The second port of resistor R36 is simultaneously connected to the second input port of the differential input pair of the differential-to-single-ended amplifier, the drain of the NMOS transistor MN34, and the first port of resistor R37. The second port of resistor R37 is connected to the output of the differential-to-single-ended amplifier; The output of the transimpedance amplifier front-end circuit is connected to one port of the signal strength decision circuit input through resistor R21, and the other port of the signal strength decision circuit input is connected to a fixed reference voltage. The output terminal of the differential-to-single-ended amplifier is used to output an analog intensity signal corresponding to the voltage signal intensity output by the front-end circuit of the transimpedance amplifier. An adjustable low-pass filter circuit is connected to the output signal of the transimpedance amplifier front-end circuit, and is also connected to the reset signal RST and the inverted reset signal RSTB generated by the automatic reset signal generation circuit. The adjustable low-pass filter circuit is used to control the MOS variable resistor and MOS switch set therein according to the reset signal RST and the inverted reset signal RSTB to form a low-pass filter with an adjustable cutoff frequency, and the signal output by the low-pass filter with an adjustable cutoff frequency conforms to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

2. The transimpedance amplifier integrating automatic reset and fast burst response as described in claim 1, characterized in that, The automatic reset signal generation circuit also includes: A signal strength monitoring circuit is connected to the front-end circuit of the transimpedance amplifier, and is used to output a corresponding analog strength signal according to the voltage signal strength output by the front-end circuit of the transimpedance amplifier. A signal strength decision circuit is connected to the output terminal of the signal strength monitoring circuit, and is used to make a digital decision on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result. A delay circuit is connected to the output terminal of the signal strength decision circuit, and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit; An XOR gate, whose input terminals are connected to the output terminals of the signal strength decision circuit and the delay circuit respectively, is used to perform XOR processing on the received digital strength signal and digital strength delay signal to obtain a reset signal RST; An inverter, the input of which is connected to the output of the XOR gate, is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

3. The transimpedance amplifier integrating automatic reset and fast burst response as described in claim 2, characterized in that, The delay circuit includes: A clock generation circuit, which is used to automatically generate and output a clock signal according to a preset frequency; The D flip-flop has its input connected to the output of the signal strength decision circuit, and is used to generate a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit under the control of the clock signal.

4. A transimpedance amplifier integrating automatic reset and fast burst response as described in claim 2, characterized in that, The signal strength decision circuit includes: NMOS transistor MN41, PMOS transistor MP41, PMOS transistor MP42, PMOS transistor MP43 and inverter 41; The gate of the NMOS transistor MN41 is connected to the output terminal of the signal strength monitoring circuit, the gate of the PMOS transistor MP41, and the gate of the PMOS transistor MP42. The source of the NMOS transistor MN41 is grounded, and the drain of the NMOS transistor MN41 is connected to the drain of the PMOS transistor MP41, the gate of the PMOS transistor MP43, and the input port of the inverter 41. The source of PMOS transistor MP41 is connected to the drain of PMOS transistor MP42 and the source of PMOS transistor MP43. The source of the PMOS transistor MP42 is connected to the power supply VCC; The drain of the PMOS transistor MP43 is grounded; The digital intensity signal is output from the output terminal of the inverter 41.

5. A transimpedance amplifier integrating automatic reset and fast burst response as described in claim 2, characterized in that, The adjustable low-pass filter circuit includes: Resistors R21 and R22 are used to reduce the influence of the parasitic parameters of resistor R22 on the bandwidth of the output of the transimpedance amplifier front-end circuit. The first port of resistor R21 is connected to the output of the transimpedance amplifier front-end circuit, and its second port is connected to the source of MOS variable resistor M22 and the first port of resistor R22. The MOS variable resistor M22 has its gate connected to the output terminal of the XOR gate and its drain connected to the second port of the resistor R22. The MOS variable resistor M22 is used to change the high or low resistance value according to the reset signal RST output by the XOR gate. The MOS switch M21 has its source grounded, its gate connected to the output terminal of the inverter, and its drain connected to the second port of capacitor C21. The MOS switch M21 is used to change its on / off state according to the inverted reset signal RSTB output by the inverter. Capacitor C21, the first port of which is connected to the second port of resistor R22; Capacitor C22 has its first port connected to the second port of resistor R22, and its second port is grounded; The resistor R22, the MOS variable resistor M22, the MOS switch M21, the capacitor C21, and the capacitor C22 are used to form the low-pass filter with adjustable cutoff frequency according to the reset signal RST and the inverted reset signal RSTB, and make the output signal of the second port of the resistor R22 conform to the mean range of the output voltage signal of the transimpedance amplifier front-end circuit.

6. A differential limiting amplifier circuit integrating automatic reset and fast burst response, characterized in that, It includes: The automatic reset signal generation circuit has its input terminal connected to the output terminal of the differential limiting amplifier, and is used to generate a delayed digital strength signal based on the output voltage signal strength of the differential limiting amplifier, and automatically output a reset signal RST through an XOR gate and an inverted reset signal RSTB through an inverter. The automatic reset signal generation circuit also includes a signal strength monitoring circuit, which includes: NMOS transistors MN30, MN31, MN32, MN33, and MN34; a current source Ibias; transistors Q31, Q32, Q33, Q34, and Q35; resistors R31, R32, R33, R34, R35, R36, and R37; capacitor C31; and a differential-to-single-ended amplifier. The first port of the current source Ibias is connected to the power supply VCC, and its second port is simultaneously connected to NMOS transistors MN30, MN31, MN32, MN33, and MN34. The source of the NMOS transistor MN30 is grounded, and its drain and gate are both connected to the second port of the current source Ibias. The source of the NMOS transistor MN31 is grounded, and its drain is connected to the emitter of the transistor Q31, the first port of the capacitor C31 and the first port of the resistor R33. The gate of the NMOS transistor MN31 is connected to the second port of the current source Ibias. The source of the NMOS transistor MN32 is grounded, and its drain is connected to the emitter of the transistor Q32, the second port of the capacitor C31 and the second port of the resistor R33. The gate of the NMOS transistor MN32 is connected to the second port of the current source Ibias. The source of the NMOS transistor MN33 is grounded, and its gate is connected to the second port of the current source Ibias. The source of the NMOS transistor MN34 is grounded, and its gate is connected to the second port of the current source Ibias. The base of transistor Q31 is connected to the input port INN, and its collector is simultaneously connected to the first port of resistor R31, the base of transistor Q33, and the first port of resistor R34. The base of transistor Q32 is connected to the input port INP, and its collector is simultaneously connected to the first port of resistor R32, the base of transistor Q34, and the first port of resistor R35. The collectors of transistors Q33 and Q34 are both connected to power supply VCC. The emitters of transistors Q33 and Q34 are shorted and then connected to the drain of NMOS transistor MN33 and the first input port of the differential input pair of the differential-to-single-ended amplifier. The collector of the transistor Q35 is connected to the power supply VCC, and its emitter is connected to the first port of the resistor R36. The second ports of both resistors R31 and R32 are connected to the power supply VCC. The second port of resistor R34 and the second port of resistor R35 are shorted and then connected to the base of transistor Q35. The second port of resistor R36 is simultaneously connected to the second input port of the differential input pair of the differential-to-single-ended amplifier, the drain of the NMOS transistor MN34, and the first port of resistor R37. The second port of resistor R37 is connected to the output of the differential-to-single-ended amplifier; An adjustable high-pass filter circuit is connected to input signals INP and INN, and is also connected to the reset signal RST and the inverted reset signal RSTB output by the automatic reset signal generation circuit. The adjustable high-pass filter circuit is used to control the variable capacitor and MOS transistor installed therein according to the reset signal RST and the inverted reset signal RSTB to form a high-pass filter with an adjustable cutoff frequency, and the signal output by the high-pass filter with an adjustable cutoff frequency conforms to the signal rate characteristics and amplitude characteristics of the input signals INP and INN. The input terminal of the differential limiting amplifier is connected to the output terminal of the high-pass filter circuit.

7. The differential limiting amplifier circuit integrating automatic reset and fast burst response as described in claim 6, characterized in that, The adjustable high-pass filter circuit includes a variable capacitor C611, a capacitor C612, a MOSFET M61, a variable capacitor C621, a capacitor C622, a MOSFET M62, and a resistor R61. The first port of the variable capacitor C611 is connected to the input signal INN and the first port of the capacitor C612. The second port of the variable capacitor C611 is connected to the source of the MOS transistor M61, the first port of the resistor R61, and the first input terminal of the differential input pair of the differential limiting amplifier. The control terminal of the variable capacitor C611 is connected to the reset signal RST. The second port of the capacitor C612 is connected to the drain of the MOS transistor M61, and the gate of the MOS transistor M61 is connected to the inverted reset signal RSTB. The first port of the variable capacitor C621 is connected to both the input signal INP and the first port of the capacitor C622. The second port of the variable capacitor C621 is connected to the source of the MOS transistor M62, the second port of the resistor R61, and the second input terminal of the differential input pair of the differential limiting amplifier. The control terminal of the variable capacitor C621 is connected to the reset signal RST. The second port of the capacitor C622 is connected to the drain of the MOS transistor M62, and the gate of the MOS transistor M62 is connected to the inverted reset signal RSTB.

8. A differential limiting amplifier circuit integrating automatic reset and fast burst response as described in claim 6, characterized in that, The automatic reset signal generation circuit also includes: A signal strength monitoring circuit, the input of which is connected to the output signal of the differential amplitude limiting amplifier, and which is used to output a corresponding analog strength signal according to the output signal strength of the differential amplitude limiting amplifier; A signal strength decision circuit is connected to the output terminal of the signal strength monitoring circuit, and is used to make a digital decision on the analog strength signal output by the signal strength monitoring circuit and output a digital strength signal according to the decision result. A delay circuit is connected to the output terminal of the signal strength decision circuit, and is used to output a digital strength delay signal corresponding to the digital strength signal output by the signal strength decision circuit; An XOR gate, whose input terminals are connected to the output terminals of the signal strength decision circuit and the delay circuit respectively, is used to perform XOR processing on the received digital strength signal and digital strength delay signal to obtain a reset signal RST; An inverter, the input of which is connected to the output of the XOR gate, is used to invert the reset signal RST output by the XOR gate to obtain an inverted reset signal RSTB.

9. A differential limiting amplifier circuit integrating automatic reset and fast burst response as described in claim 8, characterized in that, An output buffer stage is connected between the output terminal of the differential limiting amplifier and the input terminal of the signal strength monitoring circuit. A pair of differential output terminals of the differential limiting amplifier are connected to a pair of differential input terminals of the output buffer stage, and a pair of differential output terminals of the output buffer stage are connected to a pair of differential input terminals of the signal strength monitoring circuit.

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