Input / output circuit with slew rate control

Abstract

The invention relates to an input / output circuit with slew rate control. A circuit includes a first transistor (M1A) having a control terminal and includes a pre-driver (116a) having an input and an output. The output is coupled to the control terminal of the first transistor (M1A). A second transistor (M402) of a first polarity has a control terminal coupled to the output of the pre-driver (116a). A third transistor (M403) of a second polarity has a first terminal and a second terminal. The first terminal of the third transistor (M403) is coupled to the control terminal of the second transistor (M402). A fourth transistor (M404) having the second polarity has a first terminal and a second terminal. The first terminal of the fourth transistor (M404) is coupled to the second terminal of the third transistor (M403). The second terminal of the fourth transistor (M403) is coupled to a supply terminal.

Description

Technical Field

[0001] This application generally relates to circuits, and more particularly to input / output circuits with rotation rate control. Background Technology

[0002] Many circuits (both analog and digital) have one or more inputs and one or more outputs. Input / output (I / O) circuits are circuits typically used to output signals through the I / O terminals (also called pins) of an integrated circuit (IC). An IC may have multiple I / O terminals, and therefore may have individual I / O circuitry associated with one or more of these I / O terminals.

[0003] For example, some automotive applications are sensitive to electromagnetic interference (EMI). Therefore, the I / O circuitry in ICs used in such applications may include slew rate control to limit the slope of the rising and falling edges on the I / O terminals, thereby limiting the amplitude of EMI generated by one IC from adversely affecting the operation of other circuits within the system. Summary of the Invention

[0004] In one example, a circuit includes a first transistor having a control terminal and a pre-driver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the pre-driver. A third transistor of a second polarity has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor of a second polarity has a first terminal and a second terminal. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal. Attached Figure Description

[0005] Figure 1 This is a block diagram of a system that includes two integrated circuits (ICs) coupled together, as shown in the example.

[0006] Figure 2 It is included in the example Figure 1 A schematic diagram of the I / O circuit in an IC.

[0007] Figure 3 It is a drawing example Figure 2 A graph showing the gate voltage of the transistor in the I / O circuit.

[0008] Figure 4 This is a schematic diagram of the pre-driver and turn-on circuit within the I / O circuit of the example.

[0009] Figure 5 This is a schematic diagram of the pre-driver and turn-on circuit within the I / O circuitry in another example.

[0010] Figure 6 This is a schematic diagram of another pre-driver and turn-on circuit within the I / O circuit of the example. Detailed Implementation

[0011] Use the same reference numerals or other reference designators in the drawings to designate the same or similar features (functionally and / or structurally).

[0012] The examples described in this article pertain to input / output (I / O) circuits for integrated circuits (ICs), including slew rate control. Although the descriptions herein pertain to I / O circuits, the principles described herein are applicable to other types of circuits.

[0013] Some I / O circuits implement spin rate control by including resistors in the gate charging path of an n-channel field-effect transistor (NFET) or in the gate discharging path of a p-channel field-effect transistor (PFET). NFETs and PFETs are transistors of opposite polarities. The resistor and the gate capacitance of the corresponding FET limit the rate of change of the gate-to-source voltage (Vgs) of the FET, and thus limit the rate of change of the I / O terminals coupled to the FET and the amplitude of EMI generated by the IC. Unfortunately, the same resistor used for implementing spin rate control also delays the turn-on of the channel within the corresponding FET. This delay can make it difficult for the IC to meet the timing requirements of some interface protocols, such as Ethernet Media Access Control (MAC) interfaces, including, for example, Medium Independent Interface (MII), Minimal Medium Independent Interface (RMII), and Minimal Gigabit Medium Independent Interface (RGMII).

[0014] The examples described herein relate to an I / O circuit that includes spin-rate control and one or more turn-on circuits designed to rapidly turn on a corresponding FET and then automatically turn it off, allowing the spin-rate control characteristics of the I / O circuit to limit the spin-rate of the rising or falling signal edge on the I / O terminal. In one example, the I / O circuit includes two turn-on circuits, one associated with a pre-driver for a PMOS transistor within an output stage of the I / O circuit, and the other associated with a pre-driver for an NMOS transistor within the output stage. Advantageously, the two turn-on circuits turn on their corresponding output stage FETs and then automatically turn them off at substantially the same speed, regardless of process variations between PMOS and NMOS transistors in the same IC. Process variations may result in PMOS transistors being “stronger” than NMOS transistors, and vice versa. Stronger FETs have relatively lower threshold voltages and relatively higher electron mobilities compared to weaker FETs. The disclosed turn-on circuits operate at substantially the same speed to each other, regardless of any process variations between transistor polarities (types).

[0015] Figure 1 This is a block diagram of system 100, in which IC 110 is coupled to IC 150. Other ICs and other electrical components may also be included in system 100. IC 110 has I / O terminals 114a, 114b, 114c, ..., 114n (collectively referred to as I / O terminals 114). I / O terminals are externally accessible terminals, meaning they can be connected to circuitry outside the IC. IC 150 has I / O terminals 154a, 154b, 154c, ..., 154n (collectively referred to as I / O terminals 154). I / O terminals 114a to 114n are coupled to corresponding I / O terminals 154a to 154n via corresponding electrical conductors 121a, 121b, 121c, ..., 121n (collectively referred to as conductors 121). Two or more of electrical conductors 121a to 121n may be portions of a single cable.

[0016] IC 110 includes logic 111 and I / O circuits 112a, 112b, 112c, ..., 112n (collectively referred to as I / O circuits 112). Each I / O circuit 112a to 112n has an input coupled to logic 111 and an output coupled to a corresponding I / O terminal. IC 150 is similarly configured. IC 150 includes logic 151 and I / O circuits 152a, 152b, 152c, ..., 152n (collectively referred to as I / O circuits 152). Each I / O circuit 152a to 152n has an input coupled to logic 151 and an output coupled to a corresponding I / O terminal. Logic 111 and logic 151 may include a microcontroller or discrete digital logic. Logic 111 of IC 110 may generate signals to be sent to logic 151 of IC 150 via one or more of I / O pins 114a to 114n and 154a to 154n. Similarly, logic 151 can generate signals to be sent to logic 111 via one or more of its I / O pins. Therefore, any of the I / O terminals can be bidirectional, allowing one IC to send a signal to or receive a signal from another IC. In some instances, one or more of the I / O terminals can be unidirectional, where only one IC can send a signal to another IC.

[0017] I / O circuit 112b in Figure 1The diagram shows a pre-driver (PD) 116 coupled to output stage 118. One or more of the other I / O circuits 112a, 112c, ..., 112n and 152a, 152b, 152c, ..., 152n can be similarly configured. As described below, the pre-driver 116 of I / O circuit 112b includes a spin-rate control capability to limit the slope of the rising and falling edges of the corresponding I / O terminal 114b. Furthermore, the pre-driver 116 includes or is coupled to one or more turn-on circuits. The turn-on circuits help reduce the turn-on delay of the transistors in output stage 118 compared to the delay that would occur without the turn-on circuits.

[0018] Figure 2 This is a schematic diagram of a pre-driver 116 and an output stage 118 for I / O circuits (e.g., any one of I / O circuits 112a, 112b, 112c, ..., 112n or I / O circuits 152a, 152b, 152c, ..., 152n). Turn-on circuits 210 and 220 are also included and are described below. Output stage 118 includes transistors M1A and M1B. In this example, transistors M1A and M1B are field-effect transistors (FETs), where transistor M1A is a p-channel FET (PFET) and transistor M1B is an n-channel FET (NFET). The source of transistor M1A is coupled to a voltage terminal 202 (VDDIO). Voltage terminal 202 may be an externally accessible terminal (e.g., external to ICs 110, 150), and voltage VDDIO may be an externally supplied voltage.

[0019] The pre-driver 116 includes a pre-driver 116a for transistor M1A and a pre-driver 116b for transistor M1B. The drains of transistors M1A and M1B are coupled together at I / O terminal 114, and the source of transistor M1B is coupled to voltage terminal 203 (ground). Reference numeral 215 refers to the characteristic impedance of conductor 121 that couples I / O terminal 114 to an I / O terminal (e.g., I / O terminal 154) of another IC. Figure 1 In this example, resistors R118A and R118B are included and coupled between the drains of transistors M1A and M1B for impedance matching purposes (e.g., to match the output impedance of the I / O circuit to the characteristic impedance of conductor 121). Capacitor CLoad refers to the capacitive load applied to I / O terminal 114 by the parasitic capacitance of the I / O circuit of the IC coupled to conductor 121.

[0020] The pre-driver 116a includes transistors M21, M22, and M23 and resistor R21. Transistors M21 and M22 are PFETs, and transistor M23 is an NFET. The source of transistor M21 is coupled to voltage terminal 202. The drain of transistor M21 is coupled to the source of transistor M22 at terminal 205 and to the gate of transistor M1A in output stage 118. The voltage at terminal 205 to the gate of transistor M1A is PGATE. Transistor M1A is turned on when the PGATE voltage is at least a threshold voltage below VDDIO, and turned off if the PGATE voltage is not at least a threshold voltage below VDDIO.

[0021] The input signal to predrivers 116a and 116b is the SW_CTRL signal 115 (e.g., a signal from logic 111 or logic 151). The SW_CTRL signal 115 is provided to the gates of transistors M21 and M23 in predriver 116a. The gate of transistor M22 receives a bias voltage (BIAS). Figure 1 In this example, in response to a logic low level of the SW_CTRL signal 115, transistor M21 is turned on and transistor M23 is turned off. When transistor M21 is turned on, the PGATE voltage is pulled high to approximately the VDDIO voltage, thereby turning off transistor M1A.

[0022] In response to a logic high level of the SW_CTRL signal 115, transistor M21 is turned off and transistor M23 is turned on. Ignoring the turn-on circuit 210 for now, when transistor M23 is on, a current path exists through transistors M22 and M23 and resistor R21 to discharge the gate capacitance of transistor M1A, thereby turning on transistor M1A. When the channel of transistor M1A is off, current flows through transistor M1A to capacitor CLoad, which begins to charge, and the drain voltage of transistor M1A begins to increase towards VDDIO. When transistor M1A is on, the RC time constant formed by the parasitic capacitance of transistor M1A (e.g., gate capacitance) and resistor R21 controls the rise time rate at I / O terminal 114.

[0023] The pre-driver 116b includes transistors M24 and M25 and resistor R22. Transistor M24 is a PFET, and transistor M25 is an NFET. The sources of transistors M24 and M25 are coupled to voltage terminals 207 and 203, respectively. Voltage terminal 207 has a voltage VDDA, which may be a stable voltage generated within the IC containing I / O circuitry. In one example, voltage VDDA is lower than voltage VDDIO. The drain of transistor M24 is coupled to one terminal of resistor R22, and the drain of transistor M25 is coupled to the other terminal of resistor R22 and the gate of transistor M1B in output stage 118. The SW_CTRL signal is provided to the gates of transistors M24 and M25. The voltage at terminal 206 to the gate of transistor M1B is NGATE. Transistor M1B is turned on when the NGATE voltage is at least a threshold voltage above ground, and turned off if the NGATE voltage is not at least a threshold voltage above ground.

[0024] In response to a logic high of the SW_CTRL signal 115, transistor M25 turns on and transistor M24 turns off. With transistor M25 on, the NGATE voltage is pulled low to approximately ground potential, thereby turning off transistor M1B. In response to a logic low of the SW_CTRL signal 115, transistor M25 turns off and transistor M24 turns on. With transistor M24 on, the turn-on circuit 220 is temporarily ignored, and there is a current path from voltage terminal 207 through transistor M24 and resistor R22 to charge the gate capacitance of transistor M1B, thereby turning on transistor M1B. When the channel of transistor M1B turns off and the drain of the transistor begins to decrease towards ground, current flows from voltage terminal 207 through transistor M24 and resistor R22, the parasitic capacitance of transistor M1B (e.g., gate-to-drain capacitance), to ground. When transistor M1B is turned on, the RC time constant formed by the parasitic capacitance of transistor M1B and resistor R22 controls the rotation rate of the falling edge at I / O terminal 114.

[0025] As described above, resistors R21 and R22 help control the rise and fall rates on I / O terminal 114. Unfortunately, the RC time constant of resistor R21 and the gate-to-source capacitance of transistor M1A also delays the channel turn-on of transistor M1A because the current discharging from the gate of transistor M1A flows through resistor R21, thereby reducing the rate at which the gate voltage of transistor M1A reaches the threshold voltage. Similarly, the RC time constant of resistor R22 and the gate-to-source capacitance of transistor M1B also delays the channel turn-on of transistor M1B because the current charging the gate of transistor M1B flows through resistor R22.

[0026] The turn-on circuit 210 is shown separated from, but coupled to, pre-driver 116a. Similarly, the turn-on circuit 220 is shown separated from, but coupled to, pre-driver 116b. However, turn-on circuits 210 and 220 may be portions of their respective pre-drivers 116a and 116b.

[0027] The turn-on circuit 210 reduces the turn-on delay of transistor M1A. The turn-on circuit 210 has a terminal 210a coupled to terminal 205 and an input 210b for receiving the SW_CTRL signal 115. In response to the SW_CTRL signal 115 being logic high, the turn-on circuit 210 causes the PGATE voltage to drop faster than if the turn-on circuit 210 were not present. When the PGATE voltage drops to the threshold voltage of transistor M1A, transistor M1A turns on and the functionality of the turn-on circuit 210 is automatically deactivated to further pull down the PGATE voltage, thereby allowing the spin-rate control functionality of resistor R21 within the pre-driver 116a to help control the spin-rate of the rising edge on I / O terminal 114.

[0028] Similarly, turn-on circuit 220 reduces the turn-on delay of transistor M1B. Turn-on circuit 220 has a terminal 220a coupled to terminal 206 and an input 220b for receiving SW_CTRL signal 115. In response to SW_CTRL signal 115 being logic low, turn-on circuit 220 causes the NGATE voltage to increase faster than if turn-on circuit 220 were not present. When the NGATE voltage increases to the threshold voltage of transistor M1B, transistor M1B turns on and the functionality of turn-on circuit 220 is automatically deactivated to further pull up the NGATE voltage, thereby allowing the slew rate control functionality of resistor R22 within pre-driver 116b to help control the slew rate of the falling edge on I / O terminal 114.

[0029] As described above, due to process variations in IC manufacturing, the PFETs of an IC can be stronger or weaker than the NFETs of the IC. This difference between the PFETs and NFETs within the IC can cause turn-on circuit 210 to operate faster or slower than turn-on circuit 220. A faster turn-on circuit allows its corresponding output stage transistor to operate with less delay compared to a slower turn-on circuit turning on its corresponding output stage transistor. However, despite the process variations between the different polarities of the FETs within the turn-on circuits, turn-on circuits 210 and 220 described herein advantageously operate at substantially the same speed.

[0030] Figure 3Graph 301 illustrates the progression of the gate voltage NGATE of transistor M1B when it is turned on. At time T0, the SW_CTRL signal 115 is forced low to turn on transistor M1A via turn-on circuit 220, while simultaneously turning off transistor M1A via turn-on circuit 116a. Turn-on circuit 220 provides a current path (described below) to charge the gate capacitance of transistor M1B, causing the NGATE voltage to begin rising at time T0. At time T1, the gate voltage reaches the threshold voltage of transistor M1B, thus turning on transistor M1B. Turn-on circuit 220 causes the gate voltage to rise rapidly between time points T0 and T1. When the NGATE voltage reaches the threshold voltage of transistor M1B, not only does transistor M1B turn on, but turn-on circuit 220 automatically turns off, allowing the slew rate control implemented by resistor R22 to gradually increase the gate voltage of transistor M1B between time points T1 and T2. At time T2, the SW_CTRL signal 115 is forced high, causing pre-driver 116b to turn off transistor M1B and pre-driver 116a to turn on transistor M1A. Because resistor R22 is in the current path used to charge the gate of transistor M1B and not in the current path through transistor M25 used to discharge the gate of transistor M1B, transistor M1B turns off very quickly (now the spin rate control). Conversely, the spin rate control within pre-driver 116a controls the spin rate via transistor M1A.

[0031] Figure 4 This is a schematic diagram of a turn-on circuit 210 coupled to terminal 205 of pre-driver 116a. Turn-on circuit 210 includes transistors M402, M403, M404, M405, M406, M407, M409, and M410, resistor R42, and inverter 427. Transistors M402 and M409 are PFETs, and transistors M403 through M407 and M410 are NFETs. The source of transistor M402 is coupled to voltage terminal 202. The drains of transistors M402 and M407 are coupled together. The gate of transistor M402 is coupled to terminal 210a of turn-on circuit 210, terminal 205 of pre-driver 116a, and the gate of transistor M1A. The source of transistor M407 is coupled to the drain of transistor M406 and the gates of transistors M409 and M410. The source of transistor M406 is coupled to voltage terminal 203. The gate of transistor M407 is coupled to voltage terminal 207 and therefore receives a stable voltage VDDA.

[0032] The gate and drain of transistor M405 are coupled to voltage terminal 207. The sources of transistors M405 and M409 are coupled together. Transistor M405 ensures that the voltage at the source of transistor M409 is a threshold voltage of transistor M405 below voltage VDDA. The drains of transistors M409 and M410 are coupled together and coupled to the gate of transistor M403. Resistor R42 is coupled between the gate of transistor M403 and voltage terminal 203. The drain of transistor M403 is coupled to the gate of transistor M1A. The source of transistor M403 is coupled to the drain of transistor M404. The source of transistor M404 is coupled to voltage terminal 203. The gate of transistor M404 is coupled to input 210b of turn-on circuit 210 and receives SW_CTRL signal 115. Input 210b is coupled to the input of inverter 427, and the output of inverter 427 is coupled to the gate of transistor M406.

[0033] In response to SW_CTRL signal 115 being logic low, transistor M21 is turned on and the PGATE voltage is pulled high, thereby turning off transistor M1A. When the PGATE voltage is pulled high, transistor M402 is turned off. Furthermore, when SW_CTRL signal 115 is logic low, transistor M406 is turned on and transistor M404 is turned off. When transistor M406 is turned on, the gate of transistor M409 is pulled low, thereby turning on transistor M409. When transistor M404 is turned off, the Vgs of transistor M403 approaches its threshold value, and therefore transistor M403 is also turned off.

[0034] In response to the SW_CTRL signal 115 being logic high, transistor M21 is turned off and transistor M23 is turned on. Furthermore, the logic high level of the SW_CTRL signal 115 turns on transistor M404 and turns off transistor M406. The gate voltages of transistors M409 and M410 will remain low because transistor M402 is not yet turned on, otherwise the gate capacitance of transistor M410 would be charged. If transistor M409 is still turned on and transistor M404 is now turned on, transistor M403 will also turn on.

[0035] Both transistors M403 and M404 are turned on, providing a fast discharge current path for discharging the gate capacitance of transistor M1A. This discharge current path for discharging the gate of transistor M1A and thus turning it on does not include resistor R21, and therefore transistor M1A turns on much faster than if circuit 210 were not turned on.

[0036] When the PGATE voltage drops below the threshold voltage of transistor M1A, not only transistor M1A turns on, but transistor M402 also turns on. With transistor M402 on, the gate voltages of transistors M409 and M410 are pulled up to approximately a threshold voltage below VDDA for transistor M407, causing transistor M410 to turn on and transistor M409 to turn off. Transistor M405 provides a voltage below a threshold voltage below VDDA at the source of transistor M409, thus ensuring that transistor M409 is turned off when its gate voltage is also below a threshold voltage below VDDA. The turning on of transistor M410 discharges the gate capacitance of transistor M403, thereby turning transistor M403 off. When transistor M403 is off, the fast discharge current path that discharges the gate capacitance of transistor M1A by turning on circuit 210 is disabled, and the rotation rate control implemented by further discharging the gates of transistors M1A to transistors M22 and M23 and resistor R21 dominates the continued discharge of the gate of transistor M1A.

[0037] In the turn-on circuit 210, transistor M402 is a PFET, and transistors M403 and M404 are NFETs. Therefore, the polarities of transistors M403 and M404 are opposite to those of transistor M402. The time taken to turn on, for example, the PFETs M1A and M402 is the time taken to discharge the gate capacitance of the PFET. The rate of change of the voltage across the capacitor over time (dv / dt) is proportional to the ratio of the discharge current to the capacitance of the capacitor. That is, (Equation 1) where " "is the discharge current of the gate capacitor, and " "This refers to the gate capacitance. As described above, due to process variations, one polarity of a FET can be stronger than the other. For example, a PFET can be stronger than an NFET, or vice versa. For the same gate charge / discharge current, a stronger FET takes less time to reach the transistor's threshold voltage compared to a weaker FET. In an IC containing turn-on circuit 210 where the PFET is stronger than the NFET, transistor M402 will be stronger than transistors M403 and M404. The fact that transistors M403 and M404 are weaker than transistor M402 means that the discharge current of transistor M402 will be less than that of transistors M403 and M404 compared to transistors M402." When M402 has the same polarity, the turn-on time of transistor M402 is reduced. Conversely, in an IC containing turn-on circuit 210 where the PFET is weaker than the NFET, transistor M402 will be weaker than transistors M403 and M404. Transistors M403 and M404 being stronger than transistor M402 means that the discharge current of transistor M402 will be greater than when transistors M403 and M404 have the same polarity as transistor M402, thus increasing the turn-on time of transistor M402. In either case (PFET stronger than NFET or NFET stronger than PFET), the response time of turn-on circuit 210 to turn on transistor M1A is approximately the same.

[0038] Figure 5 It is the connection of circuit 210 and Figure 4 The schematic diagram is largely the same as the schematic diagram. Figure 4 and Figure 5 The difference between them is Figure 5 The examples do not include Figure 4 Transistor M405 in the example. Another difference is that resistor R42 is not included between the drain of transistor M409 and voltage terminal 203. Figure 5 In this configuration, the source of transistor M409 is coupled to voltage terminal 207, instead of... Figure 4 The source of transistor M409 is coupled to transistor M405.

[0039] exist Figure 4 and 5 In both schematic diagrams, a bias voltage derived from voltage VDDIO is not required. For example, transistor M407 is biased using voltage VDDA, which is a stable voltage generated within the IC containing I / O circuitry 112. Other I / O circuits may require bias voltages derived from VDDIO for one or more transistors. Generating such bias voltages requires a circuit system. The technical advantage of turn-on circuitry 210 is that such a circuit system is not required.

[0040] Figure 6This is a schematic diagram of the turn-on circuit 220 for the pre-driver 116b and the output stage transistor M1B. The turn-on circuit 220 includes transistors M502, M503, M504, M505, M506, M507, M509, and M510, resistor R52, and inverter 527. Transistors M502 and M509 are NFETs, and transistors M503 through M507 and M510 are PFETs. The gate of transistor M502 is coupled to terminal 206 of input 220a and pre-driver 116b. The sources of transistors M502 and M505 are coupled to voltage terminal 203 (e.g., ground). The drains of transistors M502 and M507 are coupled together. The gate of transistor M507 is coupled to ground. The source of transistor M507 is coupled to the drain of transistor M506 and the gates of transistors M509 and M510. The source of transistor M506 is coupled to voltage terminal 207. The input of inverter 527 and the gate of transistor M504 are coupled to input 220b and receive the SW_CTRL signal 115. The output of inverter 527 is coupled to the gate of transistor M506.

[0041] The sources of transistors M510 and M504 are coupled to the voltage terminal VDDA. The drains of transistors M509 and M510 are coupled together and to the gate of transistor M503 and the terminal of resistor R52. The opposite terminal of resistor R52 is coupled to the voltage terminal 207. The sources of transistors M505 and M509 are coupled together. The gate of transistor M505 is coupled to ground. The drain of transistor M504 is coupled to the source of transistor M503, and the drain of transistor M503 is coupled to the gate of transistor M502.

[0042] When the SW_CTRL signal 115 is at a logic high level, transistors M25 and M506 are turned on, and transistor M504 is turned off. Transistor M25 being turned on causes transistor M502 to be turned off. Furthermore, when transistor M506 is turned on, the voltage at the gates of transistors M509 and M510 is sufficiently high, causing transistor M509 to be turned on and transistor M510 to be turned off. When the SW_CTRL signal 115 is at a logic high level, transistor M404 is also turned off. When transistor M504 is turned off, transistor M503 is also turned off.

[0043] When the SW_CTRL signal 115 goes low, transistors M25 and M506 are turned off, and transistor M504 is turned on. The voltage on the gate of transistor M510 remains high enough that transistor M510 remains off and transistor M509 remains on. At this time, transistors M503 and M504 are both turned on. Transistors M503 and M504 are coupled in series between voltage terminal 207 and the gate of transistor M502, thus providing a fast charging current path for charging the gates of transistors M1B and M502, thereby quickly turning on transistor M1B when the NGATE voltage reaches the threshold voltage of transistor M1B. When the VGATE voltage is at the threshold voltage of transistor M1B, transistor M502 is also turned on. When transistor M502 is turned on, the gate voltage of transistor M510 is pulled low enough through transistors M507 and M502, thereby turning on transistor M510. Turning on transistor M510 turns off transistor M503, thereby disabling the fast charging current path from the gate of transistor M1B to transistors M504 and M503.

[0044] Similar to the case for switching circuit 210, in switching circuit 220, transistor M502 has a different polarity than transistors M503 and M504. Figure 6 In the example, transistor M502 is an NFET, and transistors M503 and M504 are PFETs. In an IC containing turn-on circuit 220 where the PFET is stronger than the NFET, transistor M502 will be weaker than transistors M503 and M504. The fact that transistors M503 and M504 are stronger than transistor M502 means that the charging current of transistor M502 will be greater than that of transistors M503 and M504 with the same polarity as transistor M502, thus increasing the turn-on time of transistor M502. Conversely, in an IC containing turn-on circuit 220 where the PFET is weaker than the NFET, transistor M502 will be stronger than transistors M503 and M504. The fact that transistors M503 and M504 are weaker than transistor M502 means that the charging current of transistor M502 will be less than that of transistors M503 and M504 with the same polarity as transistor M502, thus reducing the turn-on time of transistor M502. In either case (PFET is stronger than NFET or NFET is stronger than NFET), the response time of the turn-on circuit 220 to turn on transistor M1B is approximately the same.

[0045] Advantageously, if the PFET in the IC containing turn-on circuits 210 and 220 is stronger than the NFET, then the threshold voltage of the PFET is lower than the threshold voltage of the NFET. The threshold voltage of transistor M402 is lower than the threshold voltage of the NFET in the IC. Therefore, the PFET transistor M402 in turn-on circuit 210 will turn on with a smaller Vgs compared to the NFET transistor M502 in turn-on circuit 220. Therefore, turn-on circuit 210 includes NFETs (weaker) as transistors M403 and M404 to discharge the gates of PFETs (stronger) M402 and M1A, and turn-on circuit 220 includes PFETs (stronger) as transistors M503 and M504 to charge the gates of NFETs (weaker) M502 and M1B, thereby making the response times of turn-on circuits 210 and 220 to turn on their respective transistors M1A and M1B approximately the same.

[0046] Similarly, if the NFET is stronger than the PFET in the IC, then the threshold voltage of the NFET is lower than the threshold voltage of the PFET. Figure 6 The threshold voltage of transistor M502 in the IC is lower than the threshold voltage of the PFET in the IC. Therefore, the NFET transistor M502 in the turn-on circuit 220 will turn on with a smaller Vgs compared to the PFET transistor M402 in the turn-on circuit 210. Therefore, the turn-on circuit 220 includes PFETs (weaker) as transistors M503 and M504 to charge the gates of NFETs (stronger) M502 and M1B, and the turn-on circuit 210 includes NFETs (stronger) as transistors M403 and M404 to discharge the gates of NFETs (weaker) M402 and M1A, thereby making the response times of the turn-on circuits 210 and 220 to turn on their respective transistors M1A and M1B approximately the same.

[0047] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0048] Furthermore, in this description, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0049] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device, or a combination thereof.

[0050] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0051] A circuit or apparatus described herein as including certain components may conversely be adaptable to those components used to form the described circuit system or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may conversely include only semiconductor elements within a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0052] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with minimal alteration to the rest of the circuitry. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs – e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on or above silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) substrates.

[0053] Reference may be made to the control input and current terminals of the transistor in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0054] In this article, "FET on" or "enabled" means that the FET has an existing conductive channel and drain current can flow through it. "FET off" or "disabled" means that the conductive channel is absent, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0055] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0056] While some elements in the described examples are included in the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features depicted as being external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as being internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0057] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0058] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. A circuit comprising: The first transistor has a control terminal; A pre-driver having an input and an output, the output being coupled to the control terminal of the first transistor; A second transistor of a first polarity has a control terminal coupled to the output of the pre-driver; and A third transistor having a second polarity and having a first terminal and a second terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the second transistor; and A fourth transistor having the second polarity and having a first terminal and a second terminal, the first terminal of the fourth transistor being coupled to the second terminal of the third transistor, and the second terminal of the fourth transistor being coupled to a supply terminal.

2. The circuit of claim 1, wherein the pre-driver is a first pre-driver and the supply terminal is a first supply terminal, and the circuit further comprises: The fifth transistor has a control terminal; A second pre-driver has an input and an output, the output of the second pre-driver being coupled to the control terminal of the fifth transistor; The sixth transistor of the second polarity has a control terminal coupled to the output of the second pre-driver; and A seventh transistor having the first polarity and having a first terminal and a second terminal, wherein the first terminal of the seventh transistor is coupled to the control terminal of the second transistor; and An eighth transistor having the first polarity and having a first terminal and a second terminal, the first terminal of the eighth transistor being coupled to the second terminal of the seventh transistor, and the second terminal of the eighth transistor being coupled to a second supply terminal.

3. The circuit according to claim 1, wherein: The second transistor is a p-channel field-effect transistor (PFET); The third transistor and the fourth transistor are n-channel field-effect transistors (NFETs); and The supply terminal is a grounding terminal.

4. The circuit according to claim 1, wherein: The second transistor is an n-channel field-effect transistor (NFET); The third transistor and the fourth transistor are p-channel field-effect transistors (PFETs); and The supply terminal is a voltage terminal.

5. The circuit of claim 1, wherein the third transistor is configured to turn off in response to the second transistor being turned on.

6. The circuit of claim 1, wherein the pre-driver includes a fifth transistor coupled in series with a resistor between the output and the supply terminal.

7. The circuit of claim 1, wherein the supply terminal is a first supply terminal, the second transistor has a first terminal and a second terminal, and the circuit further comprises: A fifth transistor having a control terminal and a first terminal and a second terminal, wherein the control terminal of the fifth transistor is coupled to a second supply terminal, and the first terminal of the fifth transistor is coupled to the second terminal of the second transistor; and A sixth transistor having a control terminal and a first terminal and a second terminal, the control terminal of the sixth transistor being coupled to the input of the pre-driver, the first terminal of the sixth transistor being coupled to the second terminal of the fifth transistor, and the second terminal of the sixth transistor being coupled to the first supply terminal.

8. The circuit of claim 1, further comprising a semiconductor die having an externally accessible terminal, wherein the first transistor has a terminal coupled to the externally accessible terminal.

9. A circuit comprising: The first transistor has a control terminal; A pre-driver having an input and an output, the output being coupled to the control terminal of the first transistor; p-channel field-effect transistor (PFET) having a gate coupled to the output of the pre-driver; and A first n-channel field-effect transistor (NFET) has a source and a drain, the drain of the first NFET being coupled to the gate of the PFET; and A second NFET has a source and a drain, the drain of the second NFET being coupled to the source of the first NFET, and the source of the second NFET being coupled to a supply terminal.

10. The circuit of claim 9, wherein the PFET is a first PFET, the pre-driver is a first pre-driver, the supply terminal is a first supply terminal, and the circuit further comprises: The fifth transistor has a control terminal; A second pre-driver has an input and an output, the input of the second pre-driver being coupled to the input of the first pre-driver, and the output of the second pre-driver being coupled to the control terminal of the fifth transistor; A third NFET having a gate coupled to the output of the second pre-driver; and A second PFET has a source and a drain, the drain of the second PFET being coupled to the gate of the third NFET; and A third PFET has a source and a drain, the drain of the third PFET being coupled to the source of the second PFET, and the source of the third PFET being coupled to a second supply terminal.

11. The circuit of claim 9, wherein the first NFET is configured to turn off in response to the PFET being turned on.

12. The circuit of claim 9, wherein the pre-driver comprises: A second transistor having a first terminal and a second terminal, the first terminal of the second transistor being coupled to the output of the pre-driver; and A resistor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the supply terminal.

13. The circuit of claim 9, wherein the supply terminal is a first supply terminal, the PFET has a source and a drain, and the circuit further comprises: A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to a second supply terminal, and the first terminal of the second transistor is coupled to the drain of the PFET; and A third transistor has a control terminal and a first terminal and a second terminal, the control terminal of the third transistor being coupled to the input of the pre-driver, the first terminal of the third transistor being coupled to the second terminal of the second transistor, and the second terminal of the third transistor being coupled to the first supply terminal.

14. The circuit of claim 9, further comprising a semiconductor die having an externally accessible terminal, wherein the first transistor has a terminal coupled to the externally accessible terminal.

15. A circuit comprising: The first n-channel field-effect transistor (NFET) has a gate; A pre-driver having an input and an output, the output being coupled to the gate of the first NFET; A second NFET having a gate coupled to the output of the pre-driver; and A first p-channel field-effect transistor (PFET) has a source and a drain, the drain of the first PFET being coupled to the gate of the second NFET. and A second PFET has a source and a drain, the drain of the second PFET being coupled to the source of the first PFET, and the source of the second PFET being coupled to a supply terminal.

16. The circuit of claim 15, wherein the pre-driver is a first pre-driver, the supply terminal is a first supply terminal, and the circuit further comprises: The third PFET has a gate; A second pre-driver has an input and an output, the input of the second pre-driver being coupled to the input of the first pre-driver, and the output of the second pre-driver being coupled to the gate of the third PFET; A third NFET having a gate coupled to the output of the second pre-driver; and A fourth PFET having a source and a drain, the drain of the fourth PFET being coupled to the gate of the third NFET; and A fifth PFET having a source and a drain, the drain of the fifth PFET being coupled to the source of the fourth PFET, and the source of the fifth PFET being coupled to a second supply terminal.

17. The circuit of claim 16, wherein the fifth PFET has a gate coupled to the input of the pre-driver.

18. The circuit of claim 15, wherein the first PFET is configured to turn off in response to the second NFET being turned on.

19. The circuit of claim 15, wherein the pre-driver comprises: The third PFET has a source and a drain; and A resistor having a first terminal coupled to the drain of the third PFET and a second terminal coupled to the output of the pre-driver.

20. The circuit of claim 15, further comprising a semiconductor die having an externally accessible terminal, the first NFET having a drain, and the drain of the first NFET being coupled to the externally accessible terminal.

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