Time domain interleaved SAR ADC capacitor mismatch calibration method

Abstract

The invention relates to a time domain interleaving SAR ADC capacitor mismatch calibration method, which belongs to the technical field of electronic circuits, is executed by a digital calibration module, and comprises the following steps: alternately sampling and holding an input signal through a time domain interleaving sampling network, and respectively distributing the input signal to a first analog-to-digital conversion branch and a second analog-to-digital conversion branch, a positive Dither disturbance signal and a negative Dither disturbance signal are respectively applied, a first digital code and a second digital code are respectively output, and weight estimation values of capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are iteratively updated based on a minimum mean square algorithm; and a weighted difference value output by the first analog-to-digital conversion branch and the second analog-to-digital conversion branch approaches to zero. According to the method, the problem that deviation exists between the actual weight and the expected weight of the SAR ADC due to relative mismatch of the capacitor array in the manufacturing process of the SAR ADC is solved.

Description

A method for time-domain interleaved SAR ADC capacitance mismatch calibration Technical Field

[0001] This invention relates to a time-domain interleaved SAR ADC capacitance mismatch calibration method, belonging to the field of electronic circuit technology. Background Technology

[0002] Analog-to-digital converters (ADCs), as core components connecting digital and analog circuits, occupy an irreplaceable position in the field of integrated circuits. With the surge in demand for low-power, high-speed ADCs in scenarios such as base stations, radar, and high-performance communication equipment, the successive approximation register (SAR) ADC has become a research hotspot due to its simple structure, low power consumption, and fast conversion speed. Traditional SAR ADCs achieve successive approximation quantization of analog signals through a binary weighted capacitor array. Its core principle is to use the weight allocation of the capacitor array to complete voltage comparison and ultimately output the corresponding digital code. Time-domain interleaving technology further improves system throughput through multi-channel parallel sampling, giving SAR ADCs significant advantages in high-speed applications. However, existing SAR ADC designs are generally based on ideal capacitor array models, assuming that the capacitance values ​​of each unit in the capacitor array strictly follow the binary weight relationship. However, in the actual manufacturing process, due to factors such as process deviations and material inhomogeneity, the capacitor array will randomly produce relative mismatch phenomena, resulting in a systematic deviation between the actual weight and the expected weight.

[0003] Relative mismatch of the capacitor array is a key factor contributing to the performance degradation of SAR ADCs. Capacitor value deviations introduced during manufacturing disrupt the expected weight distribution of the binary weighted capacitor array, causing the ADC's input-output characteristics to deviate from the ideal linear relationship and introducing additional nonlinear errors. These nonlinear errors are further amplified in time-domain interleaved systems. When multiple SAR ADC channels operate in parallel, the weight deviations caused by capacitor mismatch in each channel couple with each other, resulting in a significant deterioration in the dynamic performance of the interleaved system. Specifically, this manifests as a decrease in the system signal-to-noise ratio (SNR), a narrowing of the spurious-free dynamic range (SFDR), and a decrease in the effective number of bits (ENOB), ultimately leading to the ADC's performance failing to meet design requirements in high-speed, high-precision scenarios. Current technologies lack effective calibration methods for capacitor array mismatch, making it difficult to dynamically correct weight deviations during manufacturing or operation, thus becoming a core bottleneck restricting the improvement of SAR ADC performance. Summary of the Invention

[0004] The purpose of this invention is to provide a time-domain interleaved SAR ADC capacitor mismatch calibration method. By reducing the impact of the weight deviation caused by capacitor array mismatch on the dynamic performance of the interleaved ADC, this method solves the problem of deviation between the actual weight and the expected weight of the SAR ADC due to the relative mismatch of the capacitor array during the manufacturing process. This method can perform real-time tracking calibration without affecting the operation of the ADC system.

[0005] To solve the above-mentioned technical problems, the present invention is implemented using the following technical solution.

[0006] This invention provides a time-domain interleaved SAR ADC capacitance mismatch calibration method, executed by a digital calibration module, comprising:

[0007] Acquire input signal;

[0008] The input signal is alternately sampled and held using a time-domain interleaved sampling network, and then distributed to the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, respectively.

[0009] During the conversion of the holding signal by the first analog-to-digital conversion branch, a positive [condition] is applied. Disturbance signal;

[0010] During the conversion of the holding signal in the second analog-to-digital conversion branch, a negative signal is applied. Disturbance signal; acquire the first digital code output by the first analog-to-digital conversion branch and the second digital code output by the second analog-to-digital conversion branch; based on the least mean square algorithm, use the first digital code and the second digital code to iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, so that the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are obtained. The weighted difference of the output approaches zero under the influence of the disturbance signal. The weight estimate of the capacitor array in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch is output to calibrate the nonlinear error introduced by capacitor mismatch.

[0011] Both the first analog-to-digital conversion branch and the second analog-to-digital conversion branch include a non-binary capacitor array. A bit successive approximation analog-to-digital converter, used for time-domain interleaved sampling and quantization of input signals.

[0012] Furthermore, the unit capacitance value of the non-binary capacitor array is... Among them, for An analog-to-digital converter with bit-level conversion accuracy, wherein the total capacitance of the non-binary capacitor array is less than or equal to 1. .

[0013] Furthermore, the positive Disturbance signal and negative The expected values ​​of the injected perturbation signals are equal in magnitude, and the expected values ​​of the injected signals are based on the... The theoretical voltage value corresponding to the least significant bit of a unit in a successive approximation analog-to-digital converter is set.

[0014] Furthermore, using the first digital code and the second digital code, the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are iteratively updated, including:

[0015] Calculate the error signal for the current iteration cycle; update the weight estimate of the first analog-to-digital conversion branch based on the error signal, the first digital code, and the first iteration step size; update the weight estimate of the second analog-to-digital conversion branch based on the error signal, the second digital code, and the first iteration step size; update the weight estimate of the second analog-to-digital conversion branch based on the error signal and the second iteration step size. Expected value of the injected disturbance signal .

[0016] Furthermore, the error signal is represented as:

[0017] ;

[0018] In the formula, This represents the error signal for the current iteration period. This represents the first reconstructed value obtained by weighted summation of the first digit code based on the current weight estimates. This represents the second reconstructed value obtained by weighted summation of the second digit code based on the current weight estimates. Indicates the current iteration cycle Expected value of the injected disturbance signal.

[0019] Furthermore, the first reconstructed value, obtained by weighted summation of the first digital code based on the current weight estimates, is expressed as:

[0020] ;

[0021] In the formula, The first digit code represents the first digit code. Bit code value In the first analog-to-digital conversion branch, the first... The current weight estimate of the bit capacitance.

[0022] Furthermore, in the first analog-to-digital conversion branch, the first... The current weighted estimate of the bit capacitance is expressed as:

[0023] ;

[0024] In the formula, Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first iteration step size. No. Error signal after the next iteration.

[0025] Furthermore, the second reconstructed value, obtained by weighted summation of the second digital code based on the current weight estimates, is expressed as:

[0026] ;

[0027] In the formula, The second digit code represents the first digit. Bit code value Indicates the second analog-to-digital conversion branch. The current weight estimate of the bit capacitance.

[0028] Furthermore, in the second analog-to-digital conversion branch, the first The current weighted estimate of the bit capacitance is expressed as:

[0029] ;

[0030] In the formula, Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the bit capacitance.

[0031] Furthermore, the aforementioned The expected value of the injected disturbance signal is expressed as:

[0032] ;

[0033] In the formula, Indicates the first After the next iteration The expected value of the injected disturbance signal. Indicates the first After the next iteration The expected value of the injected disturbance signal. This indicates the step size of the second iteration.

[0034] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0035] 1. This invention applies positive and negative Dither perturbation signals to the digital calibration module and iteratively updates the weight estimates using the least mean square algorithm. This makes the weighted difference between the outputs of the first and second analog-to-digital conversion branches approach zero under the influence of the Dither perturbation signal. This effectively calibrates the nonlinear error introduced by capacitor mismatch, significantly improves the dynamic performance of the time-domain interleaved SAR ADC system, ensures that the ADC meets design requirements in high-speed and high-precision scenarios, and solves the problem of deviation between the actual and expected weights of the SAR ADC caused by the relative mismatch of the capacitor array during the manufacturing process.

[0036] 2. This invention is designed based on a non-binary capacitor array. While ensuring bit conversion accuracy, it effectively reduces the physical size and parasitic capacitance of the capacitor array, reduces the impact of process fluctuations during manufacturing, and, together with the symmetrical injection mechanism of positive and negative Dither perturbation signals, enables the calibration system to more accurately capture capacitor mismatch characteristics during operation, achieving rapid convergence of weight estimates and high-precision calibration.

[0037] 3. Based on the least mean square algorithm, this invention uses the first digital code and the second digital code to iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, so that the weighted difference between the outputs of the first analog-to-digital conversion branch and the second analog-to-digital conversion branch under the influence of positive and negative Dither perturbation signals approaches zero, effectively suppressing the nonlinear error introduced by capacitor mismatch and significantly improving the dynamic performance of the time-domain interleaved SAR ADC.

[0038] 4. This invention achieves independent calibration of the weight deviation of the capacitor arrays of the first analog-to-digital conversion branch and the second analog-to-digital conversion branch and dynamic optimization of the Dither injection expectation value by accurately constructing the error signal and iteratively calculating the weight estimate step by step. This avoids the error coupling problem in the traditional single-channel calibration method, ensuring that high linearity output can still be maintained within the manufacturing tolerance range, and meeting the stringent performance requirements of high-speed and high-precision scenarios such as base stations and radar. Attached Figure Description

[0039] Figure 1 is a flowchart illustrating a time-domain interleaved SAR ADC capacitance mismatch calibration method provided in an embodiment of the present invention;

[0040] Figure 2 is a schematic diagram of the implementation process of a time-domain interleaved SAR ADC capacitance mismatch calibration method provided in an embodiment of the present invention;

[0041] Figure 3 is a schematic diagram comparing the FFT results before and after calibration using the time-domain interleaved SAR ADC capacitance mismatch calibration method provided in the embodiment of the present invention. Detailed Implementation

[0042] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0043] Example 1

[0044] As shown in Figure 1, this embodiment introduces a time-domain interleaved SAR ADC capacitance mismatch calibration method, which is executed by a digital calibration module and includes:

[0045] Step 1: Acquire the input signal.

[0046] This invention provides a stable and reliable raw data source for the time-domain interleaved sampling network by accurately acquiring the input signal, ensuring the accuracy of the subsequent alternating sampling and holding operations of the first and second analog-to-digital conversion branches, and fundamentally guaranteeing the quantization accuracy of the SAR ADC system for analog signals.

[0047] Step 2: The input signal is alternately sampled and held using a time-domain interleaved sampling network, and then distributed to the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, respectively.

[0048] This invention employs a time-domain interleaved sampling network to alternately sample and hold the input signal and distribute it to the first analog-to-digital conversion branch and the second analog-to-digital conversion branch. While improving the system throughput by utilizing time-domain interleaving technology, the independent sampling mechanism of the first and second analog-to-digital conversion branches effectively isolates the impact of capacitor mismatch caused by process deviations, laying the foundation for the differentiated injection of subsequent positive and negative Dither perturbation signals.

[0049] Step 3: During the conversion of the holding signal in the first analog-to-digital conversion branch, a positive voltage is applied. Disturbance signal.

[0050] This invention applies a positive Dither perturbation signal during the first analog-to-digital conversion branch conversion process. By using a controllable additional error signal to excite the weight deviation characteristics of the capacitor array, and in conjunction with the least mean square algorithm, dynamically adjusts the weight estimate, effectively capturing and quantifying the nonlinear error introduced by capacitor mismatch.

[0051] Step 4: During the conversion of the holding signal in the second analog-to-digital conversion branch, a negative [condition] is applied. Disturbance signal.

[0052] In this invention, a negative Dither perturbation signal is applied during the conversion process of the second analog-to-digital conversion branch, forming a symmetrical error excitation with the positive Dither perturbation. This enables the weighted difference generated by the first and second analog-to-digital conversion branches under the influence of the perturbation signal to accurately reflect the capacitor mismatch deviation, providing a key error signal for iteratively updating the weight estimate.

[0053] Step 5: Obtain the first digital code output by the first analog-to-digital conversion branch and the second digital code output by the second analog-to-digital conversion branch.

[0054] This invention acquires a first digital code and a second digital code. Through the accurate acquisition and storage of the digital codes, reliable data support is provided for subsequent weight iteration updates based on the least mean square algorithm, ensuring the accuracy of error signal calculation and the effectiveness of the calibration process.

[0055] Step Six: Based on the least mean square algorithm, using the first digital code and the second digital code, iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, so that the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are... The weighted difference of the output approaches zero under the influence of the disturbance signal. The weight estimate of the capacitor array in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch is output to calibrate the nonlinear error introduced by capacitor mismatch.

[0056] Both the first analog-to-digital conversion branch and the second analog-to-digital conversion branch include a non-binary capacitor array. A bit successive approximation analog-to-digital converter, used for time-domain interleaved sampling and quantization of input signals.

[0057] This invention utilizes the least mean square algorithm to iteratively update the capacitor array weight estimates using the digital codes of the first and second analog-to-digital conversion branches. Through precise calculation of the error signal and gradient updates of the weight estimates, the first and second analog-to-digital conversion branches are optimized. The weighted difference of the output approaches zero under the influence of disturbance signals, directly calibrating the nonlinear error introduced by capacitor mismatch, significantly improving the signal-to-noise ratio, spurious-free dynamic range and effective number of bits of the time-domain interleaved SAR ADC, and meeting the performance requirements of high-speed and high-precision scenarios.

[0058] Example 2

[0059] Based on the same inventive concept as Embodiment 1, this embodiment describes the implementation steps of a time-domain interleaved SAR ADC capacitance mismatch calibration method, executed by a digital calibration module, including:

[0060] Step 1: Acquire the input signal.

[0061] Step 2: The input signal is alternately sampled and held using a time-domain interleaved sampling network, and then distributed to the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, respectively.

[0062] Step 3: During the conversion of the holding signal in the first analog-to-digital conversion branch, a positive voltage is applied. Disturbance signal.

[0063] Step 4: During the conversion of the holding signal in the second analog-to-digital conversion branch, a negative [condition] is applied. Disturbance signal.

[0064] In this embodiment, the positive Disturbance signal and negative The expected values ​​of the injected perturbation signals are equal in magnitude, and the expected values ​​of the injected signals are based on the... The theoretical voltage value corresponding to the least significant bit of a unit in a successive approximation analog-to-digital converter is set.

[0065] Step 5: Obtain the first digital code output by the first analog-to-digital converter branch and the second digital code output by the second analog-to-digital converter branch.

[0066] Step 6: Based on the least mean square algorithm, using the first digital code and the second digital code, iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, so that the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are... The weighted difference of the output approaches zero under the influence of the disturbance signal. The weight estimate of the capacitor array in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch is output to calibrate the nonlinear error introduced by capacitor mismatch.

[0067] Step 6.1: Calculate the error signal for the current iteration period.

[0068] In this embodiment, the error signal is represented as:

[0069] ;

[0070] In the formula, This represents the error signal for the current iteration period. This represents the first reconstructed value obtained by weighted summation of the first digit code based on the current weight estimates. This represents the second reconstructed value obtained by weighted summation of the second digit code based on the current weight estimates. Indicates the current iteration cycle Expected value of the injected disturbance signal.

[0071] In this embodiment, the first reconstructed value obtained by weighted summation of the first digital code based on the current weight estimate is expressed as:

[0072] ;

[0073] In the formula, The first digit code represents the first digit code. Bit code value In the first analog-to-digital conversion branch, the first... The current weight estimate of the bit capacitance.

[0074] In this embodiment, the second reconstructed value, obtained by weighted summation of the second digital code based on the current weight estimate, is expressed as:

[0075] ;

[0076] In the formula, The second digit code represents the first digit. Bit code value Indicates the second analog-to-digital conversion branch. The current weight estimate of the bit capacitance.

[0077] Step 6.2: Update the weight estimate of the first analog-to-digital conversion branch according to the error signal, the first digital code and the first iteration step size.

[0078] In this embodiment, the first analog-to-digital conversion branch... The current weighted estimate of the bit capacitance is expressed as:

[0079] ;

[0080] In the formula, Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first iteration step size. No. Error signal after the next iteration.

[0081] Step 6.3: Update the weight estimate of the second analog-to-digital conversion branch based on the error signal, the second digital code, and the first iteration step size.

[0082] In this embodiment, the second analog-to-digital conversion branch... The current weighted estimate of the bit capacitance is expressed as:

[0083] ;

[0084] In the formula, Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the bit capacitance.

[0085] Step 6.4: Update the... based on the error signal and the second iteration step size. Expected value of the injected disturbance signal .

[0086] In this embodiment, the The expected value of the injected disturbance signal is expressed as:

[0087] ;

[0088] In the formula, Indicates the first After the next iteration The expected value of the injected disturbance signal. Indicates the first After the next iteration The expected value of the injected disturbance signal. This indicates the step size of the second iteration.

[0089] In this embodiment, both the first analog-to-digital conversion branch and the second analog-to-digital conversion branch include a non-binary capacitor array. A bit successive approximation analog-to-digital converter, used for time-domain interleaved sampling and quantization of input signals.

[0090] In this embodiment, the unit capacitance value of the non-binary capacitor array is Among them, for An analog-to-digital converter with bit-level conversion accuracy, wherein the total capacitance of the non-binary capacitor array is less than or equal to 1. .

[0091] In Figure 2, both the first analog-to-digital conversion branch SAR ADC A and the second analog-to-digital conversion branch SAR ADC B are SAR ADC modules based on a 10-bit architecture with two redundant bits. After the system is powered on, the first analog-to-digital conversion branch SAR ADC A and the second analog-to-digital conversion branch SAR ADC B perform parallel analog-to-digital conversion on the same input signal.

[0092] During the analog-to-digital conversion process, this embodiment injects a positive amplitude of +4 LSB into the first analog-to-digital conversion branch SAR ADC A through a non-binary capacitor array. The disturbance signal is injected into the second analog-to-digital conversion branch SAR ADC B with a negative amplitude of -4 LSB. The disturbance signal creates a symmetrical error excitation condition. After the first analog-to-digital conversion branch SAR ADC A and the second analog-to-digital conversion branch SAR ADC B complete the analog-to-digital conversion respectively, they output the first digital code. Second digital code And transmit it synchronously to the digital calibration module.

[0093] The digital calibration module first bases itself on the preset first analog-to-digital conversion branch. The initial weight estimate of the capacitor and the preset weight of the first capacitor in the analog-to-digital conversion branch. The initial weight estimate of the bit capacitance for the first digital code Second digital code Perform weighted difference operation to generate initial error signal Then it enters the iterative convergence phase, according to The weight estimates of the first analog-to-digital conversion branch SAR ADC A are updated according to... The weight estimates for the second analog-to-digital conversion branch SAR ADC B are updated, and simultaneously based on... right Expected value of signal injection Make dynamic adjustments.

[0094] During the iteration process, if the error signal If the error signal continues to approach 0, i.e., the convergence condition is met, the calibration terminates; otherwise, the system continues to perform the above update steps in a loop until the error signal stabilizes to a constant value close to 0.

[0095] In this embodiment, the first iteration step size is... Set as Second iteration step size Set as By adjusting the iteration step size parameter, the weight estimate is ensured to match the expected injection value. The rapid convergence enables effective calibration of capacitance mismatch errors, thereby improving the dynamic performance of the time-domain interleaved SAR ADC system.

[0096] Figure 3 shows a comparison of the FFT results before and after calibration using the time-domain interleaved SAR ADC capacitance mismatch calibration method in this embodiment. The spectrum comparison in Figure 3 visually verifies the effective calibration capability of this embodiment for the nonlinear error introduced by capacitance mismatch, consistent with the positive calibration method used in this embodiment. Signals and negative The signal perturbation and the least mean square algorithm iteratively achieve a calibration mechanism where the weighted difference approaches zero, and this is consistent with the weight convergence step size in the example. Set as , Set as The parameter settings are matched to ensure that the time-domain interleaved SAR ADC meets the design requirements in high-speed and high-precision scenarios.

[0097] Example 3

[0098] Based on the same inventive concept as other embodiments, this embodiment describes a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the steps of the methods of Embodiment 1 or 2 described above.

[0099] Example 4

[0100] Based on the same inventive concept as other embodiments, this embodiment introduces a computer program product, including computer instructions that, when executed by a processor, implement the steps of the methods described in Embodiment 1 or 2 above.

[0101] In summary, this invention, through a digital calibration module, applies positive and negative Dither perturbation signals and iteratively updates the weight estimates using the least mean square algorithm. This makes the weighted difference between the outputs of the first and second analog-to-digital conversion branches approach zero under the influence of the Dither perturbation signal, effectively calibrating the nonlinear error introduced by capacitor mismatch. This significantly improves the dynamic performance of the time-domain interleaved SAR ADC system, ensuring that the ADC meets design requirements in high-speed, high-precision scenarios. It also solves the problem of deviation between the actual and expected weights of the SAR ADC caused by the relative mismatch of the capacitor array during the manufacturing process.

[0102] This invention is designed based on a non-binary capacitor array. While ensuring bit conversion accuracy, it effectively reduces the physical size and parasitic capacitance of the capacitor array, reduces the impact of process fluctuations during manufacturing, and, together with the symmetrical injection mechanism of positive and negative Dither perturbation signals, enables the calibration system to more accurately capture capacitor mismatch characteristics during operation, achieving rapid convergence of weight estimates and high-precision calibration.

[0103] This invention is based on the least mean square algorithm. It uses the first digital code and the second digital code to iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch. This makes the weighted difference between the outputs of the first analog-to-digital conversion branch and the second analog-to-digital conversion branch approach zero under the influence of positive and negative Dither perturbation signals. This effectively suppresses the nonlinear error introduced by capacitor mismatch and significantly improves the dynamic performance of the time-domain interleaved SAR ADC.

[0104] This invention achieves independent calibration of the weight deviation of the capacitor arrays of the first and second analog-to-digital conversion branches and dynamic optimization of the Dither injection expectation value by accurately constructing the error signal and iteratively calculating the weight estimate step by step. This avoids the error coupling problem in traditional single-channel calibration methods, ensuring that high linearity output can still be maintained within the manufacturing tolerance range, and meeting the stringent performance requirements of high-speed and high-precision scenarios such as base stations and radar.

[0105] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0109] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A time-domain interleaved SAR ADC capacitance mismatch calibration method, characterized in that, Performed by the digital calibration module, the process includes: acquiring an input signal; alternately sampling and holding the input signal through a time-domain interleaved sampling network, and distributing the samples to a first analog-to-digital conversion branch and a second analog-to-digital conversion branch, respectively; and applying a positive voltage during the conversion of the held signal by the first analog-to-digital conversion branch. Disturbance signal; during the conversion of the holding signal in the second analog-to-digital conversion branch, a negative [signal] is applied. Disturbance signal; acquire the first digital code output by the first analog-to-digital conversion branch and the second digital code output by the second analog-to-digital conversion branch; based on the least mean square algorithm, use the first digital code and the second digital code to iteratively update the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch, so that the weight estimates of the capacitor arrays in the first analog-to-digital conversion branch and the second analog-to-digital conversion branch are obtained. Under the influence of the disturbance signal, the weighted difference of the output approaches zero, and the weight estimates of the capacitor arrays in the first and second analog-to-digital conversion branches are output to calibrate the nonlinear error introduced by capacitor mismatch; wherein, both the first and second analog-to-digital conversion branches include capacitor arrays using non-binary capacitor arrays. A bit successive approximation analog-to-digital converter, used for time-domain interleaved sampling and quantization of input signals.

2. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 1, characterized in that, The unit capacitance value of the non-binary capacitor array is Among them, for An analog-to-digital converter with bit-level conversion accuracy, wherein the total capacitance of the non-binary capacitor array is less than or equal to 1. 。 3. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 1, characterized in that, The positive Disturbance signal and negative The expected values ​​of the injected perturbation signals are equal in magnitude, and the expected values ​​of the injected signals are based on the... The theoretical voltage value corresponding to the least significant bit of a unit in a successive approximation analog-to-digital converter is set.

4. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 2, characterized in that, Using the first digital code and the second digital code, iteratively update the weight estimates of the capacitor arrays in the first and second analog-to-digital conversion branches, including: calculating the error signal of the current iteration period; updating the weight estimate of the first analog-to-digital conversion branch according to the error signal, the first digital code, and the first iteration step size; updating the weight estimate of the second analog-to-digital conversion branch according to the error signal, the second digital code, and the first iteration step size; and updating the weight estimate of the capacitor arrays in the first and second analog-to-digital conversion branches according to the error signal and the second iteration step size. Expected value of the injected disturbance signal 。 5. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 4, characterized in that, The error signal is represented as: In the formula, This represents the error signal for the current iteration period. This represents the first reconstructed value obtained by weighted summation of the first digit code based on the current weight estimates. This represents the second reconstructed value obtained by weighted summation of the second digit code based on the current weight estimates. Indicates the current iteration cycle Expected value of the injected disturbance signal.

6. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 5, characterized in that, The first reconstructed value, obtained by weighted summation of the first digit code based on the current weight estimates, is expressed as: In the formula, The first digit code represents the first digit code. Bit code value In the first analog-to-digital conversion branch, the first... The current weight estimate of the bit capacitance.

7. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 6, characterized in that, The first analog-to-digital conversion branch The current weighted estimate of the bit capacitance is expressed as: In the formula, Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the iteration, the first analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first iteration step size. The Error signal after the next iteration.

8. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 7, characterized in that, The second reconstructed value, obtained by weighted summation of the second digital code based on the current weight estimates, is expressed as: In the formula, The second digit code represents the first digit. Bit code value Indicates the second analog-to-digital conversion branch. The current weight estimate of the bit capacitance.

9. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 8, characterized in that, The second analog-to-digital conversion branch The current weighted estimate of the bit capacitance is expressed as: In the formula, Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the capacitance value. Indicates the first After the second iteration, the second analog-to-digital conversion branch... Weighted estimates of the bit capacitance.

10. The time-domain interleaved SAR ADC capacitance mismatch calibration method according to claim 9, characterized in that, The The expected value of the injected disturbance signal is expressed as: In the formula, Indicates the first After the next iteration The expected value of the injected disturbance signal. Indicates the first After the next iteration The expected value of the injected disturbance signal. This indicates the step size of the second iteration.

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