A digitally controlled bandgap reference circuit

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a band gap reference circuit controlled by a digital control module. The application adopts a relatively simple digital control module, controls the state of the band gap reference through PDN and PDP signals generated by the digital control module, controls the power-on and power-off of the band gap reference, reduces static power consumption, reduces the number of physical circuit components, greatly simplifies the working state control process of the whole BGR, and significantly reduces the design and maintenance cost of the circuit. The application guarantees the rapid and stable start of the circuit, simplifies the design, and reduces the power consumption. The application avoids the problems caused by the introduction of complex control logic and multiple circuit components for realizing the stable work of the traditional analog circuit design, reduces the physical size of the circuit, and reduces the design difficulty and cost.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically a bandgap reference circuit controlled by a digital control module. Background Technology

[0002] In the design and implementation of modern analog integrated circuits, ensuring that each circuit module operates within its optimal operating region is crucial. This necessitates the introduction of appropriate voltage or current biases to adjust and optimize the circuit's operation. Bandgap reference circuits play a central role in this process, providing the circuit system with an accurate and stable reference voltage or current, unaffected by external conditions such as temperature, power supply voltage variations, and manufacturing process differences.

[0003] Traditional bandgap reference circuits are mainly divided into two categories: voltage-mode and current-mode. Voltage-mode bandgap references achieve this by superimposing voltages with different temperature coefficients, while current-mode bandgap references achieve this by superimposing currents with different temperature coefficients. A common challenge they face is the dependence between voltage and current during startup. Specifically, during circuit startup, whether voltage is needed first to activate current, or current is needed first to generate voltage, is crucial for the circuit's rapid and stable startup.

[0004] To address this issue, the design of the startup circuit becomes particularly crucial. Traditional analog circuit design often requires complex control logic and multiple circuit components to achieve stable operation. This not only increases the physical size of the circuit but also raises the design difficulty and cost. Therefore, traditional startup circuit designs are often complex, making it difficult to achieve both fast and stable startup while simultaneously simplifying the design and reducing power consumption. Summary of the Invention

[0005] To address the aforementioned problems and shortcomings, and to resolve the issues that existing bandgap reference circuits have complex startup circuits and struggle to simultaneously achieve fast, stable, and high-power startup, this invention provides a bandgap reference circuit controlled by a digital control module. This solution utilizes a relatively simple digital control module to control the startup circuit, thus resolving the current issues.

[0006] The technical solution of the present invention is as follows:

[0007] A bandgap reference circuit controlled by a digital control module consists of four parts: a startup circuit, an operational amplifier (including a bias circuit), a voltage generation module, and a digital control module.

[0008] The startup circuit includes five PMOS transistors M1, M2, M3, M4 and M6, and three NMOS transistors M5, M7 and M8.

[0009] M1, M2, and M3 are all connected with their gate and drain shorted, forming a diode connection. The drain of M1 is connected to the source of M2, and the source of M1 is connected to a voltage source. The drain of M2 is connected to the source of M3, and the drain of M3 is connected to the source of M4.

[0010] The drain of M4 is connected to the drain of M5 and the gate of M8. The gate of M4 is connected to the gate of M5 and connected to the output signal V. OUT M4 and M5 form an inverter. The drain of M8 is connected to the source of M7, and the source of M8 is grounded. The drains of M6 and M7 are connected together. The gates of M6 and M7 are both connected to the inverted signal PDN of the digital control module input PD. The source of M6 is connected to a voltage source. M6 and M7 form an inverter.

[0011] Since M1, M2, and M3 are connected in the form of diodes with their gates and drains shorted, the diode connection can be equivalent to a small resistor, thus playing a role in reducing voltage in the startup circuit. At the same time, NMOS transistor M5 and PMOS transistor M4 form an inverter, and NMOS transistor M7 and PMOS transistor M6 also form an inverter. Then, the startup circuit is controlled by the reverse signal PDN of PD input through the digital control module to start up automatically.

[0012] The operational amplifier is a folded Cascode, including PMOS transistors M12, M13, M14, M16 and M18, and NMOS transistors M15, M17, M19 and M20, and has a bias circuit.

[0013] Among them, the differential input pair transistors are M13 and M14. The sources of M13 and M14 are directly connected, and the gates of M13 and M14 are respectively connected to the differential input. M12 is a pseudo current source. The drain of M12 is connected to the source of M13 and M14, and the source of M12 is connected to a voltage source. The drain of M13 is connected to the drain of M15 and the source of M17. The drain of M17 is connected to the drain of M16. The drain of M14 is connected to the drain of M20.

[0014] The gate and drain of M16 are shorted together and connected to the gate of M18 to form a current mirror; the drain of M18 is connected to the drain of M19, and the source of M19 is connected to the drain of M20.

[0015] The bias circuit consists of a PMOS transistor M9, and two NMOS transistors M11 and M10 connected in a diode configuration. The drain of M9 is connected to the drain of M10, and the source of M9 is connected to the voltage source and the source of M12. The source of M10 is connected to the drain of M11, and the gate of M10 is connected to the gate of M17. The source of M11 is grounded, and the gate of M11 is connected to the gate of M15.

[0016] During operation, current is generated in M9, M10 and M11, which provides bias current to the two branches containing M15, M16, M17 and M18, M19 and M20 through mirroring. This allows the operational amplifier to operate under deep negative feedback, clamping the op-amp inputs INN and INP; and at the same time, it avoids entering the bias degeneracy point, i.e., the state where the current is 0.

[0017] The voltage generation module includes three PMOS transistors M21, M22 and M24, an NMOS transistor M23, resistors R1, R2 and R3, BJT transistors Q1 and Q2, and a Miller capacitor C1.

[0018] The gate of M21 is connected to the gate of M22. The drain of M21 is connected to one end of resistor R1 and one end of Miller capacitor C1. The drain of M22 is connected to one end of resistor R2, the other end of Miller capacitor C1, and the drain of M23. INP and INN are the two inputs of the operational amplifier. INN is connected to the other end of resistor R2 and one end of R3. The other end of R3 is connected to the emitter of BJT transistor Q2, which is connected to a diode. INP is connected to the other end of resistor R1 and the emitter of BJT transistor Q1, which is connected to a diode. The bases and collectors of Q1 and Q2 are shorted, and their collectors are connected to each other. M23 acts as a switching transistor, and its drain is connected to V. OUT The source of M24 is grounded, and its gate is connected to the output PDP of the digital control module. The source of M24 is connected to a current source, and the gate of M24 is connected to the drains of M6 and M7, as well as the gates of M9, M12, M21, and M22. The drain of M24 serves as an output terminal, providing an It. PTAT Current (IB).

[0019] The voltage generation module utilizes an operational amplifier operating under deep negative feedback conditions, where the potentials at points INN and INP are equal, generating a current across R3, which is then mirrored to M24 to form a mirror current I. PTAT This also generates an output voltage V across R1 and R2. OUT M23 is used as a switching transistor, with its drain connected to V. OUT The source is grounded, and the gate is connected to the output PDP of the digital control module. A Miller capacitor C1 is added simultaneously to separate the primary and secondary poles. This increases the relative margin and circuit stability.

[0020] The digital control module includes two PMOS transistors M25 and M27, and two NMOS transistors M26 and M28. The drain of M25 is connected to the drain of M26, the drain of M27 is connected to the drain of M28, the sources of M25 and M27 are connected to a voltage source, and the sources of M26 and M28 are grounded. The input signal PD is connected to the gates of M25 and M26, and the drains of M25 and M26 are connected to the gates of M27 and M28. M25 and M26 form a first-stage inverter, and M27 and M28 form a second-stage inverter, forming an inverter chain.

[0021] The input signal PD is converted into two signals PDN and PDP through an inverter chain; the drains of M25 and M26 serve as the output signal PDN of the first-stage inverter, and the PDN signal controls the state of M6 and M7; the drains of M27 and M28 serve as the output signal PDP of the second-stage inverter, and PDP controls the state of M23, thereby achieving digital control output V. OUT The purpose.

[0022] Furthermore, the aspect ratio of M23 is at least four times that of M1, M2, and M3, such that the branch containing M23 is equivalent to a wire directly connected to GND; and M22 and M24 have the same gate-source voltage V. GS And the same width and length.

[0023] Furthermore, the ratio of the number of BJT transistors Q1 and Q2, and the resistance ratio of resistors R2 and R3, make V OUT It is unrelated to temperature.

[0024] In summary, this invention employs a relatively simple digital control module, reducing the number of physical circuit components and thus greatly simplifying the entire bandgap reference circuit (BGR) operation control process. This simplified control process significantly reduces circuit design and maintenance costs, ensuring fast and stable circuit startup while achieving simplified design and reduced power consumption. It avoids the problems caused by introducing complex control logic and multiple circuit components in traditional analog circuit design to achieve stable circuit operation, and also reduces the physical size of the circuit, lowering design difficulty and cost. Attached Figure Description

[0025] Figure 1 This is a circuit structure diagram of the present invention;

[0026] Figure 2 This is a circuit diagram of the digital control module of the present invention. Detailed Implementation

[0027] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0028] A bandgap reference circuit controlled by a digital control module, such as Figure 1 and Figure 2 As shown.

[0029] Because the various modules of the bandgap reference circuit are closely interconnected, and the operating state of each module has a significant impact on the operating state of the bandgap reference circuit, a comprehensive and detailed explanation is provided below:

[0030] When the input signal PD is high (PD=1), PDP=1, and the gate of NMOS transistor M23 is high, so M23 is turned on. In this embodiment, M23 is a MOS transistor with a width-to-length ratio of 20, compared to M1, M2, and M3 which have a width-to-length ratio of 5. Since M23 has a larger width-to-length ratio, its on-resistance is very small. Therefore, the branch containing M23 can be considered equivalent to a wire directly connected to GND, so V... OUT =0; Without considering the noise and other parasitic parameters of GND, GND is at a low level, GND=0, V OUT =0, the entire bandgap reference is not working.

[0031] When the input signal PD = 0, PDP = 0, the gate voltage of NMOS transistor M23 is low, and the on-resistance of M23 is very high. The branch containing M23 can almost be considered an open circuit, so M23 is not conducting at this time. When PD = 0, the circuit response requires a certain amount of time, so V at this time... OUT =0, PMOS transistor M4 is turned on. PMOS transistors M1, M2, and M3 connected by diodes act as step-down transistors, each diode-connected PMOS transistor reducing the voltage by one V. TH The voltage value, where V TH The threshold voltage of the PMOS transistor (using SMIC 180nmrf technology in this embodiment) is 0.4mV, and the power supply voltage is 3.3V. Therefore, the gate voltage of M18 is VCC-3V. TH When the signal is high, PMOS transistor M18 is turned on, and PDN = 1, NMOS transistor M7 is turned on, resulting in current flowing through the M7 and M8 branches. This creates a voltage drop V at M7. DS Since the drain of M7 is connected to the gate of M9, the gate voltage on M9 will turn on M9, and the diodes connected to M10 and M11 will also turn on. Then, through mirroring, M15-M20 can work normally, and thus the op-amp can work normally.

[0032] When the op-amp operates normally under deep negative feedback conditions, the ratio of Q1 to Q2 is 1:n. This can be obtained through virtual short and virtual open circuits.

[0033] Where V BE This is the difference between the base and emitter voltages of the BJT. Since M22 and M24 have the same gate-source voltage V... GS With the same width-to-length ratio, the same PTAT current can be obtained on M24 as that flowing through M22. Further adjustments The resistance ratio is 4, and n is set to 31, so that...

[0034]

[0035] A temperature-independent voltage value can be obtained. Simulation shows that at a normal temperature of 27 degrees Celsius, a high-level voltage value of 1.2V is obtained, at which point the BGR bandgap reference works normally.

[0036] As can be seen from the above embodiments, this invention employs a relatively simple digital control module. The digital control module generates PDN and PDP signals to control the state of the bandgap reference, i.e., it controls the power-on and power-off of the bandgap reference. This reduces static power consumption and the number of physical circuit components, thereby greatly simplifying the entire BGR's operating state control process and significantly reducing circuit design and maintenance costs. This invention achieves simplified design and reduced power consumption while ensuring fast and stable circuit startup. It avoids the problems caused by introducing complex control logic and multiple circuit components in traditional analog circuit design to achieve stable circuit operation, and also reduces the physical size of the circuit, thus lowering the design difficulty and cost.

Claims

1. A bandgap reference circuit controlled by a digital control module, characterized in that: It consists of four parts: a startup circuit, an operational amplifier, a voltage generation module, and a digital control module. The startup circuit includes five PMOS transistors M1, M2, M3, M4 and M6, and three NMOS transistors M5, M7 and M8; M1, M2, and M3 are all connected with their gate and drain shorted, forming a diode connection; the drain of M1 is connected to the source of M2, and the source of M1 is connected to a voltage source; the drain of M2 is connected to the source of M3, and the drain of M3 is connected to the source of M4. The drain of M4 is connected to the drain of M5 and the gate of M8. The gate of M4 is connected to the gate of M5 and connected to the output signal V. OUT M4 and M5 form an inverter; the drain of M8 is connected to the source of M7, and the source of M8 is grounded; the drain of M6 is connected to the drain of M7, and the gates of M6 and M7 are both connected to the inverted signal PDN of the digital control module input signal PD. The source of M6 is connected to a voltage source, and M6 and M7 form an inverter. The startup circuit is controlled by the inverse signal PDN of the input signal PD from the digital control module to perform self-starting. The operational amplifier is a folded CASCODE, including PMOS transistors M12, M13, M14, M16 and M18, and NMOS transistors M15, M17, M19 and M20, and has a bias circuit. Among them, the differential input pair transistors are M13 and M14. The sources of M13 and M14 are directly connected, and the gates of M13 and M14 are connected to the two inputs INN and INP of the operational amplifier, respectively. M12 is a pseudo current source. The drain of M12 is connected to the source of M13 and M14, and the source of M12 is connected to a voltage source. The drain of M13 is connected to the drain of M15 and the source of M17. The drain of M17 is connected to the drain of M16. The drain of M14 is connected to the drain of M20. The gate and drain of M16 are shorted together and connected to the gate of M18 to form a current mirror; the drain of M18 is connected to the drain of M19, and the source of M19 is connected to the drain of M20. The bias circuit consists of a PMOS transistor M9, and two NMOS transistors M11 and M10 connected in diode configuration. The drain of M9 is connected to the drain of M10, and the source of M9 is connected to the voltage source and the source of M12. The source of M10 is connected to the drain of M11, and the gate of M10 is connected to the gate of M17. The source of M11 is grounded, and the gate of M11 is connected to the gate of M15. During operation, current is generated in M9, M10 and M11, which provides bias current to the two branches containing M15, M16, M17 and M18, M19 and M20 through mirroring. This allows the operational amplifier to operate under deep negative feedback, clamping the two inputs INN and INP of the operational amplifier and preventing it from entering the bias degeneracy point, i.e., the state where the current is 0. The voltage generation module includes three PMOS transistors M21, M22 and M24, an NMOS transistor M23, resistors R1, R2 and R3, BJT transistors Q1 and Q2, and a Miller capacitor C1. The gate of M21 is connected to the gate of M22. The drain of M21 is connected to one end of resistor R1 and one end of Miller capacitor C1. The drain of M22 is connected to one end of resistor R2, the other end of Miller capacitor C1, and the drain of M23. INP and INN are the two inputs of the operational amplifier. INN is connected to the other end of resistor R2 and one end of R3. The other end of R3 is connected to the emitter of BJT transistor Q2, which is connected to a diode. INP is connected to the other end of resistor R1 and the emitter of BJT transistor Q1, which is connected to a diode. The bases and collectors of Q1 and Q2 are shorted together, and their collectors are connected to each other. M23 is used as a switching transistor, and its drain is connected to V. OUT The source of M24 is grounded, and its gate is connected to the output signal PDP of the digital control module. The source of M24 is connected to a voltage source, and the gate of M24 is connected to the drains of M6 and M7, as well as the gates of M9, M12, M21, and M22. The drain of M24 serves as an output terminal, providing an It signal. PTAT Current; The voltage generation module utilizes an operational amplifier operating under deep negative feedback conditions, where the potentials at points INN and INP are equal, generating a current across R3, which is then mirrored to M24 to form a mirror current I. PTAT It also generates an output signal V on R2 and R3. OUT M23 is used as a switching transistor, with its drain connected to V. OUT The source is grounded, and the gate is connected to the output signal PDP of the digital control module. At the same time, Miller capacitor C1 is added to separate the primary and secondary poles. The digital control module includes two PMOS transistors M25 and M27, and two NMOS transistors M26 and M28; the drain of M25 is connected to the drain of M26, the drain of M27 is connected to the drain of M28, the sources of M25 and M27 are connected to a voltage source, and the sources of M26 and M28 are grounded; the input signal PD is connected to the gates of M25 and M26, the drains of M25 and M26 are connected to the gates of M27 and M28, M25 and M26 form a first-stage inverter, and M27 and M28 form a second-stage inverter, forming an inverter chain; The input signal PD is converted into two signals PDN and PDP through an inverter chain; the drains of M25 and M26 serve as the output signal PDN of the first-stage inverter, while PDN controls the state of M6 and M7; the drains of M27 and M28 serve as the output signal PDP of the second-stage inverter, and PDP controls the state of M23, thereby achieving the digital control output signal V. OUT The purpose.

2. The bandgap reference circuit controlled by the digital control module as described in claim 1, characterized in that: The aspect ratio of M23 is at least four times that of M1, M2, and M3, such that the branch containing M23 is equivalent to a conductor directly connected to ground; and M22 and M24 have the same gate-source voltage V. GS And the same width-to-length ratio.

3. The bandgap reference circuit controlled by the digital control module as described in claim 1, characterized in that: The ratio of the number of BJT transistors Q1 and Q2, and the resistance ratio of resistors R2 and R3, make V OUT It is unrelated to temperature.

Images