Array signal processing method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of communication, in particular to an array signal processing method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining C paths of array signals, and carrying out the parallel frequency domain transformation of the C paths of array signals, and obtaining C paths of spectrum data; selecting signals of X target frequency points from the C paths of spectrum data to execute parallel autocorrelation matrix calculation so as to obtain autocorrelation matrixes corresponding to the X target frequency points respectively; performing matrix decomposition on the autocorrelation matrix to obtain a decomposed matrix; on the basis of the decomposed matrix, performing forward and backward iterative solution to obtain a solution vector; wherein at least two operations of parallel frequency domain transformation, autocorrelation matrix calculation, matrix decomposition and forward and backward iterative solution are executed in a pipeline parallel mode. Therefore, through a column parallel storage structure, pipeline matrix decomposition, forward and backward iterative solution and module-level parallel design, the hardware acceleration capability of large-scale complex matrix equation solution is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an array signal processing method, apparatus, electronic device and storage medium. Background Technology

[0002] Thanks to advancements in communication technology, satellite navigation and communication have become crucial components of modern communication systems. High-density satellite deployment enables real-time communication and navigation across vast areas of the Earth's surface. However, with the development of communication bands, the modern electromagnetic environment has become increasingly complex, often exhibiting significant random and active interference in communication links, impacting the actual performance of satellite navigation and communication products. Against this backdrop, anti-interference algorithms based on array signal processing have been extensively studied.

[0003] Anti-interference algorithms can be categorized into three main types: spatial domain anti-interference, space-time anti-interference, and space-frequency anti-interference. Spatial domain anti-interference utilizes the spatial difference information of the received signals from the array to generate nulls through weighted summation, effectively suppressing incoming signals from different directions. However, this method cannot process the signal spectrum, resulting in poor performance in broadband anti-interference scenarios. Space-time and space-frequency anti-interference, on the other hand, can significantly improve the broadband anti-interference performance of the algorithms. Space-time anti-interference directly implements an equivalent time-delay filter through tap delays in the time domain, thereby controlling the signal spectrum. However, as the number of taps increases, the dimension of the matrix that the algorithm needs to process increases quadratically, significantly increasing hardware overhead. To reduce hardware resource usage, space-frequency anti-interference divides the signal into sub-bands using Fourier transforms, directly addressing the interference on the spectral signal. This approach ensures controllable hardware resources while improving broadband anti-interference levels.

[0004] However, space-frequency anti-interference algorithms typically require a large number of sampling points to achieve sufficient beat length and spectral resolution for spectral signal storage, which leads to a significant increase in algorithm latency in real-world scenarios. Summary of the Invention

[0005] This application provides an array signal processing method, apparatus, electronic device, and storage medium, which can solve at least one of the technical problems in the background art to a certain extent.

[0006] To achieve the above objectives, this application adopts the following technical solution: Firstly, an array signal processing method is provided, including: Acquire C-channel array signals, perform parallel frequency domain transformation on the C-channel array signals, and obtain C-channel spectrum data; The signals of X target frequency points are selected from the C-channel spectrum data and their autocorrelation matrices are calculated in parallel to obtain the autocorrelation matrices corresponding to each of the X target frequency points. Perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix; Based on the decomposed matrix, perform forward and backward iterations to obtain the solution vector; Among them, at least two of the operations in the parallel frequency domain transformation, the autocorrelation matrix calculation, the matrix decomposition, and the forward and backward iterative solution are executed in a pipelined parallel manner.

[0007] Secondly, an array signal processing device is provided, comprising: The frequency domain transformation module is used to acquire C-channel array signals, perform parallel frequency domain transformation on the C-channel array signals, and obtain C-channel spectrum data. The autocorrelation calculation module is used to select X target frequency points from the C-channel spectrum data and perform parallel autocorrelation matrix calculations to obtain the autocorrelation matrix corresponding to each of the X target frequency points. The matrix decomposition module is used to perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix. The iterative solution module is used to perform forward and backward iterative solutions based on the decomposed matrix to obtain the solution vector; The pipeline scheduling module is used to control at least two of the frequency domain transformation module, the autocorrelation calculation module, the matrix decomposition module, and the iterative solution module to perform operations in a pipelined parallel manner.

[0008] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the array signal processing method as described in any one of the first aspects above.

[0009] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the array signal processing method as described in any one of the first aspects above.

[0010] Fifthly, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to execute the array signal processing method described in any of the first aspects above.

[0011] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0012] In this embodiment, C-channel array signals are first acquired, and a parallel frequency domain transformation is performed on the C-channel array signals to obtain C-channel spectrum data. X target frequency points are selected from the C-channel spectrum data, and parallel autocorrelation matrix calculations are performed to obtain the autocorrelation matrices corresponding to each of the X target frequency points. Matrix decomposition is performed on the autocorrelation matrices to obtain the decomposed matrices. Based on the decomposed matrices, forward and backward iterative solutions are performed to obtain the solution vector. At least two of the operations—parallel frequency domain transformation, autocorrelation matrix calculation, matrix decomposition, and forward and backward iterative solutions—are executed in a pipelined parallel manner. Therefore, through column-parallel storage structure, pipelined matrix decomposition, forward and backward iterative solutions, and module-level parallel design, the hardware acceleration capability for solving large-scale complex matrix equations is significantly improved, making it suitable for scenarios requiring high-dimensional matrix operations, such as signal processing, wireless communication, and artificial intelligence.

[0013] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0014] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic flowchart of the array signal processing method provided in the embodiments of this application; Figure 2 This is a flowchart illustrating the array signal spectrum autocorrelation matrix module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the Koleski decomposition module provided in an embodiment of this application; Figure 4 This is a schematic diagram of the decomposition of the forward and backward equation iterative solution provided in the embodiments of this application; Figure 5 This is a structural block diagram of the array signal processing device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0015] The embodiments of the technical solutions of this application will now be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of this application, and are therefore merely examples and should not be used to limit the scope of protection of this application. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a specific order. Furthermore, for clarity and conciseness, descriptions of features known in the art may be omitted.

[0016] The embodiments described in the following examples of this disclosure are not representative of all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0017] It should be noted that this invention belongs to the field of hardware acceleration for array anti-interference algorithms and is applicable to scenarios such as satellite navigation and satellite communication. In this context, this invention first accumulates the signal autocorrelation matrix of the target frequency points using Fast Fourier Transform. It then significantly improves the real-time performance and parallelism of solving complex symmetric matrix equations by fine-grained parallelization of the Kolesky decomposition and equation iterative solution modules, and by using a resource-controllable pipeline to expand the core computational logic of both modules. Finally, the process of accumulating the autocorrelation matrix and solving the matrix equations is pipelined to reduce the algorithm latency caused by accumulating a large number of sampling points. The execution subject of the array signal processing method in this embodiment can be an array signal processing device, but this application embodiment does not limit this.

[0018] See Figure 1 This is a flowchart illustrating the array signal processing method provided in the first embodiment of this application. Figure 1 As shown, the array signal processing method may include the following steps: Step 101: Obtain the C-channel array signal, perform parallel frequency domain transformation on the C-channel array signal, and obtain the C-channel spectrum data.

[0019] Here, C-channel array signal refers to C parallel signals synchronously acquired by an array composed of C signal receiving units (such as antenna elements, sensors, etc.), which is the raw input data for array signal processing. C is the number of array signal channels (i.e., the number of receiving units), which is a configurable positive integer, such as 16, and is not limited here.

[0020] Parallel frequency domain transformation refers to a processing method that uses C independent transformation modules to synchronously perform frequency domain transformation operations for C array signals, converting each time-domain array signal into a frequency-domain signal.

[0021] It should be noted that parallel frequency domain transformation can ensure complete synchronization of the transformation timing of the C-channel signals, avoiding signal phase deviation caused by processing delays, and significantly improving the overall transformation efficiency. Specifically, the frequency domain transformation can employ Fast Fourier Transform (FFT), which is not limited here.

[0022] Among them, C-channel spectrum data refers to the corresponding C-channel frequency domain data set obtained after parallel frequency domain transformation of C-channel array signals. Each channel spectrum data contains the frequency components corresponding to the original time-domain signal, as well as the amplitude and phase information of each frequency component, which can reflect the distribution characteristics of the signal in the frequency domain. The C-channel spectrum data corresponds one-to-one with the original C-channel array signals, preserving the spatial and phase correlation between multiple signals.

[0023] Optionally, C array signals can be processed in parallel using C Fast Fourier Transform modules to obtain C spectral data.

[0024] As an example, the value of C in this embodiment is 16, and is not limited here. That is to say, the number of array signals is set to C=16, and 16 array signals are synchronously input to the hardware module. The parallelized 256-point fast Fourier transform is performed by 16 independent fast Fourier transform modules to convert the array signals in the time domain into 16 channels of spectrum data in the frequency domain, thereby realizing the extraction of signal features from the time domain to the frequency domain.

[0025] Step 102: Select X target frequency points from the C-channel spectrum data and perform parallel autocorrelation matrix calculations to obtain the autocorrelation matrix corresponding to each of the X target frequency points.

[0026] Optionally, based on a preset target spectrum range, X target frequency points falling within the target spectrum range can be selected from the full frequency band corresponding to C channel spectrum data. Center frequency vectors of length C corresponding to each of the X target frequency points can be determined. The X center frequency vectors are temporarily cached in registers. Then, through X autocorrelation modules, multiplication and accumulation operations are performed on the X center frequency vectors to obtain the autocorrelation matrix corresponding to each of the X target frequency points.

[0027] Optionally, the entire signal frequency range can be divided into Z consecutive and non-overlapping small frequency intervals, either uniformly or non-uniformly, based on the signal bandwidth. Z is the total number of narrow sub-bands, which is a configurable positive integer. The purpose of dividing the signal into narrow sub-bands is to focus on the target frequency range, reduce interference from irrelevant frequency components, and improve the targeting and efficiency of subsequent signal processing.

[0028] The target spectrum range refers to a pre-defined frequency range that includes the target signal to be analyzed.

[0029] Optionally, X narrow subbands that fall within the target frequency range can be selected from Z narrow subbands, where X is the number of target narrow subbands (X≤Z) and is a configurable positive integer.

[0030] The signal bandwidth refers to the frequency range occupied by the original array signal, that is, the difference between the highest and lowest frequencies of the signal.

[0031] The center frequency refers to the frequency value corresponding to the midpoint of each narrow sub-band frequency range.

[0032] Understandably, the process begins by acquiring the full-band frequency range corresponding to the C-channel spectrum data. This full-band frequency range is then intersected with the preset target spectrum range to filter out frequency points that fall entirely within the target spectrum range. Combined with the narrow subband division results (Z narrow subbands), X target narrow subbands corresponding to the filtered frequency points are determined. Finally, the center frequency of each target narrow subband is used as the X target frequency points.

[0033] Then, the C-row, F-column signal matrix obtained by a single F-point Fast Fourier Transform can be used as a frame of signal. For each target frequency, the column data corresponding to that target frequency in the C-channel spectrum data can be extracted. Since each column in the C-row, F-column signal matrix corresponds to the data of the C-channel array signal at the same frequency, the extracted column data forms a vector of dimension C. This vector is the center frequency vector corresponding to the target frequency, denoted as […]. .

[0034] Furthermore, the parallel write channel of the register group is activated to synchronously write X center frequency vectors into the preset register space, with each vector occupying an independent register storage area.

[0035] Then, X independent autocorrelation modules are activated. Each autocorrelation module obtains the corresponding center frequency vector through the register read interface, thereby realizing the parallel data distribution of X vectors.

[0036] Within each autocorrelation module, the formula is used. Perform a multiply-accumulate operation.

[0037] in, The center frequency vector, for The conjugate transpose, first for and Element-wise multiplication is performed, and the results are then summed element-wise to obtain the initial autocorrelation matrix elements. Next, the initial autocorrelation matrix calculated for the current frame is summed and updated with the autocorrelation matrix of the corresponding target frequency point from the previous frame. This involves summing the corresponding elements of the two matrices and overwriting the original elements with the sum, thus accumulating correlation information across multiple frames. This process continues until all X autocorrelation modules in the current frame have completed multiplication, summation, and update, at which point the corresponding C-row, C-column autocorrelation matrices for each of the X target frequency points are synchronously output.

[0038] Optionally, the center frequency vectors of the three target narrow subbands can be cached using registers. After caching, the computation process is triggered without delay, simultaneously using three independent autocorrelation modules to perform parallel multiplication and accumulation operations on the spectral data of the three target frequencies, thus completing the parallel solution of the autocorrelation matrices for the three frequencies. During the calculation of the autocorrelation matrix, after each set of vector multiplication operations, the corresponding matrix element is read from the autocorrelation matrix storage RAM, and this matrix element is accumulated with the result of the current vector multiplication operation. After the accumulation is completed, the new matrix element value is immediately written back to its original position in the autocorrelation matrix storage RAM. This operation logic can ensure the continuity and accuracy of the autocorrelation matrix values ​​and adapt to the cumulative calculation requirements of multi-frame data. After all 256 frames of spectral signals have undergone autocorrelation operations, the obtained autocorrelation matrices of the three target frequencies are further cached in the cache RAM.

[0039] Figure 2 The process of spectrum processing and autocorrelation matrix buffering for C-channel array signals is demonstrated: the C-channel array signals are distributed to multiple Fast Fourier Transform (FFT) modules, and the time-domain signals are converted into frequency-domain signals through FFT, outputting the C-channel spectrum.

[0040] The C-channel spectrum enters the "X Target Narrowband Subband Frequency Point Selection Register" module, where X target narrowband frequency points are selected, focusing the spectrum signal onto the frequency band to be analyzed. The signal in each target frequency band will pass through: Spectrum vector autocorrelation: Calculates the autocorrelation characteristics of the signal in this frequency band; Autocorrelation matrix storage RAM: Temporarily stores the calculated autocorrelation matrix; Autocorrelation matrix cache storage RAM: The autocorrelation matrix is ​​cached.

[0041] Step 103: Perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix.

[0042] Optionally, a pipelined structure is adopted to perform Koleski decomposition on the autocorrelation matrix, sequentially completing the transformation of the main diagonal elements, updating the off-diagonal elements, and performing calculations to obtain the lower triangular matrix.

[0043] In this process, a lower triangular decomposition is performed on each autocorrelation matrix.

[0044]

[0045] Here, L is the lower triangular element matrix. Solve... The iterative formula for each element of the matrix is ​​as follows:

[0046]

[0047] in, for The first of the matrix Line number Column elements, Let the autocorrelation matrix to be decomposed be the first... Line number Column elements.

[0048] The implementation methods of the pipeline structure include: Through K pipeline scheduling, M operation units are reused to complete the cumulative calculation of matrix elements; the operation unit includes a multiply-accumulate unit.

[0049] It should be noted that the iterative solution is performed in the following order: a column of matrix coefficients is read in parallel, and the square root of the coefficients of the main diagonal elements of the matrix coefficients is obtained. The algorithm updates the matrix by subtracting the off-diagonal elements from the accumulated result of matrix L, and then divides the updated elements to obtain the final matrix elements. The accumulated result of matrix L is 0 for the first column, and for the elements in the second column and beyond, it is accumulated by multiplying and adding the inner product of the off-diagonal elements of matrix L to the accumulated elements at the corresponding indices. To ensure controllable hardware resources and optimal overall algorithm efficiency, subtraction and division operations are implemented using a pipelined subtractor and divider, respectively. This addresses the significant computational overhead... The matrix element accumulation operation is implemented by pipelined K times using M multiply-accumulate units.

[0050] In other words, the autocorrelation matrices of the X target frequency points are input into the matrix decomposition module in frequency order. The matrix decomposition module uses the Kolesky decomposition algorithm to decompose the autocorrelation matrix R(f) into the product of the lower triangular matrix L and its conjugate transpose L. To improve decomposition efficiency, the matrix decomposition module adopts a pipelined structure design. The entire decomposition process is executed sequentially in the order of "column iteration reading, main diagonal element transformation, off-diagonal element update, and off-diagonal element operation processing". Each step is continuously and uninterruptedly operated through pipeline timing scheduling.

[0051] In the decomposition process, the cumulative calculation of matrix elements and the cumulative terms for off-diagonal element calculations are implemented using a "K-time pipeline scheduling, reusing M operation units" approach. The operation units selected are multiply-accumulate units (MACs). Through K-time scheduling, the M MACs are cyclically reused to complete the multiply-accumulate operations for all cumulative terms. This eliminates the need to configure a separate MAC for each cumulative calculation step, effectively controlling hardware resource usage while ensuring computational efficiency.

[0052] Specifically, the autocorrelation matrix can be read column by column in parallel, starting from column 1, then column 2, ..., then column C. The C elements are temporarily stored in the pipeline buffer. For the diagonal elements of the current column (elements in row i and column i), a transformation operation is performed: first, the cumulative term is calculated; then, the corresponding diagonal element in the autocorrelation matrix is ​​subtracted from the cumulative term; finally, a square root operation is performed to obtain the diagonal elements of the lower triangular matrix L. For the off-diagonal elements of the current column (elements where i > j), the cumulative term is calculated first, then subtracted from the corresponding off-diagonal element in the autocorrelation matrix to update the elements. The updated off-diagonal elements are then divided by the diagonal element l of the current column to obtain the off-diagonal element l of the lower triangular matrix L. After processing all columns, the complete lower triangular matrix L (i.e., the decomposed matrix) is output.

[0053] like Figure 3 As shown, the column data of the autocorrelation matrix is ​​read column-by-column in parallel from the "Autocorrelation Matrix Cache Storage RAM" and enters the subsequent processing stage. The read column data first passes through the "Subtraction Update" unit to calculate the difference between the off-diagonal elements and the cumulative result of the L matrix. The main diagonal elements enter the "Root of Diagonal" unit to perform a square root operation on the main diagonal elements; the off-diagonal elements enter the "Division of Off-Diagonal" unit. The calculated L matrix elements are first processed through "Vector Cross Product" to generate the intermediate result required for accumulation, and then the accumulation operation is completed through "Parallel Addition". The final lower triangular matrix elements are stored in the "Lower Triangular Matrix Storage RAM" in a column-by-column parallel writing manner. At the same time, the column data of this RAM is also read out in parallel and fed back to the "Subtraction Update" stage for subsequent column accumulation calculations.

[0054] Step 104: Based on the decomposed matrix, perform forward and backward iterative solutions to obtain the solution vector.

[0055] Among them, at least two of the operations in parallel frequency domain transformation, autocorrelation matrix calculation, matrix decomposition, and forward and backward iterative solution are executed in a pipelined parallel manner.

[0056] Optionally, forward iteration can be performed based on the decomposed matrix to obtain an intermediate vector, and backward iteration can be performed based on the intermediate vector to obtain the solution vector. The forward and backward iterations can be implemented by reusing Q multiply-accumulate units through F pipeline scheduling to complete the multiply-accumulate calculations.

[0057] Specifically, the final solution vector can be obtained through two steps: forward iteration and backward iteration. Both forward and backward iterations employ pipelined reuse of multiply-accumulate units to improve efficiency. The specific implementation is as follows: The target matrix equation (Where R is the autocorrelation matrix, b is the known steering vector, and y is the weight solution vector to be solved) This is decomposed into the forward iterative equation LT=b and the backward iterative equation (where T is the intermediate vector,) (where L is the conjugate transpose matrix). The equation can be solved by a single forward iteration. get Then solve the equation through a backward iteration. get .

[0058] The forward iterative solution process of the equation can be described by the following formula:

[0059] The backward iterative solution process of the equation can be described by the following formula:

[0060] It should be noted that the coefficient matrices of the forward and backward iteration equations are respectively composed of lower triangular matrices. and upper triangular matrix The structure is as follows: After obtaining the coefficient matrices of the forward and backward iterative equations through Koleski decomposition, first, according to the forward iterative formula, ... to The intermediate vector T is calculated sequentially. When calculating t1, it is directly calculated using t1 = b1 / l. 11 (l) 11 The first element of the first row and first column of L is used to obtain t. When calculating t (m=2,3,…,C), the first element b of the known vector b is updated by subtraction (i.e., b is subtracted from the sum of the products of the previously calculated t~t and the corresponding elements of the L matrix), and then the updated b is divided by the diagonal element l of the first row and first column of L to obtain t.

[0061] like Figure 4 As shown, data is input into the module from the "cache RAM / transposed RAM" in a "column-parallel read" manner. The input data first enters the "subtraction update" unit to complete the difference calculation. The processed data then enters the "division solution element" unit to obtain the solution vector for the current iteration. This solution element is divided into two paths: one path is output as the "current solution element," and the other path is processed by "parallel multiplication + parallel addition" to complete the multiplication and accumulation operation, while simultaneously being fed back to the "subtraction update" unit as the "current update element" for the next iteration. Finally, the continuously output solution elements constitute the complete solution vector.

[0062] Optionally, by using F time-series scheduling, Q multiply-accumulate units can cyclically complete the product and calculation of all iteration steps, eliminating the need to configure a separate multiply-accumulate unit for each iteration step. This reduces hardware resource consumption while ensuring the accuracy of the iterative solution. Here, F can be a natural number from 1 to 16, Q can be a natural number from 1 to 16, and F*Q=C.

[0063] Optional, pipelined parallel execution includes: While performing parallel frequency domain transformation, the autocorrelation matrix is ​​calculated in parallel, and matrix decomposition and forward and backward iterative solutions are performed on the autocorrelation matrix.

[0064] To further reduce overall processing latency, this invention adopts a multi-step pipelined parallel execution strategy, specifically implemented as follows: in a programmable logic device, a pipeline scheduling module controls the parallel frequency domain transformation and subsequent autocorrelation matrix calculation, matrix decomposition, and forward and backward iterative solutions to be executed in a pipelined parallel manner.

[0065] Specifically, while initiating the parallel frequency domain transformation of the C-channel array signal (i.e., performing the V-frame N-point FFT operation), the pipeline scheduling module simultaneously initiates two parallel tasks: the autocorrelation matrix calculation task: for the currently completed frequency domain transformation frame data, target frequency point selection, frequency point vector caching, and multiplication-accumulation operations are performed simultaneously to achieve pipeline overlap between frequency domain transformation and autocorrelation calculation; the matrix decomposition and iterative solution task: for the autocorrelation matrix that has been calculated in the previous frame data, Koleski decomposition and forward and backward iterative solution are performed simultaneously.

[0066] Through the above-described pipelined parallel design, the total latency of the entire array signal processing is compressed to the time required to perform V-frame N-point parallel frequency domain transformation. Subsequent autocorrelation calculations, matrix decomposition, and iterative solutions are all performed concurrently with the frequency domain transformation, significantly improving overall processing efficiency. For example, when the first frame of data undergoes frequency domain transformation, there are no subsequent parallel tasks; when the second frame of data undergoes frequency domain transformation, autocorrelation calculation is performed synchronously on the first frame of data; when the third frame of data undergoes frequency domain transformation, autocorrelation calculation is performed synchronously on the second frame of data, and matrix decomposition is performed on the autocorrelation matrix of the first frame of data; and so on, forming a continuous and uninterrupted pipelined parallel processing flow.

[0067] It should be noted that, in this invention, the autocorrelation matrix can be C rows and C columns. Each row vector is allocated a separate random access memory, allowing the matrix coefficients to be read in column-parallel fashion to improve data throughput and avoid excessive memory access latency during large-scale matrix coefficient reads. Matrix coefficients are stored in parallel using C memory locations. The autocorrelation matrix for each frequency point is stored using a separate set of memory. Each memory cell uses high bits to store the complex imaginary part and low bits to store the complex real part. The lower triangular matrix and transpose matrix can also be stored in column-parallel fashion.

[0068] The autocorrelation matrix solving module and the matrix equation solving process can be executed in parallel via a pipeline. After solving for the autocorrelation matrices at multiple frequency points, the calculated autocorrelation matrices are cached in another set of cache memories. Then, the matrix coefficients of X frequency points can be read in parallel for equation solving. The time overhead of the pipelined matrix solving module is hidden in the V-frame Fast Fourier Transform, significantly reducing the overall algorithm's latency.

[0069] Where C can be a natural number between 1 and 16. Z can be a natural number between 10 and 30, X can be a natural number between 3 and 10, and V can be a natural number between 128 and 512. K can be a natural number between 1 and 16, M can be a natural number between 1 and 16, and K*M=C. In this embodiment, C-channel array signals are first acquired, and a parallel frequency domain transformation is performed on the C-channel array signals to obtain C-channel spectrum data. X target frequency points are selected from the C-channel spectrum data, and parallel autocorrelation matrix calculations are performed to obtain the autocorrelation matrices corresponding to each of the X target frequency points. Matrix decomposition is performed on the autocorrelation matrices to obtain the decomposed matrices. Based on the decomposed matrices, forward and backward iterative solutions are performed to obtain the solution vector. At least two of the operations—parallel frequency domain transformation, autocorrelation matrix calculation, matrix decomposition, and forward and backward iterative solutions—are executed in a pipelined parallel manner. Therefore, through column-parallel storage structure, pipelined matrix decomposition, forward and backward iterative solutions, and module-level parallel design, the hardware acceleration capability for solving large-scale complex matrix equations is significantly improved, making it suitable for scenarios requiring high-dimensional matrix operations, such as signal processing, wireless communication, and artificial intelligence.

[0070] It should be noted that, compared with existing navigation air frequency anti-interference hardware algorithms, this invention has the following advantages and effects: By storing the coefficients of the complex matrix in a column-parallel manner and allocating independent random access memory for each row vector, column-level parallel reading is achieved, which significantly improves data throughput and effectively avoids the bottleneck problem caused by large-scale matrices in the memory access stage.

[0071] By pipelined parallelizing the time-consuming frame cumulative Fourier transform module with the subsequent matrix solving algorithm, the overall algorithm latency is reduced to the time required for multi-frame Fourier transforms.

[0072] The parameters C, K, M, F, and Q can be flexibly configured according to different matrix sizes, and can be adapted to complex matrix operations in the range of 16×16 to 128×128, making it easy to implement on array processors or FPGA platforms of different sizes.

[0073] In summary, this invention significantly improves the hardware acceleration capability for solving large-scale complex matrix equations through column-parallel storage structure, pipelined matrix decomposition, forward and backward iterative solution, and module-level parallel design, making it suitable for scenarios requiring high-dimensional matrix operations such as signal processing, wireless communication, and artificial intelligence.

[0074] Corresponding to the array signal processing method described in the above embodiments, Figure 5 This is a structural block diagram of the array signal processing device provided in the embodiments of this application.

[0075] Reference Figure 5 The array signal processing device 200 includes: The frequency domain transformation module 210 is used to acquire C-channel array signals and perform parallel frequency domain transformation on the C-channel array signals to obtain C-channel spectrum data. The autocorrelation calculation module 220 is used to select X target frequency points from the C-channel spectrum data and perform parallel autocorrelation matrix calculations to obtain the autocorrelation matrix corresponding to each of the X target frequency points. Matrix decomposition module 230 is used to perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix; The iterative solution module 240 is used to perform forward and backward iterative solutions based on the decomposed matrix to obtain the solution vector; The pipeline scheduling module 250 is used to control at least two of the frequency domain transformation module, the autocorrelation calculation module, the matrix decomposition module, and the iterative solution module to perform operations in a pipelined parallel manner.

[0076] Optionally, the frequency domain transformation module 210 is specifically used for: The C-channel array signals are processed in parallel using C Fast Fourier Transform modules to obtain the C-channel spectrum data.

[0077] Optionally, the autocorrelation calculation module 220 is specifically used for: Based on the preset target spectrum range, X target frequency points that fall within the target spectrum range are selected from the full frequency band corresponding to the C-channel spectrum data; Determine the center frequency vector of length C corresponding to each of the X target frequency points; The X center frequency vectors are temporarily cached in the register; By using X autocorrelation modules, multiplication and accumulation operations are performed on the X center frequency vectors to obtain the autocorrelation matrix corresponding to each of the X target frequency points.

[0078] Optionally, the matrix factorization module is specifically used for: A pipelined structure is used to perform Koleski decomposition on the autocorrelation matrix, sequentially completing the transformation of the main diagonal elements, updating the off-diagonal elements, and performing calculations to obtain a lower triangular matrix.

[0079] Optionally, the pipeline structure can be implemented in the following ways: Through K pipeline scheduling, M operation units are reused to complete the cumulative calculation of matrix elements; the operation unit includes a multiply-accumulate unit.

[0080] Optionally, the iterative solution module is specifically used for: Based on the decomposed matrix, perform a forward iteration to obtain the intermediate vector; The solution vector is obtained by performing backward iteration based on the intermediate vector; The implementation of the forward and backward iterations includes: reusing Q multiply-accumulate units to complete the multiply-accumulate calculation through F pipeline scheduling.

[0081] Optionally, the pipeline is executed in parallel, including: While performing the parallel frequency domain transformation, the autocorrelation matrix calculation is performed in parallel, as well as matrix decomposition and forward and backward iterative solution of the autocorrelation matrix.

[0082] In this embodiment, C-channel array signals are first acquired, and a parallel frequency domain transformation is performed on the C-channel array signals to obtain C-channel spectrum data. X target frequency points are selected from the C-channel spectrum data, and parallel autocorrelation matrix calculations are performed to obtain the autocorrelation matrices corresponding to each of the X target frequency points. Matrix decomposition is performed on the autocorrelation matrices to obtain the decomposed matrices. Based on the decomposed matrices, forward and backward iterative solutions are performed to obtain the solution vector. At least two of the operations—parallel frequency domain transformation, autocorrelation matrix calculation, matrix decomposition, and forward and backward iterative solutions—are executed in a pipelined parallel manner. Therefore, through column-parallel storage structure, pipelined matrix decomposition, forward and backward iterative solutions, and module-level parallel design, the hardware acceleration capability for solving large-scale complex matrix equations is significantly improved, making it suitable for scenarios requiring high-dimensional matrix operations, such as signal processing, wireless communication, and artificial intelligence.

[0083] in addition, Figure 5The array signal processing device shown can be a software unit, hardware unit, or a combination of software and hardware built into an existing electronic device, or it can be integrated into the electronic device as a separate component, or it can exist as a separate electronic device.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0085] Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 6 As shown, the electronic device 5 of this embodiment includes: at least one processor 50 ( Figure 6 (Only one is shown in the diagram) a processor, a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, wherein the processor 50 executes the computer program 52 to implement the steps in any of the above-described array signal processing method embodiments.

[0086] The electronic device may be a desktop computer, laptop, handheld computer, or cloud server, etc. This electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 6 This is merely an example of electronic device 5 and does not constitute a limitation on electronic device 5. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0087] The processor 50 may be a central processing unit, or it may be other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0088] In some embodiments, the memory 51 may be an internal storage unit of the electronic device 5, such as a hard disk or memory of the electronic device 5. In other embodiments, the memory 51 may be an external storage device of the electronic device 5, such as a plug-in hard disk, smart memory card, secure digital card, flash memory card, etc., equipped on the electronic device 5. Further, the memory 51 may include both internal storage units and external storage devices of the electronic device 5. The memory 51 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of the computer program. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0089] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the above-described method embodiments.

[0090] This application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the steps described in the various method embodiments above.

[0091] If the integrated unit is implemented as a software functional unit and used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / electronic device, a recording medium, a computer memory, a read-only memory, a random access memory, an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0095] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0096] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An array signal processing method, characterized in that, include: Acquire C-channel array signals, perform parallel frequency domain transformation on the C-channel array signals, and obtain C-channel spectrum data; The signals of X target frequency points are selected from the C-channel spectrum data and their autocorrelation matrices are calculated in parallel to obtain the autocorrelation matrices corresponding to each of the X target frequency points. Perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix; Based on the decomposed matrix, perform forward and backward iterations to obtain the solution vector; Among them, at least two of the operations in the parallel frequency domain transformation, the autocorrelation matrix calculation, the matrix decomposition, and the forward and backward iterative solution are executed in a pipelined parallel manner.

2. The method according to claim 1, characterized in that, The parallel frequency domain transformation of the C-channel array signals to obtain C-channel spectrum data includes: The C-channel array signals are processed in parallel using C Fast Fourier Transform modules to obtain the C-channel spectrum data.

3. The method according to claim 1, characterized in that, The step of selecting X target frequency points from the C-channel spectrum data and performing parallel autocorrelation matrix calculations to obtain the autocorrelation matrix corresponding to each of the X target frequency points includes: Based on the preset target spectrum range, X target frequency points that fall within the target spectrum range are selected from the full frequency band corresponding to the C-channel spectrum data; Determine the center frequency vector of length C corresponding to each of the X target frequency points; The X center frequency vectors are temporarily cached in the register; By using X autocorrelation modules, multiplication and accumulation operations are performed on the X center frequency vectors to obtain the autocorrelation matrix corresponding to each of the X target frequency points.

4. The method according to claim 1, characterized in that, The step of performing matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix includes: A pipelined structure is used to perform Koleski decomposition on the autocorrelation matrix, sequentially completing the transformation of the main diagonal elements, updating the off-diagonal elements, and performing calculations to obtain a lower triangular matrix.

5. The method according to claim 4, characterized in that, The implementation methods of the pipeline structure include: Through K pipeline scheduling, M operation units are reused to complete the cumulative calculation of matrix elements; the operation unit includes a multiply-accumulate unit.

6. The method according to claim 1, characterized in that, The solution vector is obtained by performing forward and backward iterations based on the decomposed matrix, including: Based on the decomposed matrix, perform a forward iteration to obtain the intermediate vector; The solution vector is obtained by performing backward iteration based on the intermediate vector; The implementation of the forward and backward iterations includes: reusing Q multiply-accumulate units to complete the multiply-accumulate calculation through F pipeline scheduling.

7. The method according to claim 1, characterized in that, The pipeline is executed in parallel mode, including: While performing the parallel frequency domain transformation, the autocorrelation matrix calculation is performed in parallel, as well as matrix decomposition and forward and backward iterative solution of the autocorrelation matrix.

8. An array signal processing device, characterized in that, include: The frequency domain transformation module is used to perform parallel frequency domain transformation on the C-channel array signals to obtain C-channel spectrum data; The autocorrelation calculation module is used to select X target frequency points from the C-channel spectrum data and calculate the autocorrelation matrix corresponding to each of the X target frequency points in parallel. The matrix decomposition module is used to perform matrix decomposition on the autocorrelation matrix to obtain the decomposed matrix. The iterative solution module is used to perform forward and backward iterative solutions based on the decomposed matrix to obtain the solution vector; The pipeline scheduling module is used to control at least two of the frequency domain transformation module, the autocorrelation calculation module, the matrix decomposition module, and the iterative solution module to perform operations in a pipelined parallel manner.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which is loaded by a processor to perform the steps of the method according to any one of claims 1 to 7.

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