A decision feedback equalizer for PAM4 encoded band infinite impulse response filters

Abstract

The application discloses a decision feedback equalizer for PAM4 encoding band infinite impulse response filter, belongs to the field of signal processing, and comprises a high-pass filter and a linear equalizer, a decision feedback adder, and an infinite impulse response filter coefficient feedback control module; noise filtering is performed on a high-speed signal, low-frequency attenuation of the high-speed signal is compensated, a tailing effect in a frequency response is eliminated, high-speed inter-symbol interference is suppressed and eliminated, and an offline post-cursor in the frequency response is fed back and compensated; meanwhile, aiming at PAM4 encoded data, an RLM (Level separation mismatch ratio) calibration module and a clock data recovery circuit are added, which are used for improving the speed of clock receiving and recovery, and due to the addition of more high-speed modules, the load of the equalization adder is increased; the application uses a layout planning of a double-difference six-port mutual inductance bridge type (T-coil) inductive network, and bandwidth is expanded by using inductive peaking technology.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a decision feedback equalizer for PAM4 encoded filters with infinite impulse response. Background Technology

[0002] In high-speed serial signal communication links, as the demand for transmission speed increases significantly, the signal transmission loss in the medium also increases. Compared with NRZ (Non-Return-to-Zero) encoding, PAM4 (4-Level Pulse Amplitude Modulation) encoding can transmit twice the amount of data as NRZ using four levels at the same time. Therefore, under the same data volume protocol requirements, the baud rate of PAM4 encoding is half that of NRZ, which reduces the attenuation of high-speed signals. However, it requires receiving three eye diagram messages formed by four levels and processing more subtle signal amplitude changes.

[0003] Due to chip packaging, dielectric loss on the circuit board, and skin effect, high-speed signals will generate severe inter-symbol interference (ISI). Moreover, different transmission protocols require different application scenarios to resist interference from various noises such as electromagnetic noise and thermal noise at different frequencies. These non-ideal factors will seriously affect the eye height and eye width quality of the receiver, especially in PAM4 encoded transmission. Summary of the Invention

[0004] The purpose of this invention is to provide a decision feedback equalizer for PAM4 encoding with an infinite impulse response filter, in order to solve the problems in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a decision feedback equalizer for PAM4 encoded filters with infinite impulse response, comprising:

[0006] High-pass filters and linear equalizers filter low-frequency noise from the received signal, linearly amplify mid-to-high frequency signals, and improve the signal post-cursor.

[0007] The decision feedback adder uses a voltage-type DAC to generate different levels, and combines them with a high-speed sensitive amplifier for sampling and encoding to convert the thermometer code into binary code, reducing the computational load of the digital bit width.

[0008] The infinite impulse response filter coefficient feedback control module adaptively converges to obtain the feedback amplitude coefficient and the frequency coefficient of the feedback compensation filter. Based on the judgment of high-speed sampling data, it uses the binary code encoding format to feed back to the common-mode node of the source high-pass filter to compensate for and improve the low-frequency loss of the source input signal.

[0009] In one implementation, the decision feedback adder identifies different eye height information and common mode information of the three eyes in the PAM4 data through the VREF adaptive convergence algorithm to obtain the difference information of the three eye heights; through the TAP adaptive convergence algorithm, it obtains multiple discrete Post-cursor feedback coefficient information, and at the same time delays the sampled data, combines the feedback TAP coefficients at the corresponding time, and uses the binary code encoding format to perform decision feedback compensation.

[0010] In one embodiment, the decision feedback adder includes a multi-post-mark node feedback module, a level separation mismatch linear feedback calibration module, a common-mode feedback control module, and a DC voltage offset elimination module. It adopts a layout planning of a dual differential six-port mutual inductance bridge inductor network, which utilizes the mutual inductance between differential inductors to increase the inductance value while reducing the layout area.

[0011] In one embodiment, the system also includes a level separation mismatch rate calibration module and a clock data recovery circuit to improve the speed of clock reception and recovery for PAM4 encoded data.

[0012] In one implementation, the PAM4 encoded data selects a C-type transition edge based on the density of data transition edges. Simultaneously, phase detection generates an additional set of clock phase enhancement lead / hysteresis signals with strong gain capabilities. This set of enhancement lead / hysteresis signals is dynamically controlled during the locking process. It is turned on during the initial locking process of clock recovery to increase the clock recovery bandwidth, reduce the clock recovery locking time, and widen the clock phase locking range. It is turned off during the locking steady state to reduce the peak jitter of the clock eye diagram in the steady state.

[0013] This invention provides a decision feedback equalizer with an infinite impulse response filter for PAM4 encoding. Based on the PAM4 encoding structure, it uses various adaptive algorithms to process sampled data and perform dynamic feedback at both high and low speeds. For data links in various transmission protocol environments, including long-distance, high-loss, and complex noise conditions, it effectively filters environmental noise, amplifies high-frequency signals, compensates for discrete post-cursors, eliminates and suppresses inter-symbol interference, and compensates for mid- and low-frequency signal distortion. Simultaneously, it uses multiple data transition edge messages to dynamically adjust the clock recovery bandwidth and reduce recovery lock-in time. The overall circuit architecture distinguishes between high-speed and low-speed compensation loops, using differential Tcoil with better area performance to reduce power consumption while expanding bandwidth, calibrating and improving the linearity of PAM4 encoded data. The overall architecture modules are relatively independent and complete, facilitating layout routing and reducing interference, and enabling independent testing of module units and system integration. Attached Figure Description

[0014] Figure 1This is a schematic diagram of the decision feedback equalizer structure for PAM4 encoding with an infinite impulse response filter provided by the present invention.

[0015] Figure 2 This is a schematic diagram of the decision feedback adder structure provided by the present invention.

[0016] Figure 3 This is a schematic diagram of the dual differential six-port mutual inductance bridge inductor network structure provided by the present invention.

[0017] Figure 4 This is a schematic diagram of the data selected for clock recovery based on PAM4 encoding in this invention.

[0018] Figure 5 This is a diagram illustrating the compensation effect. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the decision feedback equalizer for PAM4 coded infinite impulse response filters proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] This invention provides a decision feedback equalizer for PAM4 encoding with an infinite impulse response filter, comprising a high-pass filter and a linear equalizer, a decision feedback adder, and an infinite impulse response filter coefficient feedback control module. It performs noise filtering on high-speed signals, compensates for low-frequency attenuation of high-speed signals, eliminates tailing effects in the frequency response, suppresses and eliminates high-speed inter-symbol interference, and provides feedback compensation for the offline post-cursor (the ratio of the signal amplitude at N bit transition times after the current signal transition to the signal amplitude at the current transition time). Simultaneously, for PAM4 encoded data, an RLM (Level Separation Mismatch Ratio) calibration module and a clock data recovery circuit are added to improve clock reception and recovery speed. Furthermore, due to the addition of more high-speed modules, the load on the equalizer adder is increased. This invention utilizes a layout plan of a dual-differential six-port mutual inductance bridge (T-coil) inductor network and leverages inductor peaking technology to expand bandwidth.

[0021] The chip architecture block diagram protected by this invention is as follows: Figure 1 Details shown are as follows Figure 2-4 The effect of the compensation process is as follows Figure 5For different equalization feedback influence areas, the discrete nodes such as offline cursors H1 / H2 / H3 / H4...H15 / H16 in the influence area of ​​the decision feedback equalizer are reverse compensated to reduce their offline cursor values ​​to 0. Simulated continuous reverse compensation is performed in the wireless impulse response filter area to reduce the continuous cursor curves in this area to 0. The implementation principle is as follows:

[0022] 1. High-speed data first passes through a high-pass filter and a linear equalizer to filter low-frequency noise in the received signal and linearly amplify mid-to-high frequency signals, improving the signal pre-cursor. However, there are still many discrete post-cursors at different times, and the low-frequency components of the signal will be attenuated by the high-pass filter. At the same time, thermal noise and flicker noise from the analog devices themselves are also added. Moreover, due to the influence of nonlinear factors of the devices and the characteristics of the PAM4 encoded eye diagram, the RLM index of the eye diagram will be very poor, and the difference in eye height among the three eyes (eye high / eye middle / eye low) will be large.

[0023] 2. The decision feedback adder of this invention utilizes a voltage-type DAC to generate different levels VRef, which are then sampled and encoded using an SA (high-speed sensitive amplifier) ​​to convert the thermometer code into binary code. This reduces the computational load of the digital bit width. The VREF Adaptive Algorithm identifies different eye height information in the PAM4 data and the common-mode information of the three eyes, obtaining the difference information of the three eye heights. The TAP Adaptive Algorithm obtains multiple discrete Post-cursor feedback coefficients. Simultaneously, the sampled data is delayed, and combined with the feedback TAP coefficients at the corresponding time points, decision feedback compensation is performed using the binary code encoding format. Due to the influence of long-distance cables and the higher requirements for eye height in PAM4 encoding, this invention supports up to 40 discrete Post-cursor compensations. Furthermore, it obtains feedback information for calibrating the three eye height differences in PAM4, directly feeding back the thermometer code encoding format to improve the RLM performance of the PAM4 eye diagram. It also directly compensates for the TAP1 coefficients, achieving an innovative architecture that combines module functions and multi-purpose use.

[0024] Figure 1 SA EDGE, SA DLEV, SA DM, SA DH, and SA DL all refer to the same module, SA, which functions as a high-speed clock sampling comparator. At high-speed clock transitions, it samples the difference between the high-speed input data and different threshold levels, then amplifies it to a full-swing digital signal. The different suffixes after SA are due to the different sampling clocks and the different threshold levels used for comparison.

[0025] 3. Increasing the bandwidth of the input high-pass filter can better filter low-frequency noise interference from the input environment, but it also causes low-frequency attenuation of the input signal. This is reflected in the frequency response by the post-cursor, which is further away from the main-cursor, and exhibits linear attenuation. This invention directly adds a feedback control module with infinite impulse response filter coefficients to the input high-pass filter. Using high-speed sampled PAM4 eye diagram information, it calculates and analyzes low-frequency components, adaptively converges to obtain the feedback amplitude coefficients and the frequency coefficients of the feedback compensation filter. Based on the judgment of high-speed sampled data, using a binary code encoding format, it feeds back to the common-mode node of the source high-pass filter equalizer, thereby compensating for and improving the low-frequency loss of the source input signal. The innovative node of the IIR filter feedback architecture of this invention can completely distinguish between high-frequency and low-frequency feedback paths. This reduces the load on the high-frequency path, saving more bandwidth margin for more functional modules. It also allows for a more reasonable allocation of the layout of high-speed and low-speed signals, preventing mutual interference. At the same time, it reduces the nonlinear amplification distortion and noise introduced into the subsequent high-frequency amplification path, making the low-frequency compensation of the signal more precise. It can also linearly increase the compensation range, making the compensated signal more complete and linear before entering the subsequent linear equalization and decision feedback adder.

[0026] 4. Figure 2 The diagram shown is a structural schematic of the DFE SUM module. Figure 1 Adding a multi-TAPs feedback module, a level separation mismatch linear feedback calibration module (RLM), a common-mode control feedback module, and DC offset cancel blocks to the DFE SUM module would significantly increase the load on the output nodes and affect the adder's bandwidth. Therefore, this invention employs a dual-differential 6-port coupled T-coil inductor network, such as... Figure 3 As shown, bandwidth is extended by utilizing inductor peaking. Due to the dual differential coupling, the mutual inductance between the differential inductors is effectively utilized, increasing the inductance value while significantly reducing the layout area compared to a single-ended T-coil. Moreover, differential coupling makes the inductor layout area relatively complete, independent, and compact, which reduces noise and common-mode interference in the surrounding environment of the inductor layout, and facilitates integration with other module circuit layouts, reducing unnecessary wiring space and further optimizing load and bandwidth performance.

[0027] like Figure 4As shown, to cooperate with the clock data recovery circuit, PAM4 encoded data typically selects the A-type transition edge with the highest density based on the density of data transition edges, performs phase detection to generate clock phase lead / lag signals, and locks the recovered clock. Based on this, this invention proposes using the C-type transition edge to simultaneously perform phase detection and generate an additional set of clock phase enhancement lead / lag signals with stronger gain. This set of enhanced lead / lag signals can be dynamically controlled during the locking process. It is enabled during the initial locking process of clock recovery to increase the clock recovery bandwidth, reduce the clock recovery lock time, and widen the clock phase locking range. It is disabled during the steady-state locking to reduce the peak jitter of the clock eye diagram in the steady state.

[0028] This invention proposes a novel feedback node for infinite impulse response filtering compensation, which independently distinguishes between high-speed and low-speed feedback paths, reducing the load pressure on the high-speed path and reducing high-frequency interference on the low-speed path. At the same time, it reduces the mid-to-high frequency nonlinearity introduced during high-speed signal amplification compensation, facilitates control of compensation accuracy, increases the control compensation range, improves low-frequency signal distortion caused by noise filtering, and facilitates independent testing and integration between circuits, effectively reducing wiring interference between high-speed and low-speed circuit layouts.

[0029] This invention addresses the PAM4 data encoding format by integrating an RLM linear compensation circuit and a high-speed discrete post-cursor feedback compensation point circuit. Utilizing multiple adaptive algorithms, it converges the analysis of high-speed sampled data, performs feedback compensation, and eliminates and suppresses inter-symbol interference (ISI) between high-speed signals. Simultaneously, it adjusts the RLM linearity index of the PAM4 data. To reduce power consumption and expand bandwidth requirements, a differential six-port Tcoil is used, leveraging differential mutual inductance to increase inductance, reduce layout area, and enhance noise immunity.

[0030] This invention adds a phase detection signal for time recovery locking in parallel. By utilizing the unique edge transition of PAM4 encoding, a higher gain phase detection control signal is generated to dynamically control the locking bandwidth of the clock data recovery circuit, reduce the locking time of clock recovery, and widen the locking range. At the same time, this function is turned off during the locking stabilization phase to reduce clock tracking jitter.

[0031] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A decision feedback equalizer for PAM4 encoding with an infinite impulse response filter, characterized in that, include: A high-pass filter and a linear equalizer filter low-frequency noise in the received signal, and linearly amplify the mid-to-high frequency signal before outputting it to a decision feedback adder to improve the signal post-cursor. The decision feedback adder uses a voltage-type DAC to generate different levels, and combines them with a high-speed sensitive amplifier for sampling and encoding to convert the thermometer code into binary code, reducing the computational load of the digital bit width. The infinite impulse response filter coefficient feedback control module has a decision feedback adder connected to its input. It uses the three eye diagram messages of the high-speed sampled PAM4 to calculate and analyze the low-frequency components, and adaptively converges to obtain the feedback amplitude coefficient and the frequency coefficient of the feedback compensation filter. Based on the judgment of the high-speed sampled data, it uses the binary code encoding format to feed back to the common-mode node of the source high-pass filter to compensate for and improve the low-frequency loss of the source input signal.

2. The decision feedback equalizer for PAM4 encoded infinite impulse response filters as described in claim 1, characterized in that, The decision feedback adder uses the VREF adaptive convergence algorithm to identify different eye height information in the PAM4 data and the common mode information of the three eyes to obtain the difference information of the three eye heights; it uses the TAP adaptive convergence algorithm to obtain multiple discrete Post-cursor feedback coefficient information, and at the same time delays the sampled data, combines the feedback TAP coefficients at the corresponding time, and uses the binary code encoding format to perform decision feedback compensation.

3. The decision feedback equalizer for PAM4 encoded infinite impulse response filters as described in claim 1, characterized in that, The decision feedback adder includes a multi-post-standard node feedback module, a level separation mismatch linear feedback calibration module, a common-mode feedback control module, and a DC voltage offset elimination module. It adopts a layout planning of a dual differential six-port mutual inductance bridge inductor network, which increases the inductance value while reducing the layout area by utilizing the mutual inductance between differential inductors.

4. The decision feedback equalizer for PAM4 encoded infinite impulse response filters as described in claim 1, characterized in that, It also includes a level separation mismatch rate calibration module and a clock data recovery circuit, which improve the speed of clock reception and recovery for PAM4 encoded data.

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