Edge computing heterogeneous multi-mcu architecture design and task scheduling method

Abstract

The application provides an edge computing heterogeneous multi-MCU architecture design and task scheduling method, and relates to the technical field of edge computing. The method constructs an architecture containing a management MCU, a high-performance and low-power MCU group, a shared high-speed QSPI Flash and an NB-IoT module. The management MCU gathers sensor data and stores the data to the shared Flash, monitors the system power and the MCU temperature in real time, and dynamically adjusts the time delay and energy consumption weight factors used in the task offloading decision. By running an improved particle swarm optimization algorithm, the algorithm uses the sum of the weighted time delay cost, the weighted energy consumption cost and the queuing penalty term for preventing uneven load as a comprehensive fitness function, generates an optimal task offloading decision vector, and intelligently distributes the computing task to the heterogeneous MCU group for execution. The application realizes the comprehensive optimization of the system time delay and energy consumption in a complex environment, and improves the adaptive ability and the endurance stability of the edge monitoring terminal.

Description

Technical Field

[0001] This invention relates to the field of edge computing technology, specifically to edge computing heterogeneous multi-MCU architecture design and task scheduling method. Background Technology

[0002] In the field of real-time monitoring of critical transportation infrastructure such as highway bridges, the large-scale deployment of multimodal sensors generates massive amounts of data daily. To reduce the pressure of data transmission to the cloud and meet the needs of real-time early warning, mobile edge computing has become the mainstream technology. Currently, edge monitoring nodes generally adopt a homogeneous MCU architecture, the core challenge of which lies in the difficulty of simultaneously ensuring high-performance computing and long battery life under limited power consumption. Especially in the complex open-air environment where bridges are located, equipment often faces extreme conditions such as high temperatures and extreme cold. Existing solutions often lack hardware-level environmental awareness and dynamic adaptation capabilities, leading to performance fluctuations and power consumption surges, seriously affecting the real-time performance and system stability of monitoring. Summary of the Invention

[0003] To achieve the above objectives, this invention proposes a heterogeneous multi-MCU architecture design and task scheduling method for edge computing. The MCU architecture includes at least one management MCU as a task management node, at least one high-performance computing MCU group, at least one low-power computing MCU group, a shared high-speed QSPI Flash connecting all MCUs, and an NB-IoT communication module connected to the management MCU. The task scheduling method includes the following steps:

[0004] S1. By aggregating raw data from multiple sensors through the management MCU, and by transferring the raw data to a designated data area of ​​the shared high-speed QSPI Flash through the direct memory access (DMA) controller of the management MCU;

[0005] S2. The remaining battery power and temperature of at least one MCU are obtained in real time by managing the MCU; the time delay weight factor and energy consumption weight factor in the comprehensive fitness function used for task unloading decision are dynamically adjusted according to whether the remaining battery power is lower than a preset low power threshold and whether the temperature exceeds a preset high temperature threshold.

[0006] S3. By managing the MCU to run the Particle Swarm Optimization (PSO) algorithm, a task offloading decision vector is generated based on the latency weighting factor and the energy consumption weighting factor. The comprehensive fitness function of the PSO algorithm is used to calculate the total system cost, which is the sum of the weighted latency cost, the weighted energy consumption cost, and the queuing penalty term. The weighted latency cost and the weighted energy consumption cost are weighted using the latency weighting factor and the energy consumption weighting factor dynamically adjusted in S2, respectively. The queuing penalty term imposes an additional cost on the decision scheme that excessively concentrates computational tasks on any one MCU.

[0007] S4. The management MCU sends a task unloading instruction containing a data address to the target MCU in the high-performance computing MCU group or the low-power computing MCU group according to the task unloading decision vector; after the target MCU is woken up, it reads data from the specified data area of ​​the shared high-speed QSPI Flash according to the task unloading instruction, performs calculations, writes the results back to the result storage area of ​​the shared high-speed QSPI Flash, and sends a task completion notification to the management MCU.

[0008] S5. After confirming the completion of the associated task, the management MCU controls the NB-IoT communication module to read the final result data packet from the result storage area of ​​the shared high-speed QSPI Flash, and reports it to the cloud platform through the NB-IoT communication module.

[0009] As a further technical solution, the heterogeneous multi-MCU architecture constructed in this invention includes at least one management MCU as a task management node, at least one high-performance computing MCU group, at least one low-power computing MCU group, a shared high-speed QSPI Flash connecting all MCUs, and an NB-IoT communication module connected to the management MCU. The management MCU is responsible for system perception, decision-making, and coordination. The high-performance computing MCU group consists of several MCUs with strong computing power but relatively high power consumption, used to handle computationally intensive or high real-time tasks. The low-power computing MCU group consists of several MCUs focused on low-power operation, suitable for handling periodic lightweight computing tasks. The shared high-speed QSPI Flash provides a unified data storage and exchange space for all MCUs, eliminating complex data transfer between MCUs. The NB-IoT communication module is responsible for uploading the final results to the cloud. This method dynamically senses the system status, such as power and temperature, through the management MCU, and intelligently schedules computing tasks to the most suitable computing unit accordingly, thereby achieving optimal overall system performance under multiple constraints.

[0010] As a further technical solution, in step S1, the management MCU aggregates raw data from multiple sensors and transfers the data to a designated data area of ​​the shared high-speed QSPI Flash via its Direct Memory Access (DMA) controller. Specifically, the management MCU internally has multi-level circular buffers for real-time temporary storage of raw data from different sensors. During data aggregation, the management MCU dynamically generates and attaches a header tag to each incoming data block based on the data generation rate and data type of each sensor. This header tag includes at least the data acquisition sequence number, a unique sensor identifier, and a data urgency level. The data urgency level is determined according to preset rules; for example, sensor data used for security monitoring is assigned a high urgency level, while periodic monitoring data such as environmental temperature and humidity are assigned a low urgency level. Subsequently, the management MCU's DMA controller adaptively selects the data area from the multi-level circular buffers to the designated data area of ​​the shared high-speed QSPI Flash based on the data urgency level in the header tag. Transmission modes: For data blocks marked as high urgency, the DMA controller employs a single-interrupt-triggered small-batch continuous transmission mode to minimize write latency and ensure rapid availability of critical data. For data blocks marked as low urgency, the DMA controller uses a batch aggregation transmission mode, which waits for a certain amount of data to accumulate in the buffer or for a time window to be reached before transmitting a large block of data at once. This optimizes the number of writes to the shared high-speed QSPI Flash, improving storage space utilization and overall transmission efficiency. Throughout the transmission process, the DMA controller synchronously generates a fast check sequence based on bit operations for each data block to be written, such as a simplified variant of cyclic redundancy check. This check sequence is appended to the end of the data block and written along with the data content to a designated data area of ​​the shared high-speed QSPI Flash, providing rapid integrity verification capabilities for subsequent data reading by the MCU.

[0011] As a further technical solution, in step S2, the management MCU acquires the system's remaining battery power and the temperature of at least one MCU in real time, and dynamically adjusts the delay weight factor and energy consumption weight factor in the comprehensive fitness function used for task unloading decisions accordingly. Specifically, this includes: the management MCU periodically sampling the system's remaining battery power and the temperature of each MCU, and storing them in corresponding historical data sequences; to eliminate instantaneous fluctuation interference, performing a time-window-based moving average calculation on the historical battery power data sequence to obtain a smoothed, stable battery power value; and using a hysteresis filtering algorithm on the historical temperature data sequence to eliminate measurement spikes and obtain a stable... Temperature value; the dynamic adjustment strategy is based on stable power and stable temperature values. First, the stable power value is compared with multiple preset power reduction threshold ranges, such as high power range, medium power range, and low power range. Depending on the range the power falls into, a preset mapping table is used to increase the base magnitude of the energy consumption weight factor. The lower the power level, the larger the base magnitude increase, indicating that the system is more inclined to save energy. Second, the stable temperature value is compared with a preset high temperature threshold. If the threshold is exceeded, a compensation coefficient is calculated based on the percentage exceeded. This compensation coefficient is used to temporarily reduce the magnitude of the latency weight factor, aiming to reduce the pursuit of computational speed. To reduce system load and thus mitigate temperature rise, the system will ultimately perform a superposition operation based on the base amplitude obtained from power consumption and the compensation coefficient obtained from temperature to generate synchronized adjustment values ​​for the delay weight factor and the energy consumption weight factor. The specific logic of the superposition operation is as follows: if the system is in a high power consumption range, the base amplitude of the energy consumption weight factor will be used as the primary adjustment basis, and the temperature compensation coefficient will only have a half-amplitude impact on the delay weight factor; that is, when power is sufficient, the influence of temperature on the scheduling strategy is reduced. If the system is in a medium power consumption range, the base amplitude and the compensation coefficient will be algebraically added, and then applied to the energy consumption weight factor and the delay weight factor in equal and reverse directions, respectively. The adjustment mode is as follows: if one side increases by a certain amount, the other side decreases by the same amount. If the system is in a low power range, a protective adjustment mode is activated: the base amplitude is amplified by a preset multiple as the dominant adjustment amount of the energy consumption weight factor, forcing the system to be extremely energy-efficient. At the same time, based on the frequency of the current stable temperature value exceeding the high temperature threshold in the most recent sampling periods, the effective ratio of the compensation coefficient is dynamically calculated, and the delay weight factor is reduced according to this ratio. In all adjustment cases, the management MCU ensures that the sum of the adjusted delay weight factor and the energy consumption weight factor is equal to the sum of the weights before adjustment, thereby constraining the multi-objective optimization problem within a unified weight framework for dynamic trade-offs.

[0012] As a further technical solution, in step S3, the management MCU runs a PSO algorithm based on particle swarm optimization, and combines the latency weighting factor and energy consumption weighting factor dynamically adjusted in step S2 to generate the final task offloading decision vector. In the initialization phase, the position vector of each particle in the search space is defined as a candidate task offloading decision scheme. Each dimension of the position vector corresponds to a computing task to be processed. For example, its value of 0 or 1 represents a binary decision to assign the task to a high-performance computing MCU group or a low-power computing MCU group. The comprehensive fitness function used by the PSO algorithm is used to calculate the total system cost corresponding to any decision scheme. The total system cost consists of the sum of the weighted latency cost, the weighted energy consumption cost, and the queuing penalty term.

[0013] Specifically, the total weighted latency cost is , It is the clock frequency of the target MCU. To calculate the amount of data in the program, To calculate the density (clock cycles required per bit of data); the total weighted energy cost is... ,in For effective switching of capacitors, V is the voltage; queuing penalty term. To prevent excessive task concentration on high-performance nodes, a penalty function is designed when the MCU node... Additional penalty costs during idle periods. This makes the tasks more evenly distributed; its total system cost is ,in As a time delay weighting factor, As an energy consumption weighting factor, and For each particle's position vector, the management MCU first resolves the target MCU group to which each task is assigned, and then estimates the computation completion time of each task on any MCU within the corresponding group. The sum of the estimated completion times of all tasks is used as the base latency cost. Next, a difference coefficient is introduced, determined by the ratio of the number of tasks assigned to the two types of MCU groups. When task allocation is severely biased towards one group, such as when the ratio is unbalanced, this difference coefficient will non-linearly amplify the base latency cost to simulate the increase in queue waiting delay that may be caused by uneven load. For energy consumption cost, the management MCU queries the pre-stored base power consumption values ​​of the high-performance group and the low-power group based on the type of the target MCU group to which each task belongs, and uses the sum of the base power consumption values ​​of all tasks as the base energy consumption cost. Subsequently, the base latency cost and base energy consumption cost adjusted by the difference coefficient are multiplied by the latency weighting factor and energy consumption weighting factor obtained in step S2, respectively, to obtain the final weighted latency cost and weighted energy consumption cost. At the same time, the management MCU calculates a queuing penalty term to explicitly prevent excessive task concentration. Specifically, the particle's position vector is resolved, and the total number N of tasks assigned to the high-performance group is counted. h Given the total number of tasks N1 assigned to the low-power group, calculate the total number of tasks N = N h +N1; Calculate the imbalance degree U in task allocation, its value is |N1|. h -N1| / N; The management MCU determines a load adjustment base B based on the total number M of currently active MCUs in the system (i.e., the total number of available MCUs in the high-performance group and the low-power group). B is set to the square root of M to reflect the system scale; U is multiplied by B to obtain the intermediate penalty value P1 = U × B; The final queuing penalty term is obtained by multiplying P1 by an amplification factor (1 + U) based on the imbalance degree U, i.e., the queuing penalty term is... =P1×(1+U), which makes the penalty value exhibit a nonlinear characteristic of accelerating growth with the increase of imbalance, and strongly punishes the scheme of excessive load concentration; the total system cost of the particle position vector is obtained by adding the weighted delay cost, weighted energy consumption cost and queuing penalty term.

[0014] As a further technical solution, the PSO algorithm updates the particle's own historical best position based on this cost. and the global optimal position of the particle swarm The particle velocity and position are iteratively updated; the velocity update is as follows: r1 and r2 follow a uniform distribution on [0,1]; their positions are updated as follows: PS0 ultimately outputs the optimal global position. Total system cost Where X[i] is the velocity vector of the i-th particle, V[i] is the position vector (i.e., the unloading decision vector) of the i-th particle, and W...p c1 and c2 are inertial weights, c1 and c2 are learning factors, and rand() is a random number in the interval [0,1]. When the iteration process meets the preset convergence condition, such as when the fitness value corresponding to the global optimal position no longer decreases or changes less than the threshold in consecutive iterations, the iteration terminates and the global optimal position vector at this time is output as the final task unloading decision vector.

[0015] As a further technical solution, in step S4, the management MCU sends a task offload instruction to the target MCU based on the task offload decision vector generated in S3. The management MCU first assembles a complete task offload instruction for each task to be offloaded. This instruction at least includes the starting address of the data corresponding to the task in the shared high-speed QSPI Flash, the data length, the globally unique task identifier, and the target MCU group code. The instruction sending method differs depending on the target MCU group: for high-performance computing MCU groups, the management MCU sends the task offload instruction to all MCUs in the group at once via multicast communication, allowing the MCUs in the group to compete autonomously based on their busy / idle status; for low-power computing MCU groups in low-power sleep mode, the management MCU sends a wake-up signal via a hardware wake-up line, along with a wake-up token bound to the task identifier in the task offload instruction. After the target MCU is woken up or activated, it first sends an acknowledgment signal containing the wake-up token to the management MCU to establish a communication link, and then, based on the received task offload instruction, directly retrieves the task offload instruction from the shared high-speed QSPI Flash. The Flash reads a data block of the corresponding length from the specified starting address and verifies data integrity using a fast check sequence attached during writing. During the calculation process, the target MCU writes its running status flag to a dedicated status record area in the shared high-speed QSPI Flash in real time. This flag includes the task identifier being processed and a status code indicating "calculation in progress," facilitating global monitoring of the task execution progress by the management MCU. After the target MCU completes the calculation, it writes the calculation result to the pre-allocated result storage area in the shared high-speed QSPI Flash, updates the flag of the corresponding task in the status record area to the "complete" status code, and finally sends a task completion notification containing the task identifier to the management MCU.

[0016] As a further technical solution, in step S5, after receiving notification of the completion of all associated tasks or waiting for the timeout mechanism to be triggered, the management MCU confirms that all batch computing tasks have been completed. Subsequently, the management MCU controls the NB-IoT communication module to read the calculation results of all tasks sequentially from the result storage area of ​​the shared high-speed QSPI Flash, and assembles them into a final result data packet conforming to the uplink protocol format. Finally, the management MCU reports the result data packet to the remote cloud platform through the NB-IoT communication module, completing the entire process of edge computing and data reporting.

[0017] This invention provides a heterogeneous multi-MCU architecture design and task scheduling method for edge computing, which has the following beneficial effects:

[0018] 1. This invention solves the contradiction that traditional homogeneous edge nodes cannot meet the high real-time computing requirements under limited energy consumption by constructing a heterogeneous multi-MCU architecture and combining it with a task offloading algorithm based on particle swarm optimization. It significantly reduces system latency and energy consumption compared to random offloading strategies.

[0019] 2. This invention improves the system's adaptive survivability to harsh conditions such as high temperature and low power by introducing a dual feedback mechanism based on the real-time temperature of the MCU and the remaining battery power in the task unloading algorithm, and dynamically adjusting the time delay and energy consumption weights in the optimization target. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The system constructed in this invention is a heterogeneous multi-MCU architecture. Its core includes a management MCU serving as a task management node, at least one high-performance computing MCU group, at least one low-power computing MCU group, a shared Flash memory connecting all MCUs via a high-speed QSPI interface, and an NB-IoT communication module connected to the management MCU. The management MCU preferably uses a microcontroller based on an ARM Cortex-M7 core and is responsible for global system coordination, data aggregation, environmental perception, algorithm decision-making, and communication control. The high-performance computing MCU group consists of multiple MCUs with strong computing power, such as chips using Cortex-M4 or Cortex-M7 cores. These MCUs have hardware floating-point units and high clock frequencies, making them suitable for handling computationally intensive or high-real-time tasks, such as fast Fourier transform of vibration signals and complex filtering algorithms for strain data. The low-power computing MCU group consists of multiple MCUs focused on low-power operation, such as chips using Cortex-M0+ cores. These have lower operating frequencies and significantly lower static and dynamic power consumption than the high-performance MCUs, making them suitable for handling periodic, lightweight computing tasks, such as data averaging, simple threshold judgment, and data format encapsulation. A shared high-speed QSPI interface is used. Flash serves as a unified data center, providing shared data storage and exchange space for all MCUs. Its capacity can be selected according to actual monitoring needs, such as 128Mb or 256Mb, thereby avoiding complex and inefficient data transfer operations between multiple MCUs. The NB-IoT communication module is responsible for reporting the final data packets of edge processing to the remote cloud monitoring platform in a low-power wide area network manner.

[0023] like Figure 1 As shown, the system's task scheduling and execution process includes five main stages. The first stage is data acquisition and temporary storage. Specifically, various sensors deployed at key parts of the bridge, such as strain gauges, accelerometers, and temperature and humidity sensors, continuously generate raw monitoring data. This data is aggregated to the management MCU via interfaces such as SPI, I2C, or UART. The management MCU has multiple levels of circular buffers for real-time temporary storage of these data streams. When data flows in, the management MCU dynamically generates a header tag for each data block based on the data generation characteristics and business importance of each sensor. For example, for a bridge vibration acceleration sensor with a sampling rate of 100Hz, its data is assigned a high urgency level; while for an environmental temperature and humidity sensor that samples once per minute, its data is assigned a low urgency level. The header tag includes at least the data acquisition sequence number, the sensor's unique ID, and the data urgency level.

[0024] Subsequently, the Direct Memory Access Controller (DMA) managing the MCU adaptively selects the transfer strategy from the internal buffer to the designated data area of ​​the shared QSPI Flash based on the urgency level of the data blocks. For high-urgency data, the DMA controller adopts a single-interrupt triggered small-batch continuous transfer mode, with each data block size set to 512 bytes to minimize write latency and ensure the rapid availability of critical data. For low-urgency data, a batch aggregation transfer mode is adopted, which waits for the buffer to accumulate 4KB of data or reaches a time window such as 5 seconds before transferring a large block of data at once. This optimizes the number of writes to the Flash memory, improves storage space utilization, and enhances overall transfer efficiency. During the transfer process, the DMA controller synchronously generates a simplified fast verification sequence based on the 32-bit cyclic redundancy check principle for each data block to be written. This verification sequence is appended to the end of the data block and written to the Flash along with the data content, providing a fast integrity verification capability for the subsequent MCU to read the data.

[0025] The second stage involves system state awareness and dynamic adjustment of optimization weights. The management MCU connects to the battery power monitoring circuit via its built-in ADC channel to periodically sample the system's remaining battery power. Simultaneously, it accesses digital temperature sensors distributed near each MCU via the I2C bus to obtain the junction temperature of each MCU. The sampling period is set to 10 seconds. These sampled values ​​are stored in their corresponding historical data sequences. To eliminate instantaneous fluctuations, a time-window-based moving average is calculated on the battery power history sequence, with the time window length set to 10 periods (100 seconds) to obtain a smoothed, stable power value. For the temperature history sequence, a first-order hysteresis filtering algorithm is used with a filtering coefficient of 0.2 to eliminate measurement spikes and obtain a stable temperature value. The dynamic adjustment strategy is based on these two stable values. First, the stable power value is compared with three preset power decrease threshold intervals: the high power interval is... The battery level is categorized into three ranges: above 50%, medium range (20%-50%), and low range (below 20%). Based on the battery level range, a pre-defined mapping table is used to adjust the base magnitude of the energy consumption weighting factor. For example, in the high range, the base magnitude increase is 0; in the medium range, it's 0.1; and in the low range, it's 0.3. This indicates that the lower the system battery level, the more the scheduling strategy favors energy saving. Next, the stable temperature value is compared to a preset high-temperature threshold, which can be set to 80℃. If the stable temperature of a certain MCU exceeds this threshold, a compensation coefficient is calculated based on the percentage exceeding it. For example, if it exceeds by 10%, the compensation coefficient is 0.05; if it exceeds by 20%, the compensation coefficient is 0.1. This compensation coefficient is used to temporarily reduce the magnitude of the latency weighting factor, aiming to alleviate system load by reducing the pursuit of computing speed, thereby mitigating temperature rise.

[0026] The final weight adjustment is completed through an overlay operation logic. If the system is in the high power range, the base amplitude obtained based on the power level is used as the main adjustment basis and directly applied to the increase of the energy consumption weight factor, while the temperature compensation coefficient only has a half-amplitude effect on the delay weight factor, that is, the final reduction of the delay weight factor is 0.5 times the compensation coefficient. If the system is in the medium power range, the base amplitude and the compensation coefficient are algebraically added, and then the sum is applied to the increase of the energy consumption weight factor and the decrease of the delay weight factor respectively, to achieve an equal and reverse adjustment. If the system is in the low power range, a protective adjustment mode is activated: first, the base amplitude is amplified by a preset multiple. The delay weight factor is adjusted by a factor of 1.5, for example, as the dominant adjustment amount. Simultaneously, the effective ratio of the compensation coefficient is dynamically calculated based on the frequency with which the current stable temperature value exceeds the high-temperature threshold in recent sampling periods. For example, if there are 3 over-temperature occurrences in the last 10 periods, the effective ratio is 0.3. The final reduction in the delay weight factor equals the compensation coefficient multiplied by this effective ratio. In all adjustment scenarios, the management MCU ensures that the sum of the adjusted delay weight factor and the energy consumption weight factor is strictly equal to 1, thus constraining the multi-objective optimization problem within a unified weight framework for dynamic trade-offs. After adjustment, the delay weight factor ω1 and the energy consumption weight factor ω2 are updated.

[0027] The third stage is task offloading decision generation based on particle swarm optimization (PSO). The management MCU runs the PSO algorithm, which aims to find the optimal offloading scheme for a set of k computational tasks, i.e., to determine whether each task should be assigned to the high-performance MCU group or the low-power MCU group. The position vector V[i] of each particle is a candidate decision scheme; it is a k-dimensional vector where each dimension takes the value 0 or 1, where 0 represents assigning the corresponding task to the low-power group and 1 represents assigning it to the high-performance group. The comprehensive fitness function used by the PSO algorithm is used to calculate the total system cost corresponding to any decision scheme, and its expression is: ;in, As a weighted latency cost, The weighted energy cost is penalty(V), which is the queuing penalty.

[0028] For a given position vector, the management MCU first resolves the target MCU group to which each task is assigned; the latency cost is estimated based on the task's computational load and the target MCU group's basic computing power; assuming the characteristics of each task i are (B i ,f i ), where B i f represents the amount of data to be processed, in kilobits. i To calculate density, i.e., the number of clock cycles required to process each bit of data; the average clock frequency of the target MCU group is f. mcu The sum of the estimated computation times for all tasks constitutes the basic latency cost T.base =Σ(B i *f i / f mcu To simulate the additional queuing delays that may be caused by uneven load distribution, a difference coefficient α is introduced; let N be the number of tasks assigned to the high-performance group in the decision scheme. h The number of tasks assigned to the low-power group is N. l The total number of tasks N = N h +N l The coefficient of difference α is defined as: when |N h -N l When | / N<=0.5, α=1; otherwise, α=1+2*(|N h -N l | / N-0.5) 2 This function has no effect during allocation balancing, but it nonlinearly amplifies the base delay cost in cases of severe imbalance; the adjusted delay cost is T. adjusted =T base *α.

[0029] The energy consumption cost is estimated based on the base power consumption of the MCU group where the task is located; the pre-stored unit computing power consumption P of the high-performance group is queried. h And low power group unit power consumption P l , where P h >P l Then the basic energy consumption cost E base =Σ(For high-performance group tasks: B) i *f i *P h For low-power group tasks: B i *f i *P l Weighted delay cost T total =ω1*T adjusted Weighted energy consumption cost E total =ω2*E base .

[0030] The queuing penalty (V) is used to explicitly prevent excessive task concentration on a particular type of MCU; the imbalance is calculated as U = |N h -N l | / N;Based on the total number of active MCUs M in the system, determine the load adjustment base B=sqrt(M); intermediate penalty value P1=U*B; the final queuing penalty term is P1*(1+U), which makes the penalty value exhibit a non-linear characteristic of accelerated growth with the increase of imbalance, strongly penalizing the scheme of excessive load concentration.

[0031] The MCU initializes a particle swarm, with each particle's position randomly generated and its velocity initialized to zero; the inertial weight W... p The learning factor is set to 0.8, and both the individual learning factor c1 and the group learning factor c2 are set to 1.5. In each iteration, the fitness value (V) of each particle is calculated, and the historical best position P of each particle is updated. best And the global optimal position G of the entire population best Then, the particle velocity X[i] and position V[i] are updated according to the standard PSO formula: ; After the update, each element in the position vector V[i] is rounded and corrected for out-of-bounds errors to ensure that its value is between 0 and 1. The convergence condition is set as follows: the fitness value corresponding to the global optimal position changes by less than one-thousandth in 20 consecutive iterations. When the convergence condition is met, the iteration terminates and the global optimal position vector at this time is output as the final task unloading decision vector.

[0032] The fourth stage is task instruction distribution and heterogeneous computing execution. The management MCU assembles a complete task unloading instruction for each task based on the obtained task unloading decision vector. This instruction includes the starting address of the task data in the shared QSPIFlash, the data length, a globally unique task identifier, and the target MCU group code. The instruction sending method differs depending on the target group. For high-performance computing MCU groups, the management MCU sends the task unloading instruction to all MCUs in the group at once via multicast communication, such as using a CAN bus or parallel GPIO to simulate broadcasting. After receiving the instruction, the MCUs in the group compete autonomously based on their current busy / idle status, and the first MCU to respond acquires the task. For MCUs in deep sleep, the management MCU sends a pulse signal with a specific wake-up token via a dedicated hardware wake-up line. The wake-up token is an 8-bit random number bound to the task identifier in the task unloading instruction.

[0033] After the target MCU is woken up or activated, it first sends an acknowledgment signal containing the wake-up token to the management MCU via UART to establish a reliable communication link. Subsequently, according to the received task unload instruction, the target MCU directly reads a data block of the corresponding length from the specified starting address of the shared Flash via the QSPI interface, and performs integrity verification using the fast check sequence attached to the end of the data block. After successful verification, the MCU begins to execute calculations. During execution, the target MCU marks its running status, including the task identifier and the status code 0xAA indicating "calculating", and writes it in real time to a dedicated status record area in the shared Flash, which facilitates the management MCU to monitor the task execution progress globally. After the calculation is completed, the target MCU writes the calculation result to the pre-allocated result storage area in the shared Flash, updates the corresponding task marker in the status record area to the "complete" status code 0x55, and finally sends a task completion notification containing the task identifier to the management MCU via interrupt or polling.

[0034] The fifth stage is result aggregation and reporting. After receiving notification that all related tasks have been completed, or after waiting for a preset timeout period, such as 1.5 times the maximum estimated calculation time for all tasks, the management MCU confirms that all batch calculation tasks have been completed. Subsequently, the management MCU controls the NB-IoT communication module to read all calculation result data from the shared Flash result storage area in the order of task identifiers, and assembles them into a final result data packet that conforms to the cloud platform access protocol format. Finally, the management MCU reports the result data packet to the remote cloud platform through the NB-IoT module, completing the entire process of edge computing and data reporting.

[0035] This method provides a hardware foundation for performance and power consumption through a heterogeneous hardware architecture, achieves adaptation to harsh operating conditions through a dynamic weight adjustment mechanism based on environmental and power feedback, and realizes intelligent task offloading and load balancing under multiple constraints such as latency and energy consumption by combining a PSO optimization algorithm with queuing penalties.

[0036] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A design and task scheduling method for a heterogeneous multi-MCU architecture for edge computing, characterized in that, The MCU architecture includes at least one management MCU as a task management node, at least one high-performance computing MCU group, at least one low-power computing MCU group, a shared high-speed QSPI Flash connecting all MCUs, and an NB-IoT communication module connected to the management MCU. The task scheduling method includes the following steps: S1. By aggregating raw data from multiple sensors through the management MCU, and by transferring the raw data to a designated data area of ​​the shared high-speed QSPI Flash through the direct memory access (DMA) controller of the management MCU; S2. The remaining battery power and temperature of at least one MCU are obtained in real time by managing the MCU; the time delay weight factor and energy consumption weight factor in the comprehensive fitness function used for task unloading decision are dynamically adjusted according to whether the remaining battery power is lower than a preset low power threshold and whether the temperature exceeds a preset high temperature threshold. S3. By managing the MCU to run the Particle Swarm Optimization (PSO) algorithm, a task offloading decision vector is generated based on the latency weighting factor and the energy consumption weighting factor. The comprehensive fitness function of the PSO algorithm is used to calculate the total system cost, which is the sum of the weighted latency cost, the weighted energy consumption cost, and the queuing penalty term. The weighted latency cost and the weighted energy consumption cost are weighted using the latency weighting factor and the energy consumption weighting factor dynamically adjusted in S2, respectively. The queuing penalty term imposes an additional cost on the decision scheme that excessively concentrates computational tasks on any one MCU. S4. The management MCU sends a task unloading instruction containing a data address to the target MCU in the high-performance computing MCU group or the low-power computing MCU group according to the task unloading decision vector; after the target MCU is woken up, it reads data from the specified data area of ​​the shared high-speed QSPI Flash according to the task unloading instruction, performs calculations, writes the results back to the result storage area of ​​the shared high-speed QSPI Flash, and sends a task completion notification to the management MCU. S5. After confirming the completion of the associated task, the management MCU controls the NB-IoT communication module to read the final result data packet from the result storage area of ​​the shared high-speed QSPI Flash, and reports it to the cloud platform through the NB-IoT communication module.

2. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 1, characterized in that: S1 includes: S11. When the management MCU collects raw data from multiple sensors, it temporarily stores the raw data in real time in its internal multi-level circular buffer, and assigns dynamic header tags to data blocks according to the data generation rate and data type of each sensor. The header tags include data acquisition sequence number, sensor unique identifier and data urgency level. S12. The DMA controller managing the MCU adaptively selects the transfer mode from the multi-level circular buffer to the designated data area of ​​the shared high-speed QSPI Flash based on the data urgency level in the header mark. For high-urgency data, a small batch continuous transfer write delay triggered by a single interrupt is used, and for low-urgency data, batch aggregation transfer is used to optimize storage space utilization. S13. During the transmission process, the DMA controller synchronously generates and appends a fast check sequence based on bit operations for each transmitted data block. This fast check sequence is written together with the data block into a designated data area of ​​the shared high-speed QSPI Flash.

3. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 1, characterized in that: S2 includes the following steps: S21. Manage the remaining battery power of the MCU timing sampling system and the temperature of each MCU, and store them into the corresponding historical data sequence; S22. Perform a time-window-based moving average calculation on the battery power data in the historical data sequence to smooth out instantaneous fluctuations, and use hysteresis filtering on the temperature data in the historical data sequence to eliminate measurement spikes, thereby obtaining stable power values ​​and stable temperature values ​​for decision-making. S23. The stable power value is compared with a number of preset power decrease threshold intervals, and the base magnitude of the energy consumption weight factor is increased according to the interval it falls into. S24. Compare the stable temperature value with a preset high temperature threshold. If the threshold is exceeded, calculate a compensation coefficient to temporarily reduce the amplitude of the delay weight factor based on the percentage of exceedance. S25. The base amplitude obtained in S23 is superimposed with the compensation coefficient obtained in S24 to generate the final synchronous adjustment values ​​of the time delay weight factor and the energy consumption weight factor, so that the two can be dynamically adjusted under the premise that the weight sum remains unchanged.

4. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 3, characterized in that: The superposition operation in step S25 is as follows: S251. The management MCU determines the system's current power range based on a stable power value; S252. If it is in the high power range, the basic amplitude of the energy consumption weight factor will be used as the main adjustment basis, and the compensation coefficient will only have a half amplitude effect on the delay weight factor. S253. If it is in the medium power range, the basic amplitude and the compensation coefficient are algebraically added and applied to the energy consumption weight factor and the time delay weight factor for equal and reverse adjustment respectively. S254. If in a low power range, activate the protective adjustment mode: amplify the base amplitude by a preset multiple as the dominant adjustment amount of the energy consumption weight factor, and then dynamically calculate the effective ratio of the compensation coefficient based on the frequency of the current stable temperature value exceeding the high temperature threshold in the most recent multiple sampling periods, and reduce the time delay weight factor according to this ratio. S255. In all intervals, the management MCU ensures that the sum of the adjusted delay weight factor and the energy consumption weight factor is equal to the sum of the weights before adjustment, and applies the final adjusted value to the comprehensive fitness function.

5. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 1, characterized in that: S3 includes: S31. The management MCU executes the PSO algorithm. The position vector of each particle is a decision scheme. The value of each dimension represents a binary decision to allocate a computing task to a high-performance computing MCU group or a low-power computing MCU group. S32. For each particle, the management MCU calculates the weighted delay cost and weighted energy cost corresponding to its position vector based on the adjusted delay weight factor and energy consumption weight factor; at the same time, the management MCU calculates the queuing penalty term based on the number of tasks assigned to each MCU in the decision-making scheme. S33. Add the weighted delay cost, weighted energy cost and queuing penalty term to obtain the total system cost of the particle, and update the particle's own historical best position and the global best position of the particle swarm accordingly. S34. Based on the particle's own historical best position and global best position, iteratively update the position vector of each particle according to the speed and position update rules of the PSO algorithm, and perform rounding and out-of-bounds correction on each element value in the vector after each update. S35. When the iteration process causes the fitness value corresponding to the global optimal position to no longer decrease, the iteration terminates, and the vector of the global optimal position at this time is output as the final task unloading decision vector.

6. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 5, characterized in that: The calculation of the weighted latency cost and weighted energy consumption cost corresponding to the location vector is as follows: the management MCU parses the target MCU group to which each computing task is assigned based on the location vector, and estimates the computing completion time of each task on any MCU in the corresponding group. For the calculation of weighted latency cost, the management MCU uses the sum of the estimated completion times of all tasks under the decision scheme as the base latency cost. Then, a difference coefficient is introduced, which is determined by the proportion of tasks allocated to the target MCU group. When the proportion is unbalanced, this difference coefficient nonlinearly amplifies the base latency cost. For the calculation of weighted energy consumption cost, based on the type of the target MCU group to which each task belongs, the pre-stored base power consumption values ​​of the high-performance group and the low-power group are queried. The sum of the base power consumption values ​​of all tasks under the decision scheme is used as the base energy consumption cost. The management MCU multiplies the base latency cost and base energy cost, after adjusting the difference coefficients, by the adjusted latency weighting factor and energy weighting factor, respectively, to obtain the final weighted latency cost and weighted energy cost.

7. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 5, characterized in that: The specific calculation of the queuing penalty term involves: managing the MCU to parse the particle position vectors and counting the total number N of tasks assigned to the high-performance computing MCU group. h The total number N of tasks assigned to the low-power computing MCU group l And calculate the total number of tasks N=N h +N l ; Calculate the imbalance U between the two task assignments, the calculation process is U=|N h -N l | / N, where the U value is between 0 and 1; the management MCU determines a load adjustment base B related to the system size based on the total number M of currently active MCUs in the system, where B is set as the square root of M; Multiplying U by the load adjustment base B yields the intermediate penalty value P1 = U × B; the queuing penalty term is obtained by multiplying the intermediate penalty value P1 by an amplification factor based on the imbalance degree U, where the amplification factor is (1 + U), so that the final penalty term is P1 × (1 + U), making the penalty value exhibit a non-linear growth characteristic as the imbalance degree increases.

8. The edge computing heterogeneous multi-MCU architecture design and task scheduling method according to claim 1, characterized in that, S4 includes the following steps: S41. The management MCU assembles a task unloading instruction for each task to be unloaded based on the task unloading decision vector. The task unloading instruction contains the starting address of the task data in the shared high-speed QSPI Flash, the data length, the task unique identifier, and the target MCU group code. S42. Based on the target MCU group, send the task offload command in a time-sharing manner: for the high-performance computing MCU group, send it to all MCUs in the group via multicast; for the low-power computing MCU group, send it through its corresponding wake-up line, and attach a wake-up token bound to the unique identifier of the task in the task offload command. S43. After the target MCU is woken up or activated from a low-power state, it sends an acknowledgment signal containing the wake-up token to the management MCU, and then reads data of the corresponding length directly from the specified starting address of the shared high-speed QSPI Flash according to the received task unload instruction; S44. When the target MCU performs calculations, it writes its running status flag into a dedicated status record area in the shared high-speed QSPI Flash. This flag includes a unique task identifier and a status code in progress. S45. After the target MCU completes the calculation, it writes the result to the result storage area, updates the corresponding task marker in the status record area to complete, and finally sends a task completion notification containing the task's unique identifier to the management MCU.

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