Method of using adaptive loop filter and system thereof

Abstract

The invention provides a video data processing method. The method comprises the following steps: receiving a bit stream; decoding the bit stream to obtain a first index; determining a maximum number of adaptive loop filters (ALFs) of components of the picture based on the first index; and processing the pixels in the picture by utilizing the ALF.

Description

Methods and systems using adaptive loop filters

[0001] This application is a divisional application of Chinese patent application No. 2021800700670, filed on November 29, 2021, entitled "Method and System Using Adaptive Loop Filter". Technical Field

[0002] This disclosure relates to the field of video processing, and more particularly to systems and methods for using adaptive loop filters (ALFs) in video encoding and decoding. Background Technology

[0003] Video is a set of still images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, the most common being prediction, transform, quantization, entropy coding, and loop filtering. Video coding standards, developed by standardization organizations, specify particular video coding formats; examples include the High Efficiency Video Coding (HEVC / H.265) standard, the Versatile Video Coding (VVC / H.266) standard, and the Audio Video Coding Standard (AVS) standard. As more and more advanced video coding technologies are adopted by video standards, the coding efficiency of new video coding standards is also increasing. Summary of the Invention

[0004] Embodiments of this disclosure provide a video data processing method, the method comprising: receiving a bitstream; decoding a first index from the bitstream; determining a maximum number of adaptive loop filters (ALFs) for the components of an image based on the first index; and processing pixels in the image using the ALFs.

[0005] Embodiments of this disclosure provide an apparatus for performing video data processing, the apparatus comprising: a memory configured to store instructions; and one or more processors configured to execute instructions to cause the apparatus to perform: receiving a bitstream; decoding a first index from the bitstream; determining a maximum number of adaptive loop filters (ALFs) for the components of an image based on the first index; and processing pixels in the image using the ALFs.

[0006] Embodiments of this disclosure provide a non-volatile computer-readable storage medium storing a set of instructions executable by one or more processors of a device to initiate a video data processing method. The method includes: receiving a bitstream; decoding a first index from the bitstream; determining a maximum number of adaptive loop filters (ALFs) for the components of an image based on the first index; and processing pixels in the image using the ALFs.

[0007] Embodiments of this disclosure provide a non-volatile computer-readable medium for storing a bitstream including a first index associated with video data, the first index being encoded based on one or more of a plurality of contexts used in binary entropy coding, and indicating the maximum number of adaptive loop filters (ALFs) for the components of the image. Attached Figure Description

[0008] Embodiments and corresponding aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.

[0009] Figure 1 is a schematic diagram of the structure of an example video sequence according to Embodiment 1 of this disclosure.

[0010] Figure 2A is a schematic diagram of an exemplary encoding process of a hybrid video encoding system according to Embodiment 1 of this disclosure.

[0011] Figure 2B is a schematic diagram of another exemplary encoding process of a hybrid video encoding system according to Embodiment 1 of this disclosure.

[0012] Figure 3A is a schematic diagram of an exemplary decoding process of a hybrid video coding system according to Embodiment 1 of this disclosure.

[0013] Figure 3B is a schematic diagram of another exemplary decoding process of a hybrid video coding system according to Embodiment 1 of this disclosure.

[0014] Figure 4 is a block diagram of an exemplary apparatus for encoding or decoding video according to Embodiment 1 of this disclosure.

[0015] Figure 5A is a schematic diagram illustrating, according to Embodiment 1 of the present disclosure, the exemplary division of an image into 16 adaptive loop filter (ALF) regions.

[0016] Figure 5B is a schematic diagram showing the region order and region sequence number of each of the 16 ALF regions according to Embodiment 1 of this disclosure.

[0017] Figure 5C is a schematic diagram of an exemplary merged region shown according to Embodiment 1 of this disclosure.

[0018] Figure 6A is a schematic diagram illustrating the division of an image into more than 16 ALF regions according to Embodiment 1 of this disclosure.

[0019] Figure 6B is a schematic diagram illustrating the division of an image into more than 16 ALF regions according to Embodiment 1 of this disclosure.

[0020] Figure 6C is a schematic diagram illustrating the division of an image into more than 16 ALF regions according to Embodiment 1 of this disclosure.

[0021] Figure 7A is a schematic diagram of an exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0022] Figure 7B is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0023] Figure 7C is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0024] Figure 7D is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0025] Figure 8 is a schematic diagram of a flowchart for determining the region index of each sample according to Embodiment 1 of this disclosure.

[0026] Figure 9A is a schematic diagram of an exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0027] Figure 9B is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0028] Figure 9C is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0029] Figure 9D is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure.

[0030] Figure 10A is a schematic diagram of an exemplary ALF region order of 64 regions according to Embodiment 1 of this disclosure.

[0031] Figure 10B is a schematic diagram of another exemplary ALF region order of 64 regions shown according to Embodiment 1 of this disclosure.

[0032] Figure 10C is a schematic diagram of another exemplary ALF region order of 64 regions shown according to Embodiment 1 of this disclosure.

[0033] Figure 10D is a schematic diagram of another exemplary ALF region order of 64 regions shown according to Embodiment 1 of this disclosure.

[0034] Figure 11A is a schematic diagram of an exemplary ALF region order of 256 regions according to Embodiment 1 of this disclosure.

[0035] Figure 11B is a schematic diagram of another exemplary ALF region order of 256 regions shown according to Embodiment 1 of this disclosure.

[0036] Figure 11C is a schematic diagram of another exemplary ALF region order of 256 regions shown according to Embodiment 1 of this disclosure.

[0037] Figure 11D is a schematic diagram of another exemplary ALF region order of 256 regions shown according to Embodiment 1 of this disclosure.

[0038] Figure 12A is a schematic diagram of an exemplary ALF region order of 128 regions according to Embodiment 1 of this disclosure.

[0039] Figure 12B is a schematic diagram of another exemplary ALF region order of 128 regions shown according to Embodiment 1 of this disclosure.

[0040] Figure 12C is a schematic diagram of another exemplary ALF region order of 128 regions shown according to Embodiment 1 of this disclosure.

[0041] Figure 12D is a schematic diagram of another exemplary ALF region order of 128 regions shown according to Embodiment 1 of this disclosure. Detailed Implementation

[0042] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description is illustrated with reference to the accompanying drawings, wherein the same numbers in different drawings denote the same or similar elements unless otherwise stated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with aspects of the invention as described in the appended claims. Specific aspects of this disclosure are described in more detail below. In the event of any conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0043] The Audio and Video Coding Standard (AVS) Working Group was established in China in 2002 and is currently developing the AVS video standard, specifically the third-generation AVS3 video standard. AVS3's predecessors, AVS1 and AVS2, were released in China in 2006 and 2016, respectively. In December 2017, the AVS Working Group issued a Call for Proposals (CFP) to officially launch the development of the third-generation AVS standard, AVS3. In December 2018, the High Performance Model (HPM) was selected by the working group as the new reference software platform for AVS3 standard development. HPM initially inherited the technology of the AVS2 standard, and on this basis, more and more advanced video coding technologies are used to improve compression performance. For example, in 2019, the first phase of the AVS3 standard was completed, achieving a coding performance improvement of over 20% compared to its predecessor, AVS2. The second phase of the AVS3 standard is still being developed based on the first phase to further improve coding efficiency.

[0044] The AVS3 standard is a recent development that continues to include more coding techniques that provide better compression performance. AVS3 is based on the same hybrid video coding system used in modern video compression standards such as AVS1, AVS2, H.265 / HEVC, H.264 / AVC (Advanced Video Coding), MPEG2, H.263, etc.

[0045] Video is a set of still images (or "frames") arranged in chronological order to store visual information. Video capture devices (e.g., cameras) can be used to capture and store these images in chronological order, and video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display) can be used to display these images in chronological order. Furthermore, in some applications, video capture devices can transmit captured video in real time to video playback devices (e.g., computers with displays), for example, for monitoring, conferencing, or live streaming.

[0046] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process embedded in a computer-readable medium. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, H.26x, AVS series, etc. In some applications, a codec can decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard. In this case, the codec can be called a "code converter".

[0047] Video encoding processes identify and retain useful information that can be used to reconstruct images, while ignoring information that is not important for reconstruction. If the ignored, unimportant information cannot be fully reconstructed, such an encoding process can be called "lossy"; otherwise, it can be called "lossless." Most encoding processes are "lossy," a trade-off to reduce required storage space and transmission bandwidth.

[0048] Useful information in the image being encoded (referred to as the "current image") can include changes relative to a reference image (e.g., a previously encoded and reconstructed image). These changes can include variations in pixel position, brightness, or color, with positional changes being the most important. The positional changes of a set of pixels representing an object can reflect the object's movement between the reference image and the current image.

[0049] Generally, an image encoded without referencing another image (i.e., the image is its own reference image) is called an "I-image"; if some or all of the blocks in an image (e.g., blocks that are typically part of a video image) are obtained using intra-frame prediction or inter-frame prediction (e.g., one-way prediction) with a reference image, the image is called a "P-image"; if at least one block in an image is predicted using two reference images (e.g., two-way prediction), the image is called a "B-image".

[0050] Figure 1 is a schematic diagram of the structure of an example video sequence according to Embodiment 1 of this disclosure, wherein the video sequence 100 may be a live video or a video that has been captured and archived, or it may be a real-life video, a computer-generated video (e.g., a computer game video) or a combination thereof (e.g., a real-life video with augmented reality effects), or it may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., a video file stored in a storage device), or a video feed interface (e.g., a video broadcast transceiver) to receive video from a video content provider.

[0051] As shown in Figure 1, the video sequence 100 may include a series of images arranged chronologically along a timeline, including images 102, 104, 106, and 108. Images 102-106 are consecutive, and there may be more images between images 106 and 108. In Figure 1, image 102 is an I-image, with its reference image being image 102 itself; image 104 is a P-image, as indicated by the arrow, with its reference image being image 102; and image 106 is a B-image, as indicated by the arrow, with its reference images being images 104 and 108. In some embodiments, the reference image of an image (e.g., image 104) may not be adjacent to that image; for example, the reference image of image 104 may be an image preceding image 102. It should be noted that the reference images of images 102-106 are merely examples, and this disclosure does not limit the embodiments of the reference images to the examples shown in Figure 1.

[0052] Typically, due to the high computational complexity of video encoding and decoding, video codecs do not encode or decode the entire image at once. Instead, they segment the image into basic segments and encode or decode each segment sequentially. In this disclosure, such basic segments are referred to as Basic Processing Units (BPUs). For example, structure 110 in Figure 1 illustrates an example structure of images from video sequence 100 (e.g., any of images 102 to 108). In structure 110, the images are divided into 4×4 basic processing units, the boundaries of which are shown by dashed lines. In some embodiments, the basic processing unit may be referred to as a "macroblock" in some video coding standards (e.g., MPEG series, H.261, H.263, or H.264 / AVC), or as a "Coding Tree Unit" (CTU) in some other video coding standards (e.g., H.265 / HEVC, H.266 / VVC, AVS). Basic processing units in an image can have variable sizes, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing units for an image can be selected based on a balance between encoding efficiency and the level of detail to be preserved within the basic processing units.

[0053] A basic processing unit can be a logical unit that may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may include a luminance component (Y) representing non-color luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, wherein the size of the luminance and chrominance components may be the same as the size of the basic processing unit. In some video coding standards (e.g., H.265 / HEVC, H.266 / VVC, AVS), the luminance and chrominance components may be referred to as "Coding Tree Blocks" (CTBs), and any operation performed on a basic processing unit may be repeated on each of its luminance and chrominance components.

[0054] The video encoding process has multiple operational stages, examples of which are shown in Figures 2A-2B and 3A-3B. For each stage, the size of the basic processing unit may still be too large to process, so the basic processing unit can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG series, H.261, H.263, or H.264 / AVC), or as a "coding unit" (CU) in some other video coding standards (e.g., H.265 / HEVC, H.266 / VVC, AVS). The size of the basic processing subunit may be less than or equal to the size of the basic processing unit. Similar to the basic processing unit, the basic processing subunit is also a logical unit and may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on the basic processing subunit may be repeatedly performed on each of its luminance and chrominance components. It should be noted that the basic processing sub-units can be further subdivided according to processing requirements to obtain smaller units. It should also be noted that different schemes can be used to divide the basic processing units at different stages.

[0055] For example, in the mode decision stage (an example of which is shown in Figure 2B), the encoder may decide which prediction mode (e.g., intra-frame image prediction or inter-frame image prediction) to use for the basic processing unit. However, if the basic processing unit is large, it may cause the encoder to be unable to make this decision. In this case, the encoder may divide the basic processing unit into multiple basic processing sub-units (e.g., CUs in H.265 / HEVC, H.266 / VVC, and AVS) and then decide the prediction mode for each basic processing sub-unit separately.

[0056] For example, during the prediction phase (examples of which are shown in Figures 2A-2B), the encoder can perform prediction operations on basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large for the encoder to perform prediction operations. In such cases, the encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC, H.266 / VVC, and AVS), and then perform prediction operations on these smaller segments.

[0057] For example, in the transformation phase (examples of which are shown in Figures 2A-2B), the encoder can perform transformation operations on the remaining basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large for the encoder to perform transformation operations. In this case, the encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC, H.266 / VVC, and AVS), and then perform transformation operations on these smaller segments. It should be noted that the partitioning scheme of the same basic processing subunits can be different in the prediction and transformation phases. For example, in H.265 / HEVC, H.266 / VVC, or AVS, the prediction blocks and transform blocks of the same CU can be configured with different sizes and numbers.

[0058] In the structure 110 of Figure 1, the basic processing unit 112 is further divided into 3×3 basic processing sub-units with boundaries shown by dashed lines. Different partitioning schemes can be used to divide different basic processing units into multiple basic processing sub-units.

[0059] In some implementations, to provide parallel processing and error recovery capabilities for video encoding and decoding, an image can be divided into one or more regions for processing. This allows the encoder or decoder to process these regions independently, without relying on information from any other region of the image. In other words, each region of the image can be processed independently, meaning the codec can process different regions of the image in parallel, thereby improving encoding efficiency. Furthermore, when data in a region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without relying on the corrupted or lost data, thus ensuring the codec's error recovery capability. In some video coding standards, an image can be divided into different types of regions. For example, H.265 / HEVC, H.266 / VVC, and AVS provide two types of regions: "slices" and "tiles." It should also be noted that different segmentation schemes can be used to segment different images, such as different images in video sequence 100, to obtain multiple regions.

[0060] For example, in Figure 1, structure 110 is divided into three regions 114, 116, and 118, whose boundaries are shown as solid lines within structure 110. Region 114 includes four basic processing units, while regions 116 and 118 each include six basic processing units. It should be noted that the basic processing units, basic processing subunits, and regions of structure 110 in Figure 1 are merely examples, and this disclosure does not limit its embodiments.

[0061] Figure 2A is a schematic diagram of an exemplary encoding process of a hybrid video coding system according to Embodiment 1 of this disclosure. For example, encoding process 200A can be performed by an encoder. As shown in Figure 2A, the encoder can encode video sequence 202 into video bitstream 228 according to process 200A. Similar to video sequence 100 in Figure 1, video sequence 202 may include a set of pictures (referred to as "raw pictures") arranged in chronological order. Similar to structure 110 in Figure 1, each raw picture of video sequence 202 can be divided by the encoder into basic processing units, basic processing subunits, or processing regions. In some embodiments, the encoder can perform process 200A for each basic processing unit of raw picture of video sequence 202. For example, the encoder can perform process 200A iteratively, wherein the encoder can encode the basic processing unit in one iteration of process 200A. In some embodiments, the encoder can perform process 200A in parallel for regions (e.g., regions 114-118) of each raw picture of video sequence 202.

[0062] In Figure 2A, the encoder can feed the basic processing unit (referred to as the "raw BPU") of the original image of the video sequence 202 to the prediction stage 204 to generate prediction data 206 and prediction BPU 208. Then, the prediction BPU 208 is subtracted from the raw BPU to generate the residual BPU 210. The residual BPU 210 is fed to the transform stage 212 and the quantization stage 214 to generate the quantized transform coefficients 216. Finally, the prediction data 206 and the quantized transform coefficients 216 are fed to the binary encoding stage 226 to generate the video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 in Figure 2A can be referred to as the "forward path." During process 200A, after quantization stage 214, the encoder can feed the quantized transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate a reconstructed residual BPU 222. The reconstructed residual BPU 222 is then added to prediction BPU 208 to generate a prediction reference 224, which is used in the prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A can be referred to as the "reconstruction path," which can be used to ensure that the encoder and decoder use the same reference data for prediction.

[0063] The encoder can iteratively execute process 200A to encode each original BPU of the original image (in the forward path) and generate a prediction reference 224 for encoding the next original BPU of the original image (in the reconstruction path). After encoding all the original BPUs of the original image, the encoder can continue encoding the next image in the video sequence 202.

[0064] Referring to process 200A, the encoder may receive a video sequence 202 generated by a video capture device (e.g., a camera). As used herein, the term "receive" may refer to any action in any manner of receiving, inputting, acquiring, retrieving, obtaining, reading, accessing, or using data for input.

[0065] In prediction phase 204, during the current iteration, the encoder can receive the original BPU and prediction reference 224 and perform prediction operations to generate prediction data 206 and prediction BPU 208. Prediction reference 224 can be generated from the reconstruction path of a previous iteration of process 200A. The purpose of prediction phase 204 is to reduce information redundancy by extracting prediction data 206, making the prediction data usable for reconstructing the original BPU into prediction BPU 208 based on prediction data 206 and prediction reference 224.

[0066] Ideally, the predicted BPU 208 should be identical to the original BPU. However, since the prediction and reconstruction operations do not always achieve the desired results, the predicted BPU 208 is typically slightly different from the original BPU. To record this difference, after generating the predicted BPU 208, the encoder can subtract it from the original BPU to generate a residual BPU 210 to record the difference. For example, the encoder can subtract the pixel values ​​(e.g., grayscale or RGB values) of the predicted BPU 208 from the corresponding pixel values ​​of the original BPU. Each pixel of the residual BPU 210 can have a residual value as the result of this subtraction between the corresponding pixels of the original BPU and the predicted BPU 208. Compared to the original BPU, the predicted data 206 and the residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without significant quality degradation. Therefore, the space footprint can be reduced by compressing the original BPU.

[0067] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce its spatial redundancy by decomposing the residual BPU 210 into a set of two-dimensional "basic patterns" associated with "transform coefficients". The basic patterns can have the same size (e.g., the size of the residual BPU 210), can represent the frequency of change of the components of the residual BPU 210 (e.g., the frequency of brightness changes), and no basic pattern can be replicated from any combination of any other basic patterns (e.g., a linear combination). Since the basic patterns are analogous to the basis functions of the Discrete Fourier Transform (e.g., trigonometric functions), and the transform coefficients are analogous to the coefficients associated with the basis functions, the spatial redundancy of the residual BPU 210 can be reduced by decomposing the variations in the residual BPU 210 into the frequency domain using a decomposition method similar to the Discrete Fourier Transform.

[0068] Different transformation algorithms can use different base modes. Various transformation algorithms can be used in the transform stage 212, such as discrete cosine transform, discrete sine transform, etc. Since the transformation in transform stage 212 is reversible, the encoder can recover the residual BPU 210 through the inverse operation of the transform (called the "inverse transform"). For example, to recover the pixels of the residual BPU 210, the inverse transform can be to multiply the values ​​of the corresponding pixels in the base mode by the corresponding correlation coefficients and sum the products to produce a weighted sum. For video coding standards, the encoder and decoder can use the same transformation algorithm (and therefore the same base mode). Therefore, the encoder can only record the transform coefficients, and the decoder can reconstruct the residual BPU 210 based on these transform coefficients without receiving the base mode from the encoder. Compared to the residual BPU 210, the transform coefficients can have fewer bits but can be used to reconstruct the residual BPU 210 without significant quality degradation. Therefore, the residual BPU 210 is further compressed.

[0069] The encoder can further compress the transform coefficients in the quantization stage 214. During the transform process, different fundamental modes can represent different frequencies of change (e.g., brightness change frequencies). Because the human eye is generally better at recognizing low-frequency changes, the encoder can ignore information about high-frequency changes without significantly degrading the decoding quality. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called a "quantization scaling factor") and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of the high-frequency fundamental modes can be converted to zero, and the transform coefficients of the low-frequency fundamental modes can be converted to smaller integers. The encoder can ignore the zero-value quantized transform coefficients 216, further compressing the transform coefficients. The quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (called "inverse quantization").

[0070] Because the encoder ignores the remainder of such division during rounding, quantization stage 214 can be lossy. Typically, quantization stage 214 can cause the greatest information loss in process 200A. The greater the information loss, the fewer bits are needed for the quantization transform coefficients 216. To obtain different levels of information loss, the encoder can use different quantization parameter values ​​or any other parameter of the quantization process.

[0071] In the binary encoding stage 226, the encoder can encode the prediction data 206 and the quantized transform coefficients 216 using binary encoding techniques, such as entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the encoder may also encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the transform type in the transform stage 212, the parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. The encoder can use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 can be further packaged for network transmission.

[0072] Referring to the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder can perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In the inverse transform stage 220, the encoder can generate a reconstructed residual BPU 222 based on the reconstructed transform coefficients. The encoder can add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224 that will be used in the next iteration of process 200A.

[0073] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, the stages of process 200A can be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A can be combined into a single stage. In some embodiments, a single stage of process 200A can be divided into multiple stages. For example, transform stage 212 and quantization stage 214 can be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, one or more stages in FIG. 2A may be omitted from process 200A.

[0074] Figure 2B is a schematic diagram of another exemplary encoding process of a hybrid video coding system according to Embodiment 1 of this disclosure. Process 200B can be modified from process 200A, and encoders conforming to hybrid video coding standards (e.g., H.26x series) can use process 200B. Compared to process 200A, the forward path of process 200B additionally includes a mode decision stage 230, and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B also includes a loop filter stage 232 and a buffer 234.

[0075] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-frame image prediction or "intra-prediction") uses pixels from one or more already encoded neighboring BPUs within the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs to reduce inherent spatial redundancy in the image. Temporal prediction (e.g., inter-frame image prediction or "inter-prediction") uses regions from one or more already encoded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include encoded images to reduce inherent temporal redundancy in the image.

[0076] In reference process 200B, during the forward path, the encoder performs prediction operations in the spatial prediction phase 2042 and the temporal prediction phase 2044. For example, in the spatial prediction phase 2042, the encoder may perform intra-frame prediction. For the original BPU of the image being encoded, prediction reference 224 may include one or more adjacent BPUs in the same image that have been encoded (in the forward path) and reconstructed (in the reconstruction path). The encoder can generate a predicted BPU 208 by extrapolating adjacent BPUs. Extrapolation techniques may include, for example, linear extrapolation or interpolation, polynomial extrapolation or interpolation, etc. In some embodiments, the encoder may perform extrapolation at the pixel level, for example, by extrapolating the value of the corresponding pixel for each pixel of BPU 208. The adjacent BPU used for extrapolation can be positioned relative to the original BPU from various directions, such as vertical (e.g., at the top of the original BPU), horizontal (e.g., to the left of the original BPU), diagonal (e.g., to the lower left, lower right, upper left, or upper right of the original BPU), or any direction defined in the video coding standard used. For intra-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the adjacent BPU used, the size of the adjacent BPU used, the extrapolation parameters, the orientation of the adjacent BPU used relative to the original BPU, etc.

[0077] For example, in the temporal prediction stage 2044, the encoder can perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 may include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference image may be BPU encoded and reconstructed by the BPU; for example, the encoder may add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs of the same image are generated, the encoder may generate a reconstructed image as the reference image. The encoder may perform a "motion estimation" operation to search for matching regions within the range of the reference image (referred to as a "search window"), wherein the position of the search window may be determined based on the position of the original BPU in the current image; for example, the search window may be centered at a position in the reference image that has the same coordinates as the original BPU in the current image and may extend outward by a predetermined distance. When the encoder identifies a region similar to the original BPU within the search window (e.g., using a pixel recursive algorithm, block matching algorithm, etc.), it can define such a region as a matching region. The matching region may have a different size than the original BPU (e.g., smaller, equal to, greater than, or with a different shape). Because the reference image and the current image are temporally separated in the timeline (e.g., as shown in Figure 1), it can be assumed that the matching region can "move" to the location of the original BPU over time, and the encoder can record the direction and distance of this "movement" as a "motion vector." When using multiple reference images (e.g., image 106 in Figure 1), the encoder can search for matching regions and determine its associated motion vector for each reference image. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching region of the corresponding matching reference image.

[0078] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0079] To generate the predicted BPU 208, the encoder can perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU 208 based on the predicted data 206 (e.g., motion vectors) and the predicted reference 224. For example, the encoder can move a matching region of a reference image based on the motion vectors, where the encoder can predict the original BPU of the current image. When using multiple reference images (e.g., image 106 in Figure 1), the encoder can move the matching regions of the reference images based on the corresponding motion vectors and average pixel values ​​of the matching regions. In some embodiments, if the encoder has already assigned weights to the pixel values ​​of the matching regions of the corresponding matching reference images, the encoder can add the weighted sums of the pixel values ​​of the moved matching regions.

[0080] In some embodiments, inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same temporal direction relative to the current image. For example, if image 104 in FIG1 is a unidirectional inter-frame prediction image, then reference images (e.g., image 102) can be used before image 104. Bidirectional inter-frame prediction can use one or more reference images in two temporal directions relative to the current image. For example, if image 106 in FIG1 is a bidirectional inter-frame prediction image, then reference images (e.g., images 104 and 108) can be used in two temporal directions relative to image 104.

[0081] Referring again to the forward path of process 200B, after spatial prediction 2042 and temporal prediction stages 2044, in the mode determination stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform rate-distortion optimization techniques to select a prediction mode based on the bit rate of the candidate prediction modes and the distortion of the reference image reconstructed under the candidate prediction modes, in order to minimize the cost function value. Based on the selected prediction mode, the encoder can generate the corresponding prediction BPU 208 and prediction data 206.

[0082] In the reconstruction path of process 200B, if intra-prediction mode has been selected in the forward path, the encoder can directly feed prediction reference 224 to spatial prediction stage 2042 after generating prediction reference 224 (e.g., the current BPU that has already been encoded and reconstructed in the current picture) for later use (e.g., extrapolation for the next BPU of the current picture). The encoder can also feed prediction reference 224 to loop filter stage 232, where a loop filter is applied to prediction reference 224 to reduce or eliminate distortions (e.g., blockiness) introduced during the encoding of prediction reference 224. The encoder can also apply various loop filter techniques in loop filter stage 232, such as deblocking, adaptive sampling offset, adaptive loop filter (ALF), etc. The loop-filtered reference picture can be stored in buffer 234 (or "decoded picture buffer") for later use (e.g., as an inter-frame prediction reference picture for future pictures of video sequence 202). The encoder may also store one or more reference images in buffer 234 for use in the time prediction stage 2044. In some embodiments, the encoder may encode the parameters of the loop filter (e.g., loop filter strength), as well as the quantized transform coefficients 216, prediction data 206, and other information in the binary encoding stage 226.

[0083] Figure 3A is a schematic diagram of an exemplary decoding process of a hybrid video coding system according to Embodiment 1 of this disclosure, wherein process 300A may be a decompression process corresponding to compression process 200A in Figure 2A. In some embodiments, process 300A may also be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into a video stream 304 that is very similar to the video sequence 202d according to process 300A. However, due to information loss during compression and decompression (e.g., quantization stage 214 in Figures 2A-2B), video stream 304 is not the same as video sequence 202d. Similar to processes 200A and 200B in Figures 2A-2B, the decoder can perform process 300A on each image encoded in the video bitstream 228 in a basic processing unit (BPU). For example, the decoder can decode the basic processing unit in an iterative manner in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel on regions (e.g., regions 114-118) of each image encoded in the video bitstream 228.

[0084] In Figure 3A, the decoder can feed a portion of the video bitstream 228 associated with a basic processing unit (referred to as the "encoded BPU") of the encoded image to the binary decoding stage 302, then decode this portion into prediction data 206 and quantized transform coefficients 216, and feed the quantized transform coefficients 216 to the inverse quantization stage 218 and the inverse transform stage 220 to generate a reconstructed residual BPU 222. The decoder can also feed the prediction data 206 to the prediction stage 204 to generate a prediction BPU 208, and add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 can be stored in a buffer (e.g., a decoded image buffer in computer memory) or fed by the decoder to the prediction stage 204 for performing a prediction operation in the next iteration of process 300A.

[0085] The decoder can iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for encoding the next encoded BPU of the encoded image. After decoding all encoded BPUs of the encoded image, the decoder can output the image to video stream 304 for display and continue decoding the next encoded image in video bitstream 228.

[0086] In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder may also, in the binary decoding stage 302, perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm) to decode other information, such as the prediction mode, parameters of the prediction operation, transform type, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bitrate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted over the network in packets, the decoder may unpack the video bitstream 228 before feeding it to the binary decoding stage 302.

[0087] Figure 3B is a schematic diagram of another exemplary decoding process of a hybrid video coding system according to Embodiment 1 of this disclosure, wherein process 300B can be modified from process 300A, and decoders conforming to hybrid video coding standards (e.g., H.26x series) can use process 300B. Compared with process 300A, process 300B further divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and further includes a loop filter stage 232 and a buffer 234.

[0088] In process 300B, the decoder decodes the encoded image being decoded (referred to as the "current image") from binary decoding stage 302, and the resulting prediction data 206 can include various types of data, depending on what prediction mode the encoder uses to encode the current BPU. For example, if the encoder uses intra-frame prediction to encode the current BPU, the prediction data 206 may include an indicator of the intra-frame prediction mode (e.g., a flag value), parameters of the intra-frame prediction operation, etc., wherein the parameters obtained by the intra-frame prediction operation may include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, the sizes of neighboring BPUs, extrapolation parameters, the orientations of neighboring BPUs relative to the original BPU, etc.; if the encoder uses inter-frame prediction to encode the current BPU, the prediction data 206 may include an indicator of the inter-frame prediction mode (e.g., a flag value), parameters of the inter-frame prediction operation, etc., wherein the parameters obtained by the inter-frame prediction operation may include, for example, the number of reference images associated with the current BPU, the weights associated with the reference images respectively, the positions (e.g., coordinates) of one or more matching regions in the corresponding reference images, one or more motion vectors associated with the matching regions respectively, etc.

[0089] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra-frame prediction) in the spatial prediction stage 2042 or temporal prediction (e.g., inter-frame prediction) in the temporal prediction stage 2044. The details of performing such spatial or temporal prediction are shown in Figure 2B and will not be repeated below. After performing such spatial or temporal prediction, as shown in Figure 3A, the decoder can generate a prediction BPU 208 and add the prediction BPU 208 to the reconstructed residual BPU 222 to generate a prediction reference 224.

[0090] In process 300B, the decoder can feed prediction reference 224 to spatial prediction stage 2042 or temporal prediction stage 2044 for performing prediction operations in the next iteration of process 300B. For example, if intra-frame prediction is used to decode the current BPU at spatial prediction stage 2042, the decoder can feed prediction reference 224 directly to spatial prediction stage 2042 after generating prediction reference 224 (e.g., the decoded current BPU) for later use (e.g., for extrapolation of the next BPU for the current image); if inter-frame prediction is used to decode the current BPU at temporal prediction stage 2044, the decoder can feed prediction reference 224 to loop filter stage 232 after generating prediction reference 224 (e.g., a reference image where all BPUs have been decoded) to reduce or eliminate distortion (e.g., blockiness). The decoder can apply a loop filter to prediction reference 224 in the manner described in FIG2B. The loop-filtered reference image can be stored in buffer 234 (e.g., a decoded image buffer in computer memory) for later use (e.g., as an inter-frame prediction reference image for future encoded images of video bitstream 228). The decoder can store one or more reference images in buffer 234 for use in the temporal prediction stage 2044. In some embodiments, the prediction data may also include parameters of the loop filter (e.g., loop filter strength). In some embodiments, the prediction data may also include parameters of the loop filter when the prediction mode indicator of prediction data 206 indicates that inter-frame prediction is used to encode the current BPU.

[0091] Figure 4 is a block diagram of an exemplary apparatus for encoding or decoding video according to Embodiment 1 of this disclosure. As shown in Figure 4, apparatus 400 may include a processor 402. When the processor 402 executes the instructions described herein, apparatus 400 may become a dedicated machine for video encoding or decoding. The processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any combination of any number of Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Microcontroller Units (MCUs), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), systems-on-chips (SoCs), application-specific integrated circuits (ASICs), etc. In some embodiments, processor 402 may also be a group of processors grouped into individual logic components. For example, as shown in FIG4, processor 402 may include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0092] The device 400 may also include a memory 404 configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in FIG4, the stored data may include program instructions (e.g., program instructions for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). The processor 402 may access the program instructions and data for processing (e.g., via bus 410) and execute the program instructions to perform operations or manipulations on the data for processing. The memory 404 may include a high-speed random access memory device or a non-volatile memory device. In some embodiments, the memory 404 may include any combination of any number of random-access memory (RAM), read-only memory (ROM), optical disc, magnetic disk, hard disk, solid-state drive, flash drive, security digital (SD) card, memory stick, compact flash (CF) card, etc. Memory 404 can also be a group of memories grouped into individual logical components (not shown in Figure 4).

[0093] Bus 410 may be a communication device for transmitting data between components within device 400, such as an internal bus (e.g., CPU memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Fast Port), etc.

[0094] For ease of explanation and to avoid ambiguity, the processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. The data processing circuitry can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. Furthermore, the data processing circuitry can be a single, independent module, or it can be wholly or partially integrated into any other component of the device 400.

[0095] Device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, repeaters, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near-field communication (NFC) adapters, cellular network chips, etc.

[0096] In some embodiments, the device 400 may optionally include a peripheral interface 408 to provide connectivity to one or more peripheral devices. As shown in FIG4, peripheral devices may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces coupled to video archives), etc.

[0097] It should be noted that the video codec (e.g., the codec for executing processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instructions that can be loaded into memory 404. Similarly, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0098] An adaptive loop filter (ALF) is an in-loop filter (e.g., the loop filter 232 of H.266 / VVC in Figures 2B and 3B) that is applied to the reconstructed sample to further refine it and obtain the final decoded sample output by the decoder. The purpose of the ALF is to improve the quality of the reconstructed sample and reduce coding errors.

[0099] ALF introduces a Wiener filter in the encoding loop to minimize the mean square error between the original and decoded samples. The values ​​of the filtered samples are generated by taking a weighted average of the values ​​of the current unfiltered sample and the values ​​of its spatially adjacent unfiltered samples. The weights, called the filter coefficients, are determined by the encoder and explicitly sent to the decoder as signals.

[0100] Figure 5A is a schematic diagram illustrating an exemplary division of an image into 16 adaptive loop filter (ALF) regions according to Embodiment 1 of this disclosure. As shown in Figure 5A, for example in AVS3, to adapt the filters to the content, the entire image is divided into 16 regions (4 columns × 4 rows), and each region has an index that identifies that region. Different regions can have different filters (e.g., different sets of coefficients) within the 16 regions. Therefore, for a single image, a maximum of 16 signals can be sent to the filters (e.g., 16 sets of coefficients), meaning that these sets of coefficients can be sent to the filters one after another in the order of the regions. Since a filter is generally applied to one region, the ALF index for each region can be easily determined.

[0101] Figure 5B is a schematic diagram of the region order and region sequence number of each of the 16 ALF regions shown in Embodiment 1 of this disclosure. The curve shows the order of the regions. As shown in Figure 5B, the 16 regions are numbered from 0 to 15 with region sequence numbers and traversed along the curve.

[0102] By dividing an image into multiple regions and deriving the coefficients for each region separately, the effect of filter localization can be achieved. However, the cost of doing so increases with the number of coefficients that need to be sent. Considering that for some smooth content, different regions in an image can share similar content features, it is not necessary to derive different filters for each different region. Therefore, to save on the signaling cost of these video sequences, i.e., the cost of transmitting signals, a region merging mechanism can be used. Any two connected regions in region order (e.g., regions with consecutive sequence numbers) can be merged into a single region with a set of filter coefficients. The merged region can then be further merged with its connected regions. For example, regions 4 and 5 can be merged into region 45, and region 45 can be continuously merged with region 3 or region 6 until the entire image is a single region. The encoder can decide how to merge these 16 regions and send the merged region signaling to the decoder. Therefore, as shown above, the number of filters (e.g., the number of coefficient sets) for each image can change from image to image based on the merging result, which can be determined by the encoder based on the current image content.

[0103] Figure 5C is a schematic diagram of an exemplary merging region according to Embodiment 1 of this disclosure. As shown in Figure 5C, region 0 can be merged as merging region A; regions 1 to 3 can be merged into merging region B; regions 4 to 8 can be merged into merging region C; regions 9 to 12 can be merged into merging region D; and regions 13 to 15 can be merged into merging region E. Therefore, there are a total of 5 merging regions in an image, where 5 sets (instead of 16 sets) of signals corresponding to coefficients can be sent for the image, thereby saving signaling overhead. On the decoder side, by decoding the merging region information, the ALF index of the region can be determined. Considering that a filter can be applied to a merging region, the decoder can utilize the ALF to process the current region based on the ALF index. In some embodiments, during ALF processing, a region can be divided into one or more ALF units, and the ALF can process pixels unit by unit. Since an ALF unit is a subset of a region, all pixels in an ALF unit are processed by one ALF (i.e., sharing a set of ALF coefficients), therefore, pixels in an ALF unit have the same ALF index.

[0104] However, there are several problems in the current ALF design.

[0105] On the one hand, in the current ALF design, an image can be divided into a maximum of 16 regions. However, for high-resolution images, such as 2K and 4K, the content contained is much larger. When an image is divided into 16 regions, each region may contain various contents that may require different filters. However, each region can only have one filter. Applying a single filter to all these samples may degrade the coding performance of ALF. Therefore, dividing an image into 16 regions may not be sufficient.

[0106] On the other hand, in the current ALF design, the partitioning pattern when an image is divided into 16 regions is fixed. However, since the video content of each image is different, in some cases, different content must be included in the same region that affects the encoding performance of ALF. Therefore, the fixed partitioning pattern cannot be suitable for all images.

[0107] On the other hand, in the current design, only a fixed order is defined for the 16 regions, and only connected regions within the sequence can be merged. However, because some spaces are not connected in the defined order, they cannot be merged even if they are adjacent. For example, as shown in Figure 5C, taking two spatially adjacent regions (e.g., region 2 and region 11) as an example, they cannot be merged even if they share similar content because they are not in the connected sequence. This forces the encoder to signal two similar filters in these two regions, increasing signaling overhead.

[0108] This disclosure provides methods and systems for solving some or all of the above-mentioned problems.

[0109] According to some exemplary embodiments, since an image can be divided into more than 16 regions, in some embodiments, the same number of region columns and region rows can be used to divide the image. For example, FIG6A is a schematic diagram of dividing an image into more than 16 ALF regions according to Embodiment 1 of the present disclosure, and FIG6B is a schematic diagram of dividing an image into more than 16 ALF regions according to Embodiment 1 of the present disclosure. As shown in FIG6A, the image is divided into 8 region columns and 8 region rows to obtain 64 regions; as shown in FIG6B, the image is divided into 16 region columns and 16 region rows to obtain 256 regions.

[0110] In some embodiments, the image can also be divided into different numbers of region columns and region rows. Figure 6C is a schematic diagram showing the division of an image into more than 16 ALF regions according to Embodiment 1 of this disclosure. As shown in Figure 6C, the image is divided into 16 region columns and 8 region rows, thereby obtaining 128 regions. The number of region columns (i.e., 16) is different from the number of region rows (i.e., 8) because the image width is usually greater than the image height.

[0111] While increasing the number of regions is beneficial for larger images, it may not be beneficial for smaller images because it increases the signaling burden. Therefore, in some embodiments, the number of regions can be set to be variable, and this number can depend on the image resolution; for example, a large image can have more ALF regions than a small image.

[0112] In some embodiments, the number of regions can be determined by different scales or one or more thresholds. For example, let the width of the image be W and the height be H. If W × H is less than or equal to a first threshold TH1 (e.g., 1920 × 1080), the image is divided into a first number of regions (e.g., 64 regions as shown in Figure 6A); if W × H is greater than TH1 but less than a second threshold TH2 (e.g., 3840 × 2160), the image is divided into a second number of regions (e.g., 128 regions as shown in Figure 6C); if W × H is greater than or equal to TH2, the image is divided into a third number of regions (e.g., 256 regions as shown in Figure 6B). In some embodiments, the number of regions is proportional to the threshold. It is understood that there is no limit to the number of thresholds, and different numbers of regions can correspond to different threshold intervals.

[0113] In some embodiments, the number of regions can be determined based on both width and height. If W is less than the width threshold TW, the image is divided into 8 region columns; if W is greater than or equal to TW, the image is divided into 16 region columns. If H is less than the height threshold TH, the image is divided into 8 region rows; if H is greater than or equal to TH, the image is divided into 16 region rows. It is understood that there can be more than one width threshold and more than one height threshold. The number of region columns and the number of region rows correspond to different width threshold intervals and height threshold intervals, respectively.

[0114] In some embodiments, the number of regions can be selected from a set of preset region numbers based on the size of the image. For example, a basic region (e.g., 16×16=256 pixels) is defined as Ba, and the number N of basic regions in an image is calculated as N=W×H / Ba, where N is rounded to a set of preset region numbers. As shown in Figures 6A-6C, this set of preset region numbers includes 64, 128, and 256, so N can be rounded to 64, 128, and 256.

[0115] In some embodiments, the number of regions can be selected from a set of preset column numbers and a set of preset row numbers, respectively, based on width and height. Width and height define two basic lengths, Lw and Lh. The basic length in the image width is calculated as Nw = W / Lw, and the basic length in the image height is calculated as Nh = H / Lh, where Nw is rounded to a set of preset column numbers, and Nh is rounded to a set of preset row numbers. As shown in Figures 6A-6C, this set of preset column numbers includes 8 and 16, so Nw is rounded to 8 or 16. The set of preset row numbers is 8 and 16, so Nh is rounded to 8 or 16. The encoder / decoder supports preset column and row numbers for images.

[0116] In some embodiments, to simplify the filtering operation, the regions can be obtained by aligning with the maximum coding unit (LCU). That is, the boundary of each region should be the LCU boundary or the image boundary, such that all pixels within an LCU have the same filter.

[0117] In some embodiments, a variable number of regions is supported in a video sequence. That is, in a video sequence, the number of regions may differ between different images to adapt the number of regions to the images, thereby improving video processing efficiency. In some embodiments, a region may have at most one ALF, but different regions can share an ALF; therefore, the maximum number of ALFs can be equal to the number of regions in the image. In some embodiments, ALFs can be performed on images containing different components (e.g., chroma and luma components). Therefore, the encoder can determine how many regions are in an image at the image level or sequence level, and the signaling indicates the index of the maximum number of ALFs for the image components in the bitstream. After receiving the bitstream, the decoder can determine the maximum number of ALFs for the current image or the current video sequence based on the indexes parsed from the bitstream.

[0118] According to some exemplary embodiments, this disclosure also provides different partitioning patterns, and Figures 7A-7D illustrate examples of different partitioning patterns according to some embodiments of this disclosure.

[0119] Figure 7A is a schematic diagram of an exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure. As shown in Figure 7A, an image can be divided into multiple region columns and region rows. If the image width is not a multiple of the number of region columns, all region columns except the last column 701A can have the same width; similarly, if the image height is not a multiple of the number of region rows, all region rows except the last row 702A have the same height. Figure 7B is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure; Figure 7C is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure; Figure 7D is a schematic diagram of another exemplary ALF region partitioning pattern according to Embodiment 1 of this disclosure. Figures 7B-7D illustrate exemplary ALF region partitioning patterns according to some embodiments of this disclosure. As shown in Figures 7B-7D, if the image width is not a multiple of the number of region columns, the first column or the last column can have a width different from the other columns; if the image height is not a multiple of the number of region rows, the height of the first row or the last row can be different from the other rows. If the image width and height are not multiples of the number of columns and rows in the region, respectively, there are four different ALF region partitioning modes, as shown in Figures 7A-7D. For example, in Figure 7B, the first column 701B has a width different from the other columns, and the last row 702B has a height different from the other rows; in Figure 7C, the first column 701C has a width different from the other columns, and the first row 702C has a height different from the other rows; in Figure 7D, the last column 701D has a width different from the other columns, and the first row 702D has a height different from the other rows.

[0120] If the image width (in LCU width units) is 30 and the image height (in LCU height units) is 17, and if the image is divided into 8 column regions and 8 row regions, then for the division pattern in Figure 7A, the width of each column region (in LCU width units) is 4, 4, 4, 4, 4, 4, 4, 2, and the height of each row region (in LCU height units) is 2, 2, 2, 2, 2, 2, 2, 3; for the division pattern in Figure 7B, the width of each column region (in LCU width units) is 2, 4, 4, 4, 4, 4, 4, 4, and the height of each row region (in LCU height units) is 2, 2, 2, 2, 2, 2, 2, 3; and for the division pattern in Figure 7C, the width of each column region (in LCU width units) is 2, 4, 4, 4, 4, 4, 4, 4. 4. The height of each region row, in units of LCU height, is 3, 2, 2, 2, 2, 2, 2, 2; for the division pattern in Figure 7D, the width of each region column, in units of LCU width, is 4, 4, 4, 4, 4, 4, 4, 2, and the height of each region row, in units of LCU height, is 3, 2, 2, 2, 2, 2, 2, 2.

[0121] Figure 8 is a schematic flowchart illustrating a process for determining a region index for each sample according to Embodiment 1 of this disclosure. As shown in Figure 8, method 800 may be executed by an encoder (e.g., process 200A of Figure 2A or process 200B of Figure 2B), a decoder (e.g., process 300A of Figure 3A or process 300B of Figure 3B), or by one or more software or hardware components of a device (e.g., device 400 of Figure 4). For example, a processor (e.g., processor 402 of Figure 4) may execute method 800. In some embodiments, method 800 may be implemented by a computer program product contained in a computer-readable medium, including computer-executable instructions, such as program code, that are executed by a computer (e.g., device 400 of Figure 4). Referring to Figure 8, method 800 may include steps 801-805.

[0122] In step 801, the first column width and the first row height are determined. Determining the first column width further includes: calculating the number of LCUs in the image width by rounding up using one LCU; obtaining the column width in units of LCU width by dividing the number of LCUs in the image by the number of rows in the region; and obtaining the first column width in units of pixels by multiplying the column width in units of LCU width by the LCU width. The first row height can be determined in a similar manner. In some embodiments, the first column width x_interval and the first row height y_interval can be determined as follows: x_interval = ((((img_width + lcu_width - 1) / lcu_width) + RE_OFFSET_X) / INTERVAL_X lcu_width);y_interval = ((((img_height + lcu_height - 1) / lcu_height) + RE_OFFSET_Y) / INTERVAL_Y `lcu_height`, where `img_width` is the width of the image, `img_height` is the height of the image, and `lcu_width` and `lcu_height` are the width and height of the LCU. `INTERVAL_X` is the number of columns in the region, and `INTERVAL_Y` is the number of rows in the region. `RE_OFFSET_X` and `RE_OFFSET_Y` are two predefined offsets.

[0123] In step 803, the second column width and the second row height are determined. Determining the second column width further includes: calculating the number of the first column based on the image and the first column width, and cropping the first column number to the number of region columns; calculating the second column width based on the image width, the first column width, and the number of the first column; and aligning the second column width with the LCU width. The second row height can be determined in a similar manner. In some embodiments, the second column width x_st_offset and the second row height y_st_offset can be determined as follows: if (y_interval == 0){y_st_offset = 0;}else{y_cnt = Clip3(0, INTERVAL_Y, (img_height + y_interval - 1) / y_interval); y_st_offset = img_height - y_interval (y_cnt - 1); y_st_offset = (y_st_offset + lcu_height / 2) / lcu_height lcu_height;}if (x_interval == 0){x_st_offset = 0;}else{x_cnt = Clip3(0, INTERVAL_X, (img_width + x_interval - 1) / x_interval); x_st_offset = img_width - x_interval (x_cnt - 1); x_st_offset = (x_st_offset + lcu_width / 2) / lcu_width lcu_width;} where Clip3(x, y, t) is a function that clips t to y if t is greater than y, and clips t to x if t is less than x.

[0124] In step 805, a region index is determined for each sample (e.g., using a coordinator (g, i)). The coordinates (g, i) indicate the sample's position in the image, and the region index is the index of the region where the sample is located. For example, coordinates (0, 0) refer to the top-left sample of the entire image. In this embodiment, region indices are assigned in raster scan order, e.g., from left to right, from top to bottom, starting from 0. The region index of a sample is obtained by calculating the relationship between the sample's coordinates (g, i) and the position of each region. Because four different partitioning modes (e.g., as shown in Figures 7A-7D) can be applied to an image, samples may be in different regions when different partitioning modes are applied, thus having different region indices. In some embodiments, the region index of a sample with a coordinator (g, i) can be determined as follows: y_idx = (y_interval == 0) ? (INTERVAL_Y-1) : (Clip3(0, INTERVAL_Y-1,i / y_interval)); y_idx_offset = y_idx INTERVAL_X;y_index2= (y_interval == 0 || i <y_st_offset) ? (0) : (Clip3(-1,INTERVAL_Y-2, (i - y_st_offset) / y_interval) + 1);y_index_offset2 = y_index2 INTERVAL_X; x_index = (x_interval == 0)? (INTERVAL_X - 1) : (Clip3(0, INTERVAL_X - 1, g / x_interval)); x_index2 = (x_interval == 0 || g < x_st_offset)? (0) : (Clip3(-1, INTERVAL_X - 2, (g - x_st_offset) / x_interval) + 1); 1) For the partitioning pattern in Figure 7A: The region index of the sample (g, i) is y_index_offset + x_index; 2) For the partitioning pattern in Figure 7B: The region index of the sample (g, i) is y_index_offset + x_index2; 3) For the partitioning pattern in Figure 7C: The region index of the sample (g, i) is y_index_offset2 + x_index2; 4) For the partitioning pattern in Figure 7D: The region index of the sample (g, i) is y_index_offset2 + x_index.

[0125] Figures 9A-9D illustrate another example of different partitioning patterns according to some embodiments of the present disclosure, wherein Figure 9A is a schematic diagram of an exemplary ALF region partitioning pattern shown according to Embodiment 1 of the present disclosure; Figure 9B is a schematic diagram of another exemplary ALF region partitioning pattern shown according to Embodiment 1 of the present disclosure; Figure 9C is a schematic diagram of another exemplary ALF region partitioning pattern shown according to Embodiment 1 of the present disclosure; and Figure 9D is a schematic diagram of another exemplary ALF region partitioning pattern shown according to Embodiment 1 of the present disclosure. In this example, the image can be divided into multiple region columns and region rows. If the image width W is not a multiple of the number of region columns CN, then the width of the region column is W / CN or W / CN+1; if the image height H is not a multiple of the number of region rows RN, then the height of the region row is H / RN or H / RN+1, where " / " represents integer splitting; if the image width is 19 in LCU width units and the image height is 11 in LCU height units, and if the image is divided into 8 region columns and 8 region rows, then for the partitioning pattern in Figure 9A, the width of each region column in LCU width units is 2, 3, 2, 3, 2, 3, 2, 2, and the height of each region row in LCU height units is 1, 2, 1, 2, 1, 2, 1, 1; for the partitioning pattern in Figure 9B, the width of each region column in LCU width units is 3, 2, 3, 2, 3, 2, 2, 2, and the height of each region row in LCU height units is 1, 2, 1. For the partitioning pattern in Figure 9C, the width of each region column (in LCU width) is 3, 2, 3, 2, 3, 2, 2, 2, and the height of each region row (in LCU height) is 2, 1, 2, 1, 2, 1, 1, 1; for the partitioning pattern in Figure 9D, the width of each region column (in LCU width) is 2, 3, 2, 3, 2, 3, 2, 2, and the height of each region row (in LCU height) is 2, 1, 2, 1, 2, 1, 1, 1. It can be understood that columns and rows with different widths and heights can have other possible arrangements.

[0126] In some embodiments, the video sequence supports variable partitioning modes (e.g., the partitioning modes shown in Figures 9A-9D). The encoder determines which partitioning mode to use at the picture level or the sequence level and signals an index of the partitioning mode used in the bitstream. The decoder determines the partitioning mode for the current picture or the current sequence based on the partitioning mode index parsed from the bitstream. For example, an index with a value between 0 and 3 corresponds to one of the partitioning modes shown in Figures 9A-9D.

[0127] Different region orders are proposed according to some exemplary embodiments. In some embodiments, Hilbert-like curves can be extended or reversed to be used as region orders. For example, FIG10A is a schematic diagram of an exemplary ALF region order of 64 regions according to Embodiment 1 of this disclosure; FIG10B is a schematic diagram of another exemplary ALF region order of 64 regions according to Embodiment 1 of this disclosure; FIG10C is a schematic diagram of another exemplary ALF region order of 64 regions according to Embodiment 1 of this disclosure; FIG10D is a schematic diagram of another exemplary ALF region order of 64 regions according to Embodiment 1 of this disclosure. As shown in FIG10A-10D, the image is divided into 8 region columns and 8 region rows, and the curves in the figures indicate the region order. Four different orders are shown in FIG10A-10D respectively, and the numbers in the figures represent region sequence numbers. These orders can be reversed, flipped, or rotated. If sequence number i is replaced with 64-i, the order is reversed.

[0128] If the image is scanned in raster order, the region sequence number of each region in Figure 10A is: {0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,} 47,44,43,42} or {63,62,49,48,47,44,43,42,60,61,50,51,46,45,40,41,59,56,55,52,53,33,34,49,38,58,57,54,53,32,35,36,37,5,6,9,10,31,28,27,26,4,7,8,11,30,29,24,25,3,2,13,12,17,18,23,22,0,1,14,15,16,19,20,21}.

[0129] If the image is scanned in raster order, the region sequence number of each region in Figure 10B is: {63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,3} 7,26,25,22,21} or {0,3,4,5,58,59,60,63,1,2,7,6,57,56,61,62,14,13,8,9,54,55,50,49,15,12,11,10,53,52,51,48,16,17,30,31,32,33,46,47,19,18,29,28,35,34,45,44,20,23,24,27,36,39,40,43,21,22,25,26,27,38,41,42}.

[0130] If the image is scanned in raster order, the region sequence number of each region in Figure 10C is: {42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19} ,16,15,14,1,0}, or {21,20,19,16,15,14,1,0,22,23,18,17,12,13,2,3,25,24,29,30,11,8,7,4,26,27,28,31,10,9,6,5,37,36,35,32,53,54,57,58,38,39,34,33,52,55,56,59,41,40,45,46,51,50,61,60,42,43,41,47,48,49,62,63}.

[0131] If the image is scanned in raster order, the region sequence number of each region in Figure 10D is: {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57,56,61,62,0,3,4} 5,58,59,60,63}, or {42,41,38,37,26,25,22,21,43,40,39,36,27,24,23,20,44,45,34,35,28,29,18,19,47,46,33,32,31,30,17,16,48,51,52,53,10,11,12,15,49,50,55,54,9,8,13,14,62,61,56,57,6,7,2,1,63,60,59,58,5,4,3,0}.

[0132] In some embodiments, the image can be divided into 16 columns and 16 rows of regions, with the curves in the figures indicating the region order. Figures 11A-11D illustrate four different region orders, where Figure 11A is a schematic diagram of an exemplary ALF region order of 256 regions according to Embodiment 1 of this disclosure; Figure 11B is a schematic diagram of another exemplary ALF region order of 256 regions according to Embodiment 1 of this disclosure; Figure 11C is a schematic diagram of another exemplary ALF region order of 256 regions according to Embodiment 1 of this disclosure; and Figure 11D is a schematic diagram of another exemplary ALF region order of 256 regions according to Embodiment 1 of this disclosure. These orders can be reversed, flipped, or rotated.

[0133] If the image is scanned in raster order, the region sequence number of each region in Figure 11A is as follows: {0, 3, 4, 5, 58, 59, 60, 63, 64, 65, 78, 79, 80, 83, 84, 85, 1, 2, 7, 6, 57, 56, 61, 62, 67, 66, 77, 76, 81, 82, 87, 86, 14, 13, 8, 9, 54, 55, 50, 49, 68, 71, 72, 75, 94, 93, 88, 89, 15, 12, 11, 10, 53, 52, 51, 48, 69, 70, 73,} 74, 95, 92, 91, 90, 16, 17, 30, 31, 32, 33, 46, 47, 122, 121, 118, 117, 96, 99, 100, 91, 19, 18, 29, 28, 35, 34, 45, 44, 123, 120, 119, 116, 97, 98, 103, 102, 20, 23, 24, 27, 36, 39, 40, 43, 124, 125, 114, 115, 110, 109, 104, 105, 21, 22, 25, 26, 27, 38, 41, 42, 127, 126, 113, 112, 111, 108, 107, 106, 234, 233, 230, 219, 218, 217, 214, 213, 128, 129, 142, 143, 144, 147, 148, 149, 235, 232, 231, 228, 219, 216, 215, 212, 131, 130, 141, 140, 145, 146, 151, 150, 236, 237, 226, 227, 220, 221, 210, 211, 132, 135, 136, 139, 158, 157, 152, 153, 239, 238, 225, 224, 223, 222, 209, 208, 133, 134, 137, 138, 159, 156, 155, 154, 240, 243, 244, 245, 202, 203, 204, 207, 186, 185, 182, 181, 160, 163, 164, 155, 241, 242, 247, 246, 201, 200, 205, 206, 187, 184, 183, 180,161, 162,167, 166,254, 253, 248, 249, 198, 199, 194, 193, 188, 189, 178, 179, 174, 173,168, 169,255, 252, 251, 250, 197, 196, 195, 192, 191, 190, 177, 176, 175, 172,171, 170}。,

[0134] If the image is scanned in raster order, the region sequence number of each region in Figure 11B is as follows: {0, 1, 14, 15, 16, 19, 20, 21, 234, 235, 236, 239, 240, 241, 254, 255, 3, 2, 13, 12, 17, 18, 23, 22, 233, 232, 237, 238, 243, 242, 253, 252, 4, 7, 8, 11, 30, 29, 24, 25, 230, 231, 226, 225, 244, 247, 248, 251, 5, 6, 9, 10, 31,} 28, 27, 26, 219, 228, 227, 224, 245, 246, 249, 250, 58, 57, 54, 53, 32, 35, 36, 27, 218, 219, 220, 223, 202, 201, 198, 197, 59, 56, 55, 52, 33, 34, 39, 38, 217, 216, 221, 222, 203, 200, 199, 196, 60, 61, 50, 51, 46, 45, 40, 41, 214, 215, 210, 209, 204, 205, 194,195,63, 62, 49, 48, 47, 44, 43, 42, 213, 212, 211, 208, 207, 206, 193,192,64, 67, 68, 69, 122, 123, 124, 127, 128, 131, 132, 133, 186, 187,188, 191,65, 66, 71, 70, 121, 120, 125, 126, 129, 130, 135, 134, 185, 184,189, 190,78, 77, 72, 73, 118, 119, 114, 113, 142, 141, 136, 137, 182, 183, 178, 177, 79, 76, 75, 74, 117, 116, 115, 112, 143, 140, 139, 138, 181, 180, 179, 176, 80, 81, 94, 95, 96, 97, 110, 111, 144, 145, 158, 159, 160, 161, 174, 175, 83, 82, 93, 92, 99, 98, 109, 108, 147, 146,157, 156, 163, 162, 173,172,84, 87, 88, 91, 100, 103, 104, 107, 148, 151, 152, 155, 164, 167,168, 171,85, 86, 89, 90, 91, 102, 105, 106, 149, 150, 153, 154, 155, 166, 169,170}。,

[0135] The region sequence numbers for each region in Figure 11C are as follows: {170, 171, 172, 175, 176, 177, 190, 191, 192, 195, 196, 197, 250, 251, 252, 255, 169, 168, 173, 174, 179, 178, 189, 188, 193, 194, 199, 198, 249, 248, 253, 254, 166, 167, 162, 161, 180, 183, 184, 187, 206, 205, 200, 201, 246, 247, 242,} 241,155, 164, 163, 160, 181, 182, 185, 186, 207, 204, 203, 202, 245, 244,243, 240,154, 155, 156, 159, 138, 137, 134, 133, 208, 209, 222, 223, 224, 225,238, 239,153, 152, 157, 158, 139, 136, 135, 132, 211, 210, 221, 220, 227, 226,237, 236,150, 151, 146, 145, 140, 141, 130, 131, 212, 215, 216, 219, 228, 231,232, 235, 149, 148, 147, 144, 143, 142, 129, 128, 213, 214, 217, 218, 219, 230,233, 234, 106, 107, 108, 111, 112, 113, 126, 127, 42, 41, 38, 27, 26, 25, 22,21, 105, 104, 109, 110, 115, 114, 125, 124, 43, 40, 39, 36, 27, 24, 23, 20, 102, 103, 98, 97, 116, 119, 120, 123, 44, 45, 34, 35, 28, 29, 18, 19, 91, 100, 99, 96, 117, 118, 121, 122, 47, 46, 33, 32, 31, 30, 17, 16, 90, 91, 92, 95, 74, 73, 70, 69, 48, 51, 52, 53, 10, 11, 12, 15, 89, 88, 93, 94,75, 72, 71, 68, 49, 50, 55, 54, 9, 8, 13, 14,86, 87, 82, 81, 76, 77, 66, 67, 62, 61, 56, 57, 6, 7, 2, 1,85, 84, 83, 80, 79, 78, 65, 64, 63, 60, 59, 58, 5, 4, 3, 0}。,

[0136] If the image is scanned in raster order, the region sequence number of each region in Figure 11D is as follows: {170, 169, 166, 155, 154, 153, 150, 149, 106, 105, 102, 91, 90, 89, 86, 85, 171, 168, 167, 164, 155, 152, 151, 148, 107, 104, 103, 100, 91, 88, 87, 84, 172, 173, 162, 163, 156, 157, 146, 147, 108, 109, 98, 99, 92, 93, 82, 83, 175,} 174, 161, 160, 159, 158, 145, 144, 111, 110, 97, 96, 95, 94, 81, 80, 176, 179, 180, 181, 138, 139, 140, 143, 112, 115, 116, 117, 74, 75, 76, 79, 177, 178, 183, 182, 137, 136, 141, 142, 113, 114, 119, 118, 73, 72, 77, 78, 190, 189, 184, 185, 134, 135, 130, 129, 126, 125, 120, 121, 70, 71, 66, 65, 191, 188, 187, 186, 133, 132, 131, 128, 127, 124, 123, 122, 69, 68, 67, 64, 192, 193, 206, 207, 208, 211, 212, 213, 42, 43, 44, 47, 48, 49, 62, 63, 195, 194, 205, 204, 209, 210, 215, 214, 41, 40, 45, 46, 51, 50, 61,60,196, 199, 200, 203, 222, 221, 216, 217, 38, 39, 34, 33, 52, 55, 56,59,197, 198, 201, 202, 223, 220, 219, 218, 27, 36, 35, 32, 53, 54, 57,58,250, 249, 246, 245, 224, 227, 228, 219, 26, 27, 28, 31, 10, 9, 6, 5,251, 248, 247, 244, 225, 226,231, 230, 25, 24, 29, 30, 11, 8, 7, 4,252, 253, 242, 243, 238, 237, 232, 233, 22, 23, 18, 17, 12, 13, 2, 3,255, 254, 241, 240, 239, 236, 235, 234, 21, 20, 19, 16, 15, 14, 1,0}.

[0137] In the above four regional sequences, the regional sequence number i may be replaced with 255-i, which means that the regional order is reversed.

[0138] In some embodiments, since the number of region columns is not equal to the number of region rows, a Hilbert-like curve cannot be directly applied; instead, a portion of a Hilbert-like curve can be used. For example, Figure 12A is a schematic diagram of an exemplary ALF region order of 128 regions according to Embodiment 1 of this disclosure; Figure 12B is a schematic diagram of another exemplary ALF region order of 128 regions according to Embodiment 1 of this disclosure; Figure 12C is a schematic diagram of another exemplary ALF region order of 128 regions according to Embodiment 1 of this disclosure; Figure 12D is a schematic diagram of another exemplary ALF region order of 128 regions according to Embodiment 1 of this disclosure. As shown in Figures 12A-12D, the image is divided into 16 region columns and 8 region rows, in which case only half a Hilbert-like curve needs to be used. Four region orders are shown in Figures 12A-12D, and these region orders can be reversed, flipped, or rotated.

[0139] If the image is scanned in raster order, the region sequence number of each area in Figure 12A is as follows: {0, 3, 4, 5, 58, 59, 60, 63, 64, 65, 78, 79, 80, 83, 84, 85, 1, 2, 7, 6, 57, 56, 61, 62, 67, 66, 77, 76, 81, 82, 87, 86, 14, 13, 8, 9, 54, 55, 50, 49, 68, 71, 72, 75, 94, 93, 88, 89, 15, 12, 11, 10, 53, 52, 51, 48, 69, 70, 73,} 74, 95, 92, 91, 90, 16, 17, 30, 31, 32, 33, 46, 47, 122, 121, 118, 117, 96, 99, 100, 91, 19, 18, 29, 28, 35, 34, 45, 44, 123, 120, 119, 116, 97, 98, 103, 102, 20, 23, 24, 27, 36, 39, 40, 43, 124, 125, 114, 115, 110, 109, 104, 105, 21, 22, 25, 26, 27, 38, 41, 42, 127, 126, 113, 112, 111, 108, 107,106}.

[0140] If the image is scanned in raster order, the region sequence number of each region in Figure 12B is as follows: {0, 3, 4, 5, 58, 59, 60, 63, 64, 67, 68, 69, 122, 123, 124, 127, 1, 2, 7, 6, 57, 56, 61, 62, 65, 66, 71, 70, 121, 120, 125, 126, 14, 13, 8, 9, 54, 55, 50, 49, 78, 77, 72, 73, 118, 119, 114, 113, 15, 12, 11, 10, 53, 52, 51, 48,} 79, 76, 75, 74, 117, 116, 115, 112, 16, 17, 30, 31, 32, 33, 46, 47, 80, 81, 94, 95, 96, 97, 110, 111, 19, 18, 29, 28, 35, 34, 45, 44, 83, 82, 93, 92, 99, 98, 109, 108, 20, 23, 24, 27, 36, 39, 40, 43, 84, 87, 88, 91, 100, 103, 104, 107, 21, 22, 25, 26, 27, 38, 41, 42, 85, 86, 89, 90, 91, 102, 105, 106}.

[0141] If the image is scanned in raster order, the region sequence number of each region in Figure 12C is as follows: {106, 107, 108, 111, 112, 113, 126, 127, 42, 41, 38, 27, 26, 25, 22, 21, 105, 104, 109, 110, 115, 114, 125, 124, 43, 40, 39, 36, 27, 24, 23, 20, 102, 103, 98, 97, 116, 119, 120, 123, 44, 45, 34, 35, 28, 29, 18, 19, 91, 100, 99,} 96, 117, 118, 121, 122, 47, 46, 33, 32, 31, 30, 17, 16, 90, 91, 92, 95, 74, 73, 70, 69, 48, 51, 52, 53, 10, 11, 12, 15, 89, 88, 93, 94, 75, 72, 71, 68, 49, 50, 55, 54, 9, 8, 13, 14, 86, 87, 82, 81, 76, 77, 66, 67, 62, 61, 56, 57, 6, 7, 2, 1, 85, 84, 83, 80, 79, 78, 65, 64, 63, 60, 59, 58, 5, 4, 3, 0}.

[0142] If the image is scanned in raster order, the region sequence number of each region in Figure 12D is as follows: {106, 105, 102, 101, 90, 89, 86, 85, 42, 41, 38, 27, 26, 25, 22, 21, 107, 104, 103, 100, 91, 88, 87, 84, 43, 40, 39, 36, 27, 24, 23, 20, 108, 109, 98, 99, 92, 93, 82, 83, 44, 45, 34, 35, 28, 29, 18, 19, 111, 110, 97, 96, 95, 94,} 81, 80, 47, 46, 33, 32, 31, 30, 17, 16, 112, 115, 116, 117, 74, 75, 76, 79, 48, 51, 52, 53, 10, 11, 12, 15, 113, 114, 119, 118, 73, 72, 77, 78, 49, 50, 55, 54, 9, 8, 13, 14, 126, 125, 120, 121, 70, 71, 66, 65, 62, 61, 56, 57, 6, 7, 2, 1, 127, 124, 123, 122, 69, 68, 67, 64, 63, 60, 59, 58, 5, 4, 3, 0}.

[0143] In the above four regional sequences, the regional sequence number i can be replaced by 127-i so that the regional order can be reversed.

[0144] In some embodiments, the region order is variable. The encoder determines which region order to use at the picture level or sequence level, and signaling indicates the index of the region order used in the bitstream. The decoder determines the region order of the current picture or the current sequence based on the region order index parsed from the bitstream. As an example shown in Figures 12A-12D, the picture supports four different orders, so 2 bits are used to encode the index with values ​​from 0 to 3.

[0145] Consistent with the disclosed embodiments, partitioning modes and region orders can be combined. According to some exemplary embodiments, variable partitioning modes and variable region orders are supported. The combination of partitioning modes and region orders is determined by the encoder and signaled in the bitstream. The decoder determines the partitioning mode and region order of the current image or current sequence based on the index of the signaling in the bitstream.

[0146] For example, an image is divided into 8 region columns and 8 region rows, supporting two partitioning modes as shown in Figures 7A and 7C, and two region orders as shown in Figures 10A and 10B, for a total of 4 supported combinations. The encoder selects a combination from these four options at the image or sequence level and signals the index of the selected partitioning mode and region order combination in the bitstream. Since there are four combinations, their index values ​​are set from 0 to 3. The decoder determines the combination of the current image or sequence based on the index of the signal in the bitstream. For example, if the index equals 0, the partitioning mode in Figure 7A and the region order in Figure 10A are used. If the index equals 1, the partitioning mode in Figure 7B and the region order in Figure 10A are used. For example, if the index equals 2, the partitioning mode in Figure 7A and the region order in Figure 10B are used. For example, if the index equals 3, the partitioning mode in Figure 7B and the region order in Figure 10B are used.

[0147] Consistent with the disclosed embodiments, partitioning modes and region orders can be combined, but this combination is limited. That is, a partitioning mode can only be applied to an image or video sequence with its corresponding region order. According to some exemplary embodiments, variable partitioning modes and variable region orders are supported. However, it may not be allowed to combine partitioning modes with every supported region order. If a partitioning mode is selected, only the specified scan order or certain specified scans can be used. In some exemplary embodiments, each partitioning mode can only be applied with its corresponding region order, and each region order can only be applied with its corresponding partitioning mode. Therefore, an index can be used to indicate the region order and partitioning mode. The decoder determines the partitioning mode and region order based on the index of the signaling in the bitstream. After determining the partitioning mode and region order, the decoder can determine the ALF index of the current region and process the region with the correct ALF based on the ALF index.

[0148] For example, an image is divided into 8 column regions and 8 row regions, supporting four partitioning modes as shown in Figures 7A-7D and four region orders as shown in Figures 10A-10D. Therefore, there are a total of 16 different combinations of partitioning modes and scan orders. However, not all 16 combinations are allowed. The partitioning mode in Figure 7A can only be combined with the scan order in Figure 10A; the partitioning mode in Figure 7B can only be combined with the scan order in Figure 10B; the partitioning mode in Figure 7C can only be combined with the scan order in Figure 10C; and the partitioning mode in Figure 7D can only be combined with the scan order in Figure 10D. That is, only four combinations are allowed. Therefore, the encoder selects one of these four options for each image or the entire sequence and signals an index with a value from 0 to 3 in the bitstream. The decoder determines the partitioning mode and region order based on the index in the bitstream. This disclosure does not limit the combinations of partitioning modes and region orders. Therefore, in another example, the partitioning pattern in FIG7A can be combined with the scan order in FIG10B; the partitioning pattern in FIG7B can be combined with the scan order in FIG10C; the partitioning pattern in FIG7C can be combined with the scan order in FIG10D; and the partitioning pattern in FIG7D can be combined with the scan order in FIG10A. In these embodiments, the signaling index indicates the partitioning pattern and the region order.

[0149] According to an embodiment of this disclosure, a video data processing method is also provided, comprising: determining the maximum number of adaptive loop filters (ALFs) for the components of an image; processing pixels in the image using ALFs; and signaling a first index indicating the maximum number of ALFs for the components of the image.

[0150] In the above embodiments of this disclosure, the maximum number of ALFs indicated by the first index equal to the first value is 64; the maximum number of ALFs indicated by the first index equal to the second value or not equal to the first value is 16.

[0151] In the above embodiments of this disclosure, it further includes: determining the order of the ALF regions of the image; and a second index indicating the order of the ALF regions of the image via signaling.

[0152] In the embodiments described above, the second index is encoded using 2 bits.

[0153] In the above embodiments of this disclosure, the method further includes: determining the ALF index based on the second index; and processing the pixels in the image using ALF according to the ALF index.

[0154] In the embodiments disclosed above, determining the ALF index based on the second index includes: determining the first column width based on the image width and the maximum coding unit (LCU) width; determining the first row height based on the image height and the LCU height; determining the region index based on the first column width and the first row height; and determining the ALF index based on the region index and the second index.

[0155] In the embodiments disclosed above, determining the ALF index based on the regional index and the second index includes: determining the second column width based on the first column width, the image width, and the LCU width; determining the second row height based on the first row height, the image height, and the LCU height; determining the regional index based on the first column width, the second column width, the first row height, and the second row height; and determining the ALF index based on the regional index and the second index.

[0156] In the above embodiments of this disclosure, determining the region index based on the first column width and the first row height includes: determining the first horizontal region index and the second horizontal region index based on the first column width; determining the first vertical region index and the second vertical region index based on the first row height; and determining the region index based on the first horizontal region index, the second horizontal region index, the first vertical region index, the second vertical region index, and the second index.

[0157] In the above embodiments of this disclosure, determining the ALF index based on the region index and the second index includes: determining the serial number based on the region index and the second index; and determining the ALF index based on the serial number.

[0158] In the above embodiments of this disclosure, the sequence number = regionTable[second index][region index], where regionTable is a two-dimensional circular table, defined as regionTable[4]

[64] ={{63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24}. 23,20,42,41,38,37,26,25,22,21},{42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0},{21,22,25,26,37,38,41,42,2 0,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57,56,61,62,0,3,4,5,58,59,60,63},{0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27 According to an embodiment of this disclosure, a video data processing apparatus is also provided, comprising: a memory configured to store instructions; and one or more processors configured to execute instructions to cause the apparatus to perform: receiving a bitstream; decoding a first index from the bitstream; determining a maximum number of adaptive loop filters (ALFs) for the components of an image based on the first index; and processing pixels in the image using the ALFs.

[0159] In the embodiments described above, the processor is further configured to execute instructions to cause the device to: determine that the maximum number of ALFs is 64 in response to the first index being equal to the first value; or determine that the maximum number of ALFs is 16 in response to the first index being equal to the second value or not equal to the first value.

[0160] In the embodiments described above, before processing the pixels in the image with ALF, the processor is further configured to execute instructions to cause the apparatus to perform: decoding a second index from the bitstream, wherein the second index indicates the order of the ALF regions of the image.

[0161] In the above embodiments of this disclosure, the second index is encoded using 2 bits.

[0162] In the embodiments described above, when processing pixels in an image using ALF, the processor is further configured to execute instructions to cause the device to perform: determining an ALF index based on a second index; and processing pixels in the image using ALF according to the ALF index.

[0163] In the embodiments described above, when determining the ALF index based on the second index, the processor is further configured to execute instructions to cause the device to perform: determining a first column width based on the image width and the maximum coding unit (LCU) width; determining a first row height based on the image height and the LCU height; determining a region index based on the first column width and the first row height; and determining the ALF index based on the region index and the second index.

[0164] In the embodiments described above, when determining the ALF index based on the region index and the second index, the processor is further configured to execute instructions to cause the device to perform: determining the second column width based on the first column width, the image width, and the LCU width; determining the second row height based on the first row height, the image height, and the LCU height; determining the region index based on the first column width, the second column width, the first row height, and the second row height; and determining the ALF index based on the region index and the second index.

[0165] In the above embodiments of this disclosure, when determining the region index based on the first column width and the first row height, the processor is further configured to execute instructions to cause the device to perform: determining a first horizontal region index and a second horizontal region index based on the first column width; determining a first vertical region index and a second vertical region index based on the first row height; and determining a region index based on the first horizontal region index, the second horizontal region index, the first vertical region index, the second vertical region index, and the second index.

[0166] In the embodiments described above, when determining the ALF index based on the region index and the second index, the processor is further configured to execute instructions to cause the device to perform: determining the serial number based on the region index and the second index; and determining the ALF index based on the serial number.

[0167] In the above embodiments of this disclosure, the processor is further configured to execute instructions to cause the device to determine a serial number based on a region index and a second index as follows: Serial number = regionTable[second index][region index], where regionTable is a two-dimensional circular table, and the two-dimensional circular table is defined as regionTable[4]

[64] ={{63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,4 7,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22,21},{42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25 ,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0},{21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,5 7,56,61,62,0,3,4,5,58,59,60,63},{0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,43,42}}.

[0168] According to an embodiment of this disclosure, an apparatus for performing video data processing is also provided. The apparatus includes: a memory configured to store instructions; and one or more processors configured to execute instructions to cause the apparatus to perform: determining a maximum number of adaptive loop filters (ALFs) for the components of an image; processing pixels in the image with the ALFs; and signaling a first index indicating the maximum number of ALFs for the components of the image.

[0169] In the above embodiments of this disclosure, the maximum number of ALFs indicated by the first index equal to the first value is 64; the maximum number of ALFs indicated by the first index equal to the second value or not equal to the first value is 16.

[0170] In the embodiments described above, the processor is further configured to execute instructions to cause the apparatus to perform: determining the order of the ALF regions of the image; and signaling a second index indicating the order of the ALF regions of the image.

[0171] In the embodiments described above, the second index is encoded using 2 bits.

[0172] In the embodiments described above, the processor is further configured to execute instructions to cause the device to perform: determining an ALF index based on a second index; and processing pixels in an image using an ALF index.

[0173] In the embodiments described above, when determining the ALF index based on the second index, the processor is further configured to execute instructions to cause the device to perform: determining the first column width based on the image width and the maximum coding unit (LCU) width; determining the first row height based on the image height and the LCU height; determining the region index based on the first column width and the first row height; and determining the ALF index based on the region index and the second index.

[0174] In the embodiments described above, when determining the ALF index based on the region index and the second index, the processor is further configured to execute instructions to cause the device to perform: determining the second column width based on the first column width, the image width, and the LCU width; determining the second row height based on the first row height, the image height, and the LCU height; determining the region index based on the first column width, the second column width, the first row height, and the second row height; and determining the ALF index based on the region index and the second index.

[0175] In the embodiments described above, when determining the region index based on the first column width and the first row height, the processor is further configured to execute instructions to cause the device to perform: determining a first horizontal region index and a second horizontal region index based on the first column width; determining a first vertical region index and a second vertical region index based on the first row height; and determining a region index based on the first horizontal region index, the second horizontal region index, the first vertical region index, the second vertical region index, and the second index.

[0176] In the embodiments described above, when determining the ALF index based on the region index and the second index, the processor is further configured to execute instructions to cause the device to perform: determining the serial number based on the region index and the second index; and determining the ALF index based on the serial number.

[0177] In the above embodiments of this disclosure, the processor is further configured to execute instructions to cause the device to determine a serial number based on a region index and a second index as follows: Serial number = regionTable[second index][region index], where regionTable is a two-dimensional circular table, defined as regionTable[4]

[64] ={{63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47, 46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22,21},{42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,2 4,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0},{21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57 ,56,61,62,0,3,4,5,58,59,60,63},{0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,43,42}}.

[0178] According to an embodiment of this disclosure, a non-volatile computer-readable medium storing an instruction set executable by one or more processors of a device is also provided to cause the device to initiate a method for performing video data processing, the method comprising: receiving a bitstream; decoding a first index from the bitstream; determining a maximum number of adaptive loop filters (ALFs) for the components of an image based on the first index; and processing pixels in the image using the ALFs.

[0179] In the embodiments described above, the instruction set may be executed by one or more processors of the device to cause the device to further perform: determining that the maximum number of ALFs is 64 in response to a first index being equal to a first value; or determining that the maximum number of ALFs is 16 in response to a first index being equal to a second value or not equal to the first value.

[0180] In the embodiments described above, before processing the pixels in an image with ALF, a set of instructions may be executed by one or more processors of the device to cause the device to further perform: decoding a second index from a bitstream, wherein the second index indicates the order of ALF regions of the image.

[0181] In the embodiments described above, the second index is encoded using 2 bits.

[0182] In the embodiments described above, when processing pixels in an image using ALF, the instruction set can be executed by one or more processors of the device to cause the device to further perform: determining an ALF index based on a second index; and processing pixels in the image using ALF according to the ALF index.

[0183] In the embodiments described above, when determining the ALF index based on the second index, the instruction set may be executed by one or more processors of the device to enable the device to further perform: determining the first column width based on the image width and the maximum coding unit (LCU) width; determining the first row height based on the image height and the LCU height; determining the region index based on the first column width and the first row height; and determining the ALF index based on the region index and the second index.

[0184] In the embodiments described above, when determining the ALF index based on the region index and the second index, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining the second column width based on the first column width, the image width, and the LCU width; determining the second row height based on the first row height, the image height, and the LCU height; determining the region index based on the first column width, the second column width, the first row height, and the second row height; and determining the ALF index based on the region index and the second index.

[0185] In the above embodiments of this disclosure, when determining the region index based on the first column width and the first row height, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining a first horizontal region index and a second horizontal region index based on the first column width; determining a first vertical region index and a second vertical region index based on the first row height; and determining a region index based on the first horizontal region index, the second horizontal region index, the first vertical region index, the second vertical region index, and the second index.

[0186] In the embodiments described above, when determining the ALF index based on the region index and the second index, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining the serial number based on the region index and the second index; and determining the ALF index based on the serial number.

[0187] In the above embodiments of this disclosure, the instruction set can be executed by one or more processors of the device to enable the device to further determine the sequence number based on the region index and the second index as follows: sequence number = regionTable[second index][region index], where regionTable is a two-dimensional circular table, and the two-dimensional circular table is defined as regionTable[4]

[64] ={{63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12 ,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22,21},{42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5 {25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0}, {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6} 57,56,61,62,0,3,4,5,58,59,60,63},{0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,43,42}}.

[0188] According to an embodiment of this disclosure, a non-volatile computer-readable medium storing an instruction set executable by one or more processors of the device is also provided to cause the device to initiate a method for performing video data processing, the method comprising: determining a maximum number of adaptive loop filters (ALFs) for the components of an image; processing pixels in the image with the ALFs; and signaling a first index indicating the maximum number of ALFs for the components of the image.

[0189] In the above embodiments of this disclosure, the maximum number of ALFs indicated by the first index equal to the first value is 64; the maximum number of ALFs indicated by the first index equal to the second value or not equal to the first value is 16.

[0190] In the embodiments described above, the instruction set may be executed by one or more processors of the device to cause the device to further perform: determining the order of ALF regions of an image; and signaling a second index indicating the order of ALF regions of an image.

[0191] In the above embodiments of this disclosure, the second index is encoded using 2 bits.

[0192] In the embodiments described above, the instruction set may be executed by one or more processors of the device to cause the device to further perform: determining an ALF index based on a second index; and processing pixels in an image with an ALF according to the ALF index.

[0193] In the embodiments described above, when determining the ALF index based on the second index, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining the first column width based on the image width and the maximum coding unit (LCU) width; determining the first row height based on the image height and the LCU height; determining the region index based on the first column width and the first row height; and determining the ALF index based on the region index and the second index.

[0194] In the embodiments described above, when determining the ALF index based on the region index and the second index, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining the second column width based on the first column width, the image width, and the LCU width; determining the second row height based on the first row height, the image height, and the LCU height; determining the region index based on the first column width, the second column width, the first row height, and the second row height; and determining the ALF index based on the region index and the second index.

[0195] In the above embodiments of this disclosure, when determining the region index based on the first column width and the first row height, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining a first horizontal region index and a second horizontal region index based on the first column width; determining a first vertical region index and a second vertical region index based on the first row height; and determining a region index based on the first horizontal region index, the second horizontal region index, the first vertical region index, the second vertical region index, and the second index.

[0196] In the embodiments described above, when determining the ALF index based on the region index and the second index, the instruction set can be executed by one or more processors of the device to enable the device to further perform: determining the serial number based on the region index and the second index; and determining the ALF index based on the serial number.

[0197] In the above embodiments of this disclosure, the instruction set can be executed by one or more processors of the device to enable the device to further determine the sequence number based on the region index and the second index as follows: sequence number = regionTable[second index][region index], where regionTable is a two-dimensional circular table, and the two-dimensional circular table is defined as regionTable[4]

[64] ={{63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12 ,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22,21},{42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5 {25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0}, {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6} 57,56,61,62,0,3,4,5,58,59,60,63},{0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,43,42}}.

[0198] According to an embodiment of this disclosure, a non-volatile computer-readable medium for storing a bitstream is also provided, wherein the bitstream includes a first index associated with video data, the first index indicating the maximum number of adaptive loop filters (ALFs) for the components of the image.

[0199] In the embodiments described above, the bitstream includes a second index associated with video data, the second index indicating the order of ALF regions of the image.

[0200] In some embodiments, a non-volatile computer-readable storage medium including instructions is also provided, and these instructions can be executed by a device (e.g., the disclosed encoder and decoder) to perform the methods described above. Common forms of non-volatile media include, for example, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a hole pattern, RAM, PROMs and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, caches, registers, any other memory chips or cassette memories and their network versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0201] It should be noted that the relational terms used herein (e.g., “first” and “second”) are used only to distinguish one entity or operation from another, and do not require or imply any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” “containing,” and “comprising,” as well as other similar forms, are intended to be semantically equivalent and open-ended, as one or more items following any of these terms do not imply an exhaustive list of those items, nor do they imply limitation to the listed items.

[0202] As used herein, unless otherwise expressly stated, the term "or" includes all possible combinations unless impractical. For example, if it is specified that a database may include A or B, then unless otherwise specified or impractical, the database may include A, B, or A and B. As a second example, if it is specified that a database may include A, B, or C, then unless otherwise specified or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0203] It should be understood that the above embodiments can be implemented by hardware, software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. When executed by a processor, the software can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, software, or a combination of hardware and software. Those skilled in the art will also understand that multiple of the above modules / units can be combined into one module / unit, and each of the above modules / units can be further divided into multiple sub-modules / sub-units.

[0204] In the foregoing description, numerous specific details have been described with reference to embodiments, which may vary depending on the implementation. Certain adjustments and modifications may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the detailed description and practice of the invention disclosed herein. The description and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims. The sequence of steps shown in the figures is also intended for illustrative purposes only and is not intended to limit one to any particular order of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order when implementing the same method.

[0205] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used only in a general and descriptive sense and not to limit the scope of the embodiments as defined by the appended claims.

Claims

1. A method for encoding a video sequence into a bitstream, the method comprising: receiving a video sequence; encoding one or more images of the video sequence, wherein the encoding comprises: determining an index value associated with loop filtering based on a region sequence list, wherein the index value is an integer greater than or equal to 0 and less than or equal to 63; and performing a filtering operation on the one or more images according to the index value.

2. The method according to claim 1, wherein, The region sequence list is as follows: {0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,} 43,42}; or {63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22} ,21} or {42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0}}; or {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57,56,61,62,0,3,4,5,58,59,60,63}.

3. A method for decoding a bitstream to output one or more images of a video stream, the method comprising: receiving the bitstream; and decoding the one or more images using encoding information of the bitstream, wherein, The decoding includes: determining an index value associated with loop filtering based on a region sequence list, wherein the index value is an integer greater than or equal to 0 and less than or equal to 63; and performing a filtering operation on the one or more images according to the index value.

4. The method according to claim 3, wherein, The region sequence list is as follows: {0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,} 43,42}; or {63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22} ,21} or {42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0}}; or {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57,56,61,62,0,3,4,5,58,59,60,63}.

5. A non-transitory computer-readable storage medium storing an instruction set and a bit stream, the instruction set being executable by one or more processors of a system to cause the system to perform a method to generate the bit stream, the method comprising: receiving a video sequence; encoding one or more images of the video sequence, wherein the encoding comprises: determining an index value associated with loop filtering based on a regional sequential list, wherein the index value is an integer greater than or equal to 0 and less than or equal to 63; and performing a filtering operation on the one or more images according to the index value.

6. The non-transitory computer-readable storage medium according to claim 5, wherein, The region sequence list is as follows: {0,1,14,15,16,19,20,21,3,2,13,12,17,18,23,22,4,7,8,11,30,29,24,25,5,6,9,10,31,28,27,26,58,57,54,53,32,35,36,37,59,56,55,52,33,34,39,38,60,61,50,51,46,45,40,41,63,62,49,48,47,44,} 43,42}; or {63,60,59,58,5,4,3,0,62,61,56,57,6,7,2,1,49,50,55,54,9,8,13,14,48,51,52,53,10,11,12,15,47,46,33,32,31,30,17,16,44,45,34,35,28,29,18,19,43,40,39,36,27,24,23,20,42,41,38,37,26,25,22} ,21} or {42,43,44,47,48,49,62,63,41,40,45,46,51,50,61,60,38,39,34,33,52,55,56,59,37,36,35,32,53,54,57,58,26,27,28,31,10,9,6,5,25,24,29,30,11,8,7,4,22,23,18,17,12,13,2,3,21,20,19,16,15,14,1,0}}; or {21,22,25,26,37,38,41,42,20,23,24,27,36,39,40,43,19,18,29,28,35,34,45,44,16,17,30,31,32,33,46,47,15,12,11,10,53,52,51,48,14,13,8,9,54,55,50,49,1,2,7,6,57,56,61,62,0,3,4,5,58,59,60,63}.

Images