Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a glass layer including a first region and a second region surrounding the first region; a plurality of first metal vias spaced apart from each other in the first region and each including a first via portion penetrating the glass layer; and a plurality of second metal vias spaced apart from each other in the second region and each including a second via portion penetrating the glass layer, in which the first via portion may have a maximum width smaller than a maximum width of the second via portion in a cross section of the printed circuit board.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0152703, filed on October 31, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] To meet the demands of high-performance and miniaturization strategies in the semiconductor industry, printed circuit boards (PCBs) require increasingly higher levels of miniaturization and density. For example, manufacturing high-end products such as server motherboards necessitates high wiring layer counts and large body sizes. However, as the number of wiring layers increases and the body size grows, PCBs can become prone to warping. To address this issue, the use of glass cores has been considered. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that increases the processing capability and design freedom of metal vias formed in a glass layer.

[0005] One of the various solutions disclosed herein is to form fine metal vias in the central region of the glass layer (as a signal concentration area and / or an electronic component mounting area) and to form metal vias in the peripheral region of the glass layer in a manner focused on heat dissipation and / or power transmission.

[0006] For example, a printed circuit board according to an example embodiment may include: a glass layer including a first region and a second region surrounding the first region; a plurality of first metal vias spaced apart from each other in the first region and each including a first via portion penetrating the glass layer; and a plurality of second metal vias spaced apart from each other in the second region and each including a second via portion penetrating the glass layer, wherein in a cross-section of the printed circuit board, the first via portion may have a maximum width smaller than the maximum width of the second via portion.

[0007] For example, a printed circuit board according to another example embodiment may include: a glass layer including a first region and a second region surrounding the first region; a first metal via disposed in the first region and including a first via portion, a first-first pad portion and a first-second pad portion, the first via portion penetrating the glass layer, the first-first pad portion being disposed on a first surface of the glass layer, and the first-second pad portion being disposed on a second surface of the glass layer; and a second metal via disposed in the second region and including a second via portion, a second-first pad portion and a second-second pad portion, the second via portion penetrating the glass layer, the second-first pad portion being disposed on the first surface of the glass layer, and the second-second pad portion being disposed on the second surface of the glass layer, and in the cross-section of the printed circuit board, the first-first pad portion may have a maximum width smaller than the maximum width of the second-first pad portion.

[0008] One of the various effects of this disclosure is to provide a printed circuit board that increases the processing capability and design freedom of metal vias formed in a glass layer. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which: Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system; Figure 2 This is a schematic cross-sectional view illustrating an example of a printed circuit board; Figure 3 It is a schematic representation of what it looks like when viewed from above. Figure 2 A plan view of the glass layer of a printed circuit board; Figure 4 This is a schematic cross-sectional view illustrating another example of a printed circuit board; Figure 5 It is a schematic representation of what it looks like when viewed from above. Figure 4 A plan view of the glass layer of a printed circuit board; Figure 6 This is a schematic cross-sectional view illustrating another example of a printed circuit board; and Figure 7 It is a schematic representation of what it looks like when viewed from above. Figure 6 A plan view of the glass layer of a printed circuit board. Detailed Implementation

[0010] In the following description, this disclosure will be made with reference to the accompanying drawings. In the drawings, the shape and size of the elements may be exaggerated or reduced for clarity.

[0011] Figure 1 This is a block diagram that schematically illustrates an example of an electronic device system.

[0012] Reference Figure 1 The electronic device 1000 houses a motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the motherboard 1010. These components are also connected to other electronic components, which will be described below, via various signal lines 1090.

[0013] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.); application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0014] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Global Microwave Access Interoperability (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolved Data Optimized (Ev-DO), Enhanced High-Speed ​​Packet Access+ (HSPA+), Enhanced High-Speed ​​Downlink Packet Access+ (HSDPA+), Enhanced High-Speed ​​Uplink Packet Access+ (HSUPA+), Global System for Mobile Communications (GSM), Evolution of GSM with Enhanced Data Rates (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (LAN), 3G, 4G, and 5G protocols, and any other wireless or wired standards or protocols specified after the foregoing. However, network-related components 1030 are not limited to these and may also include components compatible with or operating according to any of the various other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0015] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components in the form of chip modules for various other purposes. Furthermore, other components 1040 may be combined with each other in conjunction with chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), optical disc (CD) drives, digital versatile disc (DVD) drives, etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0017] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital camera, network system, computer, monitor, tablet computer (PC), laptop PC, netbook PC, television, video game console, smartwatch, automotive component, and server. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0018] Figure 2 This is a schematic cross-sectional view of an example of a printed circuit board.

[0019] Figure 3 It is a schematic representation of what it looks like when viewed from above. Figure 2 A plan view of the glass layer of a printed circuit board.

[0020] Reference Figure 2 and Figure 3 According to an example embodiment, a printed circuit board 100A (also referred to as a substrate) may include: a glass layer 111, including a first region R1 and a second region R2 surrounding the first region R1; a plurality of first metal vias 131, spaced apart from each other in the first region R1 and each including a first via portion 131a penetrating the glass layer 111; and a plurality of second metal vias 132, spaced apart from each other in the second region R2 and each including a second via portion 132a penetrating the glass layer 111. The first region R1 may include a portion adjacent to the center of the glass layer 111, and the second region R2 may include a portion adjacent to the edge of the glass layer 111. For example, the first region R1 may correspond to the central region of the glass layer 111, and the second region R2 may correspond to the peripheral region of the glass layer 111.

[0021] In this case, in the cross-section, the first via portion 131a may have a maximum width smaller than the maximum width of the second via portion 132a. For example, the maximum width (or diameter) of the first via portion 131a may be less than or equal to 60 μm, and the maximum width (or diameter) of the second via portion 132a may be greater than or equal to 100 μm. Here, for example, the maximum width (or diameter) of each via portion in the cross-section may be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by vertically polishing or cutting the substrate, and the cross-section may be a cross-section obtained by cutting the corresponding via portion along the central axis of the via portion. For example, in signal concentration areas, a denser design may be required, thereby forming a plurality of first metal vias 131 with small dimensions in the first region R1. For example, each of the plurality of first metal vias 131 may include a metal via for signal transmission. On the other hand, in other regions, a design focused on heat dissipation characteristics and / or power transmission rather than density may be required, thereby forming a plurality of second metal vias 132 with large dimensions in the second region R2. For example, each of the plurality of second metal vias 132 may include a metal via for power transmission and / or a metal via for heat dissipation. Here, the metal via for power transmission can also be used as a metal via for heat dissipation. This improves manufacturing capabilities. In addition, a high degree of design freedom is achieved.

[0022] From this perspective, the average pitch between the plurality of first metal vias 131 can be smaller than the average pitch between the plurality of second metal vias 132. Here, for example, the average pitch between the plurality of metal vias can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the substrate in a vertical direction, and the average pitch between adjacent metal vias can be used as the average pitch. In this case, as described above, a denser design can be more easily implemented in signal-concentrated areas, while in other areas, a design focused on heat dissipation characteristics and / or power transmission rather than density can be more easily implemented.

[0023] Furthermore, each of the plurality of first metal vias 131 may further include: a first-first pad portion 131b disposed on the upper surface (first surface) of the glass layer 111; and a first-second pad portion 131c disposed on the lower surface (second surface) of the glass layer 111. The first via portion 131a of each of the plurality of first metal vias 131 may connect to the corresponding first-first pad portion 131b and first-second pad portion 131c of the plurality of first metal vias 131. The first via portion 131a and the first-first pad portion 131b and the first-second pad portion 131c may be integrated with each other without boundaries, but this disclosure is not limited thereto. In addition, the plurality of second metal vias 132 may further include: a second-first pad portion 132b disposed on the upper surface (first surface) of the glass layer 111; and a second-second pad portion 132c disposed on the lower surface (second surface) of the glass layer 111. Each of the plurality of second metal vias 132 has a second via portion 132a that can connect to a corresponding second-first pad portion 132b and second-second pad portion 132c in the plurality of second metal vias 132. The second via portion 132a, the second-first pad portion 132b, and the second-second pad portion 132c can be integrated with each other without boundaries, but this disclosure is not limited thereto. In this way, when the metal via includes a pad portion, the connection reliability of the metal via with other connecting vias can be improved.

[0024] In this case, the maximum width (or diameter) of the first-first pad portion 131b in the cross-section can be smaller than the maximum width (or diameter) of the second-first pad portion 132b. Similarly, the maximum width (or diameter) of the first-second pad portion 131c in the cross-section can be smaller than the maximum width (or diameter) of the second-second pad portion 132c. Here, for example, the maximum width (or diameter) of each pad portion in the cross-section can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the substrate in a vertical direction, and the cross-section can be obtained by cutting the corresponding pad portion along its central axis. In this case, as described above, a denser design can be more easily implemented in signal-concentrated areas, while in other areas, a design focused on heat dissipation characteristics and / or power transmission rather than density can be more easily implemented.

[0025] From this perspective, the first-first pad portion 131b may have a smaller planar area than the second-first pad portion 132b. Similarly, the first-second pad portion 131c may have a smaller planar area than the second-second pad portion 132c. Here, for example, the planar area of ​​each pad portion may be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the substrate along a horizontal direction (perpendicular to the vertical direction). Other methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure. In this case, as described above, denser designs can be more easily implemented in signal-concentrated areas, while in other areas, designs focused on heat dissipation characteristics and / or power transmission rather than density can be more easily implemented.

[0026] Furthermore, if desired, the printed circuit board 100A according to the example embodiment may also include an electronic component 150 embedded in a first region R1 of the glass layer 111. A plurality of first metal vias 131 may be respectively disposed around the electronic component 150. For example, the plurality of first metal vias 131 may be centrally disposed in the region where the electronic component 150 is embedded. Furthermore, for example, the embedding step of the electronic component 150 may be implemented by forming a blind cavity or through cavity in the glass layer 111, disposing of the electronic component 150 in the blind cavity or through cavity, and then covering the electronic component 150 with an insulating material. Furthermore, a plurality of electronic components 150 may be provided, each of the plurality of electronic components 150 including a connection pad P. The plurality of electronic components 150 may be embedded together in a single cavity, or may be embedded separately in each cavity.

[0027] Furthermore, if necessary, the printed circuit board 100A according to the example embodiment may include: a frame 105 having a through portion H in which at least a portion of the glass layer 111 is disposed; a first insulating layer 112 covering the upper surface (first surface) and lower surface (second surface) of each of the frame 105 and the glass layer 111 and filling the space in the through portion H between the frame 105 and the glass layer 111; a first wiring layer 121 disposed on the upper surface (first surface) of the first insulating layer 112; and a first via layer 141 including a plurality of first connection vias, a plurality of first connections The vias penetrate the upper side (first side) of the first insulating layer 112 and connect the first wiring layer 121 to a plurality of first metal vias 131 and a plurality of second metal vias 132 and the connection pad P of the electronic component 150, respectively; the second wiring layer 122 is disposed on the lower surface (second surface) of the first insulating layer 112; and the second via layer 142 includes a plurality of second connection vias, which penetrate the lower side (second side) of the first insulating layer 112 and connect the second wiring layer 122 to a plurality of first metal vias 131 and a plurality of second metal vias 132, respectively.

[0028] In this way, the printed circuit board 100A according to the example embodiment may also include a frame 105 having a through-hole H, through which process warpage can be more easily controlled. Furthermore, the frame 105 can be arranged at the panel level, and in this case, the frame 105 can be used as a fixture to manufacture multiple printed circuit board 100A units in a single process, and multiple unit boards can be obtained through a splitting process. Additionally, the first insulating layer 112 may surround the frame 105 and the glass layer 111 and may fill the through-hole H, thereby achieving a stress relief effect. Furthermore, the freedom of wiring design can be increased by forming a first wiring layer 121 and a second wiring layer 122 on the upper surface (first surface) and lower surface (second surface) of the first insulating layer 112, respectively. Additionally, electrical connection paths can be provided in the substrate through the first via layer 141 and the second via layer 142.

[0029] Furthermore, if necessary, the printed circuit board 100A according to the example embodiment may also include: a plurality of second insulating layers 113 disposed on the upper surface (first surface) of the first insulating layer 112; a plurality of third wiring layers 123 disposed on the upper surface (first surface) of a corresponding second insulating layer 113 among the plurality of second insulating layers 113; and a plurality of third via layers 143 that penetrate the plurality of second insulating layers 113 and are respectively connected to adjacent third wiring layers 123 among the plurality of third wiring layers 123.

[0030] In this way, the printed circuit board 100A according to the example embodiment may have a multilayer substrate structure in which stacked layers (e.g., a plurality of second insulating layers 113, a plurality of third wiring layers 123, and / or a plurality of third via layers 143) are further formed on the upper side of the glass layer 111. For example, the printed circuit board 100A according to the example embodiment may be an intermediate substrate with an asymmetric structure. However, this disclosure is not limited thereto, and if desired, the stacked layers may be formed on both the upper and lower sides of the glass layer 111, and may be formed in an asymmetric manner. Optionally, if desired, the stacked layers may also be formed only on the lower side of the glass layer 111. In this case, the printed circuit board 100A according to the example embodiment may be a package substrate on which semiconductor chips are mounted. The package substrate may be a large-area substrate for servers, etc.

[0031] In the following description, the components of the printed circuit board 100A according to an exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0032] Frame 105 may comprise a material with excellent rigidity and may include, for example, copper-clad laminate (CCL) or bare CCL, but this disclosure is not limited thereto. For example, frame 105 may comprise other organic materials with excellent rigidity, or may comprise various types of inorganic materials with excellent rigidity. During the process, frame 105 can be used as a fixture, thus allowing panel-level processing via frame 105. Additionally, frame 105 may be retained in the final unit after the splitting process, which can further facilitate warpage control.

[0033] Glass layer 111 may comprise glass, which is an amorphous solid. The glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, this disclosure is not limited thereto, and alternative glass materials (such as fluorine glass, phosphate glass, and chalcogenide glass) may also be used as materials for glass layer 111. Additionally, glass layer 111 may further comprise other additives to form glass with specific physical properties. These additives may include elements such as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and / or carbonates (e.g., calcium carbonate (e.g., limestone), sodium carbonate (e.g., soda ash)) and / or oxides containing at least one of these elements. Furthermore, glass layer 111 may be a layer different from an organic insulating material layer (e.g., copper-clad laminate (CCL), prepreg (PPG), etc.) comprising glass fibers (e.g., glass fabric, such as glass cloth). Glass layer 111 may be in the form of, for example, a glass plate.

[0034] Each of the first insulating layer 112 and the second insulating layer 113 may comprise an organic insulating material. The organic insulating material may comprise a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating inorganic fillers, organic fillers, and / or glass fibers (e.g., glass fabric, such as glass cloth) in the aforementioned resin. For example, the organic insulating material may comprise prepreg (PPG), Ajinomoto laminate (ABF), photosensitive dielectric (PID), and bonding sheet (BS), but this disclosure is not limited thereto. The first insulating layer 112 and the second insulating layer 113 may comprise substantially the same material, but this disclosure is not limited thereto, and the first insulating layer 112 and the second insulating layer 113 may also comprise different materials. The second insulating layer 113 may be formed with a greater number of layers than shown in the figures or with a smaller number of layers than shown in the figures.

[0035] Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may include a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed based on the seed layer by an electrolytic plating process as a patterning layer. Each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may perform various functions according to the design. For example, each of the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123 may include signal patterns, power patterns, and ground patterns. Each of these patterns may have various shapes such as lines, traces, planes, and pads. Pads may be a concept including solder pads. The third wiring layer 123 may have more layers than shown in the figure, or it may have fewer layers than shown in the figure.

[0036] Each of the first metal via 131 and the second metal via 132 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first metal via 131 and the second metal via 132 may have a stacked structure of titanium and copper layers formed by sputtering and / or electroless plating processes as a seed layer. For example, each of the first metal via 131 and the second metal via 132 may include a sputtered titanium layer and a sputtered copper layer, a sputtered titanium layer and an electroless copper plating layer, or a sputtered titanium layer, a sputtered copper layer and an electroless copper plating layer. Alternatively, a copper layer formed based on the seed layer by an electrolytic plating process may be included as a plating layer. For example, each of the first metal via 131 and the second metal via 132 may include an electrolytically plated copper layer. The first metal via 131 may include a metal via for signal transmission. The second metal via 132 may include a metal via for power transmission and / or heat dissipation. The first via portion 131a of the first metal via 131 and the second via portion 132a of the second metal via 132 may each have a shape in which the side surfaces of the first via portion 131a and the second via portion 132a taper (e.g., hourglass shape), but are not limited thereto, and may each have a cylindrical shape in which the side surfaces of the first via portion 131a and the second via portion 132a are substantially vertical. Figure 3In the plan view shown, each of the first-first pad portion 131b and the first-second pad portion 131c of the first metal via 131, and the second-first pad portion 132b and the second-second pad portion 132c of the second metal via 132, may have a circular or elliptical shape, but is not limited thereto, and may have a polygonal shape if desired. Each of the first metal via 131 and the second metal via 132 may be provided in multiples.

[0037] Each of the first via layer 141, the second via layer 142, and the third via layer 143 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the first via layer 141, the second via layer 142, and the third via layer 143 may include a chemically plated copper layer formed by an electroless plating process as a seed layer, and may include an electrolytically plated copper layer formed based on the seed layer by an electrolytic plating process as a patterned plating layer. Each of the first via layer 141, the second via layer 142, and the third via layer 143 may perform various functions according to the design. For example, each of the first via layer 141, the second via layer 142, and the third via layer 143 may include signal vias, power vias, and ground vias. Each of the first via layer 141, the second via layer 142, and the third via layer 143 may include a filled via in which the via hole is filled with metal, or may include a conformal via in which metal is disposed along the wall surface of the via hole. Each of the first via layer 141, the second via layer 142, and the third via layer 143 may have a tapered shape. Each of the first via layer 141, the second via layer 142, and the third via layer 143 may include a plurality of connecting vias. The third via layer 143 may have more layers than shown in the figures or may have fewer layers than shown in the figures.

[0038] Electronic component 150 can be various types of active and / or passive components. For example, electronic component 150 may include integrated circuit devices (ICDs) and embedded passive integrated components (EPICs), but this disclosure is not limited thereto. Electronic component 150 may include connection pads P that contact the connection vias of the first via layer 141. Multiple electronic components 150 may be provided, and the multiple electronic components 150 may be identical to each other or may be different from each other.

[0039] Figure 4 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0040] Figure 5 It is a schematic representation of what it looks like when viewed from above. Figure 4 A plan view of the glass layer of a printed circuit board.

[0041] Reference Figure 4 and Figure 5 Compared to the printed circuit board 100A according to the above example embodiment, the printed circuit board 100B according to another example embodiment may further include a plurality of third metal vias 133. The plurality of third metal vias 133 may be respectively disposed in the first region R1, and may be disposed between the plurality of first metal vias 131 and the plurality of second metal vias 132. Each of the plurality of third metal vias 133 may include: a third via portion 133a, penetrating the glass layer 111; a third-first pad portion 133b, disposed on the upper surface (first surface) of the glass layer 111; and a third-second pad portion 133c, disposed on the lower surface (second surface) of the glass layer 111. In this case, in cross-section, the third via portion 133a may have a maximum width (or diameter) smaller than the maximum width (or diameter) of the second via portion 132a, but may have a maximum width (or diameter) larger than the maximum width (or diameter) of the first via portion 131a. Here, in the cross-section, the maximum width (or diameter) of each via portion can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the substrate in a vertical direction, and the cross-section can be obtained by cutting the corresponding via portion along the central axis of the via portion. For example, combinations of metal vias of various sizes can be designed according to design purposes.

[0042] From this perspective, the average pitch between the plurality of third metal vias 133 can be smaller than the average pitch between the plurality of second metal vias 132, but larger than the average pitch between the plurality of first metal vias 131. Here, for example, the average pitch between the plurality of metal vias can be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by polishing or cutting the substrate in a vertical direction, and the average pitch between adjacent metal vias can be used as the average pitch. In addition, in the cross-section, the third-first pad portion 133b and the third-second pad portion 133c can each have a maximum width (or diameter) smaller than the maximum width (or diameter) of the second-first pad portion 132b and the second-second pad portion 132c, but can each have a maximum width (or diameter) larger than the maximum width (or diameter) of the first-first pad portion 131b and the first-second pad portion 131c. Here, for example, the maximum width (or diameter) of each pad portion can be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by polishing or cutting the substrate in a vertical direction, and the cross-section can be obtained by cutting the corresponding pad portion along its central axis. Additionally, the third-first pad portion 133b and the third-second pad portion 133c may each have a smaller planar area than the second-first pad portion 132b and the second-second pad portion 132c, but may each have a larger planar area than the first-first pad portion 131b and the first-second pad portion 131c. Here, for example, the planar area of ​​each pad portion can be measured using a scanning electron microscope or an optical microscope based on a cross-section obtained by polishing or cutting the substrate in a horizontal direction.

[0043] In the following, the components of a printed circuit board 100B according to another exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0044] The third metal via 133 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the third metal via 133 may include a stacked structure of titanium and copper layers formed by sputtering and / or electroless plating processes as a seed layer. For example, the third metal via 133 may include a sputtered titanium layer and a sputtered copper layer, a sputtered titanium layer and an electroless copper plating layer, or a sputtered titanium layer, a sputtered copper layer, and an electroless copper plating layer. Alternatively, the third metal via 133 may include a copper layer formed based on the seed layer by an electrolytic plating process as a plating layer. For example, the third metal via 133 may include an electrolytic copper plating layer. The third metal via 133 may include a metal via for signal transmission, a metal via for power transmission, and / or a metal via for grounding transmission. The third via portion 133a of the third metal via 133 may have a shape in which the side surface of the third via portion 133a tapers (e.g., hourglass shape), but this disclosure is not limited thereto, and may have a cylindrical shape in which the side surface of the third via portion 133a is substantially vertical. In a plane, each of the third-first pad portion 133b and the third-second pad portion 133c of the third metal via 133 may have a circular shape or an elliptical shape, but is not limited thereto, and may have a polygonal shape if desired. Multiple third metal vias 133 may be provided.

[0045] Other descriptions are substantially the same as those in the printed circuit board 100A according to the above example embodiment, and therefore repeated descriptions will be omitted.

[0046] Figure 6 This is a schematic cross-sectional view illustrating another example of a printed circuit board.

[0047] Figure 7 It is a schematic representation of what it looks like when viewed from above. Figure 6 A plan view of the glass layer of a printed circuit board.

[0048] Reference Figure 6 and Figure 7Compared to the printed circuit board 100A according to the above example embodiment, the printed circuit board 100C according to another example embodiment can be constructed such that it includes a plurality of fourth metal vias 134 in the second region R2 instead of the plurality of second metal vias 132 described above. The plurality of fourth metal vias 134 may be located at substantially the same positions as the plurality of second metal vias 132 described above, and may perform substantially the same functions, but may have different via shapes. For example, each of the plurality of fourth metal vias 134 may include: a fourth via portion 134a penetrating the glass layer 111; a fourth-first pad portion 134b disposed on the upper surface (first surface) of the glass layer 111; and a fourth-second pad portion 134c disposed on the lower surface (second surface) of the glass layer 111. In this case, the fourth via portion 134a of each of the plurality of fourth metal vias 134 may include a plurality of vias. For example, the fourth via portion 134a of each of the plurality of fourth metal vias 134 can be in the form that the plurality of vias respectively penetrate the glass layer 111 located between the fourth-first pad portion 134b and the fourth-second pad portion 134c of each of the plurality of fourth metal vias 134 and respectively connect the fourth-first pad portion 134b and the fourth-second pad portion 134c. For example, each of the plurality of fourth metal vias 134 can have a form in which the pads and vias are connected in a one-to-many relationship. In this case, the effect can be further improved by increasing the surface area of ​​the fourth via portion 134a of each of the plurality of fourth metal vias 134 used for power transmission or heat dissipation.

[0049] Furthermore, in the cross-section, the maximum width (or diameter) of the fourth via portion 134a can be the sum of the maximum widths (or diameters) of each of the plurality of vias included in the fourth via portion 134a. Additionally, similar to the second via portion 132a described above, in the cross-section, the fourth via portion 134a may also have a maximum width (or diameter) larger than the maximum width (or diameter) of the first via portion 131a. Here, for example, in the cross-section, the maximum width (or diameter) of the via portion or the maximum width (or diameter) of each via can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by vertically polishing or cutting the substrate, and the cross-section can be a cross-section obtained by cutting the via portion or corresponding via along the central axis of the via portion or via.

[0050] In the following, the components of a printed circuit board 100C according to another exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0051] The fourth metal via 134 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the fourth metal via 134 may include a stacked structure of titanium and copper layers formed by sputtering and / or electroless plating processes as a seed layer. For example, the fourth metal via 134 may include a sputtered titanium layer and a sputtered copper layer, a sputtered titanium layer and an electroless copper plating layer, or a sputtered titanium layer, a sputtered copper layer, and an electroless copper plating layer. Alternatively, the fourth metal via 134 may include a copper layer formed based on the seed layer by an electrolytic plating process as a plating layer. For example, the fourth metal via 134 may include an electrolytic copper plating layer. The fourth metal via 134 may include metal vias for power transmission and / or metal vias for heat dissipation. Each of the plurality of vias included in the fourth via portion 134a of the fourth metal via 134 may have a tapered shape (e.g., hourglass shape) of the side surfaces of the plurality of vias, but is not limited thereto, and may also have a cylindrical shape in which the side surfaces of the plurality of vias are substantially vertical. In a planar plane, each of the fourth-first pad portion 134b and the fourth-second pad portion 134c of the fourth metal via 134 may have a circular or elliptical shape, but is not limited thereto, and may have a polygonal shape if desired. Multiple fourth metal vias 134 may be provided. There is no particular limitation on the number of vias included in the fourth via portion 134a.

[0052] Other descriptions are substantially the same as those in the printed circuit board 100A according to the above example embodiment, and therefore their repetition will be omitted. Furthermore, the plurality of fourth metal vias 134 in the printed circuit board 100C according to another example embodiment described above can also be applied to the printed circuit board 100B according to another example, replacing the plurality of second metal vias 132.

[0053] In this disclosure, the term "cover" can include covering a portion or the entirety of a component, and can also include direct and indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling, and can also include general filling. For example, "general filling" can include the presence of holes or gaps. Additionally, the term "surround" can include not only complete surrounding but also partial and general surrounding. Furthermore, the term "expose" can include not only complete exposure but also partial exposure, and can indicate that a feature is exposed from the component in which it is embedded. For example, exposing a pad through an opening in the resist layer can mean exposing the pad from the resist layer, and a surface treatment layer or the like can be further disposed on the exposed pad.

[0054] In this disclosure, in cross-section, the case where an object is disposed in a cavity or through portion includes not only cases where the object is completely disposed in the cavity or through portion, but also cases where the object partially protrudes upward or downward from the cavity or through portion. Furthermore, in a plane, this can be defined in a broader sense when an object is placed in a cavity or through portion.

[0055] In this disclosure, "basic" can be a concept that includes process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, "basically coplanar" can include not only cases where they are completely coplanar, but also cases where they are substantially coplanar. Furthermore, "set at substantially the same height" can include cases where they are set at substantially the same height and cases where they are set at exactly the same height. Additionally, "having a basically specific shape" can include not only cases where it completely has such a shape, but also cases where it substantially has such a shape.

[0056] In this disclosure, "the same insulating material" can refer not only to completely identical insulating materials, but also to insulating materials of the same type. Therefore, the composition of the insulating materials can be substantially the same, but the specific composition ratios of the insulating materials can be slightly different.

[0057] In this disclosure, the term "section" can refer to the cross-sectional shape when an object is cut vertically or the shape of an object when viewed from a side view. Furthermore, the term "plane" can refer to the cross-sectional shape when an object is cut horizontally or the planar shape of an object when viewed from a top or bottom view.

[0058] In this disclosure, for convenience, the term "lower" in "lower side," "lower part," and "lower surface" refers to a downward direction relative to the cross-section of the figures, and the term "upper side," "upper part," and "upper surface" refers to a direction opposite to the downward direction. However, the above directions are defined for ease of interpretation, and the scope of the claims is not specifically limited by the description of the directions, and the concepts of upper / lower can be changed at any time.

[0059] In this disclosure, the term "connection" is meant not only to include direct connections but also to include indirect connections such as those via adhesive layers. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, the first component may be referred to as the second component, or similarly, the second component may be referred to as the first component.

[0060] In this disclosure, thickness, width, length, depth, linewidth, gap, pitch, spacing, surface roughness, etc., can be measured using a scanning electron microscope, optical microscope, etc., based on a cross-section obtained by polishing or cutting a printed circuit board. The cross-section can be a vertical or horizontal cross-section, and the corresponding values ​​can be measured based on the desired cross-section. For example, the width of the upper and / or lower portion of a via can be measured in a cross-section already cut along the central axis of the via. In this case, when the value measured for one of them is not constant, the value of said one can be determined as the average of the values ​​measured at five arbitrary points. Other methods and / or other tools understood by those skilled in the art can be used even if not described in this disclosure.

[0061] The term "example embodiment" as used in this disclosure does not imply the same embodiment, but is provided to explain different unique characteristics. However, the example embodiments presented above do not preclude implementation through combinations of features with other example embodiments. For example, unless there is an interpretation contrary to or contradicting that of other example embodiments, even if content described in a particular example embodiment is not described in other example embodiments, it may be understood as an interpretation relating to other example embodiments.

[0062] The terminology used in this disclosure is for describing exemplary embodiments only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0063] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A glass layer, comprising a first region and a second region surrounding the first region; A plurality of first metal vias are spaced apart from each other in the first region and each includes a first via portion that penetrates the glass layer; as well as Multiple second metal vias, spaced apart from each other in the second region, each including a second via portion penetrating the glass layer. In the cross-section of the printed circuit board, the first via has a maximum width that is smaller than the maximum width of the second via.

2. The printed circuit board according to claim 1, in, The average pitch of the plurality of first metal vias is smaller than the average pitch of the plurality of second metal vias.

3. The printed circuit board according to claim 1, in, The first region includes a portion adjacent to the center of the glass layer, and The second region includes the portion adjacent to the edge of the glass layer.

4. The printed circuit board according to claim 1, in, Each of the plurality of first metal vias includes a metal via configured to transmit signals, and Each of the plurality of second metal vias includes a metal via configured to transmit power and / or a metal via configured to dissipate heat.

5. The printed circuit board according to claim 1, further comprising: Electronic components are embedded in the first region of the glass layer. The plurality of first metal vias are respectively disposed around the electronic components.

6. The printed circuit board according to claim 1, further comprising: Multiple third metal vias, spaced apart from each other in the first region, each include a third via portion penetrating the glass layer. The plurality of third metal vias are disposed between the plurality of first metal vias and the plurality of second metal vias, and In the cross-section of the printed circuit board, the third via portion has a maximum width that is smaller than the maximum width of the second via portion and larger than the maximum width of the first via portion.

7. The printed circuit board according to claim 6, in, The average pitch of the plurality of third metal vias is smaller than the average pitch of the plurality of second metal vias, but larger than the average pitch of the plurality of first metal vias.

8. The printed circuit board according to claim 1, further comprising: A frame having a through portion, wherein at least a portion of the glass layer is disposed in the through portion; A first insulating layer covers the first and second surfaces of the frame and the first and second surfaces of the glass layer, and fills the space in the through portion between the frame and the glass layer. A first wiring layer is disposed on a first surface of the first insulating layer; The first via layer includes a plurality of first connection vias that penetrate the first insulating layer on a first side and connect the first wiring layer to the plurality of first metal vias and the plurality of second metal vias respectively; A second wiring layer is disposed on a second surface of the first insulating layer; and The second via layer includes a plurality of second connection vias that penetrate the second side of the first insulating layer and connect the second wiring layer to the plurality of first metal vias and the plurality of second metal vias, respectively.

9. The printed circuit board according to claim 8, further comprising: Multiple second insulating layers are disposed on the first surface of the first insulating layer; Multiple third wiring layers are respectively disposed on the first surface of a corresponding second insulating layer in the multiple second insulating layers; as well as Multiple third via layers penetrate the multiple second insulating layers and are respectively connected to adjacent third wiring layers among the multiple third wiring layers.

10. The printed circuit board according to claim 1, wherein, Each of the plurality of second metal vias includes a plurality of vias in its second via portion.

11. The printed circuit board according to claim 1, wherein, In the plan view of the printed circuit board, the plurality of second metal vias surround the plurality of first metal vias.

12. The printed circuit board according to claim 6, wherein, In the plan view of the printed circuit board, the plurality of third metal vias surround the plurality of first metal vias.

13. A printed circuit board, comprising: A glass layer, comprising a first region and a second region surrounding the first region; A first metal via is disposed in the first region and includes a first via portion, a first-first pad portion and a first-second pad portion. The first via portion penetrates the glass layer, the first-first pad portion is disposed on a first surface of the glass layer, and the first-second pad portion is disposed on a second surface of the glass layer. as well as A second metal via is disposed in the second region and includes a second via portion, a second-first pad portion, and a second-second pad portion. The second via portion penetrates the glass layer, the second-first pad portion is disposed on the first surface of the glass layer, and the second-second pad portion is disposed on the second surface of the glass layer. In the cross-section of the printed circuit board, the first-first pad portion has a maximum width that is smaller than the maximum width of the second-first pad portion.

14. The printed circuit board according to claim 13, in, In the cross-section of the printed circuit board, the first-second pad portion has a maximum width smaller than the maximum width of the second-second pad portion.

15. The printed circuit board according to claim 14, wherein, The first-first pad portion has a smaller planar area than the second-first pad portion, and The first-second pad portion has a smaller planar area than the second-second pad portion.

16. The printed circuit board of claim 13, further comprising: A third metal via is disposed in the first region and includes a third via portion, a third-first pad portion, and a third-second pad portion. The third via portion penetrates the glass layer. The third-first pad portion is disposed on the first surface of the glass layer, and the third-second pad portion is disposed on the second surface of the glass layer. The third metal via is disposed between the first metal via and the second metal via, and In the cross-section of the printed circuit board: The third-first pad portion has a maximum width that is smaller than the maximum width of the second-first pad portion and larger than the maximum width of the first-first pad portion, and The third-second pad portion has a maximum width that is smaller than the maximum width of the second-second pad portion and larger than the maximum width of the first-second pad portion.

17. The printed circuit board according to claim 16, in, The third-first pad portion has a planar area that is smaller than the planar area of ​​the second-first pad portion and larger than the planar area of ​​the first-first pad portion, and The third-second pad portion has a planar area that is smaller than that of the second-second pad portion and larger than that of the first-second pad portion.

18. The printed circuit board according to claim 13, in, The second via portion includes a plurality of vias, which respectively penetrate the glass layer located between the second-first pad portion and the second-second pad portion and respectively connect the second-first pad portion and the second-second pad portion.

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