Manufacturing method of semiconductor memory device

Abstract

The invention relates to a manufacturing method of a semiconductor memory device. A method of manufacturing a semiconductor memory device includes forming an insulating layer; forming a preliminary laminate by alternately laminating a first material layer and a second material layer in a lamination direction over a surface of the insulating layer; forming a mask pattern over the preliminary stack, the mask pattern including a first opening, a second opening, and a plurality of grooves disposed around the first opening; forming a first hole and a second hole with different depths towards the insulating layer in a direction opposite to the lamination direction by etching the preliminary lamination piece under the condition that the plurality of grooves are shielded; and etching the preliminary stack through the first hole and the second hole with the plurality of grooves, the first opening, and the second opening being opened such that the first hole and the second hole extend deeper toward the insulating layer.

Description

Manufacturing method of semiconductor memory device Technical Field

[0001] Various embodiments of this disclosure generally relate to a method of manufacturing a semiconductor memory device, and more specifically, to a method of manufacturing a three-dimensional semiconductor memory device. Background Technology

[0002] Semiconductor memory devices are not only suitable for small electronic devices, but also for electronic systems in a wide range of fields such as automobiles, healthcare, and data centers. As a result, the demand for semiconductor memory devices is increasing.

[0003] Semiconductor memory devices include memory cells for data storage. A three-dimensional semiconductor memory device includes a plurality of memory cells arranged in a three-dimensional manner. Therefore, compared with two-dimensional semiconductor memory devices, three-dimensional semiconductor memory devices are more advantageous for increasing capacity.

[0004] The integration density of memory cells in a three-dimensional semiconductor memory device can be increased by increasing the number of stacked memory cells. As the number of stacked memory cells increases, the number of stacked conductive layers connected to the memory cells also increases. These conductive layers are connected to gate contact plugs and electrically connected to peripheral circuitry via the gate contact plugs. However, increasing the number of stacked conductive layers may lead to a deterioration in the process stability and operational reliability of the semiconductor memory device. Summary of the Invention

[0005] According to one embodiment, a method of manufacturing a semiconductor memory device may include the following steps: forming a first insulating layer; forming a preliminary stack by alternately stacking a second insulating layer of a plurality of second insulating layers and a sacrificial layer of a plurality of sacrificial layers above the surface of the first insulating layer along a stacking direction; forming a mask pattern above the preliminary stack, the mask pattern including a plurality of first openings, a plurality of second openings, a plurality of third openings, and a plurality of grooves disposed around the plurality of first openings; forming a first set of holes exposing the uppermost sacrificial layer among the sacrificial layers by etching the preliminary stack through the plurality of first openings, the plurality of second openings, and the plurality of third openings; forming a second set of holes corresponding to the plurality of first openings, the plurality of second openings, and the plurality of third openings respectively by repeatedly performing an etching process on the preliminary stack while the plurality of grooves are masked, the plurality of holes in the second set of holes having different depths facing the first insulating layer in a direction opposite to the stacking direction; and forming a third set of holes by etching the preliminary stack through the plurality of first openings and the plurality of second openings while leaving the plurality of grooves open and leaving one or more of the plurality of holes in the second set of holes open.

[0006] According to one embodiment, a method of manufacturing a semiconductor memory device may include the following steps: forming an insulating layer; forming a preliminary stack by alternately stacking a first material layer of a plurality of first material layers and a second material layer of a plurality of second material layers in a stacking direction above the surface of the insulating layer; forming a mask pattern above the preliminary stack, the mask pattern including a first opening, a second opening, and a plurality of grooves disposed around the first opening; forming a first hole and a second hole of different depths toward the insulating layer in a direction opposite to the stacking direction by etching the preliminary stack through the first opening and the second opening while the plurality of grooves are blocked; and etching the preliminary stack through the first hole and the second hole while the plurality of grooves, the first opening, and the second opening are open, such that the first hole and the second hole extend deeper toward the insulating layer. Attached Figure Description

[0007] Figure 1 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure;

[0008] Figure 2 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figures 3A and 3B are diagrams illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figures 4A and 4B are plan views and cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Figures 5A and 5B are plan and cross-sectional views illustrating a preliminary laminate, unit pillar, and mask layer according to an embodiment of the present disclosure.

[0012] Figures 6A and 6B are plan and cross-sectional views illustrating a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure;

[0013] Figures 7A, 7B, 7C, 7D, 7E and 7F are cross-sectional views showing a plurality of holes and a plurality of sacrificial pillars according to an embodiment of the present disclosure;

[0014] Figures 8A and 8B are plan and cross-sectional views illustrating a gate stack according to an embodiment of the present disclosure.

[0015] Figures 9A and 9B are cross-sectional views showing a plurality of contact holes and a plurality of contact posts according to an embodiment of the present disclosure;

[0016] Figures 10A and 10B are plan views and cross-sectional views illustrating a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure; and

[0017] Figure 11 is a cross-sectional view showing a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure. Detailed Implementation

[0018] The specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are shown only for the purpose of illustrating examples of embodiments of the concepts, and examples of embodiments of the concepts can be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0019] Terms such as “first” and “second” are used to distinguish various elements without implying the size, order, priority, quantity, or importance of the elements. For example, in one example, a first element may be named a second element, and in another example, a second element may be named a first element. Terms such as “top,” “above,” “upper,” “side,” “upper,” “lower,” “row,” “column,” “inner,” and “outer,” as well as other terms that imply relative spatial relationships or directions, are used only for the purpose of description or reference to the accompanying drawings and are not intended to be limiting in any other way. Cross-shading throughout the drawings indicates corresponding or similar areas between the drawings and does not indicate material associated with these areas. It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “attached to” another element or layer, that element or layer may be directly on, directly connected to, or directly attached to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly linked to" another element or layer, there is no intermediate element or layer.

[0020] Various embodiments of this disclosure provide a method for manufacturing a semiconductor memory device that can improve process stability and operational reliability.

[0021] Figure 1 is a block diagram illustrating an electronic system 1000 including a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Referring to Figure 1, the electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200.

[0023] Host 1100 can store data in storage device 1200 or retrieve data stored in storage device 1200 based on an interface. The interface may include one or more of the following: Double Data Rate (DDR) interface, Universal Serial Bus (USB) interface, Multimedia Card (MC) interface, Embedded MMC (eMMC) interface, Peripheral Component Interconnect (PCI) interface, PCI Express (PCI-E) interface, Advanced Technology Attachment (ATA) interface, Serial ATA interface, Parallel ATA interface, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE) interface, FireWire interface, Universal Flash Memory (UFS) interface, and Non-Volatile Memory Express (NVMe) interface.

[0024] Storage device 1200 may include memory controller 1210 and semiconductor memory device 1220. In one embodiment, storage device 1200 may be a storage medium such as a solid-state drive (SSD), universal serial bus (USB) memory, etc.

[0025] The memory controller 1210 can store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100.

[0026] Semiconductor memory device 1220 may include one or more memory chips. Semiconductor memory device 1220 may store data or output stored data under the control of memory controller 1210.

[0027] Semiconductor memory device 1220 may be a non-volatile memory device. Semiconductor memory device 1220 may include a memory cell array and peripheral circuitry for controlling the operation of the memory cell array. The memory cell array may include a plurality of memory cells. Each memory cell may be a non-volatile memory cell. In one embodiment, each memory cell may be a NAND flash memory cell. Hereinafter, embodiments of the present disclosure are described based on semiconductor memory devices including NAND flash memory cells, but the teachings are not limited thereto. In another embodiment, each memory cell may be configured as a ferroelectric memory cell, a variable resistance memory cell, etc.

[0028] Figure 2 is a circuit diagram illustrating a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure.

[0029] Referring to Figure 2, the memory cell array may include multiple memory cell strings CS1 and CS2. The multiple memory cell strings CS1 and CS2 can form a memory block, and the memory block is electrically connected to peripheral circuitry (not shown) through a gate array GA, a bit line array BA, and a common source layer CSR.

[0030] Each of the plurality of memory cell strings CS1 and CS2 includes at least one source selection transistor (e.g., SST1), a plurality of memory cells MC1 to MCn (where n is a natural number greater than or equal to 2), and at least one drain selection transistor (e.g., DST1). In one embodiment, each of the plurality of memory cell strings CS1 and CS2 may include: a plurality of source selection transistors SST1 to SSTk (where k is a natural number greater than or equal to 2 and less than n), which are connected in series between the common source layer CSR and the plurality of memory cells MC1 to MCn; and a plurality of drain selection transistors DST1 to DSTm (where m is a natural number greater than or equal to 2 and less than n), which are connected in series between the bit line array BA and the plurality of memory cells MC1 to MCn. The plurality of memory cells MC1 to MCn are connected in series between the drain selection transistor (e.g., DST1) and the source selection transistor (e.g., SSTk).

[0031] A gate array (GA) includes at least one source-select gate group (e.g., SSG), a cell gate group (CG), and at least one drain-select gate group (e.g., DSG1). In one embodiment, the gate array (GA) may include: a first drain-select gate group (DSG1) and a second drain-select gate group (DSG2) connected to a memory cell string in units smaller than the cell gate group (CG); and a source-select gate group (SSG) connected to the memory cell string in units equal to the cell gate group (CG). For example, multiple memory cell strings (CS1 and CS2) may include a first memory cell string (CH1) connected to the first drain-select gate group (DSG1) and a second memory cell string (CS2) connected to the second drain-select gate group (DSG2). Each of the cell gate group (CG) and the source-select gate group (SSG) may be connected to the first memory cell string (CS1) and may extend to be connected to the second memory cell string (CS2).

[0032] A source-select gate group (SSG) includes at least one source select line (e.g., SSL1). In one embodiment, the source-select gate group (SSG) may include multiple source select lines SSL1 to SSLk. The multiple source select lines SSL1 to SSLk are respectively connected to multiple gate electrodes of multiple source select transistors SST1 to SSTk.

[0033] The cell gate group CG may include multiple word lines WL1 to WLn. The multiple word lines WL1 to WLn are respectively connected to multiple gate electrodes of multiple memory cells MC1 to MCn.

[0034] Each of the first drain-select gate group DSG1 and the second drain-select gate group DSG2 includes at least one drain select line (e.g., DSL1). According to one embodiment, each of the first drain-select gate group DSG1 and the second drain-select gate group DSG2 may include multiple drain select lines DSL1 to DSLm. The multiple drain select lines DSL1 to DSLm are respectively connected to multiple gate electrodes of multiple drain select transistors DST1 to DSTm.

[0035] The bit line array BA includes multiple bit lines BL. Multiple memory cell strings CS1 and CS2 can be divided into multiple columns connected to the multiple bit lines BL. In one embodiment, each column of memory cell strings can be connected to its corresponding bit line BL. For example, a pair of first memory cell strings CS1 and second memory cell strings CS2 can be included in one column.

[0036] The gate array GA is electrically connected to the external circuitry via gate contact plugs on contact posts. The contact posts are described below with reference to Figures 3A and 3B.

[0037] Figures 3A and 3B are diagrams illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0038] Referring to Figures 3A and 3B, the semiconductor memory device includes a peripheral circuit structure PCS, a doped semiconductor structure DPS, multiple gate stacks GST, a bit line array BA, multiple cell pillars CPL, and multiple contact pillars CTP. The doped semiconductor structure DPS, multiple gate stacks GST, bit line array BA, multiple cell pillars CPL, and multiple contact pillars CTP are disposed above the peripheral circuit structure PCS.

[0039] The peripheral circuit structure (PCS) may include input / output circuits, control circuits, voltage generation circuits, row decoders, column decoders, page buffers, etc. The peripheral circuit structure may include multiple transistor PTRs constituting at least some of the above components and multiple interconnect ICs connected to the transistors. The multiple transistor PTRs may include transmission transistors constituting transmission circuits.

[0040] Each transistor PTR is disposed in the active region of the semiconductor substrate SUB, and the active region is separated by an isolation layer ISO. The semiconductor substrate SUB includes a semiconductor material. In one embodiment, the semiconductor material may include one or more of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, and InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0041] The semiconductor substrate SUB may also include a dielectric layer. In one embodiment, the semiconductor substrate SUB may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor substrate SUB may also include organic materials. In one embodiment, the semiconductor substrate SUB may include graphene.

[0042] The semiconductor substrate SUB can be a bulk wafer or an epitaxial layer grown by selective epitaxial growth (SEG). Alternatively, the semiconductor substrate SUB can be a layer formed by metal-induced lateral crystallization (MILC) and may partially include metal.

[0043] The semiconductor substrate SUB can be monocrystalline, polycrystalline, or amorphous. The semiconductor substrate SUB can include Group II, III, IV, V, or VI impurities. In one embodiment, the semiconductor substrate SUB can include an n-well region doped with n-type impurities, a p-well region doped with p-type impurities, or both an n-well region and a p-well region.

[0044] Multiple transistors (PTRs) are covered by a peripheral insulating structure (PIS) on a semiconductor substrate (SUB). Multiple interconnects (ICs) can be formed within the PIS and include multiple conductive lines and multiple conductive contacts for electrical connections.

[0045] The semiconductor substrate SUB may include a cell array region (CAR) and a gate contact region (GCR). Multiple transistor PTRs may be disposed within the cell array region (CAR) and the gate contact region (GCR) of the semiconductor substrate SUB. The multiple transistor PTRs may include transfer transistors disposed within the gate contact region (GCR).

[0046] Multiple gate stacks (GSTs) are disposed between the bit line array (BA) and the doped semiconductor structure (DPS). A first insulating layer (IL1) is disposed between each gate stack (GST) and the doped semiconductor structure (DPS).

[0047] Each gate stack (GST) includes multiple conductive layers (CDLs). The multiple conductive layers (CDLs) are stacked spaced apart from each other over the surface of the first insulating layer (IL1) opposite the doped semiconductor structure (DPS). Each of the multiple conductive layers (CDLs) may include various conductive materials such as doped semiconductor layers and metal layers. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. Each of the multiple conductive layers (CDLs) may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The multiple conductive layers (CDLs) can be used as the gate array (GA) shown in FIG2. The multiple conductive layers (CDLs) can be used as the source-select gate group (SSG) shown in FIG2, the first drain-select gate group (DSG1) and the second drain-select gate group (DSG2) shown in FIG2, and the unit gate group (CG) shown in FIG2. At least one conductive layer among the multiple conductive layers (CDLs) adjacent to the doped semiconductor structure (DPS) can be used as the source-select gate group (SSG) shown in FIG2. At least one conductive layer in the multiple conductive layers CDL that is adjacent to the bit line array BA can be used as the first drain-select gate group DSG1 and the second drain-select gate group DSG2 as shown in FIG2.

[0048] Each gate layer stack (GST) may also include multiple second insulating layers (IL2). The multiple second insulating layers (IL2) may be arranged alternately with multiple conductive layers (CDL). Each of the first insulating layer (IL1) and the multiple second insulating layers (IL2) may include an insulating material such as a silicon oxide layer or a silicon oxide nitride layer.

[0049] Each of the first insulating layer IL1, the plurality of conductive layers CDL, and the plurality of second insulating layers IL2 is disposed on the cell array region CAR of the semiconductor substrate SUB and extends to be disposed on the gate contact region GCR of the semiconductor substrate SUB. A gate separation structure GSS may be disposed between adjacent gate layer stacks GST. The gate separation structure GSS may include filler in the slot formed between adjacent gate layer stacks GST. The filler may be designed in various ways. In one embodiment, the filler may include an insulating layer. In another embodiment, in addition to an insulating layer, the filler may also include one or both of a conductive layer and a semiconductor layer.

[0050] Multiple cell pillars (CPLs) are disposed on the cell array region (CAR) of the semiconductor substrate (SUB) and extend through each gate layer stack (GST). The cell pillars (CPLs) extend through the first insulating layer (IL1) to contact the doped semiconductor structure (DPS). Each of multiple conductive layers (CDLs) and multiple second insulating layers (IL2s) may surround the sidewall of each cell pillar (CPL). The cell pillars (CPLs) include channel pillars (CHPs) and memory layers (MLs).

[0051] The channel pillar CHP can be electrically connected to a corresponding bit line in the multiple bit lines BL of the bit line array BA via the bit line connection structure BCC. The channel pillar CHP may include a contact surface that contacts the doped semiconductor structure DPS. The contact surface may be located on a portion of the sidewall of the channel pillar CHP, the end of the channel pillar CHP, etc. According to one embodiment, referring to FIG3B, the doped semiconductor structure DPS may include a groove for inserting the end of the channel pillar CHP, and the contact surface between the end of the channel pillar CHP and the doped semiconductor structure DPS may be formed along the groove.

[0052] Multiple contact pillars (CTPs) are disposed on the gate contact region (GCR) of the semiconductor substrate (SUB). The contact pillars (CTPs) are embedded in each gate stack (GST). The contact pillars (CTPs) are spaced apart from the first insulating layer (IL1) at varying distances and extend in a direction opposite to that toward the first insulating layer (IL1). Each contact pillar (CTP) includes a gate contact plug (GCT) and a sidewall insulating layer (SWI).

[0053] A gate contact plug (GCT) is a conductive pattern that contacts a corresponding conductive layer among multiple conductive layers (CDL). The gate contact plug (GCT) can include various conductive materials. In one embodiment, the gate contact plug (GCT) can include a barrier layer and a metal layer. The barrier layer can include a conductive metal nitride layer such as titanium nitride, tantalum nitride, or molybdenum nitride. The metal layer can include tungsten, molybdenum, etc. The barrier layer can extend along the outer wall of the metal layer.

[0054] The sidewall insulating layer (SWI) surrounds the sidewall of the gate contact plug (GCT). The portion of the multiple conductive layers (CDL) that is penetrated by the gate contact plug (GCT) is insulated from the gate contact plug (GCT) by the sidewall insulating layer (SWI).

[0055] One of the doped semiconductor structure (DPS) and the bit line array (BA) is positioned closer to the peripheral circuit structure (PCS) than the other. In one embodiment, as shown in FIG3A, the doped semiconductor structure (DPS) may be positioned closer to the peripheral circuit structure (PCS) than the bit line array (BA). In another embodiment, as shown in FIG3B, the bit line array (BA) may be positioned closer to the peripheral circuit structure (PCS) than the doped semiconductor structure (DPS).

[0056] Referring to Figures 3A and 3B, a doped semiconductor structure (DPS) may include at least one doped semiconductor layer. The doped semiconductor layer of the DPS may include either n-type or p-type impurities. In one embodiment, the DPS includes one or both of a first conductivity type doped semiconductor layer containing n-type impurities as majority carriers and a second conductivity type doped semiconductor layer containing p-type impurities as majority carriers. The first conductivity type doped semiconductor layer may be used as a common source layer (CSR) as described with reference to Figure 2, and the second conductivity type doped semiconductor layer may be used as a well region.

[0057] Referring to Figure 3A, a doped semiconductor structure (DPS) can be disposed between a peripheral insulating structure (PIS) and a gate stack (GST). The doped semiconductor structure (DPS) can be penetrated by a source isolation insulating layer (SIL). In one embodiment, the first insulating layer (IL1) and the gate stack (GST) can overlap with the doped semiconductor structure (DPS) and the source isolation insulating layer (SIL). A gate contact plug (GCT) can be electrically connected to a transfer transistor in a plurality of transistor PTRs via a gate contact connection structure (GCC) and a gate contact pad (GCP). For this purpose, the semiconductor memory device may also include conductive connection structures (not shown) for electrically connecting interconnects corresponding to transfer transistors and gate contact pads (GCPs) in a plurality of interconnects (ICs).

[0058] Referring to Figure 3B, the gate stack GST and bit line array BA can be disposed between the doped semiconductor structure DPS and the peripheral circuit structure PCS. The semiconductor memory device may include: a gate contact pad GCP disposed between the gate contact region GCR and the gate stack GST of the semiconductor substrate SUB; and a gate contact connection structure GCC disposed between the gate contact pad GCP and the gate contact plug GCT. The gate contact plug GCT can be electrically connected to the gate contact pad GCP through the gate contact connection structure GCC.

[0059] Referring to FIG3B, a semiconductor memory device may include a plurality of first conductive bonding patterns BP1 and a plurality of second conductive bonding patterns BP2 disposed between a bit line array BA and a peripheral insulating structure PIS. The plurality of first conductive bonding patterns BP1 may be disposed in a first intermediate insulating structure IS1. Each of the plurality of bit lines BL and the gate contact pad GCP may be connected to a corresponding first conductive bonding pattern BP1 among the plurality of first conductive bonding patterns BP1. The plurality of second conductive bonding patterns BP2 may be disposed in a second intermediate insulating structure IS2 between the first intermediate insulating structure IS1 and the peripheral insulating structure PIS. Each of the plurality of second conductive bonding patterns BP2 may be connected to a corresponding interconnect IC. The plurality of second conductive bonding patterns BP2 may be bonded to the plurality of first conductive bonding patterns BP1. Therefore, the gate contact plug GCT may be electrically connected to a corresponding transfer transistor in a plurality of transistors PTR via the gate contact connection structure GCC, the gate contact pad GCP, the first conductive bonding patterns BP1, the second conductive bonding patterns BP2, and the interconnect IC.

[0060] Figures 4A and 4B are plan and cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0061] Referring to Figure 4A, each of the plurality of gate stacks (GSTs) can extend in the XY plane to overlap with the cell array region (CAR) and gate contact region (GCR) of the semiconductor substrate in the Z-axis direction. A plurality of cell pillars (CPLs) and a plurality of contact pillars (CTP1 and CTP2) extend in the respective gate stacks (GSTs) along the Z-axis direction.

[0062] Multiple cell pillars (CPLs) can be arranged in multiple rows and multiple columns. Each row includes cell pillars arranged in a straight line in the X-axis direction, and each column includes cell pillars arranged in a straight line in the Y-axis direction. Multiple rows can be divided into multiple groups using a select line separation structure (SLS). In one embodiment, the multiple cell pillars (CPLs) can be divided into a first group of rows and a second group of rows using the select line separation structure (SLS). The select line separation structure (SLS) is embedded in the gate stack (GST) and has a shorter length in the Z-axis direction than the gate separation structure (GSS). Cell pillars in different groups of rows can be controlled group-by-group using select lines separated by the select line separation structure (SLS). In one embodiment, the select line separation structure (SLS) can divide a portion of the multiple conductive layers (CDLs) shown in Figures 3A and 3B into a first drain select gate group (DSG1) and a second drain select gate group (DSG2) as shown in Figure 2. For example, the cell pillars constituting the first group of rows can correspond to the cell pillars of the first memory cell string (CS1) shown in Figure 2, and they can be controlled by the drain select lines of the first drain select gate group (DSG1) as shown in Figure 2. The cell pillars constituting the second row can correspond to the cell pillars of the second memory cell string CS2 as shown in Figure 2, and they can be controlled by the drain select line of the second drain select gate group DSG2 as shown in Figure 2.

[0063] The gate stack (GST) may include a first gate contact region (GCR1) and a second gate contact region (GCR2) extending from the first gate contact region (GCR1) along the XY plane. The first gate contact region (GCR1) may be disposed between the cell array region (CAR) and the second gate contact region (GCR2). The select line separation structure (SLS) may extend on the boundary between the first gate contact region (GCR1) and the second gate contact region (GCR2).

[0064] Multiple contact pillars CTP1 and CTP2 can be divided into multiple first contact pillars CTP1 and multiple second contact pillars CTP2. The multiple first contact pillars CTP1 are embedded in the gate stack GST in the first gate contact region GCR1, and the multiple second contact pillars CTP2 are embedded in the gate stack GST in the second gate contact region GCR2.

[0065] Multiple support pillars SP can be arranged around each second contact pillar CTP2. Each of the support pillars SP can extend in the Z-axis direction to penetrate the gate stack GST.

[0066] Figure 4B is a cross-sectional view of a semiconductor memory device taken along line I-I' shown in Figure 4A.

[0067] Referring to Figures 4A and 4B, each unit pillar CPL and each support pillar SP penetrate the first insulating layer IL1, multiple conductive layers 1CDL and 2CDL of the gate stack GST, and multiple second insulating layers 1IL2 and 2IL2 of the gate stack GST.

[0068] The support column SP may include insulating material.

[0069] The unit column CPL includes the memory layer ML and the channel column CHP.

[0070] A memory layer ML is disposed between a channel pillar CHP and a gate stack GST. The memory layer ML may include a tunnel insulating layer extending along the sidewalls of the channel pillar CHP, a data storage layer disposed between the tunnel insulating layer and the gate stack GST, and a barrier insulating layer disposed between the data storage layer and the gate stack GST. The tunnel insulating layer may include an oxide such as silicon dioxide (SiO2). The barrier insulating layer may include an oxide such as silicon dioxide (SiO2), a high-k dielectric insulating material having a higher dielectric constant than silicon dioxide, etc. The high-k dielectric insulating material may include an aluminum oxide layer, a hafnium oxide layer, etc. The data storage layer may include a material layer capable of storing data altered by using Fowler-Nordheim tunneling. In one embodiment, the data storage layer may include a charge-trapping insulating layer, a floating gate layer, or an insulating layer comprising conductive nanodots. The charge-trapping insulating layer may include a silicon nitride layer. The data storage layer including the floating gate layer may be separated into multiple data storage patterns. Multiple data storage patterns can be spaced apart from each other in the Z-axis direction, which is the stacking direction of the first insulating layer IL1, multiple conductive layers 1CDL and 2CDL, and multiple second insulating layers 1IL2 and 2IL2. The multiple data storage patterns can be respectively disposed at the heights of the multiple conductive layers 1CDL and 2CDL. The data storage layer, including a charge-trapping insulating layer or an insulating layer containing conductive nanodots, can be separated into multiple data storage patterns as described above, or can extend continuously in the Z-axis direction.

[0071] Each channel pillar CHP may include a channel layer CLL. The channel layer CLL may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof, serving as the channel region for a string of memory cells. The channel layer CLL may have a tubular shape. The channel pillar CHP may also include a core insulating layer CO and a capping pattern CAP disposed in the central region of the tubular shape including the channel layer CLL. The capping pattern CAP may include a semiconductor layer doped with conductive impurities. The conductive impurities may include n-type impurities, or n-type and p-type impurities. In one embodiment, the capping pattern CAP may include n-type doped silicon, which includes n-type impurities as majority carriers.

[0072] The gate stack GST may include a plurality of sub-layer stacks arranged continuously along the Z-axis. In one embodiment, the gate stack GST may include a first sub-layer stack S1 above a first insulating layer IL1 and a second sub-layer stack S2 above the first sub-layer stack S1. A plurality of conductive layers 1CDL and 2CDL may be divided into a plurality of first sub-conductive layers 1CDL of the first sub-layer stack S1 and a plurality of second sub-conductive layers 2CDL of the second sub-layer stack S2, and a plurality of second insulating layers 1IL2 and 2IL2 may be divided into a plurality of first sub-second insulating layers 1IL2 of the first sub-layer stack S1 and a plurality of second sub-second insulating layers 2IL2 of the second sub-layer stack S2.

[0073] Each of the memory layer ML and the channel layer CLL may have a corner portion formed near the interface between the plurality of sublayers. In one embodiment, each of the memory layer ML and the channel layer CLL may have a corner portion formed near the interface between the first sublayer stack S1 and the second sublayer stack S2.

[0074] The upper surface of the gate stack GST, which is opposite to the first insulating layer IL1, can be covered by the third insulating layer 41.

[0075] The select line separation structure SLS can penetrate the third insulating layer 41 and extend into the gate stack GST. The select line separation structure SLS may include an insulator. The select line separation structure SLS can be formed in a conductive layer that serves as a drain select line, penetrating through multiple conductive layers 1CDL and 2CDL, but not penetrating to the depth of the conductive layer that serves as a word line.

[0076] Each of the plurality of first contact pillars CTP1 and the plurality of second contact pillars CTP2 has a gate contact plug GCT1 or GCT2 and a sidewall insulating layer SWI1 or SWI2 that can penetrate the third insulating layer 41 and extend into the gate layer stack GST. The plurality of first contact pillars CTP1 are respectively connected to a plurality of drain select lines separated by a select line separation structure SLS. In the Z-axis direction, the depth of the plurality of second contact pillars CTP2 toward the first insulating layer IL1 is greater than the depth of the plurality of first contact pillars CTP1 toward the first insulating layer IL1. The plurality of second contact pillars CTP2 can be formed at different depths toward the first insulating layer IL1 in a direction opposite to the Z-axis direction to connect to other conductive layers in the plurality of conductive layers 1CDL and 2CDL besides the conductive layer provided as the drain select line.

[0077] The upper surface of the third insulating layer 41, which is opposite to the gate stack GST, can be covered by the fourth insulating layer 43.

[0078] The bit line connection structure BCC may include conductive material that passes through the third insulating layer 41 and the fourth insulating layer 43 and is connected to the channel post CHP. The fourth insulating layer 43 may be penetrated by a first gate contact connection structure GCC1 and a second gate contact connection structure GCC2, both including conductive material. The first gate contact connection structure GCC1 is connected to the first gate contact plug GCT1 of the corresponding first contact post CTP1. The second gate contact connection structure GCC2 is connected to the second gate contact plug GCT2 of the corresponding second contact post CTP2.

[0079] As described above, the depth of the plurality of second contact posts CTP2 toward the first insulating layer IL1 in the Z-axis direction is greater than the depth of the plurality of first contact posts CTP1 toward the first insulating layer IL1 in the Z-axis direction. The second contact posts CTP2 have different aspect ratios.

[0080] Hereinafter, embodiments of a method for providing a semiconductor memory device as shown in Figures 4A and 4B are described.

[0081] Figures 5A and 5B are plan and cross-sectional views illustrating a preliminary laminate, unit pillars, and mask layer according to an embodiment of the present disclosure.

[0082] Referring to Figures 5A and 5B, a first insulating layer 101 and a preliminary laminate 100 can be formed over a lower structure (not shown). Although not shown, according to one embodiment, the lower structure may include a semiconductor substrate SUB, which includes a plurality of transistor PTRs (as shown in Figure 3A) and a doped semiconductor structure DPS (as shown in Figure 3A). In another embodiment, the lower structure may be a sacrificial substrate including a silicon wafer or the like. In subsequent processes, the sacrificial substrate can be replaced by the doped semiconductor structure DPS as shown in Figure 3B.

[0083] The first insulating layer 101 may include an insulating material such as a silicon oxide layer or a silicon oxide nitride layer. The first insulating layer 101 may include a surface 101S extending in the XY plane and facing the Z-axis direction. The first insulating layer 101 may include a cell array region CAR and a gate contact region GCR extending from the cell array region CAR. The gate contact region GCR may include a first gate contact region GCR1 and a second gate contact region GCR2. The first gate contact region GCR1 may be disposed between the cell array region CAR and the second gate contact region GCR2.

[0084] The initial laminate 100 may include a plurality of first material layers and a plurality of second material layers different from the plurality of first material layers. In one embodiment, the plurality of first material layers may include a plurality of sacrificial layers 103A and 103B having etch selectivity relative to the first insulating layer 101, and the plurality of second material layers may include a plurality of second insulating layers 105A and 105B. In one embodiment, the first insulating layer 101 and the plurality of second insulating layers 105A and 105B may include insulating materials such as silicon oxide layers or silicon oxide nitride layers, and the plurality of sacrificial layers 103A and 103B may include sacrificial insulating materials such as silicon nitride layers. The plurality of sacrificial layers 103A and 103B and the plurality of second insulating layers 105A and 105B may be laminated in the Z-axis direction facing the surface 101S of the first insulating layer 101. The plurality of sacrificial layers 103A and 103B and the plurality of second insulating layers 105A and 105B may be alternately arranged with each other in the Z-axis direction, which is the lamination direction.

[0085] A portion of the first insulating layer 101 of the cell array region CAR and a portion of the preliminary stack 100 on the cell array region CAR can be penetrated by a plurality of cell posts 120. Each cell post 120 is disposed in a channel hole penetrating the preliminary stack 100 and the first insulating layer 101. In one embodiment, the channel hole can be provided by performing a process of forming a plurality of sub-holes such that the plurality of sub-holes can be interconnected with each other. For example, the process of forming the channel hole may include: forming a lower stack 100A of the preliminary stack 100; forming a first sub-hole penetrating the lower stack 100A and the first insulating layer 101; forming a fill structure in the first sub-hole; forming an upper stack 100B of the preliminary stack 100 above the lower stack 100A such that the fill structure can be covered; forming a second sub-hole penetrating the upper stack 100B and aligned with the fill structure; and removing the fill structure such that the first sub-hole can be opened. Multiple sacrificial layers 103A and 103B can be divided into a first sub-sacrificial layer 103A of the lower stack 100A and a second sub-sacrificial layer 103B of the upper stack 100B, and multiple second insulating layers 105A and 105B of the preliminary stack 100 can be divided into a first sub-second insulating layer 105A of the lower stack 100A and a second sub-second insulating layer 105B of the upper stack 100B. A first sub-via penetrates the first sub-sacrificial layer 103A and the first sub-second insulating layer 105A, and a second sub-via penetrates the second sub-sacrificial layer 103B and the second sub-second insulating layer 105B.

[0086] The process of forming multiple cell pillars 120 includes forming a memory layer 121 on the inner wall of a channel via and forming channel pillars 123 in the channel via. The memory layer 121 may include a barrier insulating layer, a data storage layer, and a tunnel insulating layer as described with reference to Figures 4A and 4B. The channel pillars 123 are formed in the central region of the channel via exposed by the memory layer 121. In one embodiment, the step of forming the channel pillars 123 may include forming a channel layer 123A on the inner wall of the memory layer 121; and filling the central region of the tubular structure formed by the channel layer 123A with a core insulating layer 125 and a cover pattern 123B. The channel layer 123A may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof serving as the channel region. The cover pattern 123B may include a doped semiconductor layer.

[0087] The initial stack 100 is penetrated by a plurality of support pillars 131. In one embodiment, the plurality of support pillars 131 may penetrate the first insulating layer 101 of the second gate contact region GCR2 and extend along the Z-axis to pass through the initial stack 100. In one embodiment, the plurality of support pillars 131 may include an insulating material. Embodiments of this disclosure are not limited thereto, and each support pillar 131 may be provided using a process for forming a channel via and a process for forming a cell pillar 120, and may be configured in the same manner as the cell pillar 120.

[0088] Figure 5B is a cross-sectional view of the preliminary laminate 100 taken along line I-I' in Figure 5A.

[0089] Referring to FIG5B, the initial laminate 100, which is penetrated by the memory layer 121, the channel post 123, and the plurality of support posts 131, may be covered by a third insulating layer 141. The third insulating layer 141 may include an insulating material such as a silicon oxide layer or a silicon oxide nitride layer.

[0090] Subsequently, a mask layer 151L may be formed over the third insulating layer 141. The mask layer 151L has etch selectivity relative to the first insulating layer 101, the plurality of sacrificial layers 103A and 103B, the plurality of second insulating layers 105A and 105B, and the third insulating layer 141. In one embodiment, the mask layer 151L may include a silicon layer.

[0091] Figures 6A and 6B are plan and cross-sectional views illustrating a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure.

[0092] Referring to Figures 6A and 6B, a first photoresist pattern 161 is formed over the mask layer 151L shown in Figure 5B. The first photoresist pattern 161 has a plurality of etched holes 161H1A, 161H1B, 161H2, and 161H3, and a plurality of auxiliary holes AH. The plurality of etched holes 161H1A, 161H1B, 161H2, and 161H3, and the plurality of auxiliary holes AH overlap with the first insulating layer 101 of the gate contact region GCR. In the XY plane, each of the plurality of auxiliary holes AH and the plurality of etched holes 161H1A, 161H1B, 161H2, and 161H3 may have a cross-sectional structure, which has various shapes including polygons (such as rectangles or squares), ellipses, circles, and semicircles. In the XY plane, each of the multiple auxiliary holes AH is narrower than each of the multiple etched holes 161H1A, 161H1B, 161H2 and 161H3.

[0093] The plurality of etched holes 161H1A, 161H1B, 161H2, and 161H3 may include a plurality of first etched holes 161H1A and 161H1B, a plurality of second etched holes 161H2, and a plurality of third etched holes 161H3. The plurality of third etched holes 161H3 overlap with the first insulating layer 101 of the first gate contact region GCR1, and the plurality of first etched holes 161H1A and 161H1B and the plurality of second etched holes 161H2 overlap with the first insulating layer 101 of the second gate contact region GCR2. The plurality of first etched holes 161H1A and 161H1B may be divided into a first group of first etched holes 161H1A and a second group of first etched holes 161H1B.

[0094] Multiple auxiliary holes AH can be disposed around multiple first etched holes 161H1A and 161H1B. Compared with the auxiliary holes AH around the first etched holes 161H1A in the first group, more auxiliary holes AH are disposed around the first etched holes 161H1B in the second group. In one embodiment, two auxiliary holes AH can be disposed around each first etched hole 161H1A in the first group, and four auxiliary holes AH can be disposed around each first etched hole 161H2B in each second group.

[0095] Figure 6B is a cross-sectional view of the first photoresist pattern 161 and mask pattern 151 taken along line I-I' of Figure 6A.

[0096] Referring to Figure 6B, a mask pattern 151 is formed by etching some areas of the mask layer 151L shown in Figure 5B using a first photoresist pattern 161 as an etching barrier. The mask pattern 151 has a plurality of grooves GV and a plurality of openings 151OP1A, 151OP1B, 151OP2, and 151OP3. The plurality of grooves GV are formed by etching areas of the mask layer corresponding to a plurality of auxiliary holes AH, and the plurality of openings 151OP1A, 151OP1B, 151OP2, and 151OP3 are formed by etching areas of the mask layer corresponding to a plurality of etched holes 161H1A, 161H1B, 161H2, and 161H3. Therefore, in the XY plane, each of the plurality of grooves GV is narrower than each of the plurality of openings 151OP1A, 151OP1B, 151OP2, and 151OP3.

[0097] Because the multiple etched holes 161H1A, 161H1B, 161H2, and 161H3 are wider than the multiple auxiliary holes AH, during the etching of the mask layer, the etching depth of the regions of the mask layer corresponding to the multiple etched holes 161H1A, 161H1B, 161H2, and 161H3 is greater than the etching depth of the regions of the mask layer corresponding to the multiple auxiliary holes AH. The etching process of the mask layer can be controlled so that the depths of the multiple openings 151OP1A, 151OP1B, 151OP2, and 151OP3 can have a depth that completely penetrates the mask layer, and the bottom surface of each of the multiple recesses GV can be disposed in the mask layer. Therefore, the third insulating layer 141 can be exposed through the multiple openings 151OP1A, 151OP1B, 151OP2, and 151OP3, and a portion of the mask layer can be inserted between the multiple recesses GV and the third insulating layer 141.

[0098] During the etching of the mask layer, the upper end of each of the plurality of auxiliary holes AH may be spaced apart from the upper end of the first etched hole 161H1A or 161H1B adjacent to it.

[0099] The plurality of openings 151OP1A, 151OP1B, 151OP2, and 151OP3 may include a plurality of first openings 151OP1A and 151OP1B, a plurality of second openings 151OP2, and a plurality of third openings 151OP3. The plurality of first openings 151OP1A and 151OP1B are divided into a first group of first openings 151OP1A corresponding to a first group of first etched holes 161H1A and a second group of first openings 151OP1B corresponding to a second group of first etched holes 161H1B. The plurality of second openings 151OP2 correspond to a plurality of second etched holes 161H2. The plurality of first openings 151OP1A and 151OP1B, and the plurality of second openings 151OP2 overlap with the first insulating layer 101 of the second gate contact region GCR2. The plurality of third openings 151OP3 correspond to a plurality of third etched holes 161H3 and overlap with the first insulating layer 101 of the first gate contact region GCR1.

[0100] Multiple grooves GV can be arranged around multiple first openings 151OP1A and 151OP1B. The grooves GV arranged around the first opening 151OP1B in the second group are more numerous than the grooves arranged around the first opening 151OP1A in the first group.

[0101] Figures 7A, 7B, 7C, 7D, 7E and 7F are cross-sectional views showing a plurality of holes and a plurality of sacrificial pillars according to an embodiment of the present disclosure.

[0102] Referring to FIG7A, a portion of the preliminary laminate 100 and the third insulating layer 141 can be etched such that the uppermost sacrificial layer among the plurality of sacrificial layers 103A and 103B of the preliminary laminate 100 can be exposed by a first etching process. The first etching process can be performed by introducing etching gas via a plurality of first openings 151OP1A and 151OP1B, a plurality of second openings 151OP2 and a plurality of third openings 151OP3 as described with reference to FIG6B. The uppermost second insulating layer among the plurality of second insulating layers 105A and 105B of the preliminary laminate 100 can be etched by the first etching process.

[0103] A first set of holes HA1, HB1, HC1, HD1, HE1, HF1, HG1, and HH1 can be formed through a first etching process to have a first depth D1 in the Z-axis direction toward the first insulating layer 101. Each hole can have a first depth D1 to penetrate the third insulating layer 141 and the uppermost second insulating layer of the preliminary laminate 100. The plurality of holes HA1, HB1, HC1, HD1, HE1, HF1, HG1, and HH1 in the first set of holes include a first contact hole HA1 and first preliminary holes HB1, HC1, HD1, HE1, HF1, HG1, and HH1.

[0104] Referring to FIG7B, after removing the first photoresist pattern 161 shown in FIG7A, a second photoresist pattern 163 can be formed. The second photoresist pattern 163 can open at least one of the first opening 151OP1B, the plurality of second openings 151OP2, and at least one of the plurality of third openings 151OP3 in the second group, and can fill and block the first opening 151OP1A, the other second openings 151OP2, the other third openings 151OP3, and the plurality of grooves GV in the first group. A portion of the first preliminary holes HB1, HC1, HD1, HE1, HF1, HG1, and HH1 shown in FIG7A, as well as the first contact hole HA1, are filled by the second photoresist pattern 163, while the other first preliminary holes (e.g., HB1, HD1, HF1, and HH1 shown in FIG7A) are left open.

[0105] Subsequently, the preliminary stack 100 is etched using a second photoresist pattern 163 as an etching barrier via a second etching process. The second etching process can be performed by introducing etching gas through a first preliminary aperture (e.g., HB1, HD1, HF1, and HH1 shown in FIG. 7A) opened by the second photoresist pattern 163. The second etching process is performed such that it penetrates the uppermost sacrificial layer among the plurality of sacrificial layers 103A and 103B of the preliminary stack 100. According to one embodiment, the preliminary stack 100 can be etched in the Z-axis direction toward the first insulating layer 101 to a second etching depth D2 via the second etching process. The preliminary stack 100 can be etched to the second etching depth D2 to penetrate the uppermost sacrificial layer (the uppermost of the plurality of sacrificial layers 103A and 103B) and the lower second insulating layer (the second insulating layer 105B located below the uppermost sacrificial layer among 105A and 105B).

[0106] Through a second etching process, a second contact hole HB2 and multiple second preliminary holes HD2, HF2 and HH2 are formed to have a greater depth than the first depth D1 in the Z-axis direction toward the first insulating layer 101.

[0107] Referring to FIG7C, after removing the second photoresist pattern 163 shown in FIG7B, a third photoresist pattern 165 can be formed. The third photoresist pattern 165 can open a portion of the plurality of first openings 151OP1A and 151OP1B, a portion of the plurality of second openings 151OP2, and a portion of the plurality of third openings (not shown in FIG7C), and can fill and block other second openings 151OP2, other third openings 151OP3, and a plurality of grooves GV. The third photoresist pattern 165 fills a portion (HF2) of the plurality of second preliminary holes HD2, HF2, and HH2 shown in FIG7B, and leaves the others (HD2 and HH2) open. A portion (HE1) of the first preliminary holes HC1, HE1, and HG1 shown in FIG7B is filled by the third photoresist pattern 165, while the others (HC1 and HG1) are left open. The first contact hole HA1 and the second contact hole HB2 are filled by the third photoresist pattern 165.

[0108] Subsequently, the preliminary laminate 100 is etched using a third photoresist pattern 165 as an etching barrier via a third etching process. The third etching process can be performed by introducing etching gas through first preliminary vias (e.g., HC1 and HG1 shown in FIG. 7B) and second preliminary vias HD2 and HH2 opened by the third photoresist pattern 165. The third etching process can be performed by etching the preliminary laminate 100 toward the first insulating layer 101 in the Z-axis direction to a third etching depth D3, thereby further penetrating the two sacrificial layers 103A and 103B and the two second insulating layers 105A and 105B.

[0109] Through the third etching process, multiple third preliminary holes HC3, HD3, HG3 and HH3 can be formed to have a depth greater than the depth of the second contact hole HB2 in the Z-axis direction toward the first insulating layer 101.

[0110] Referring to FIG7D, after removing the third photoresist pattern 165 as shown in FIG7C, a fourth photoresist pattern 167 can be formed. The fourth photoresist pattern 167 can open a portion of the plurality of first openings 151OP1A and 151OP1B, a portion of the plurality of second openings 151OP2, and a portion of the plurality of third openings (not shown in FIG7C), and can fill and block other second openings 151OP2, other third openings 151OP3, and a plurality of grooves GV. The fourth photoresist pattern 167 fills a portion (HC3 and HD3) of the third preliminary holes HC3, HD3, HG3, and HH3 as shown in FIG7C, and leaves the others (HG3 and HH3) open. As shown in FIG7C, the first preliminary hole HE1 and the second preliminary hole HF2, the first contact hole HA1, and the second contact hole HB2 are filled by the third photoresist pattern 165.

[0111] Subsequently, the preliminary laminate 100 is etched using a fourth photoresist pattern 167 as an etching barrier via a fourth etching process. The fourth etching process can be performed by introducing etching gas through the third preliminary vias HG3 and HH3 (as shown in FIG. 7C) opened by the fourth photoresist pattern 167, and the first preliminary via HE1 and the second preliminary via HF2 (as shown in FIG. 7C) also opened by the fourth photoresist pattern 167. The fourth etching process can be performed by etching the preliminary laminate 100 toward the first insulating layer 101 in the Z-axis direction to a third etching depth D3, thereby further penetrating the two sacrificial layers 103A and 103B and the two second insulating layers 105A and 105B.

[0112] Through the fourth etching process, multiple fourth preliminary holes HE4, HF4, HG4 and HH4 can be formed to have a depth greater than that of the third preliminary holes HC3 and HD3 in the Z-axis direction toward the first insulating layer 101.

[0113] Multiple holes in the second set of holes formed by the second to fourth etching processes, corresponding to multiple first openings 151OP1A and 151OP1B, multiple second openings 151OP2, and multiple third openings 151OP3, can be formed at different depths facing the first insulating layer 101 in a direction opposite to the Z-axis direction. The multiple holes in the second set of holes include multiple first holes corresponding to multiple first openings 151OP1A and 151OP1B, multiple second holes corresponding to multiple second openings 151OP2, and multiple third holes corresponding to multiple third openings 151OP3. The multiple first holes include fourth preliminary holes HG4 and HH4, the multiple second holes include third preliminary holes HC3 and HD3 and fourth preliminary holes HE4 and HF4, and the multiple third holes include a first contact hole HA1 and a second contact hole HB2. Compared to the first contact hole HA1 and the second contact hole HB2 of the plurality of third holes, the fourth preliminary holes HG4 and HH4 of the plurality of first holes, and the third preliminary holes HC3 and HD3 and the fourth preliminary holes HE4 and HF4 of the plurality of second holes, have a greater depth toward the first insulating layer 101. Compared to the third preliminary holes HC3 and HD3 and the fourth preliminary holes HE4 and HF4 of the plurality of second holes, the fourth preliminary holes HG4 and HH4 of the plurality of first holes have a greater depth toward the first insulating layer 101. Compared to the fourth preliminary hole HG4 corresponding to the second opening 151OP1A in the first group, the fourth preliminary hole HH4 corresponding to the first opening 151OP1B in the second group has a greater depth toward the first insulating layer 101.

[0114] Referring to FIG7E, after removing the fourth photoresist pattern 167 as shown in FIG7D, a fifth photoresist pattern 169 can be formed. The fifth photoresist pattern 169 can open a plurality of first openings 151OP1A and 151OP1B, a plurality of second openings 151OP2, and a plurality of grooves GV, and can fill and block a plurality of third openings 151OP3. The fifth photoresist pattern 169 can open a portion of the plurality of holes HA1, HB2, HC3, HD3, HE4, HF4, HG4, and HH4 of the second group of holes (as shown in FIG7D), and can block other holes. In one embodiment, the third preliminary holes HC3 and HD3 and the fourth preliminary holes HE4, HF4, HG4, and HH4 as shown in FIG7D can be opened by the fifth photoresist pattern 169, and the first contact hole HA1 and the second contact hole HB2 can be blocked by the fifth photoresist pattern 169.

[0115] The fifth etching process can be performed by introducing etching gas through multiple first openings 151OP1A and 151OP1B and multiple second openings 151OP2 while multiple grooves GV are open.

[0116] A fifth etching process is performed to expose the lowest sacrificial layer (the lowest of sacrificial layers 103A and 103B). This fifth etching process can be performed by etching the initial stack 100 toward the first insulating layer 101 in the Z-axis direction to a depth greater than the etching depth in each of the first through fourth etching processes. According to one embodiment, the fifth etching process can be performed by etching the initial stack 100 to a fourth etching depth D4, thereby further etching four of the plurality of sacrificial layers 103A and 103B and two of the plurality of second insulating layers 105A and 105B.

[0117] Through the fifth etching process, as shown in Figure 7D, the plurality of holes HC5, HD5, HE5, HF5, HG5, and HH5 in the third group of holes can be formed to have a greater depth in the Z-axis direction toward the first insulating layer 101 than the depths of the fourth preliminary holes HG4 and HH4 of the plurality of first holes, the third preliminary holes HC3 and HD3 of the plurality of second holes, and the fourth preliminary holes HE4 and HF4. The plurality of holes HC5, HD5, HE5, HF5, HG5, and HH5 in the third group of holes are plurality of third contact holes having a greater depth than the depths of the first contact hole HA1 and the second contact hole HB2 and having different depths.

[0118] In the fifth etching process, which is performed at a greater etching depth compared to the first through fourth etching processes, the etching rate at the bottom of the hole can be significantly lower. Specifically, the larger the aspect ratio of the hole, the lower the ion energy reaching the bottom of the hole. According to one embodiment of this disclosure, by forming multiple grooves GV around the first openings 151OP1A and 151OP1B corresponding to the holes with larger aspect ratios, the inflow of etching gas can be increased, thereby compensating for the reduction in ion energy reaching the bottom surface of the holes with high aspect ratios. Therefore, according to one embodiment of this disclosure, even if holes with different aspect ratios are formed simultaneously at greater depths, holes with different aspect ratios can be stably provided at the target depth.

[0119] Referring to FIG7F, after removing the fifth photoresist pattern 169 to open the first contact hole HA1 and the second contact hole HA2 as shown in FIG7E, a plurality of holes HC5, HD5, HE5, HF5, HG5 and HH5 in the third group of holes are filled with a plurality of sacrificial pillars 171. Each sacrificial pillar 171 has etch selectivity relative to the plurality of sacrificial layers 103A and 103B and the plurality of second insulating layers 105A and 105B. In one embodiment, the sacrificial pillar 171 may comprise an amorphous carbon layer.

[0120] Figures 8A and 8B are plan views and cross-sectional views illustrating a gate stack according to an embodiment of the present disclosure. Figure 8B is a cross-sectional view of the gate stack taken along line I-I' of Figure 8A.

[0121] Referring to Figures 8A and 8B, a slit 191 is formed through the preliminary laminate 100 shown in Figure 7F. Subsequently, the plurality of sacrificial layers 103A and 103B of the preliminary laminate 100 shown in Figure 7F can be replaced by a plurality of conductive layers 193 through the slit 191. As a result, a gate laminate 190 can be formed. When the plurality of sacrificial layers 103A and 103B shown in Figure 7F are replaced by a plurality of conductive layers 193, a plurality of support pillars 131, a plurality of unit pillars 120, and a plurality of sacrificial pillars 171 can be used as a support structure.

[0122] After the gate stack 190 is formed, the slit 191 can be filled with a filler. As a result, a gate-separated structure GSS as described with reference to FIG4A can be provided.

[0123] Subsequently, a selective line separation structure 195 can be formed that passes through a portion of the multiple conductive layers 193.

[0124] Figures 9A and 9B are cross-sectional views showing a plurality of contact holes and a plurality of contact posts according to embodiments of the present disclosure.

[0125] Referring to FIG9A, the multiple sacrificial pillars 171 shown in FIG8B can be removed to expose multiple conductive layers 193. As a result, the first contact hole HA1, the second contact hole HB2, and multiple holes HC5, HD5, HE5, HF5, HG5, and HH5, which are multiple third contact holes, can be opened.

[0126] Referring to FIG9B, a first contact post 180A can be formed in each of the first contact hole HA1 and the second contact hole HB2 shown in FIG9A, and a second contact post 180B can be formed in the plurality of holes HC5, HD5, HE5, HF5, HG5 and HH5 of the third group of holes shown in FIG9A. The process of forming the first contact post 180A and the second contact post 180B may include: a process of forming a sidewall insulating layer 181A or 181B on the sidewall of each of the first contact hole HA1, the second contact hole HB2 and the plurality of holes HC5, HD5, HE5, HF5, HG5 and HH5 of the third group of holes shown in FIG9A; and a process of forming a gate contact plug 183A or 183B by filling the central region of each of the first contact hole HA1, the second contact hole HB2 and the plurality of holes HC5 and HD5, HE5, HF5, HG5 and HH5 of the third group of holes shown in FIG9A with a conductive material. Gate contact plugs 183A or 183B include a bottom surface that contacts a corresponding one of the plurality of conductive layers 193, and the gate contact plugs are insulated from the other conductive layers by sidewall insulating layers 181A or 181B.

[0127] After the first contact post 180A and the second contact post 180B are formed, subsequent processes can be performed, such as forming the fourth insulating layer 43 as shown in FIG4B, and forming the bit line connection structure BCC through the fourth insulating layer 43 as shown in FIG4B, as well as the first gate contact connection structure GCC1 and the second gate contact connection structure GCC2.

[0128] Figures 10A and 10B are plan and cross-sectional views illustrating a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure. Figure 10B is a cross-sectional view of the first photoresist pattern 161 and mask pattern 151 taken along line I-I' of Figure 10A.

[0129] Referring to Figures 10A and 10B, after forming the first insulating layer 101, the preliminary laminate 100, the memory layer 121, the channel layer 123A and cover pattern 123B of the channel pillar 123 as described with reference to Figures 5A and 5B, the core insulating layer 125, the third insulating layer 141, and the mask layer (151L shown in Figure 5B), a first photoresist pattern 161 is formed above the mask layer. As described above with reference to Figures 6A and 6B, the first photoresist pattern 161 includes a plurality of first etched holes 161H1A′ and 161H1B′, a plurality of second etched holes 161H2, a plurality of third etched holes 161H3, and a plurality of auxiliary holes AH′. In the XY plane, the plurality of auxiliary holes AH′ can have a smaller area than each of the plurality of first etched holes 161H1A′ and 161H1B′, the plurality of second etched holes 161H2, and the plurality of third etched holes 161H3, and can have a shape in which the major axis faces the plurality of first etched holes 161H1A′ and 161H1B′ and the minor axis intersects the major axis. According to one embodiment, in the XY plane, each of the plurality of auxiliary holes AH′ can have an elliptical or rectangular cross-sectional structure with its major axis facing the adjacent first etched hole 161H1A′ or 161H1B′ and the minor axis orthogonal to the major axis.

[0130] Subsequently, some areas of the mask layer 151L shown in FIG. 5B are etched using the first photoresist pattern 161 as an etching barrier, thereby forming the mask pattern 151. As described with reference to FIG. 6B, the mask pattern 151 has a plurality of grooves GV and a plurality of openings 151OP1A, 151OP1B, 151OP2 and 151OP3. During the etching of the mask layer, the upper ends of each of the plurality of auxiliary holes AH′ and the upper ends of the plurality of first etched holes 161H1A′ and 161H1B′ can extend in the XY plane. Therefore, the upper end of each auxiliary hole AH′ can be connected to the adjacent first etched hole 161H1A′ or 161H1B′.

[0131] Subsequently, the semiconductor memory device shown in FIG4A and FIG4B can be provided by performing the processes described with reference to FIG7A to FIG7F, the processes described with reference to FIG8A and FIG8B, and the processes described with reference to FIG9A and FIG9B.

[0132] Figure 11 is a cross-sectional view showing a first photoresist pattern and a mask pattern according to an embodiment of the present disclosure.

[0133] Referring to FIG11, after forming the first insulating layer 101, the preliminary laminate 100, the memory layer 121, the channel layer 123A and the cover pattern 123B of the channel pillar 123 as described with reference to FIGS. 5A and 5B, the core insulating layer 125, the third insulating layer 141, and the mask layer (151L shown in FIG. 5B), a first photoresist pattern 161 is formed above the mask layer. As shown in FIGS. 10A and 10B, the first photoresist pattern 161 includes a plurality of first etched holes 161H1A′ and 161H1B′, a plurality of second etched holes 161H2, a plurality of third etched holes 161H3, and a plurality of auxiliary holes AH′.

[0134] Subsequently, a portion of the mask layer 151L, as shown in FIG. 5B, is etched using a first photoresist pattern 161 as an etching barrier, thereby forming the mask pattern 151. As described with reference to FIG. 5B, the mask pattern 151 has a plurality of grooves GV″, a plurality of first openings 151OP1A″ and 151OP1B″, a plurality of second openings 151OP2, and a plurality of third openings 151OP3. During the etching of the mask layer, each of the plurality of auxiliary holes AH′ shown in FIG. 10B and the corresponding first etched hole 161H1A′ or 161H1B′ can extend in the XY plane to connect with each other. Thus, a plurality of extended first etched holes 161H1A″ and 161H1B″ as shown in FIG. 11 can be formed. During the etching of the mask layer, the upper ends of each of the plurality of grooves GV″ and the upper ends of the plurality of first openings 151OP1A″ and 151OP1B″ can extend in the XY plane. Therefore, the top of each groove GV” can be connected to the first opening 151OP1A″ or 151OP1B″ adjacent to it.

[0135] Subsequently, the semiconductor memory device shown in FIG4A and FIG4B can be provided by performing the processes described with reference to FIG7A to FIG7F, the processes described with reference to FIG8A and FIG8B, and the processes described with reference to FIG9A and FIG9B.

[0136] According to one embodiment of this disclosure, the inflow of etching gas can be increased by using a groove disposed around an opening in a mask pattern.

[0137] According to one embodiment of this disclosure, by controlling the position of the grooves, holes with different aspect ratios can be formed simultaneously, thereby reducing the difference in etching rates when forming holes with different aspect ratios. Therefore, the process of forming holes with different aspect ratios can be simplified and the process stabilized. Furthermore, by reducing defects in holes with different aspect ratios, the operational reliability of the semiconductor memory device can be improved.

[0138] Cross-references to related applications

[0139] This application claims priority to Korean Patent Application No. 10-2024-0152946, filed with the Korean Intellectual Property Office on October 31, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Form the first insulating layer; A preliminary laminate is formed by alternately stacking a second insulating layer of a plurality of second insulating layers and a sacrificial layer of a plurality of sacrificial layers above the surface of the first insulating layer along the stacking direction; A mask pattern is formed over the initial laminate, the mask pattern including a plurality of first openings, a plurality of second openings, a plurality of third openings, and a plurality of grooves disposed around the plurality of first openings; A first set of holes is formed by etching the initial stack through the plurality of first openings, the plurality of second openings and the plurality of third openings to expose the uppermost sacrificial layer in the sacrificial layer; By repeatedly performing an etching process on the preliminary laminate while the plurality of grooves are blocked, a second set of holes is formed corresponding to the plurality of first openings, the plurality of second openings and the plurality of third openings, respectively. The plurality of holes in the second set of holes have different depths toward the first insulating layer in a direction opposite to the lamination direction. And a third set of holes is formed by etching the preliminary stack through the plurality of first openings and the plurality of second openings, with the plurality of grooves open and one or more of the plurality of holes in the second set of holes open.

2. The method according to claim 1, wherein, Compared to repeatedly etching the initial stack, the etching depth of the initial stack toward the first insulating layer is greater when forming multiple holes in the third set of holes.

3. The method according to claim 1, wherein, When measured on a plane parallel to the surface of the first insulating layer, each of the plurality of grooves is narrower than each of the plurality of first openings, each of the plurality of second openings, and each of the plurality of third openings.

4. The method according to claim 1, wherein, When the plurality of recesses are obscured, the step of repeatedly performing an etching process on the preliminary laminate includes repeating the etching cycle at least twice, wherein the etching cycle includes: forming a photoresist pattern over the mask pattern to fill the plurality of recesses and open at least one first opening of the plurality of first openings, at least one second opening of the plurality of second openings, and at least one third opening of the plurality of third openings; etching the preliminary laminate by using the photoresist pattern as an etching barrier to penetrate at least one of the sacrificial layers; and removing the photoresist pattern.

5. The method according to claim 1, wherein, The second group of holes includes a plurality of first holes corresponding to the plurality of first openings, a plurality of second holes corresponding to the plurality of second openings, and a plurality of third holes corresponding to the plurality of third openings, wherein, in a direction opposite to the stacking direction, the plurality of first holes and the plurality of second holes have a greater depth toward the first insulating layer than the plurality of third holes, and wherein, in a direction opposite to the stacking direction, the plurality of first holes have a greater depth toward the first insulating layer than the plurality of second holes.

6. The method according to claim 5, wherein, The step of forming the third set of holes includes the following steps: forming a photoresist pattern over the mask pattern to open the plurality of recesses, open the plurality of first holes, and open and fill the plurality of third holes; using the photoresist pattern as an etching barrier to etch the initial stack to expose the lowest sacrificial layer among the sacrificial layers; and removing the photoresist pattern.

7. The method according to claim 5, wherein, The plurality of first openings includes a first group of first openings and a second group of first openings, wherein the plurality of first holes includes a first hole in the first group of holes corresponding to a first opening in the first group of first openings and a first hole in the second group of holes corresponding to a first opening in the second group of first openings. Compared with the first hole in the first group of holes, the first hole in the second group of holes has a greater depth toward the first insulating layer in a direction opposite to the stacking direction, and wherein the number of plurality of grooves provided around the first opening in the second group of first openings is greater than the number of plurality of grooves provided around the first opening in the first group of first openings.

8. The method according to claim 1, wherein, The step of forming the mask pattern over the preliminary laminate includes the following steps: forming a mask layer over the preliminary laminate; forming a photoresist pattern including a plurality of etched holes and a plurality of auxiliary holes over the mask layer; and forming the plurality of first openings, the plurality of second openings, the plurality of third openings and the plurality of grooves by etching the areas of the mask layer corresponding to the etched holes and the plurality of auxiliary holes, wherein the plurality of first openings, the plurality of second openings and the plurality of third openings correspond to the plurality of etched holes, and wherein the grooves in the plurality of grooves correspond to the auxiliary holes in the plurality of auxiliary holes.

9. The method according to claim 8, wherein, When measured on a plane parallel to the surface of the first insulating layer, each of the auxiliary holes is narrower than each of the plurality of etched holes.

10. The method according to claim 8, wherein, The upper end of each of the auxiliary holes is spaced apart from the upper end of the etched hole adjacent to the corresponding auxiliary hole among the plurality of etched holes.

11. The method according to claim 8, wherein, When the area of ​​the mask layer corresponding to the plurality of etched holes and the plurality of auxiliary holes is etched, the upper end of each of the auxiliary holes is connected to the etched hole adjacent to the corresponding auxiliary hole among the plurality of etched holes.

12. The method according to claim 8, wherein, When the regions of the mask layer corresponding to the plurality of etched holes and the plurality of auxiliary holes are etched, each of the auxiliary holes and the corresponding etched hole among the plurality of etched holes are connected to each other to form an extended etched hole, and the upper end of each of the grooves is connected to the first opening among the plurality of first openings.

13. The method according to claim 1, further comprising the following steps: Each of the plurality of holes in the third set of holes is filled with a sacrificial column; a slit is formed through the preliminary stack; The plurality of sacrificial layers are replaced by a plurality of conductive layers through the slit; Remove multiple sacrificial pillars to expose multiple conductive layers and open multiple holes in the third set of holes; A sidewall insulating layer is formed on the sidewall of each of the plurality of holes in the third group of holes; And a plurality of gate contact plugs are formed in the plurality of holes in the third group of holes to be respectively connected to the plurality of conductive layers.

14. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Form an insulating layer; A preliminary laminate is formed by alternately stacking a first material layer of a plurality of first material layers and a second material layer of a plurality of second material layers above the surface of the insulating layer along the stacking direction; A mask pattern is formed over the preliminary laminate, the mask pattern including a first opening, a second opening, and a plurality of grooves disposed around the first opening; by etching the preliminary laminate through the first opening and the second opening while the plurality of grooves are blocked, a first hole and a second hole of different depths are formed toward the insulating layer in a direction opposite to the lamination direction; And with the plurality of grooves, the first opening and the second opening open, the preliminary laminate is etched through the first hole and the second hole, such that the first hole and the second hole extend deeper toward the insulating layer.

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