Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of non-uniform potential distribution of a channel structure caused by coexistence of multiple phases in a ferroelectric layer. The semiconductor structure comprises a stack structure, a channel structure, a ferroelectric layer and a conductive layer. The stacked structure comprises a plurality of first dielectric layers and a plurality of gate layers which are alternately stacked in the first direction. The channel structure passes through the stack structure along a first direction. The ferroelectric layer is located between the gate layer and the channel structure. The conductive layer is at least partially located between the ferroelectric layer and the channel structure. Through the arrangement, the potential of the side, close to the ferroelectric layer, of the conductive layer is the same as the potential of the side, close to the channel structure, of the conductive layer, the problem of uneven potential distribution of the channel structure caused by random distribution of multiple phases in the ferroelectric layer is solved, the uniformity of potential distribution of the channel structure is improved, and the storage performance of the semiconductor structure is further optimized.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] NAND flash memory is currently the mainstream product in the high-density memory market, but its operating voltage is too high (generally requiring 20V), and its actual write / erase cycle capability is only about 10. 4 This makes it difficult to meet the future demands for low-voltage, high-reliability, and high-density devices. To overcome the shortcomings of conventional NAND flash memory in terms of high operating voltage and write / erase capabilities, the industry has developed FeNAND (ferroelectric memory). FeNAND has the same circuit structure as conventional NAND, the difference being the addition of a ferroelectric layer between the gate layer and the channel structure.

[0003] FeNAND offers advantages over conventional NAND, including faster write and erase speeds and lower operating voltages. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, a memory system, and an electronic device.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, some embodiments of this disclosure provide a semiconductor structure, including: a stacked structure, a channel structure, a ferroelectric layer, and a conductive layer. The stacked structure includes a plurality of first dielectric layers and a plurality of gate layers alternately stacked along a first direction; the channel structure extends through the stacked structure along the first direction; the ferroelectric layer is located between the gate layers and the channel structure; at least a portion of the conductive layer is located between the ferroelectric layer and the channel structure.

[0007] In some embodiments, the conductive layer is in contact with the ferroelectric layer.

[0008] In some embodiments, the gate layer, the ferroelectric layer, and the conductive layer are all the same size in the first direction.

[0009] In some embodiments, the system further includes: a second dielectric layer located between the gate layer and the ferroelectric layer, wherein the dimensions of the second dielectric layer along the first direction are the same as the dimensions of the ferroelectric layer along the first direction.

[0010] In some embodiments, the dimension of the conductive layer along the first direction is smaller than the dimension of the gate layer along the first direction; a portion of the ferroelectric layer is also located on at least one side of the conductive layer along the first direction.

[0011] In some embodiments, the portion of the ferroelectric layer located on one side of the conductive layer along the first direction is a first sub-part, and the portion of the ferroelectric layer located on the other side of the conductive layer along the first direction is a second sub-part. The sum of the dimensions of the first sub-part along the first direction, the dimensions of the conductive layer along the first direction, and the dimensions of the second sub-part along the first direction is less than or equal to the dimensions of the gate layer along the first direction.

[0012] In some embodiments, the ferroelectric layer extends through the stacked structure along the first direction.

[0013] In some embodiments, the system further includes: a second dielectric layer, a portion of which is located between the gate layer and the ferroelectric layer, and a portion of which is located on the side of the ferroelectric layer away from the conductive layer along the first direction.

[0014] In some embodiments, the second dielectric layer is further located between the ferroelectric layer and the first dielectric layer.

[0015] In some embodiments, the system further includes a third dielectric layer, at least a portion of which is located between the conductive layer and the channel structure, and the third dielectric layer extends through the stacked structure along the first direction.

[0016] In some embodiments, the material of the conductive layer includes metal and / or polycrystalline silicon.

[0017] In some embodiments, the size of the conductive layer in the second direction ranges from 1 nm to 6 nm, and the second direction intersects with the first direction.

[0018] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, comprising: forming a first stacked structure, the first stacked structure including a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked along a first direction; forming a channel via, the channel via penetrating the first stacked structure along the first direction; sequentially forming a ferroelectric layer, a conductive layer and a channel structure within the channel via; removing the first sacrificial layers to form a first filling space; removing a portion of the ferroelectric layer and a portion of the conductive layer through the first filling space; forming a first dielectric layer within the first filling space; and replacing the second sacrificial layer with a gate layer.

[0019] In some embodiments, after forming the channel hole and before sequentially forming the ferroelectric layer, the conductive layer, and the channel structure within the channel hole, the method further includes: forming a gate material layer within the channel hole, the gate material layer covering the hole wall of the channel hole; the removal of a portion of the ferroelectric layer and a portion of the conductive layer through the first filling space includes: removing a portion of the gate material layer through the first filling space.

[0020] In some embodiments, after the gate material layer is formed in the channel hole and before the ferroelectric layer, conductive layer and channel structure are sequentially formed in the channel hole, a second dielectric layer is formed on the side of the gate material layer opposite to the first stacked structure.

[0021] In some embodiments, a ferroelectric layer, a conductive layer, and a channel structure are sequentially formed within the channel hole, including: after forming the conductive layer and before forming the channel structure, forming a third dielectric layer on the side of the conductive layer away from the ferroelectric layer.

[0022] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, including: forming a second stacked structure, the second stacked structure including a plurality of third sacrificial layers and a plurality of gate layers alternately stacked along a first direction; forming a channel via, the channel via penetrating the second stacked structure along the first direction; sequentially forming a ferroelectric layer, a conductive layer and a channel structure within the channel via; removing the third sacrificial layers to form a second filling space; and removing a portion of the ferroelectric layer and a portion of the conductive layer through the second filling space;

[0023] A first dielectric layer is formed within the second filling space.

[0024] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, comprising: forming a stacked structure, the stacked structure including a plurality of first dielectric layers and a plurality of gate layers alternately stacked along a first direction; forming a channel via, the channel via penetrating the stacked structure along the first direction; removing a portion of the gate layer to form a third filling space, the third filling space communicating with the channel via; sequentially forming a ferroelectric layer and a conductive layer in the third filling space, the ferroelectric layer being located between the gate layer and the conductive layer; and forming a channel structure in the channel via, the channel structure being located on the side of the conductive layer away from the ferroelectric layer.

[0025] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, comprising: forming a third stacked structure, the third stacked structure including a plurality of first dielectric layers and a plurality of fourth sacrificial layers alternately stacked along a first direction; forming a channel via, the channel via penetrating the third stacked structure along the first direction; removing a portion of the fourth sacrificial layer to form a fourth filling space, the fourth filling space communicating with the channel via; sequentially forming a ferroelectric layer and a conductive layer in the fourth filling space, the ferroelectric layer being located between the gate layer and the conductive layer; forming a channel structure in the channel via, the channel structure being located on the side of the conductive layer away from the ferroelectric layer; and replacing the fourth sacrificial layer with a gate layer.

[0026] In another aspect, a storage system is also provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data.

[0027] In another aspect, an electronic device is also provided, including: a motherboard and a storage system as described above, wherein the motherboard is electrically connected to the storage system. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments;

[0030] Figure 2 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0031] Figure 3 This is a schematic diagram of the structure of a string of storage cells in a three-dimensional memory according to some embodiments;

[0032] Figure 4 for Figure 3 Equivalent circuit diagram of the memory cell string;

[0033] Figure 5 This is a schematic diagram of a semiconductor structure according to some embodiments;

[0034] Figure 6 This is a schematic diagram of a semiconductor structure according to some other embodiments;

[0035] Figure 7 This is a schematic diagram of a semiconductor structure according to some other embodiments;

[0036] Figure 8 for Figure 7 Exploded view of the structure of the intermediate conductive layer, ferroelectric layer and gate layer;

[0037] Figures 9 to 17 These are schematic diagrams of semiconductor structures according to different embodiments;

[0038] Figure 18 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0039] Figures 19 to 25 These are structural diagrams of semiconductor structures according to some embodiments in different fabrication processes;

[0040] Figure 26 This is a flowchart of a method for fabricating a semiconductor structure according to some other embodiments;

[0041] Figures 27 to 30 The following are structural diagrams of semiconductor structures according to other embodiments in different fabrication processes;

[0042] Figure 31 This is a flowchart of a method for fabricating a semiconductor structure according to some other embodiments;

[0043] Figures 32 to 37 The following are structural diagrams of semiconductor structures according to other embodiments in different fabrication processes;

[0044] Figure 38 This is a flowchart of a method for fabricating a semiconductor structure according to some other embodiments;

[0045] Figures 39 to 43 The following are structural diagrams of semiconductor structures according to other embodiments in different fabrication processes;

[0046] Figure 44 This is a block diagram of a storage system according to some embodiments;

[0047] Figure 45 A block diagram of a storage system according to some other embodiments;

[0048] Figure 46 This is a block diagram of an electronic device according to some embodiments.

[0049] Reference numerals: 10, 3D memory; 100, peripheral device; 110, substrate; 120, transistor; 130, peripheral interconnect layer; 200, semiconductor device; 290, array interconnect layer; 400, memory cell string; 410, channel structure; 500, bonding interface; SL, source layer; X, first direction; Y, second direction; Z, third direction; 600, semiconductor structure; 610, stacked structure; 611, first dielectric layer; 612, gate layer; 620, ferroelectric layer; 621, first sub-section; 622, second sub-section Part; 630, conductive layer; 640, second dielectric layer; 650, third dielectric layer; 660, semiconductor layer; 670, first stacked structure; 680, channel via; 690, gate material layer; 710, first stacked structure; 711, first sacrificial layer; 712, second sacrificial layer; 713, first fill space; 720, second stacked structure; 721, third sacrificial layer; 722, second fill space; 730, third stacked structure; 731, fourth sacrificial layer; 732, fourth fill space; 740, third fill space. Detailed Implementation

[0050] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0051] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0052] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0053] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0054] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0055] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0056] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0058] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0060] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0061] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0062] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0063] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0064] The term "three-dimensional memory" refers to a semiconductor structure formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0065] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments. Figure 2 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Figure 3 This is a schematic diagram of the structure of a string of storage cells in a three-dimensional memory according to some embodiments. Figure 4 for Figure 3 Equivalent circuit diagram of the storage cell string.

[0066] Please refer to Figure 1 and Figure 2 This disclosure provides a three-dimensional memory 10 located in a three-dimensional coordinate system XYZ. The three-dimensional memory 10 extends in the YZ plane, with the second direction Y being, for example, the extension direction of the bit line BL, and the third direction Z being, for example, the extension direction of the word line WL. The first direction X is perpendicular to the YZ plane.

[0067] It should be noted that the first direction X intersects with the second direction Y, and the third direction Z intersects with the XY plane. This disclosure only uses the example of the first direction X, the second direction Y, and the third direction Z being mutually perpendicular to each other to explain the structure provided in some embodiments of this disclosure.

[0068] See Figure 1 and Figure 2 Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor device 200. The three-dimensional memory 10 may also include a source layer SL coupled to the semiconductor device 200, and a peripheral device 100 coupled to the semiconductor device 200. The peripheral device 100 may be disposed on the side of the semiconductor device 200 away from the source layer SL.

[0069] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0070] Semiconductor device 200 may also include arrayed strings of memory cell transistors (referred to herein as “memory cell strings”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0071] Specifically, see Figure 3 and Figure 4 The storage cell string 400 may include multiple transistors T, one transistor T (e.g. Figure 4 Transistors T2 to T5 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (e.g., each transistor T) can be formed by a channel structure 410 and a gate line G surrounding the channel structure 410. The gate line G is configured to control the conduction state of the transistor.

[0072] like Figure 3 As shown, the channel structure 410 includes a channel layer 411 and a functional layer 412. The channel layer 411 can be made of a semiconductor material, including but not limited to amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The voltage provided by the gate line G can control the movement or cessation of charge carriers (electrons or holes) within the channel layer 411.

[0073] Functional layer 412 is disposed around a portion of channel layer 411. Functional layer 412 may include a tunneling layer 4121, a storage layer 4122, and a barrier layer 4123 disposed sequentially in a direction away from channel layer 411. Carriers in channel layer 411 can tunnel through tunneling layer 4121 into storage layer 4122, storage layer 4122 is configured to store carriers, and barrier layer 4123 is configured to prevent carrier overflow.

[0074] The material of the tunneling layer 4121 may be, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. In some examples, the tunneling layer 4121 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the tunneling layer 4121 may be a composite dielectric layer, such as a stacked structure of a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

[0075] The material of the barrier layer 4123 may include one or more combinations of silicon oxide, silicon nitride, and high dielectric constant materials. In some examples, the barrier layer 4123 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 4123 may be a composite dielectric layer, such as a stacked structure of silicon nitride and aluminum oxide layers.

[0076] The storage layer 4122 is configured to store charge carriers. The material of the storage layer 4122 may include silicon nitride, or other suitable materials for storing charge carriers, which are not limited here.

[0077] It should be noted that, Figures 1-4 The number of transistors T is only illustrative. The storage cell string 400 of the three-dimensional memory 10 provided in this embodiment may also include other numbers of transistors, such as 4, 16, 32, 64, etc.

[0078] Further, along the first direction X, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. Along the first direction X, the uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages onto the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0079] See also Figure 1 and Figure 2 In some embodiments, the semiconductor device 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0080] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT, drain select gate contacts SGD-CNT, and gate line contacts G-CNT. Specifically, the bit line contacts BL-CNT are coupled to the bit line BL, the drain select gate contacts SGD-CNT are coupled to the drain select gate SGD, and the gate line contacts G-CNT are coupled to the gate line G. The array interconnect layer 290 may also include one or more first interconnect conductive layers 291. The first interconnect conductive layers 291 may include multiple interconnect lines, such as bit lines BL, and word line interconnect lines WL-CL coupled to word lines WL. The materials of the first interconnect conductive layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other conductive materials. The material of the first interlayer insulation layer 292 is an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other insulating materials.

[0081] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0082] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a peripheral transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the peripheral transistor 120.

[0083] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0084] The peripheral interconnect layer 130 is coupled to the peripheral transistor 120 to transmit electrical signals between the peripheral transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductive layers 132. Different second interconnect conductive layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductive layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0085] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor device 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor device 200 to achieve the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an adhesive interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled to each other through the adhesive interface 500.

[0086] The three-dimensional ferroelectric memory is based on the three-dimensional memory 10 in some of the above embodiments, with a ferroelectric layer added between the gate line G and the channel structure 410 to obtain advantages such as faster erase and write speed and lower operating voltage.

[0087] The ferroelectric layer is located between the gate line G and the channel structure 410, and its potential affects the potential of the channel structure 410. However, the ferroelectric layer presents the problem of multiple phases (ferroelectric and non-ferroelectric phases) coexisting and randomly distributed within it. The potential at areas where the ferroelectric phase accumulates may be higher or lower, leading to varying potentials in the channel structure opposite to these areas, resulting in an uneven potential distribution within the channel structure.

[0088] Based on this, some embodiments of this disclosure provide a semiconductor structure. It should be noted that, referring to... Figure 2 The semiconductor structure can be part of the three-dimensional memory 10 in some of the above embodiments. For example, the semiconductor structure can be a semiconductor device 200, bonded to the peripheral device 100. Alternatively, the semiconductor structure can be another type of three-dimensional ferroelectric memory, which also has peripheral devices and other structures.

[0089] Figure 5 This is a schematic diagram of a semiconductor structure according to some embodiments. Please refer to... Figure 5 The semiconductor structure 600 provided in some embodiments of this disclosure includes: a stacked structure 610, a channel structure 410, a ferroelectric layer 620, and a conductive layer 630.

[0090] The stacked structure 610 includes a plurality of first dielectric layers 611 and a plurality of gate layers 612 alternately stacked along the first direction X. For example, the first dielectric layers 611 and gate layers 612 alternately stacked along the first direction X form a plurality of spaced-apart first dielectric layers 611 and a plurality of gate layers 612. It can also be understood that a first dielectric layer 611 and a gate layer 612 together form a structural pair, and the stacked structure 610 includes a plurality of structural pairs stacked along the first direction X.

[0091] For example, the number of gate layer 612 and first dielectric layer 611 can be 4, 16, 32, 64, 128, 256, etc. The thickness of gate layer 612 (i.e., the dimension along the first direction XX) can be approximately equal to or different from the thickness of first dielectric layer 611. For example, the thickness of first dielectric layer 611 can be greater than the thickness of gate layer 612.

[0092] Exemplarily, the constituent material of the gate layer 612 may include a conductive material. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the gate layer 612 includes a metal layer, such as a tungsten layer. In some examples, the gate layer 612 includes a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using suitable dopant, making it a conductive material for use as the gate layer 612.

[0093] Exemplarily, the constituent material of the first dielectric layer 611 may include an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials. Silicon oxynitride has a higher dielectric constant than silicon oxide; for example, at approximately 20°C, the dielectric constant of silicon oxynitride is in the range of approximately 4 to approximately 7, such as 3.8, 4, 4.8, 5.3, 5.9, 6, 6.36, 6.88, 7, 7.2, etc. In some examples, the first dielectric layer 611 includes a silicon oxide layer. In some examples, the first dielectric layer 611 includes a silicon oxynitride layer.

[0094] For example, the thickness of the gate layer 612 (i.e., the dimension along the first direction XX) can range from 10 nm to 50 nm. For instance, the thickness of the gate layer 612 can be: 10 nm, 15 nm, 18.3 nm, 20 nm, 25 nm, 27.7 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. Similarly, the thickness of the first dielectric layer 611 (i.e., the dimension along the first direction XX) can also be between 10 nm and 50 nm. The gate layer 612 can be a gate line G surrounding the memory cell string (see...). Figure 3 ), and can be used as a word line WL (see Figure 1 It extends in the horizontal plane (YZ plane).

[0095] In this embodiment, the channel structure 410 penetrates the stacked structure 610 along the first direction X. Please refer to... Figure 3 Specifically, the channel structure 410 may include a channel layer 411 and a functional layer 412, as described in the previous embodiments, and will not be repeated here.

[0096] Continue to refer to Figure 5 The ferroelectric layer 620 is located between the gate layer 612 and the channel structure 410. The conductive layer 630 is at least partially located between the ferroelectric layer 620 and the channel structure 410.

[0097] In some examples, such as Figure 5 As shown, the conductive layer 630 can be entirely located between the ferroelectric layer 620 and the channel structure 410. The edge of the conductive layer 630 in the first direction X can be located inside the edge of the ferroelectric layer 620 in the first direction X, or the edge of the conductive layer 630 in the first direction X can be aligned with the edge of the ferroelectric layer 620 in the first direction X. The orthographic projection of the conductive layer 630 in the second direction Y is located inside the edge of the orthographic projection of the ferroelectric layer 620 in the second direction Y, or the edge of the orthographic projection of the conductive layer 630 in the second direction Y coincides with the edge of the orthographic projection of the ferroelectric layer 620 in the second direction Y.

[0098] In other examples, such as Figure 6 As shown, the conductive layer 630 may be partially located between the ferroelectric layer 620 and the channel structure 410, and partially extend beyond the edge of the ferroelectric layer 620 in the first direction X. In this case, the orthographic projection of the conductive layer 630 in the second direction Y and the orthographic projection of the ferroelectric layer 620 in the second direction Y partially overlap and partially do not overlap.

[0099] For example, the constituent materials of the conductive layer 630 may include conductive materials. Conductive materials include, but are not limited to, one or more combinations of metals (e.g., tungsten, cobalt, copper, aluminum, etc.), carbon materials (e.g., graphite), polycrystalline silicon, doped silicon, silicides, or other suitable conductive materials.

[0100] In this embodiment, reference Figure 5 and Figure 6 The conductive layer 630 is a conductor. When in electrostatic equilibrium, the conductive layer 630 is an equipotential body. Therefore, in the second direction Y, the potentials on both surfaces of the conductive layer 630 are the same; that is, the surface potential of the conductive layer 630 near the gate layer 612 is the same as the surface potential of the conductive layer 630 near the channel structure 410. Furthermore, the surface of the conductive layer 630 near the channel structure 410 is an equipotential surface, and the potential distribution on this surface is uniform. By placing the conductive layer 630 between the channel structure 410 and the ferroelectric layer 620, it is beneficial to reduce the influence of the random distribution of multiple phases in the ferroelectric layer 620 on the potential of the channel structure 410, improve the uniformity of the potential distribution of the channel structure 410, and thus optimize the storage performance of the semiconductor structure 600.

[0101] In some embodiments, such as Figure 7 As shown, the material of the conductive layer 630 may include metal or polycrystalline silicon. Both metal and polycrystalline silicon are good materials for fabricating conductors. When the material of the conductive layer 630 includes metal or polycrystalline silicon, it is more beneficial to improve the conductivity of the conductive layer 630, making it a good conductor. Furthermore, the conductive layer 630, as an equipotential body disposed between the ferroelectric layer 620 and the channel structure 410, can reduce the influence of the random distribution of multiple phases in the ferroelectric layer 620 on the potential of the channel structure 410, which is beneficial to improving the uniformity of the potential distribution of the channel structure 410, thereby optimizing the storage performance of the semiconductor structure 600.

[0102] In some embodiments, such as Figure 7 As shown, the conductive layer 630 can be in contact with the ferroelectric layer 620. For example, the surface of the conductive layer 630 near the ferroelectric layer 620 can be in contact with the surface of the ferroelectric layer 620 near the conductive layer 630. When the conductive layer 630 is in contact with the ferroelectric layer 620, the electrical signal conducted through the ferroelectric layer 620 will pass through the conductive layer 630. The surface of the conductive layer 630 away from the ferroelectric layer 620 is an equipotential surface. This arrangement helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0103] In some embodiments, such as Figure 7 As shown, in the first direction X, the dimensions d1 of the gate layer 612, d2 of the ferroelectric layer 620, and d3 of the conductive layer 630 are all the same. This can be understood as the gate layer 612 having the same thickness in the first direction X, the ferroelectric layer 620 having the same thickness in the first direction X, and the conductive layer 630 having the same thickness in the first direction X.

[0104] It should be noted that, due to possible errors in the fabrication of the semiconductor structure 600, the dimensions of the gate layer 612, the ferroelectric layer 620, and the conductive layer 630 in the first direction X can be approximately the same. If the difference between any two dimensions is within an acceptable deviation range (for example, the ratio of the difference between any two dimensions to one dimension is less than 5%), it can be considered that the dimensions of the gate layer 612, the ferroelectric layer 620, and the conductive layer 630 are the same in the first direction X.

[0105] In this embodiment, as Figure 7 and Figure 8 As shown, d1 equals d2 and d3. When the edge of the ferroelectric layer 620 in the first direction X is aligned with the edge of the gate layer 612 in the first direction X, the interface for transmitting electrical signals between the gate layer 612 and the ferroelectric layer 620 is larger, which is beneficial to improving the transmission strength of the electrical signal. Furthermore, when the edge of the ferroelectric layer 620 in the first direction X is aligned with the edge of the conductive layer 630 in the first direction X, a conductive layer 630 is disposed between the ferroelectric layer 620 and the channel structure 410, and there is no direct contact between the ferroelectric layer 620 and the channel structure 410. Through the above arrangement, the electrical signal applied by the gate layer 612 is transmitted to the channel structure 410 through the ferroelectric layer 620 and the conductive layer 630, which helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0106] In some embodiments, reference Figure 9 The semiconductor structure 600 also includes a second dielectric layer 640. The second dielectric layer 640 is located between the gate layer 612 and the ferroelectric layer 620, and the dimension d4 of the second dielectric layer 640 along the first direction X is the same as the dimension d2 of the ferroelectric layer 620 along the first direction X.

[0107] For example, the material of the second dielectric layer 640 may include a dielectric material, such as zirconium oxide, hafnium oxide, aluminum oxide, silicon nitride, etc.

[0108] Through the above configuration, the second dielectric layer 640 can induce the ferroelectric layer 620 to generate more ferroelectric phases and suppress the generation of non-ferroelectric phases in the ferroelectric layer 620, which is beneficial to optimizing the conductivity of the ferroelectric phase. Furthermore, since the dimension d4 of the second dielectric layer 640 along the first direction X is the same as the dimension d2 of the ferroelectric layer 620 along the first direction X, when the edge of the second dielectric layer 640 along the first direction X is aligned with the edge of the ferroelectric layer 620 along the first direction X, the contact area between the ferroelectric layer 620 and the second dielectric layer 640 is maximized. This increases the optimized area of ​​the second dielectric layer 640 on the ferroelectric layer 620, which is beneficial to further optimizing the conductivity of the ferroelectric layer 620.

[0109] In some embodiments, reference Figure 10 and Figure 11 The dimension d1 of the conductive layer 630 along the first direction X is smaller than the dimension d3 of the gate layer 612 along the first direction X. For example, the edge of the conductive layer 630 along the first direction X can be located within the edge of the gate layer 612 along the first direction X. The edge of the orthogonal projection of the conductive layer 630 in the second direction Y can be located within the edge of the orthogonal projection of the gate layer 612 in the second direction Y.

[0110] A portion of the ferroelectric layer 620 is also located on at least one side of the conductive layer 630 along the first direction X. For example, a portion of the ferroelectric layer 620 is located on one side of the conductive layer 630 along the first direction X. Alternatively, a portion of the ferroelectric layer 620 can be provided on both sides of the conductive layer 630 along the first direction X, with a portion of the ferroelectric layer 620 located on one side of the conductive layer 630 along the first direction X and a portion of the ferroelectric layer 620 located on the other side of the conductive layer 630 along the first direction X. In this case, the portion of the ferroelectric layer 620 is disposed around the conductive layer 630.

[0111] like Figure 11 As shown, this embodiment provides another way to dispose of the conductive layer 630 between the ferroelectric layer 620 and the channel structure 410. Part of the ferroelectric layer 620 can be located on one or both sides of the conductive layer 630 along the first direction X. With this arrangement, the entire conductive layer 630 is located between the ferroelectric layer 620 and the channel structure 410, which helps to reduce the influence of the random distribution of multiple phases in the ferroelectric layer 620 on the potential of the channel structure 410, improves the uniformity of the potential distribution of the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0112] Furthermore, a portion of the ferroelectric layer 620 may be located on one or both sides of the conductive layer 630 along the first direction X. When ferroelectric layers 620 and conductive layers 630 are provided between two adjacent gate layers 612 and the channel structure 410 along the first direction X, the portion of the ferroelectric layer 620 located on one or both sides of the conductive layer 630 along the first direction X can be used to isolate the two adjacent conductive layers 630, preventing the two adjacent conductive layers 630 from connecting, so that the semiconductor structure 600 can work normally, thereby improving the storage stability of the semiconductor structure 600.

[0113] In addition, in this embodiment, a portion of the ferroelectric layer 620 can be disposed around the conductive layer 630. This structure can be formed by sequentially depositing ferroelectric materials and conductive materials, which is simple to prepare and has fewer preparation steps. This helps to simplify the preparation process of the semiconductor structure 600 and improve the production efficiency of the semiconductor structure 600.

[0114] In some embodiments, reference Figure 11 and Figure 12A portion of the ferroelectric layer 620 may be disposed around the conductive layer 630. The ferroelectric layer 620 includes a first sub-part 621 and a second sub-part 622. The portion of the ferroelectric layer 620 located on one side of the conductive layer 630 along the first direction X is the first sub-part 621, and the portion of the ferroelectric layer 620 located on the other side of the conductive layer 630 along the first direction X is the second sub-part 622.

[0115] like Figure 11 As shown, the sum of the dimensions d5 of the first sub-part 621 along the first direction X, d1 of the conductive layer 630 along the first direction X, and d6 of the second sub-part 622 along the first direction X is equal to the dimension d3 of the gate layer 612 along the first direction X. The first sub-part 621, the conductive layer 630, and the second sub-part 622 can be aligned with the gate layer 612 in the second direction Y. For example, the edge of the common orthographic projection of the first sub-part 621, the conductive layer 630, and the second sub-part 622 in the second direction Y can coincide with the edge of the orthographic projection of the gate layer 612 in the second direction Y. With this arrangement, the contact area between the ferroelectric layer 620 and the gate layer 612 is maximized, which is beneficial for improving the strength of the electrical signal transmitted between the gate layer 612 and the ferroelectric layer 620.

[0116] like Figure 11 As shown, the sum of the dimensions d5 of the first sub-part 621 along the first direction X, d1 of the conductive layer 630 along the first direction X, and d6 of the second sub-part 622 along the first direction X is less than the dimension d3 of the gate layer 612 along the first direction X. Exemplarily, the edge of the orthographic projection of the first sub-part 621, the conductive layer 630, and the second sub-part 622 together in the second direction Y can be located within the edge of the orthographic projection of the gate layer 612 in the second direction Y. With the above arrangement, a gap exists between the ferroelectric layer 620 and the gate layer 612, which can be used to additionally construct other structural layers.

[0117] In addition, in the semiconductor structure 600 provided in this embodiment, a portion of the ferroelectric layer 620 is disposed around the conductive layer 630. The semiconductor structure 600 can be formed by sequentially depositing ferroelectric material and conductive material, which is simple in preparation process and has fewer preparation steps. This helps to simplify the preparation process of the semiconductor structure 600 and improve the production efficiency of the semiconductor structure 600.

[0118] In some embodiments, such as Figure 10 As shown, the ferroelectric layer 620 penetrates the stacked structure 610 along the first direction X. When the ferroelectric layer 620 is disposed between the multiple gate layers 612 and the channel structure 410 in the stacked structure 610, the multiple gate layers 612 can share the same ferroelectric layer 620. In this case, the ferroelectric layer 620 penetrates the stacked structure 610 along the first direction X, and the ferroelectric layer 620 is located between the multiple gate layers 612 and the channel structure 410.

[0119] In this embodiment, the ferroelectric layer 620 can be formed in a single deposition process, and multiple gate layers 612 can share the ferroelectric layer 620, which helps to simplify the fabrication process of the semiconductor structure 600.

[0120] In some embodiments, such as Figure 12 As shown, the semiconductor structure 600 further includes a second dielectric layer 640. A portion of the second dielectric layer 640 is located between the gate layer 612 and the ferroelectric layer 620, and a portion of the second dielectric layer 640 is also located on the side of the ferroelectric layer 620 away from the conductive layer 630 along the first direction X.

[0121] For example, the material of the second dielectric layer 640 may include a dielectric material, which may include zirconium oxide, hafnium oxide, aluminum oxide, silicon nitride, etc.

[0122] When a portion of the ferroelectric layer 620 is located on one side of the conductive layer 630 along the first direction X, and a portion of the ferroelectric layer 620 is located on the other side of the conductive layer 630 along the first direction X, a portion of the second dielectric layer 640 can be disposed around the ferroelectric layer 620. When a second dielectric layer 640 is disposed between multiple gate layers 612 and the ferroelectric layer 620 in the stacked structure 610, the multiple gate layers 612 can share the same second dielectric layer 640, and the second dielectric layer 640 can penetrate the stacked structure 610 along the first direction X.

[0123] By providing a second dielectric layer 640 between the ferroelectric layer 620 and the gate layer 612, the second dielectric layer 640 can induce the ferroelectric layer 620 to form more ferroelectric phases and suppress the formation of more non-ferroelectric phases in the ferroelectric layer 620, thereby optimizing the storage performance of the semiconductor structure 600. Furthermore, this arrangement helps to increase the contact area between the second dielectric layer 640 and the ferroelectric layer 620, which is beneficial for the ferroelectric layer 620 to form more ferroelectric phases, further improving the storage performance of the semiconductor structure 600.

[0124] In some embodiments, such as Figure 12 As shown, when the ferroelectric layer 620 penetrates the stacked structure 610 along the first direction X, the ferroelectric layer 620 can be located between the first dielectric layer 611 and the channel structure 410. At this time, the second dielectric layer 640 is also located between the ferroelectric layer 620 and the first dielectric layer 611. The second dielectric layer 640 can also penetrate the stacked structure 610 along the first direction X, and multiple gate layers 612 share one second dielectric layer 640 and one first ferroelectric layer 620.

[0125] The above configuration helps to increase the contact area between the second dielectric layer 640 and the ferroelectric layer 620, which in turn helps the ferroelectric layer 620 generate more ferroelectric phases, further improving the storage performance of the semiconductor structure 600.

[0126] In addition, in this embodiment, the ferroelectric layer 620 and the second dielectric layer 640 can both penetrate the stacked structure 610 along the first direction X, and can be formed by deposition process without the need for additional etching process, etc. Therefore, the above settings help to simplify the preparation process of semiconductor structure 600 and improve the production efficiency of semiconductor structure 600.

[0127] In some embodiments, such as Figure 13 and Figure 14 As shown, the semiconductor structure 600 further includes a third dielectric layer 650. The third dielectric layer 650 extends through the stacked structure 610 along the first direction X, and at least a portion of the third dielectric layer 650 is located between the conductive layer 630 and the channel structure 410, while a portion of the third dielectric layer 650 is located between the first dielectric layer 611 and the channel structure 410.

[0128] For example, the material of the third dielectric layer 650 may include an insulating material, which may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials. The constituent materials of the third dielectric layer 650 may be the same as those of the first dielectric layer 611.

[0129] In some examples, reference Figure 13 and Figure 14 The third dielectric layer 650 can be disposed around the channel structure 410. On the side of the third dielectric layer 650 facing away from the channel structure 410, a conductive layer 630, a ferroelectric layer 620, and a gate layer 612 can be disposed sequentially. The edges of the conductive layer 630, the ferroelectric layer 620, and the gate layer 612 can be aligned in the first direction X.

[0130] In some examples, reference Figure 15 The third dielectric layer 650 can be disposed around the channel structure 410. On the side of the third dielectric layer 650 facing away from the channel structure 410, a conductive layer 630, a ferroelectric layer 620, a second dielectric layer 640, and a gate layer 612 can be disposed sequentially. The edges of the conductive layer 630, the ferroelectric layer 620, the second dielectric layer 640, and the gate layer 612 can be aligned in the first direction X.

[0131] In some examples, reference Figure 16 The third dielectric layer 650 may be disposed around the channel structure 410. On the side of the third dielectric layer 650 facing away from the channel structure 410, a conductive layer 630, a ferroelectric layer 620, and a gate layer 612 may be disposed sequentially. The ferroelectric layer 620 may penetrate the stacked structure 610 along the first direction X, and the ferroelectric layer 620 may be disposed around the third dielectric layer 650. The ferroelectric layer 620 may be partially located on both sides of the conductive layer 630 along the first direction X, and the ferroelectric layer 620 may be disposed around the conductive layer 630.

[0132] In some examples, reference Figure 17 The third dielectric layer 650 may be disposed around the channel structure 410. On the side of the third dielectric layer 650 facing away from the channel structure 410, a conductive layer 630, a ferroelectric layer 620, a second dielectric layer 640, and a gate layer 612 may be disposed sequentially. The ferroelectric layer 620 may penetrate the stacked structure 610 along the first direction X, and the ferroelectric layer 620 may be disposed around the third dielectric layer 650. The ferroelectric layer 620 may be partially located on both sides of the conductive layer 630 along the first direction X, and the ferroelectric layer 620 may be disposed around the conductive layer 630. The second dielectric layer 640 may penetrate the stacked structure 610 along the first direction X, and the second dielectric layer 640 may be disposed around the ferroelectric layer 620.

[0133] In this embodiment, by providing a third dielectric layer 650 between the conductive layer 630 and the channel structure 410, the third dielectric layer 650 can capture charge when writing or erasing the semiconductor structure 600, which helps the channel structure 410 store more charge, thereby optimizing the storage performance of the semiconductor structure 600.

[0134] In some of the above embodiments, reference is made to Figure 8 The dimension d7 of the conductive layer 630 in the second direction Y ranges from 1 nm to 6 nm. For example, the dimension d7 of the conductive layer 630 in the second direction Y can be 1 nm, 3 nm, or 6 nm.

[0135] With the above configuration, the conductive layer 630 can reduce the influence of the random distribution of multiple phases in the ferroelectric layer 620 on the potential of the channel structure 410. At the same time, it can save conductive materials and help control the production cost of the semiconductor structure 600.

[0136] This disclosure also provides various methods for fabricating semiconductor structures 600 through some embodiments, which are described below in conjunction with... Figures 18-43 The fabrication methods of various semiconductor structures 600 are explained and described.

[0137] Figure 18 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments. For example... Figure 18 As shown, some embodiments of this disclosure provide a method for fabricating a semiconductor structure 600, including: S1 to S7.

[0138] S1. A first stacked structure is formed, the first stacked structure including a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked along a first direction.

[0139] In this step, refer to Figure 19A semiconductor layer 660 is provided, and a first stacked structure 710 is formed on the semiconductor layer 660. For example, a plurality of first sacrificial layers 711 and a plurality of second sacrificial layers 712 may be alternately formed above the semiconductor layer 660 by a deposition process.

[0140] The semiconductor layer 660 may be made of silicon (e.g., monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and / or any other suitable semiconductor material. In some examples, the semiconductor layer 660 comprises silicon, such as monocrystalline silicon or polycrystalline silicon.

[0141] S2. Forming a channel hole, the channel hole penetrates the first stacked structure along the first direction.

[0142] In this step, refer to Figure 19 A channel hole 680 is formed within the semiconductor layer 660 and the first stacked structure 710. The channel hole 680 can penetrate the first stacked structure 710 along the first direction X and extend into a portion of the semiconductor layer 660.

[0143] The via 680 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed on the first stacked structure 710. The patterned photoresist layer can expose the portion of the first stacked structure 710 used to form the via 680. A suitable etching process can be performed to remove the portion of the first stacked structure 710 used to form the via 680. The etching process can include a dry etching process.

[0144] refer to Figure 19 and Figure 20 After forming the channel via 680, a gate material layer 690 can be formed within the channel via 680 by a deposition process, the gate material layer 690 covering the via wall of the channel via 680. The deposition process includes, but is not limited to, one or more thin film deposition processes among physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0145] In some embodiments, reference Figure 19 and Figure 20 After the gate material layer 690 is formed in the channel hole 680, a dielectric material can be deposited on the side of the gate material layer 690 away from the first stacked structure 710 by employing one or more thin film deposition processes including but not limited to PVD, CVD, and ALD to form a second dielectric layer 640.

[0146] S3. A ferroelectric layer, a conductive layer, and a channel structure are formed sequentially within the channel hole.

[0147] refer to Figure 19 and Figure 20 In this step, ferroelectric material, conductive material and channel material can be sequentially deposited in the channel hole 680 by using one or more thin film deposition processes including but not limited to PVD, CVD and ALD, so as to sequentially form ferroelectric layer 620, conductive layer 630 and channel structure 410.

[0148] In some embodiments, reference Figure 19 and Figure 20 In this step, ferroelectric material, conductive material, dielectric material, and channel material can be sequentially deposited within the channel hole 680 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to sequentially form a ferroelectric layer 620, a conductive layer 630, a third dielectric layer 650, and a channel structure 410. The third dielectric layer 650 is located on the side of the conductive layer 630 away from the ferroelectric layer 620.

[0149] In some embodiments, reference Figure 19 and Figure 21 In this step, dielectric material, ferroelectric material, conductive material, dielectric material and channel material can be sequentially deposited in the channel hole 680 by using one or more thin film deposition processes including but not limited to PVD, CVD and ALD, so as to sequentially form a second dielectric layer 640, a ferroelectric layer 620, a conductive layer 630, a third dielectric layer 650 and a channel structure 410.

[0150] S4. Remove the first sacrificial layer to form the first filling space.

[0151] refer to Figure 20 and Figure 22 The first sacrificial layer 711 can be removed by using a wet etching process to form the first filling space 713.

[0152] S5. Remove part of the ferroelectric layer and part of the conductive layer through the first filling space.

[0153] In this step, refer to Figure 22 The channel structure 410 can be exposed by using a wet etching process, such as injecting an etching solution into the first filling space 713, to remove part of the gate material layer 690, part of the ferroelectric layer 620 and part of the conductive layer 630.

[0154] In some embodiments, reference Figure 20 and Figure 22A wet etching process can be used, for example, by injecting an etching solution into the first filling space 713, to remove part of the gate material layer 690, part of the ferroelectric layer 620 and part of the conductive layer 630 until the third dielectric layer 650 is exposed.

[0155] S6. A first dielectric layer is formed within the first filling space.

[0156] In this step, such as Figure 22 and Figure 23 As shown, an insulating material can be deposited within the first filled space 713 by a deposition process to form a first dielectric layer 611. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0157] S7. Replace the second sacrificial layer with the gate layer.

[0158] In this step, refer to Figure 23 , Figure 24 and Figure 25 The second sacrificial layer 712 can be removed by wet etching, and gate material can be deposited at the location of the original second sacrificial layer 712 to form gate layer 612, thereby achieving gate replacement.

[0159] The semiconductor structure 600 prepared by the above-described method has at least a portion of the conductive layer 630 located between the ferroelectric layer 620 and the channel structure 410. The potential of the conductive layer 630 on the side closer to the ferroelectric layer 620 is the same as the potential of the conductive layer 630 on the side closer to the channel structure 410. This helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0160] Figure 26 This is a flowchart illustrating a method for fabricating a semiconductor structure according to other embodiments. For example... Figure 26 As shown, some embodiments of this disclosure provide a method for fabricating a semiconductor structure 600, including: S8 to S13.

[0161] S8. A second stacked structure is formed, the second stacked structure including a plurality of third sacrificial layers and a plurality of gate layers alternately stacked along the first direction.

[0162] In this step, refer to Figure 27 A semiconductor layer 660 is provided, and a second stacked structure 720 is formed on the semiconductor layer 660. For example, a plurality of third sacrificial layers 721 and a plurality of gate layers 612 may be alternately formed above the semiconductor layer 660 by a deposition process.

[0163] For example, the constituent material of the gate layer 612 may include polysilicon.

[0164] S9. Form a channel hole, which penetrates the stacked structure along the first direction.

[0165] In this step, refer to Figure 27 A channel hole 680 is formed within the semiconductor layer 660 and the second stacked structure 720. The channel hole 680 can penetrate the second stacked structure 720 along the first direction X and extend into a portion of the semiconductor layer 660.

[0166] The via 680 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed on the second stacked structure 720. The patterned photoresist layer can expose the portion of the second stacked structure 720 used to form the via 680. A suitable etching process can be performed to remove the portion of the second stacked structure 720 used to form the via 680. The etching process can include a dry etching process.

[0167] S10. A ferroelectric layer, a conductive layer, and a channel structure are sequentially formed within the channel hole.

[0168] In this step, refer to Figure 27 and Figure 28 The ferroelectric layer 620, the conductive layer 630, and the channel structure 410 can be sequentially formed within the channel hole 680 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0169] In some embodiments, the test Figure 27 and Figure 28 An auxiliary gate layer 612, a ferroelectric layer 620, a conductive layer 630, a third dielectric layer 650, and a channel structure 410 can be sequentially formed within a channel hole 680 using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD. Exemplarily, the constituent material of the auxiliary gate layer 612 may include metal. The constituent material of the auxiliary gate layer 612 may be different from the constituent material of the gate layer 612. Alternatively, the constituent material of the auxiliary gate layer 612 may be different from the constituent material of the gate layer 612.

[0170] S11. Remove the third sacrificial layer to form a second filling space.

[0171] refer to Figure 28 and Figure 29 The third sacrificial layer 721 can be removed by using a wet etching process to form the second filling space 722.

[0172] S12. Remove part of the ferroelectric layer and part of the conductive layer through the second filling space.

[0173] In this step, refer to Figure 29 A portion of the ferroelectric layer 620 and a portion of the conductive layer 630 can be removed using a wet etching process to expose the channel structure 410.

[0174] In some embodiments, reference Figure 28 and Figure 29 A portion of the auxiliary gate layer 612, a portion of the ferroelectric layer 620, and a portion of the conductive layer 630 can be removed using a wet etching process to expose the third dielectric layer 650.

[0175] S13. A first dielectric layer is formed within the second filling space.

[0176] In this step, refer to Figure 29 and Figure 30 An insulating material can be deposited in the second filled space 722 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a first dielectric layer 611.

[0177] The semiconductor structure 600 prepared by the above-described method has at least a portion of the conductive layer 630 located between the ferroelectric layer 620 and the channel structure 410. The potential of the conductive layer 630 on the side closer to the ferroelectric layer 620 is the same as the potential of the conductive layer 630 on the side closer to the channel structure 410. This helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0178] Figure 31 This is a flowchart illustrating a method for fabricating a semiconductor structure according to other embodiments. For example... Figure 31 As shown, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, including: S14 to S18.

[0179] S14. A stacked structure is formed, the stacked structure including a plurality of first dielectric layers and a plurality of gate layers alternately stacked along a first direction.

[0180] In this step, refer to Figure 32 A semiconductor layer 660 is provided, and a stacked structure 610 is formed on the semiconductor layer 660. For example, a plurality of first dielectric layers 611 and a plurality of gate layers 612 may be alternately formed above the semiconductor layer 660 by a deposition process.

[0181] S15. Form a channel hole, which penetrates the stacked structure along the first direction.

[0182] In this step, refer to Figure 32A channel hole 680 is formed within the semiconductor layer 660 and the stacked structure 610. The channel hole 680 can penetrate the stacked structure 610 along the first direction X and extend into a portion of the semiconductor layer 660.

[0183] S16. Remove part of the gate layer to form a third fill space, which is connected to the channel via.

[0184] In this step, refer to Figure 33 A portion of the gate layer 612 can be removed using a wet etching process to form a third fill space 740. For example, an etching solution can be injected into the channel via 680 to remove a portion of the gate layer 612, thereby forming a third fill space 740 and connecting the third fill space 740 to the channel via 680.

[0185] S17. A ferroelectric layer and a conductive layer are formed sequentially in the third filling space, with the ferroelectric layer located between the gate layer and the conductive layer.

[0186] In this step, such as Figure 34 and Figure 35 As shown, a ferroelectric layer 620 and a conductive layer 630 can be sequentially formed in the channel hole 680 and the third filling space 740 by employing one or more thin film deposition processes including but not limited to PVD, CVD, and ALD, with the ferroelectric layer 620 located between the gate layer 612 and the conductive layer 630.

[0187] The conductive layer 630 covering the sidewall of the channel hole 680 can be removed by wet etching, while retaining the conductive layer 630 located in the third filling space 740.

[0188] After removing the conductive layer 630 covering the sidewall of the channel hole 680, a third dielectric layer 650 can be formed in the channel hole 680 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, the third dielectric layer 650 covering the sidewall of the channel hole 680.

[0189] S18. A channel structure is formed in the channel hole, and the channel structure is located on the side of the conductive layer away from the ferroelectric layer.

[0190] In this step, refer to Figure 36 and Figure 37 A deposition process can be used to form a channel structure 410 within the channel hole 680.

[0191] The semiconductor structure 600 prepared by the above-described method has at least a portion of the conductive layer 630 located between the ferroelectric layer 620 and the channel structure 410. The potential of the conductive layer 630 on the side closer to the ferroelectric layer 620 is the same as the potential of the conductive layer 630 on the side closer to the channel structure 410. This helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0192] Figure 38 This is a flowchart illustrating a method for fabricating a semiconductor structure according to other embodiments. For example... Figure 38 As shown, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, including: S19 to S24.

[0193] S19. A third stacked structure is formed, the third stacked structure including a plurality of first dielectric layers and a plurality of fourth sacrificial layers alternately stacked along a first direction.

[0194] In this step, refer to Figure 39 A semiconductor layer 660 is provided, and a third stacked structure 730 is formed on the semiconductor layer 660. For example, a plurality of first dielectric layers 611 and a plurality of fourth sacrificial layers 731 may be alternately formed above the semiconductor layer 660 by a deposition process.

[0195] S20, forming a channel hole, the channel hole penetrating the third stacked structure along the first direction.

[0196] In this step, refer to Figure 39 A channel hole 680 is formed within the semiconductor layer 660 and the third stacked structure 730. The channel hole 680 can penetrate the third stacked structure 730 along the first direction X and extend into a portion of the semiconductor layer 660.

[0197] S21. Remove part of the fourth sacrificial layer to form a fourth filling space, which is connected to the channel hole.

[0198] In this step, refer to Figure 39 and Figure 40 A portion of the fourth sacrificial layer 731 can be removed using a wet etching process to form a fourth filling space 732, which is connected to the channel hole 680.

[0199] S22. A ferroelectric layer and a conductive layer are formed sequentially in the fourth filling space, with the ferroelectric layer located between the gate layer and the conductive layer.

[0200] In this step, refer to Figure 41 and Figure 42A ferroelectric layer 620 and a conductive layer 630 can be sequentially formed in the fourth filling space 732 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, with the ferroelectric layer 620 located between the gate layer 612 and the conductive layer 630.

[0201] The conductive layer 630 covering the sidewall of the channel hole 680 can be removed by wet etching process, while retaining the conductive layer 630 located in the fourth filling space 732.

[0202] After removing the conductive layer 630 covering the sidewall of the channel hole 680, a third dielectric layer 650 can be formed in the channel hole 680 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, the third dielectric layer 650 covering the sidewall of the channel hole 680.

[0203] S23. A channel structure is formed in the channel hole, and the channel structure is located on the side of the conductive layer away from the ferroelectric layer.

[0204] In this step, refer to Figure 41 and Figure 42 The channel structure 410 can be formed within the channel hole 680 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0205] S24. Replace the fourth sacrificial layer with the gate layer.

[0206] In this step, refer to Figure 42 and Figure 43 The fourth sacrificial layer 731 can be removed by wet etching, and gate material can be filled in the original location of the fourth sacrificial layer 731 by deposition to form the gate layer 612.

[0207] The semiconductor structure 600 prepared by the above-described method has at least a portion of the conductive layer 630 located between the ferroelectric layer 620 and the channel structure 410. The potential of the conductive layer 630 on the side closer to the ferroelectric layer 620 is the same as the potential of the conductive layer 630 on the side closer to the channel structure 410. This helps to improve the problem of uneven potential distribution in the channel structure 410 caused by the random distribution of multiple phases in the ferroelectric layer 620, improves the uniformity of the potential distribution in the channel structure 410, and thus optimizes the storage performance of the semiconductor structure 600.

[0208] Figure 44 This is a block diagram of a storage system according to some embodiments. Figure 45 This is a block diagram of a storage system according to some other embodiments. Please refer to... Figure 44 and Figure 45This disclosure also provides a storage system 1000 in some embodiments, which includes a controller 20 and a semiconductor structure 600 provided in the above embodiments. The controller 20 is coupled to the semiconductor structure 600 to control the semiconductor structure 600 to store data.

[0209] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0210] In some embodiments, see Figure 44 The storage system 1000 includes a controller 20 and a semiconductor structure 600, and the storage system 1000 can be integrated into a memory card. Exemplarily, the semiconductor structure 600 can be a memory with a three-dimensional structure (3D NAND).

[0211] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD device) card, and UFS.

[0212] In other embodiments, see Figure 45 The storage system 1000 includes a controller 20 and multiple semiconductor structures 600, and the storage system 1000 is integrated into a solid state drive (SSD device).

[0213] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD device card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0214] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment in an SSD device or eMMC used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays.

[0215] In some embodiments, controller 20 may be configured to manage data stored in semiconductor structure 600 and to communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of semiconductor structure 600, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in semiconductor structure 600, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to semiconductor structure 600.

[0216] Of course, controller 20 can also perform any other suitable functions, such as formatting semiconductor structure 600; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0217] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESD Device I) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0218] The controller 20 in the above embodiments may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0219] In this embodiment, the storage system 1000 includes the semiconductor structure 600 provided in some of the above embodiments, which is beneficial to optimizing the storage performance of the storage system 1000.

[0220] This disclosure also provides an electronic device in some embodiments. Figure 46 This is a block diagram of an electronic device according to some embodiments. For example... Figure 46 As shown, the electronic device 3000 includes a motherboard 2000 and a storage system 1000 provided in some of the above embodiments. The motherboard 2000 is electrically connected to the storage system 1000. In addition, the electronic device 3000 may also include at least one of a central processing unit (CPU) and a cache.

[0221] For example, the electronic device 3000 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0222] In this embodiment, the electronic device 3000 may include the storage system 1000 provided in some of the above embodiments, which is beneficial to optimizing the device performance of the electronic device.

[0223] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The stacked structure includes a plurality of first dielectric layers and a plurality of gate layers alternately stacked along a first direction; A channel structure that penetrates the stacked structure along the first direction; A ferroelectric layer is located between the gate layer and the channel structure; A conductive layer, at least partially located between the ferroelectric layer and the channel structure.

2. The semiconductor structure according to claim 1, characterized in that, The conductive layer is in contact with the ferroelectric layer.

3. The semiconductor structure according to claim 1, characterized in that, In the first direction, the gate layer, the ferroelectric layer, and the conductive layer all have the same size.

4. The semiconductor structure according to claim 3, characterized in that, Also includes: A second dielectric layer is located between the gate layer and the ferroelectric layer, and the dimensions of the second dielectric layer along the first direction are the same as the dimensions of the ferroelectric layer along the first direction.

5. The semiconductor structure according to claim 1, characterized in that, The dimension of the conductive layer along the first direction is smaller than the dimension of the gate layer along the first direction; a portion of the ferroelectric layer is also located on at least one side of the conductive layer along the first direction.

6. The semiconductor structure according to claim 5, characterized in that, The portion of the ferroelectric layer located on one side of the conductive layer along the first direction is a first sub-part, and the portion of the ferroelectric layer located on the other side of the conductive layer along the first direction is a second sub-part. The sum of the dimensions of the first sub-part along the first direction, the dimensions of the conductive layer along the first direction, and the dimensions of the second sub-part along the first direction is less than or equal to the dimensions of the gate layer along the first direction.

7. The semiconductor structure according to claim 5, characterized in that, The ferroelectric layer penetrates the stacked structure along the first direction.

8. The semiconductor structure according to claim 5, characterized in that, Also includes: The second dielectric layer is partially located between the gate layer and the ferroelectric layer, and a portion of the second dielectric layer is also located on the side of the ferroelectric layer away from the conductive layer along the first direction.

9. The semiconductor structure according to claim 8, characterized in that, The second dielectric layer is also located between the ferroelectric layer and the first dielectric layer.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, Also includes: A third dielectric layer is located at least partially between the conductive layer and the channel structure, and the third dielectric layer penetrates the stacked structure along the first direction.

11. The semiconductor structure according to any one of claims 1-9, characterized in that, The conductive layer is made of metal and / or polycrystalline silicon.

12. The semiconductor structure according to any one of claims 1-9, characterized in that, The size of the conductive layer in the second direction ranges from 1 nm to 6 nm, and the second direction intersects with the first direction.

13. A method for fabricating a semiconductor structure, characterized in that, include: A first stacked structure is formed, the first stacked structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked along a first direction; A channel hole is formed, which penetrates the first stacked structure along the first direction; A ferroelectric layer, a conductive layer, and a channel structure are sequentially formed within the channel hole; Remove the first sacrificial layer to form a first filling space; A portion of the ferroelectric layer and a portion of the conductive layer are removed through the first filling space; A first dielectric layer is formed within the first filling space; The second sacrificial layer is replaced with a gate layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, After the formation of the channel hole, and before the sequential formation of the ferroelectric layer, the conductive layer, and the channel structure within the channel hole, the method further includes: A gate material layer is formed inside the channel hole, and the gate material layer covers the hole wall of the channel hole; The removal of a portion of the ferroelectric layer and a portion of the conductive layer through the first filling space includes: A portion of the gate material layer is removed through the first filling space.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, After the gate material layer is formed in the channel hole, and before the ferroelectric layer, conductive layer, and channel structure are sequentially formed in the channel hole, the method further includes: A second dielectric layer is formed on the side of the gate material layer opposite to the first stacked structure.

16. The method for fabricating a semiconductor structure according to claim 13 or 14, characterized in that, A ferroelectric layer, a conductive layer, and a channel structure are sequentially formed within the channel hole, including: After the conductive layer is formed and before the channel structure is formed, a third dielectric layer is formed on the side of the conductive layer away from the ferroelectric layer.

17. A method for fabricating a semiconductor structure, characterized in that, include: A second stacked structure is formed, the second stacked structure including a plurality of third sacrificial layers and a plurality of gate layers alternately stacked along a first direction; A channel hole is formed, which penetrates the second stacked structure along the first direction; A ferroelectric layer, a conductive layer, and a channel structure are sequentially formed within the channel hole; Remove the third sacrificial layer to form a second filling space; The ferroelectric layer and the conductive layer are removed through the second filling space; A first dielectric layer is formed within the second filling space.

18. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure comprising a plurality of first dielectric layers and a plurality of gate layers alternately stacked along a first direction; A channel hole is formed, which penetrates the stacked structure along the first direction; A portion of the gate layer is removed to form a third fill space, the third fill space being in communication with the channel via; A ferroelectric layer and a conductive layer are sequentially formed within the third filling space, with the ferroelectric layer located between the gate layer and the conductive layer; A channel structure is formed within the channel hole, and the channel structure is located on the side of the conductive layer away from the ferroelectric layer.

19. A method for fabricating a semiconductor structure, characterized in that, include: A third stacked structure is formed, the third stacked structure comprising a plurality of first dielectric layers and a plurality of fourth sacrificial layers alternately stacked along a first direction; A channel hole is formed, which penetrates the third stacked structure along the first direction; A portion of the fourth sacrificial layer is removed to form a fourth fill space, which communicates with the channel hole; A ferroelectric layer and a conductive layer are sequentially formed within the fourth filling space, with the ferroelectric layer located between the gate layer and the conductive layer; A channel structure is formed within the channel hole, and the channel structure is located on the side of the conductive layer away from the ferroelectric layer; The fourth sacrificial layer is replaced with a gate layer.

20. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-12; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

21. An electronic device, characterized in that, include: The motherboard and the storage system as described in claim 20, wherein the motherboard is electrically connected to the storage system.

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