Semiconductor device and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of signal delay caused by a relatively far path of a bonding pad structure to a peripheral circuit. The semiconductor device includes an array structure, a semiconductor layer and a pad structure. The array structure comprises a first transistor and a ferroelectric capacitor which are stacked in the first direction. The semiconductor layer is located on one side of the array structure along the first direction. And the bonding pad structure is positioned on one side, deviating from the array structure, of the semiconductor layer along the first direction. Through the above arrangement, the line of the bonding pad structure for supplying power to the peripheral circuit in the semiconductor layer does not need to pass through the array structure, so that the path length of the line of the bonding pad structure for supplying power to the peripheral circuit in the semiconductor layer can be reduced, and the speed of supplying power to the peripheral circuit in the semiconductor layer by the bonding pad structure can be improved. The problem of signal delay caused by the fact that a bonding pad structure provides a far path for a peripheral circuit is solved, and the performance of a semiconductor device is optimized.

Description

Semiconductor devices and their fabrication methods, memory systems, electronic devices Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] Ferroelectric RAM (FRAM) is a type of random access memory that combines the fast read and write access of dynamic random access memory (DRAM) with the ability to retain data after power is turned off. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device, a method for fabricating the same, a storage system, and an electronic device.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor device is provided. The semiconductor device includes: an array structure, a semiconductor layer, and a pad structure. The array structure includes a first transistor and a ferroelectric capacitor stacked along a first direction; the semiconductor layer is located on one side of the array structure along the first direction; and the pad structure is located on the side of the semiconductor layer opposite to the array structure along the first direction.

[0006] In some embodiments, the semiconductor layer includes a first CMOS transistor and a second CMOS transistor, wherein the first CMOS transistor is connected to the first transistor and the second CMOS transistor is connected to the ferroelectric capacitor.

[0007] In some embodiments, the system further includes: a connection structure extending through at least a portion of the semiconductor layer, the connection structure being connected to the first CMOS transistor and the second CMOS transistor, and the connection structure being further connected to the pad structure.

[0008] In some embodiments, the semiconductor layer further includes a substrate and a first interconnect structure, the first interconnect structure being located between the array structure and the substrate, the first CMOS transistor being connected to the first interconnect structure, and the second CMOS transistor being connected to the first interconnect structure.

[0009] In some embodiments, the connection structure extends through the substrate and is connected to the first interconnect structure.

[0010] In some embodiments, the first interconnect structure includes a first bonding contact disposed on the side of the first interconnect structure away from the substrate; the semiconductor device further includes a second interconnect structure located between the array structure and the first interconnect structure; the second interconnect structure includes a second bonding contact disposed on the side of the second interconnect structure away from the array structure; the first bonding contact is in contact with the second bonding contact.

[0011] In some embodiments, the array structure includes a plurality of ferroelectric capacitors stacked along the first direction, the first capacitor electrodes of the plurality of ferroelectric capacitors being stacked along the first direction, and the plurality of ferroelectric capacitors sharing the same second capacitor electrode; the first transistor includes a first channel structure and a first gate layer, the first channel structure extending along the first direction, one end of the first channel structure along the first direction being connected to the second capacitor electrode, and the other end of the first channel structure along the first direction being connected to a transistor in the first CMOS transistor; the first gate layer is disposed around the first channel structure, and the first gate layer is also connected to another transistor in the first CMOS transistor.

[0012] In some embodiments, the array structure further includes a second transistor located on the side of the ferroelectric capacitor opposite to the first transistor; the second transistor includes a second channel structure and a second gate layer, the second gate layer extending along the first direction, one end of the second gate layer along the first direction being connected to the second capacitor electrode; the second channel structure is disposed around a portion of the second gate layer; the semiconductor layer further includes a third CMOS transistor connected to the second channel structure.

[0013] In some embodiments, the array structure includes a stacked structure, the stacked structure including a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along the first direction; the array structure further includes a dielectric layer and an electrode post penetrating the stacked structure, the dielectric layer being located between the electrode post and the second conductive layer, wherein the electrode post is the second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is the first capacitance electrode of the ferroelectric capacitor, the first capacitance electrode being connected to the second CMOS transistor.

[0014] In some embodiments, the constituent materials of the dielectric layer include ferroelectric materials.

[0015] In some embodiments, the first transistor is located on the side of the ferroelectric capacitor away from the semiconductor layer; the array structure further includes a first conductive pillar and a second conductive pillar, the first conductive pillar penetrating at least a portion of the stacked structure, the first transistor being connected to the first CMOS transistor through the first conductive pillar; the second conductive pillar penetrating a portion of the dielectric layer, the second transistor being connected to the third CMOS transistor through the second conductive pillar.

[0016] In some embodiments, the first transistor is located between the ferroelectric capacitor and the semiconductor layer; the array structure further includes a first conductive pillar and a second conductive pillar, the first conductive pillar penetrating a portion of the dielectric layer, the first transistor being connected to the first CMOS transistor through the first conductive pillar; the second conductive pillar penetrating the first gate layer and at least a portion of the stacked structure, the second transistor being connected to the third CMOS transistor through the second conductive pillar.

[0017] In some embodiments, the pad structure includes: a second conductive layer and a third interconnect structure stacked together, the third interconnect structure being located between the second conductive layer and the semiconductor layer, and the third interconnect structure being connected to the second conductive layer and the connection structure respectively.

[0018] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor device, comprising: providing an array structure, the array structure including a first transistor and a ferroelectric capacitor stacked along a first direction; forming a semiconductor layer located on one side of the array structure along the first direction; and forming a pad structure located on the side of the semiconductor layer opposite to the array structure along the first direction.

[0019] In some embodiments, providing the array structure includes: providing a substrate; forming a stacked structure, a ferroelectric capacitor, and a first transistor, the stacked structure including a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along a first direction, the ferroelectric capacitor including a dielectric layer penetrating the stacked structure and an electrode post, the dielectric layer being located between the electrode post and the first conductive layer, wherein the electrode post is a second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is a first capacitance electrode of the ferroelectric capacitor; the first transistor being located on the side of the ferroelectric capacitor away from the substrate; forming a first conductive post penetrating a portion of the dielectric layer, and one end of the first conductive post along the first direction being connected to the first transistor.

[0020] In some embodiments, providing the array structure includes: providing a substrate; forming a stacked structure, a ferroelectric capacitor, a first transistor, and a second transistor, wherein the stacked structure includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along a first direction, the ferroelectric capacitor includes a dielectric layer and an electrode post penetrating the stacked structure, the dielectric layer being located between the electrode post and the first conductive layer, wherein the electrode post is a second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is a first capacitance electrode of the ferroelectric capacitor; the first transistor is located between the ferroelectric capacitor and the substrate; the second transistor is located on the side of the ferroelectric capacitor away from the first transistor; forming a first conductive post and a second conductive post, the first conductive post penetrating at least a portion of the stacked structure, and one end of the first conductive post along the first direction being connected to the first transistor; the second conductive post penetrating a portion of the dielectric layer, and one end of the second conductive post along the first direction being connected to the second transistor.

[0021] In some embodiments, after forming the semiconductor layer and before forming the pad structure, the method further includes: forming an interconnect structure that extends through at least a portion of the semiconductor layer, and the first interconnect structure being connected to a first interconnect structure in the semiconductor layer; forming the pad structure includes: connecting the pad structure to the interconnect structure.

[0022] In another aspect, a storage system is provided, comprising: a semiconductor device and a controller as described above. The controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0023] In another aspect, an electronic device is provided, including a storage system and a motherboard as described above, wherein the motherboard is electrically connected to the storage system. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0025] Figure 1 is a structural block diagram of an electronic device provided in some embodiments of this disclosure;

[0026] Figure 2 is a structural block diagram of a memory provided in some embodiments of this disclosure;

[0027] Figure 3 is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure;

[0028] Figure 4 is a schematic diagram of the structure of another semiconductor device provided in some embodiments of this disclosure;

[0029] Figure 5 is a schematic diagram of the structure of another semiconductor device provided in some embodiments of this disclosure;

[0030] Figure 6 is a flowchart of a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0031] Figure 7 is a schematic diagram of the structure of a semiconductor device after an array structure is formed, according to some embodiments of the present disclosure;

[0032] Figure 8 is a schematic diagram of the structure of another semiconductor device after forming an array structure according to some embodiments of the present disclosure;

[0033] Figure 9 is a schematic diagram of the structure of a semiconductor device after the formation of a semiconductor layer according to some embodiments of this disclosure;

[0034] Figure 10 is a schematic diagram of the structure of another semiconductor device provided in some embodiments of this disclosure after the formation of a semiconductor layer.

[0035] Reference numerals: X, first direction; 1000, semiconductor device; 100, array structure; 110, first transistor; 111, first channel structure; 112, first gate layer; 120, ferroelectric capacitor; 121, first capacitor electrode; 122, second capacitor electrode; 123, dielectric layer; 124, electrode post; 130, second transistor; 131, second channel structure; 132, second gate layer; 140, first conductive post; 150, second conductive post. 160, Third conductive pillar; 200, Semiconductor layer; 210, Substrate; 220, First interconnect structure; 221, First bonding contact; 300, Pad structure; 310, Second conductive layer; 320, Third interconnect structure; 400, Connection structure; 410, Insulating layer; 420, Conductive pillar; 500, Second interconnect structure; 510, Second bonding contact; 600, Stacked structure; 610, First conductive layer; 620, Dielectric layer; 700, Substrate. Detailed Implementation

[0036] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0037] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0039] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0040] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0041] Figure 1 is a structural block diagram of an electronic device 9000 provided in some embodiments of this disclosure. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0042] As shown in Figure 1, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0043] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0044] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., a host computer).

[0045] The storage system 910 can contain one or more memories 911; Figure 1 illustrates this with three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. The controller 912 can also perform any other suitable functions. The controller 912 can communicate with external devices (e.g., the motherboard 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0046] Figure 2 is a structural block diagram of a memory 911 provided in some embodiments of this disclosure. As shown in Figure 2, the memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. The peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 913. For example, the peripheral circuitry 914 may include one or more of the following: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., a transistor, diode, resistor, or capacitor).

[0047] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0048] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. As shown in Figure 2, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 can include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 can include the memory cell array 913, and the second semiconductor structure 902 can include the peripheral circuitry 914.

[0049] The memory cell array 913 may be an array of memory cells using vertical transistors as switches and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, an FRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to an FRAM cell array, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switches and selection devices, such as DRAM (Dynamic Random Access Memory) cell arrays, PCM cell arrays, static random-access memory (SRAM) cell arrays, FRAM cell arrays, resistive memory cell arrays, magnetic memory cell arrays, spin transfer torque (STT) memory cell arrays, etc.

[0050] When the memory cell array 913 is an FRAM cell array, the memory cells therein are FRAM cells, each FRAM cell including a ferroelectric capacitor for storing data bits as positive or negative charges and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to the FRAM cell. In some embodiments, each FRAM cell is a transistor and a ferroelectric capacitor (1T1C) cell. In other embodiments, each FRAM cell is two transistors and multiple ferroelectric capacitors (2TXC). According to some embodiments, the FRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0051] Currently, in the X-tacking architecture, the memory cell array 913 and peripheral circuits 914 (sensor amplifier circuits, CMOS circuits, etc.) are fabricated on different wafers, and then the two wafers are bonded together by hybrid bonding before packaging. This process can improve the array density of the memory 911. In the X-tacking architecture, the wafer containing the memory cell array 913 and the wafer containing the peripheral circuits 914 are stacked face-to-face via a bonding interface, with the memory cell array 913 and the peripheral circuits 914 sandwiched between the two wafers.

[0052] In some embodiments, the memory 911 further includes a pad structure disposed on the back of the memory cell array 913. The pad structure is connected to the peripheral circuit 914 via metal wires or conductive posts, thereby supplying power to the peripheral circuit 914. Since the metal wires or conductive posts need to pass through the memory cell array 913, which contains some conductive devices such as transistors, the metal wires or conductive posts need to avoid these conductive devices. Therefore, the metal wires or conductive posts occupy a large amount of space, which is not conducive to further miniaturization of the memory 911.

[0053] In addition, the power supply line from the pad structure to the peripheral circuit 914 needs to pass through the memory cell array 913, which increases the length of the power supply line from the pad structure to the peripheral circuit 914. The longer path of the power supply from the pad structure to the peripheral circuit 914 causes signal delay, and the power supply speed from the pad structure to the peripheral circuit 914 needs to be improved.

[0054] Based on this, some embodiments of the present disclosure provide a semiconductor device, which may be the memory 911 in the above embodiments, or may be a part of the memory 911 in the above embodiments.

[0055] Figure 3 is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure.

[0056] As shown in Figure 3, in some embodiments, the semiconductor device 1000 includes an array structure 100, a semiconductor layer 200, and a pad structure 300. The semiconductor layer 200 is located on one side of the array structure 100 along a first direction X. The pad structure 300 is located on the side of the semiconductor layer 200 opposite to the array structure 100 along the first direction X.

[0057] In this embodiment, as shown in FIG3, the semiconductor device 1000 can adopt an X-tacking architecture. For example, the semiconductor layer 200 and the array structure 100 can be fabricated on different wafers, and then the two wafers can be bonded together by hybrid bonding and packaged. The semiconductor layer 200 and the array structure 100 can be located between the two wafers, thereby improving the storage density of the semiconductor device 1000.

[0058] Please refer to Figures 2 and 3. The bonding interface can be used as the dividing line. The part between the bonding interface and the pad structure 300 can be considered as the semiconductor layer 200. For example, peripheral circuits 914 (e.g., CMOS circuits) and interconnect structures can be set in the semiconductor layer 200.

[0059] In this embodiment, as shown in FIG3, the array structure 100 includes a first transistor 110 and a ferroelectric capacitor 120 stacked along a first direction X. In some embodiments, the array structure 100 may include a first transistor 110 and a ferroelectric capacitor 120 (1T1C) stacked along the first direction X. In other embodiments, the array structure 100 may include a first transistor 110 and a plurality of ferroelectric capacitors 120 (1TXC) stacked along the first direction X. The first transistor 110 is electrically connected to the ferroelectric capacitor 120, and the first transistor 110 can perform read and write operations on the ferroelectric capacitor 120.

[0060] Referring again to Figure 3, the pad structure 300 is used to supply power to peripheral circuits (e.g., CMOS circuits) in the semiconductor layer 200. For example, the pad structure 300 can be electrically connected to the peripheral circuits in the semiconductor layer 200 via interconnect structures. Exemplarily, the constituent materials of the pad structure 300 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), platinum (Pt), ruthenium (Ru), titanium nitride, polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0061] In this embodiment, the pad structure 300 is disposed on the side of the semiconductor layer 200 facing away from the array structure 100 along the first direction X. The pad structure 300 can be electrically connected to the peripheral circuits in the semiconductor layer 200 through interconnect structures, thereby supplying power to the peripheral circuits in the semiconductor layer 200. With the above arrangement, the power supply line from the pad structure 300 to the peripheral circuits in the semiconductor layer 200 does not need to pass through the array structure 100, which can reduce the path length of the power supply line from the pad structure 300 to the peripheral circuits in the semiconductor layer 200. This is beneficial to improve the power supply speed from the pad structure 300 to the peripheral circuits in the semiconductor layer 200, improve the signal delay problem caused by the long path of the pad structure 300 to the peripheral circuits, and optimize the performance of the semiconductor device 1000.

[0062] Furthermore, since the lines supplying power to the peripheral circuits in the semiconductor layer 200 do not need to pass through the array structure 100, there is no need to reserve layout positions for the aforementioned power supply lines in the array structure 100. This helps to reduce the space occupied by the aforementioned power supply lines and facilitates further miniaturization of the semiconductor device 1000 in terms of size.

[0063] In some embodiments, the lines supplying power to the peripheral circuits in the semiconductor layer 200 via the pad structure 300 pass through the array structure 100, increasing the size of the array structure 100 while maintaining the same total storage capacity. Consequently, the unit storage efficiency of the array structure 100 decreases. In this embodiment, however, the lines supplying power to the peripheral circuits in the semiconductor layer 200 via the pad structure 300 do not need to pass through the array structure 100, which improves the unit storage efficiency of the array structure 100.

[0064] In addition, the lines that supply power to the peripheral circuits in the semiconductor layer 200 from the pad structure 300 do not need to pass through the array structure 100, which can reduce the complexity of the internal trace layout of the semiconductor device 1000. This avoids mutual interference between the lines that supply power to the peripheral circuits in the semiconductor layer 200 from the pad structure 300 and other conductive devices, thereby reducing line loss and optimizing the storage performance of the semiconductor device 1000.

[0065] In some embodiments, as shown in FIG3, the semiconductor layer 200 includes a first CMOS transistor 230 and a second CMOS transistor 240. The first CMOS transistor 230 is connected to the first transistor 110, and the second CMOS transistor 240 is connected to the ferroelectric capacitor 120. The first CMOS transistor 230 and the second CMOS transistor 240 can each constitute part of different CMOS circuits (peripheral circuits).

[0066] For example, the first CMOS transistor 230 can be electrically connected to the first transistor 110 through interconnect structures, such as conductive layers, through-silicon contacts (TSCs), or through-silicon contacts. Similarly, the second CMOS transistor 240 can also be electrically connected to the ferroelectric capacitor 120 through interconnect structures.

[0067] With the above configuration, electrical signals can be transmitted between the first CMOS transistor 230 and the first transistor 110, and electrical signals can be transmitted between the second CMOS transistor 240 and the ferroelectric capacitor 120. The semiconductor layer 200 can control the first transistor 110 to perform read and write operations on the ferroelectric capacitor 120 through the first CMOS transistor 230 and the second CMOS transistor 240.

[0068] In some embodiments, as shown in FIG3, the semiconductor structure further includes a connection structure 400. The connection structure 400 extends through at least a portion of the semiconductor layer 200, and is connected to the first CMOS transistor 230 and the second CMOS transistor 240, and is also connected to the pad structure 300.

[0069] For example, the connection structure 400 may include a through silicon contact (TSC), a through silicon contact, etc.

[0070] It should be noted that the semiconductor structure may include multiple connection structures 400. The pad structure 300 can be connected to the first CMOS transistor 230 in the semiconductor layer 200 through one connection structure 400, and to the second CMOS transistor 240 in the semiconductor layer 200 through another connection structure 400.

[0071] In this embodiment, as shown in FIG3, the connection structure 400 may include an insulating layer 410 and a conductive pillar 420. The conductive pillar 420 may penetrate a portion or all of the semiconductor layer 200 along a first direction X. The conductive pillar 420 is used to connect the first CMOS transistor 230 or the second CMOS transistor 240, and also to connect the pad structure 300. The insulating layer 410 is disposed around the conductive pillar 420, and the insulating layer 410 is used to isolate the conductive layer and the semiconductor layer 200, improving the reliability of the semiconductor device 1000.

[0072] For example, the material of the insulating layer 410 may include an insulating material, such as one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride).

[0073] For example, the material of the conductive post 420 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), platinum (Pt), ruthenium (Ru), titanium nitride, polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0074] With the above configuration, the pad structure 300 is connected to the first CMOS transistor 230 and the second CMOS transistor 240 in the semiconductor layer 200 through the connection structure 400, which can realize the electrical connection between the pad structure 300 and the peripheral circuit, so that the pad structure 300 can supply power to the peripheral circuit in the semiconductor layer 200.

[0075] In some embodiments, as shown in FIG3, the semiconductor layer 200 further includes a substrate 210 and a first interconnect structure 220. The first interconnect structure 220 is located between the array structure 100 and the substrate 210, a first CMOS transistor 230 is connected to the first interconnect structure 220, and a second CMOS transistor 240 is connected to the first interconnect structure 220.

[0076] Exemplarily, the substrate 210 can be made of a semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), etc. The material of the semiconductor layer 200120 can also include a compound semiconductor, such as gallium arsenide (GaAs), indium phosphide (InP), or silicon carbide (SiC), etc. The substrate 210 of this disclosure can also be prepared using other semiconductor materials commonly used in the art, and this disclosure does not limit this application.

[0077] In this embodiment, as shown in FIG3, the first interconnection structure 220 may include a circuit layer and a plurality of interconnection contacts. Some interconnection contacts may be used to connect the circuit layer and the first CMOS transistor 230, and some interconnection contacts may be used to connect the circuit layer and the second CMOS transistor 240.

[0078] The circuit layer may include at least one circuit structure to electrically connect the first CMOS transistor 230 to the connection structure 400 via its internal circuit structures (e.g., interconnects) and interconnect contacts. Furthermore, the circuit layer may include an interlayer dielectric to isolate the circuit structures within the circuit layer. The interlayer dielectric may be made of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The interconnect contacts may include conductive materials; exemplaryly, conductive materials include, but are not limited to, one or more combinations of W, Co, Cu, Al, doped silicon, and silicides.

[0079] By setting the first interconnect structure 220, it is easy to connect the connection structure 400 to the first CMOS transistor 230 and the second CMOS transistor 240. Furthermore, it also facilitates the bonding connection between the semiconductor layer 200 and the array structure 100.

[0080] In some embodiments, as shown in FIG3, the connection structure 400 penetrates the substrate 210 and is connected to the first interconnect structure 220. The conductive posts 420 of the connection structure 400 can penetrate the substrate 210 and be connected to the first interconnect structure 220. In this embodiment, both the first CMOS transistor 230 and the second CMOS transistor 240 are connected to the first interconnect structure 220. Therefore, the connection structure 400 can be connected to the first CMOS transistor 230 and the second CMOS transistor 240 through the first interconnect structure 220.

[0081] As shown in Figure 3, the insulating layer 410 can be located between the conductive pillar 420 and the substrate 210 to isolate the conductive pillar 420 and the substrate 210 and improve the reliability of the semiconductor device 1000.

[0082] In some embodiments, continuing to refer to FIG3, the first interconnect structure 220 includes a first bonding contact 221, which is disposed on the side of the first interconnect structure 220 away from the substrate 210.

[0083] The semiconductor device 1000 further includes a second interconnect structure 500, which is located between the array structure 100 and the first interconnect structure 220. The second interconnect structure 500 includes a second bonding contact 510, which is disposed on the side of the second interconnect structure 500 away from the array structure 100. The first bonding contact 221 contacts and the second bonding contact 510, thereby achieving a bonding connection between the semiconductor layer 200 and the array structure 100.

[0084] The constituent materials of the first bonding contact 221 and the second bonding contact 510 may include conductive materials. For example, the conductive materials include, but are not limited to, one or more combinations of W, Co, Cu, Al, doped silicon, and silicides.

[0085] In some embodiments, as shown in FIG3, in the first direction X, the area of ​​the surface of the first bonding contact 221 near the second bonding contact 510 is larger than the area of ​​the surface of the first bonding contact 221 away from the second bonding contact 510. Similarly, in the first direction X, the area of ​​the surface of the second bonding contact 510 near the first bonding contact 221 is larger than the area of ​​the surface of the second bonding contact 510 away from the first bonding contact 221. This arrangement helps to increase the connection window between the first bonding contact 221 and the second bonding contact 510, facilitating contact and connection between them.

[0086] In some embodiments, please refer to FIG3, the array structure 100 may include a plurality of ferroelectric capacitors 120 stacked along a first direction X, the first capacitor electrodes 121 of the plurality of ferroelectric capacitors 120 being stacked along the first direction X, and the plurality of ferroelectric capacitors 120 sharing the same second capacitor electrode 122.

[0087] For example, the materials of the first capacitor electrode 121 and the second capacitor electrode 122 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), platinum (Pt), ruthenium (Ru), titanium nitride, polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0088] The first transistor 110 includes a first channel structure 111 and a first gate layer 112. The first channel structure 111 extends along a first direction X, and the first gate layer 112 is disposed around the first channel structure 111. Then the first transistor 110 is a GAA (Gate All Around) transistor.

[0089] The first CMOS transistor 230 includes a P-type transistor (PMOS) and an N-type transistor (NMOS), with the PMOS and NMOS sharing the same gate.

[0090] One end of the first channel structure 111 along the first direction X is connected to the second capacitor electrode 122, and the other end of the first channel structure 111 along the first direction X is connected to one of the transistors (PMOS or NMOS) in the first CMOS transistor 230. The first gate layer 112 is also connected to another transistor (NMOS or PMOS) in the first CMOS transistor 230.

[0091] With the above settings, the semiconductor device 1000 can provide voltage to the first gate layer 112 or the first channel structure 111 through the first CMOS transistor 230, which is beneficial for the semiconductor device 1000 to perform read and write operations on the ferroelectric capacitor 120 through the first transistor 110.

[0092] In some embodiments, as shown in Figures 4 and 5, the array structure 100 includes a first transistor 110, a plurality of ferroelectric capacitors 120, and a second transistor 130 (2TXC) stacked along a first direction X.

[0093] In this embodiment, the array structure 100 includes not only the first transistor 110 in some of the above embodiments, but also a second transistor 130, which is located on the side of the ferroelectric capacitor 120 away from the first transistor 110.

[0094] In some embodiments, as shown in FIG4, the first transistor 110 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200, and the second transistor 130 is located between the ferroelectric capacitor 120 and the semiconductor layer 200. In other embodiments, as shown in FIG5, the first transistor 110 is located between the ferroelectric capacitor 120 and the semiconductor layer 200, and the second transistor 130 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200.

[0095] The second transistor 130 includes a second channel structure 131 and a second gate layer 132. The second gate layer 132 extends along a first direction X, and the second channel structure 131 is disposed around a portion of the second gate layer 132, so the second transistor 130 is a CAA (Channel All Around) transistor.

[0096] For example, the material of the second channel structure 131 may include indium gallium zinc oxide (IGZO).

[0097] In this embodiment, as shown in Figures 4 and 5, the semiconductor layer 200 further includes a third CMOS transistor 250, which is connected to the second channel structure 131. One transistor (PMOS or NMOS) of the third CMOS transistor 250 is connected to the source of the second channel structure 131, and the other transistor (NMOS or PMOS) of the third CMOS transistor 250 is connected to the drain of the second channel structure 131. One end of the second gate layer 132 along the first direction X is connected to the second capacitor electrode 122.

[0098] Furthermore, one end of the first channel structure 111 of the first transistor 110 along the first direction X is connected to the second capacitor electrode 122, and the other end of the first channel structure 111 along the first direction X is connected to one of the transistors (PMOS or NMOS) in the first CMOS transistor 230. The first gate layer 112 is also connected to another transistor (NMOS or PMOS) in the first CMOS transistor 230.

[0099] With the above configuration, the semiconductor device 1000 can perform write operations on the ferroelectric capacitor 120 through the first transistor 110, and read operations on the ferroelectric capacitor 120 through the second transistor 130. By performing write and read operations on the ferroelectric capacitor 120 through the first transistor 110 and the second transistor 130 respectively, the semiconductor device 1000 can achieve non-destructive read operations, which is beneficial for optimizing the device performance of the semiconductor device 1000. Furthermore, after performing a read operation on the ferroelectric capacitor 120, the semiconductor device 1000 does not need to perform a write-back operation, which simplifies the read and write operation process of the semiconductor device 1000.

[0100] In some embodiments, as shown in FIG4, the array structure 100 includes a stack structure 600, which includes a plurality of first conductive layers 610 and a plurality of dielectric layers 620 alternately stacked along a first direction X.

[0101] Multiple first conductive layers 610 and multiple dielectric layers 620 are alternately spaced along a first direction X. For example, the first conductive layers 610 and dielectric layers 620 are alternately spaced along the first direction X and stacked to form multiple first conductive layers 610 and multiple dielectric layers 620 spaced apart from each other.

[0102] For example, the material of the first conductive layer 610 may include a conductive material, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), platinum (Pt), ruthenium (Ru), titanium nitride, polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0103] For example, the material of the dielectric layer 620 may include an insulating material, such as one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride).

[0104] In this embodiment, as shown in FIG4, the array structure 100 further includes a dielectric layer 123 and an electrode post 124 penetrating the stacked structure 600. The dielectric layer 123 is located between the electrode post 124 and the second conductive layer 310. The electrode post 124 is the second capacitor electrode 122 of a plurality of ferroelectric capacitors 120, and the portion of the conductive layer surrounding the dielectric layer 123 is the first capacitor electrode 121 of the ferroelectric capacitors 120. The first capacitor electrode 121 is connected to the second CMOS transistor 240.

[0105] For example, the dielectric layer 123 is composed of ferroelectric materials, such as HfZrO, SiHfO, AlHfO, ZrO, etc. In this way, the semiconductor device 1000 can utilize the ferroelectric polarization characteristics to store data, increase the storage capacitance by polarizing the charge, and reduce the capacitance height for the same capacitance value, which is beneficial for further miniaturization of the semiconductor device 1000.

[0106] The semiconductor device 1000 provided in this embodiment can increase the number of ferroelectric capacitors 120 by increasing the height of the electrode post 124 and the dielectric layer 123 in the first direction X and the number of stacked layers of the first conductive layer 610. The above setting method is simple to operate and facilitates increasing the number of ferroelectric capacitors 120, thereby improving the storage capacity of the semiconductor device 1000.

[0107] Furthermore, multiple ferroelectric capacitors 120 share an electrode post 124 as the second capacitor electrode 122, which does not require breaking, thus simplifying the fabrication process of the semiconductor device 1000 and improving the fabrication efficiency of the semiconductor device 1000.

[0108] In some embodiments, as shown in FIG4, when the first transistor 110 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200, and the second transistor 130 is located between the ferroelectric capacitor 120 and the semiconductor layer 200, the array structure 100 further includes a first conductive pillar 140 and a second conductive pillar 150. The first conductive pillar 140 penetrates at least a portion of the stacked structure 600, and the first transistor 110 is connected to the first CMOS transistor 230 through the first conductive pillar 140. The second conductive pillar 150 penetrates a portion of the dielectric layer 620, and the second transistor 130 is connected to the third CMOS transistor 250 through the second conductive pillar 150.

[0109] It should be noted that "the first conductive post 140 penetrates at least part of the stacked structure 600" can be understood as the first conductive post 140 penetrating part of the stacked structure 600, or the first conductive post 140 penetrating the entire stacked structure 600.

[0110] The materials of both the first conductive post 140 and the second conductive post 150 include conductive materials.

[0111] The array structure 100 may include a plurality of first conductive pillars 140. A first gate layer 112 may be electrically connected to one transistor of a first CMOS transistor 230 via one of the first conductive pillars 140. A first channel structure 111 may be electrically connected to another transistor of the first CMOS transistor 230 via one of the first conductive pillars 140. The first conductive pillars 140 may be connected to the first CMOS transistor 230 via a second interconnect structure 500 and a first interconnect structure 220.

[0112] The array structure 100 may include multiple second conductive pillars 150. The source (or drain) of the second channel structure 131 can be electrically connected to one transistor of the third CMOS transistor 250 via one second conductive pillar 150. The drain (or source) of the second channel structure 131 can be electrically connected to another transistor of the third CMOS transistor 250 via one second conductive pillar 150. The second conductive pillars 150 can be connected to the third CMOS transistor 250 via the second interconnect structure 500 and the first interconnect structure 220.

[0113] With the above settings, the CMOS circuit containing the first CMOS transistor 230 can perform write operations on the ferroelectric capacitor 120 by controlling the first transistor 110, and the CMOS circuit containing the third CMOS transistor 250 can perform read operations on the ferroelectric capacitor 120 by controlling the second transistor 130. This enables non-destructive read operations and helps optimize the device performance of the semiconductor device 1000.

[0114] In other embodiments, as shown in FIG5, when the first transistor 110 is located between the ferroelectric capacitor 120 and the semiconductor layer 200, and the second transistor 130 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200, the array structure 100 further includes a first conductive pillar 140 and a second conductive pillar 150. The first conductive pillar 140 penetrates a portion of the dielectric layer 620, and the first transistor 110 is connected to the first CMOS transistor 230 through the first conductive pillar 140. The second conductive pillar 150 penetrates the first gate layer 112 and at least a portion of the stacked structure 600, and the second transistor 130 is connected to the third CMOS transistor 250 through the second conductive pillar 150.

[0115] The array structure 100 may include a plurality of first conductive pillars 140. A first gate layer 112 may be electrically connected to one transistor of a first CMOS transistor 230 via one of the first conductive pillars 140. A first channel structure 111 may be electrically connected to another transistor of the first CMOS transistor 230 via one of the first conductive pillars 140. The first conductive pillars 140 may be connected to the first CMOS transistor 230 via a second interconnect structure 500 and a first interconnect structure 220.

[0116] The array structure 100 may include multiple second conductive pillars 150. The source (or drain) of the second channel structure 131 can be electrically connected to one transistor of the third CMOS transistor 250 via one second conductive pillar 150. The drain (or source) of the second channel structure 131 can be electrically connected to another transistor of the third CMOS transistor 250 via one second conductive pillar 150. The second conductive pillars 150 can be connected to the third CMOS transistor 250 via the second interconnect structure 500 and the first interconnect structure 220.

[0117] With the above settings, the CMOS circuit containing the first CMOS transistor 230 can perform write operations on the ferroelectric capacitor 120 by controlling the first transistor 110, and the CMOS circuit containing the third CMOS transistor 250 can perform read operations on the ferroelectric capacitor 120 by controlling the second transistor 130. This enables non-destructive read operations and helps optimize the device performance of the semiconductor device 1000.

[0118] In some embodiments, as shown in Figures 4 and 5, the array structure 100 may further include a plurality of third conductive pillars 160. The third conductive pillars 160 are used to connect the first conductive layer 610 and the second interconnect structure 500.

[0119] As shown in Figure 4, when the first transistor 110 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200, and the second transistor 130 is located between the ferroelectric capacitor 120 and the semiconductor layer 200, the third conductive post 160 penetrates the partially stacked structure 600, and a third conductive post 160 can be connected to a first conductive layer 610.

[0120] As shown in Figure 5, when the first transistor 110 is located between the ferroelectric capacitor 120 and the semiconductor layer 200, and the second transistor 130 is located on the side of the ferroelectric capacitor 120 away from the semiconductor layer 200, the third conductive pillar 160 penetrates the first gate layer 112 and part of the stacked structure 600, and a third conductive pillar 160 can be connected to a first conductive layer 610.

[0121] In some embodiments, as shown in Figures 4 and 5, the pad structure 300 includes a second conductive layer 310 and a third interconnect structure 320 stacked together. The third interconnect structure 320 is located between the second conductive layer 310 and the semiconductor layer 200, and is connected to the second conductive layer 310 and the connection structure 400, respectively.

[0122] For example, the material of the second conductive layer 310 may include a conductive material.

[0123] The third interconnect structure 320 may include multiple circuit layers and multiple interconnect contacts. The second conductive layer 310 can be electrically connected to the peripheral circuits (e.g., CMOS circuits) in the semiconductor layer 200 through the third interconnect structure 320, the connection structure 400 and the first interconnect structure, thereby enabling power supply to the peripheral circuits in the semiconductor layer 200.

[0124] With the above configuration, the power supply line from the second conductive layer 310 to the peripheral circuits in the semiconductor layer 200 does not need to pass through the array structure 100. This reduces the path length of the power supply line from the second conductive layer 310 to the peripheral circuits in the semiconductor layer 200, which helps to improve the power supply speed from the second conductive layer 310 to the peripheral circuits in the semiconductor layer 200, improves the signal delay problem caused by the long path from the second conductive layer 310 to the peripheral circuits, and optimizes the performance of the semiconductor device 1000.

[0125] Based on the semiconductor device 1000 provided in the above embodiments, some embodiments of this disclosure also provide a method for fabricating the semiconductor device 1000, which is used to fabricate the semiconductor device 1000 provided in the above embodiments.

[0126] Figure 6 is a flowchart of a method for fabricating a semiconductor device according to some embodiments of this disclosure.

[0127] As shown in Figure 6, the method for fabricating semiconductor device 1000 includes the following steps S1 to S3.

[0128] S1. Provide an array structure, the array structure including a first transistor and a ferroelectric capacitor stacked along a first direction.

[0129] In this step, the array structure 100 can be fabricated on a wafer using appropriate processes such as deposition and etching.

[0130] In some embodiments, referring to FIG7, a substrate 700 may be provided in this step. Exemplarily, the substrate 700 may be a rigid substrate 700, such as a glass substrate 700 or a PMMA (Polymethyl methacrylate) substrate 700. Alternatively, the substrate 700 may be a flexible substrate 700, such as a PET (Polyethylene terephthalate) substrate 700, a PEN (Polyethylenenaphthalate dimethyl methacrylate) substrate 700, or a PI (Polyimide) substrate 700.

[0131] After providing the substrate 700, a stacked structure 600, a ferroelectric capacitor 120, and a first transistor 110 can be formed.

[0132] In this step, referring to Figure 7, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form the first conductive layer 610 and the dielectric layer 620 on the substrate 700 multiple times to form the stacked structure 600.

[0133] The dielectric layer 123 and electrode pillars 124 can be formed using etching and deposition processes. Both the dielectric layer 123 and electrode pillars 124 penetrate the stacked structure 600. The dielectric layer 123 is located between the electrode pillars 124 and the first conductive layer 610 to form a ferroelectric capacitor 120. The electrode pillars 124 serve as the second capacitor electrodes 122 of the plurality of ferroelectric capacitors 120, and the portion of the conductive layer surrounding the dielectric layer 123 serves as the first capacitor electrode 121 of the ferroelectric capacitors 120.

[0134] For example, after the ferroelectric capacitor 120 is formed, an etching process and a deposition process can be used to form a first transistor 110, which is located on the side of the ferroelectric capacitor 120 away from the substrate 700.

[0135] After the first transistor 110 is formed, a plurality of first conductive pillars 140 can be formed by etching and deposition processes. The first conductive pillars 140 penetrate a portion of the dielectric layer 620, and one end of the first conductive pillar 140 along the first direction X is connected to the first gate layer 112, and one end of the first conductive pillar 140 along the first direction X is connected to the first channel structure 111.

[0136] The array structure 100 shown in Figure 7 can be obtained through the preparation steps of the above embodiments.

[0137] In some other embodiments, referring to FIG8, this step includes providing a substrate 700.

[0138] After providing the substrate 700, a stacked structure 600, a ferroelectric capacitor 120, and a first transistor 110 can be formed.

[0139] In this step, referring to Figure 8, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form the first conductive layer 610 and the dielectric layer 620 on the substrate 700 multiple times to form the stacked structure 600.

[0140] A first transistor 110, a ferroelectric capacitor 120, and a second transistor 130 can be formed by etching and deposition processes, stacked along a first direction X. The first transistor 110 is located between the ferroelectric capacitor 120 and the substrate 700, and the second transistor 130 is located on the side of the ferroelectric capacitor 120 away from the first transistor 110.

[0141] Forming a ferroelectric capacitor 120 includes forming a dielectric layer 123 and an electrode post 124 that penetrate the stacked structure 600 using etching and deposition processes. The dielectric layer 123 is located between the electrode post 124 and the first conductive layer 610. The electrode post 124 serves as the second capacitor electrode 122 of the plurality of ferroelectric capacitors 120, and a portion of the conductive layer surrounding the dielectric layer 123 serves as the first capacitor electrode 121 of the ferroelectric capacitor 120.

[0142] After forming the first transistor 110, ferroelectric capacitor 120, and second transistor 130 stacked along the first direction X, a plurality of first conductive pillars 140 and a plurality of second conductive pillars 150 can be formed using etching and deposition processes. One first conductive pillar 140 penetrates a portion of the stacked structure 600 to the first gate layer 112 and is connected to the first gate layer 112; another first conductive pillar 140 penetrates the stacked structure 600 to the substrate 700 and is connected to the first channel structure 111 through the substrate 700. A second conductive pillar 150 penetrates a portion of the dielectric layer 620. One end of one second conductive pillar 150 along the first direction X is connected to the source terminal of the second channel structure 131, and another end of one second conductive pillar 150 along the first direction X is connected to the drain terminal of the second channel structure 131.

[0143] The array structure 100 shown in FIG8 can be obtained through the preparation steps of the above embodiments.

[0144] S2. Form a semiconductor layer, which is located on one side of the array structure along the first direction.

[0145] In this step, a semiconductor layer 200 can be fabricated on another wafer.

[0146] Referring to Figures 9 and 10, for example, a substrate 210 can be provided. An n / p impurity can be implanted on one side of the substrate 210 using an ion implantation process to form multiple doped regions. In some examples, when high-energy boron ions are implanted, local p-type regions can be formed for subsequent fabrication of NMOS transistors. In other examples, when high-energy phosphorus ions are implanted, local n-type regions can be formed for subsequent fabrication of PMOS transistors.

[0147] A CMOS circuit and a first interconnect structure 220 are formed on the substrate 210. Exemplarily, the CMOS circuit may include a first CMOS transistor 230, a second CMOS transistor 240, and a third CMOS transistor 250, etc.

[0148] After the semiconductor layer 200 is fabricated on the wafer, the wafer with the semiconductor layer 200 and the wafer with the array structure 100 can be bonded face to face through a hybrid bonding process, so that the semiconductor layer 200 and the array structure 100 are bonded together.

[0149] Referring to Figures 3, 4, 9 and 10, after the semiconductor layer 200 is bonded to the array structure 100, an etching process and a deposition process can be used to form a connection structure 400. The connection structure 400 penetrates at least a portion of the semiconductor layer 200, and the first connection structure 400 is connected to the first interconnect structure 220 in the semiconductor layer 200.

[0150] S3. Form a pad structure, the pad structure is located on the side of the semiconductor layer away from the array structure along the first direction.

[0151] In this step, referring to Figures 3, 4, 9, and 10, a deposition process can be used to sequentially form the third interconnect structure 320 and the second conductive layer 310. The third interconnect structure 320 is located between the semiconductor layer 200 and the second conductive layer 310. The third interconnect structure 320 and the second conductive layer 310 together constitute the pad structure 300. Furthermore, when forming the third interconnect structure 320, the third interconnect structure 320 is connected to the other end of the connection structure 400 along the first direction X.

[0152] The semiconductor device 1000 prepared by the above method has a pad structure 300 disposed on the side of the semiconductor layer 200 facing away from the array structure 100 along the first direction X. The pad structure 300 can be electrically connected to the peripheral circuits in the semiconductor layer 200 through interconnect structures, thereby supplying power to the peripheral circuits in the semiconductor layer 200. Therefore, the power supply line from the pad structure 300 to the peripheral circuits in the semiconductor layer 200 does not need to pass through the array structure 100, which can reduce the path length of the power supply line from the pad structure 300 to the peripheral circuits in the semiconductor layer 200, which is beneficial to improve the power supply speed from the pad structure 300 to the peripheral circuits in the semiconductor layer 200, improve the signal delay problem caused by the long path of the pad structure 300 to the peripheral circuits, and optimize the performance of the semiconductor device 1000.

[0153] Furthermore, since the lines supplying power to the peripheral circuits in the semiconductor layer 200 do not need to pass through the array structure 100, there is no need to reserve layout positions for the aforementioned power supply lines in the array structure 100. This helps to reduce the space occupied by the aforementioned power supply lines and facilitates further miniaturization of the semiconductor device 1000 in terms of size.

[0154] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: An array structure, the array structure comprising a first transistor and a ferroelectric capacitor stacked along a first direction; A semiconductor layer is located on one side of the array structure along the first direction; a pad structure is located on the side of the semiconductor layer opposite to the array structure along the first direction.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor layer includes a first CMOS transistor and a second CMOS transistor, the first CMOS transistor being connected to the first transistor, and the second CMOS transistor being connected to the ferroelectric capacitor.

3. The semiconductor device according to claim 2, characterized in that, Also includes: A connection structure extends through at least a portion of the semiconductor layer, the connection structure being connected to the first CMOS transistor and the second CMOS transistor, and the connection structure also being connected to the pad structure.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor layer further includes a substrate and a first interconnect structure, the first interconnect structure being located between the array structure and the substrate, the first CMOS transistor being connected to the first interconnect structure, and the second CMOS transistor being connected to the first interconnect structure.

5. The semiconductor device according to claim 4, characterized in that, The connection structure extends through the substrate and is connected to the first interconnect structure.

6. The semiconductor device according to claim 5, characterized in that, The first interconnect structure includes a first bonding contact, which is disposed on the side of the first interconnect structure away from the substrate; The semiconductor device further includes: a second interconnect structure, wherein the second interconnect structure is located between the array structure and the first interconnect structure; The second interconnect structure includes a second bonding contact, which is disposed on the side of the second interconnect structure away from the array structure; the first bonding contact is in contact with the second bonding contact.

7. The semiconductor device according to claim 1, characterized in that, The array structure includes a plurality of ferroelectric capacitors stacked along the first direction, with first capacitor electrodes of the plurality of ferroelectric capacitors stacked along the first direction, and the plurality of ferroelectric capacitors sharing the same second capacitor electrode; the first transistor includes a first channel structure and a first gate layer, the first channel structure extending along the first direction, one end of the first channel structure along the first direction being connected to the second capacitor electrode, and the other end of the first channel structure along the first direction being connected to a transistor in the first CMOS transistor; the first gate layer is disposed around the first channel structure, and the first gate layer is also connected to another transistor in the first CMOS transistor.

8. The semiconductor device according to claim 7, characterized in that, The array structure further includes a second transistor located on the side of the ferroelectric capacitor opposite to the first transistor; the second transistor includes a second channel structure and a second gate layer, the second gate layer extending along the first direction, one end of the second gate layer along the first direction being connected to the second capacitor electrode; the second channel structure is disposed around a portion of the second gate layer; the semiconductor layer further includes a third CMOS transistor connected to the second channel structure.

9. The semiconductor device according to claim 8, characterized in that, The array structure includes a stacked structure, which includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along the first direction; the array structure also includes a dielectric layer and an electrode post penetrating the stacked structure, the dielectric layer being located between the electrode post and the second conductive layer, wherein the electrode post is the second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is the first capacitance electrode of the ferroelectric capacitor, the first capacitance electrode being connected to the second CMOS transistor.

10. The semiconductor device according to claim 9, characterized in that, The dielectric layer is composed of ferroelectric materials.

11. The semiconductor device according to claim 9, characterized in that, The first transistor is located on the side of the ferroelectric capacitor away from the semiconductor layer; the array structure further includes a first conductive pillar and a second conductive pillar, the first conductive pillar penetrating at least a portion of the stacked structure, the first transistor being connected to the first CMOS transistor through the first conductive pillar; the second conductive pillar penetrating a portion of the dielectric layer, the second transistor being connected to the third CMOS transistor through the second conductive pillar.

12. The semiconductor device according to claim 9, characterized in that, The first transistor is located between the ferroelectric capacitor and the semiconductor layer; the array structure further includes a first conductive pillar and a second conductive pillar, the first conductive pillar penetrates a portion of the dielectric layer, and the first transistor is connected to the first CMOS transistor through the first conductive pillar; the second conductive pillar penetrates the first gate layer and at least a portion of the stacked structure, and the second transistor is connected to the third CMOS transistor through the second conductive pillar.

13. The semiconductor device according to claim 1, characterized in that, The pad structure includes: a second conductive layer and a third interconnect structure stacked together, the third interconnect structure being located between the second conductive layer and the semiconductor layer, and the third interconnect structure being connected to the second conductive layer and the connection structure respectively.

14. A method for fabricating a semiconductor device, characterized in that, include: An array structure is provided, the array structure comprising a first transistor and a ferroelectric capacitor stacked along a first direction; A semiconductor layer is formed on one side of the array structure along the first direction; a pad structure is formed on the side of the semiconductor layer opposite to the array structure along the first direction.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The provision of the array structure includes: providing a substrate; forming a stacked structure, a ferroelectric capacitor, and a first transistor, wherein the stacked structure includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along a first direction, the ferroelectric capacitor includes a dielectric layer penetrating the stacked structure and an electrode post, the dielectric layer being located between the electrode post and the first conductive layer, wherein the electrode post is a second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is a first capacitance electrode of the ferroelectric capacitor; the first transistor is located on the side of the ferroelectric capacitor away from the substrate; forming a first conductive post, the first conductive post penetrating a portion of the dielectric layer, and one end of the first conductive post along the first direction being connected to the first transistor.

16. The method for fabricating a semiconductor device according to claim 14, characterized in that, The array structure includes: providing a substrate; forming a stacked structure, a ferroelectric capacitor, a first transistor, and a second transistor, wherein the stacked structure includes a plurality of first conductive layers and a plurality of dielectric layers alternately stacked along a first direction, the ferroelectric capacitor includes a dielectric layer and an electrode post penetrating the stacked structure, the dielectric layer being located between the electrode post and the first conductive layer, wherein the electrode post is a second capacitance electrode of the plurality of ferroelectric capacitors, and a portion of the conductive layer surrounding the dielectric layer is a first capacitance electrode of the ferroelectric capacitor; the first transistor is located between the ferroelectric capacitor and the substrate; the second transistor is located on the side of the ferroelectric capacitor away from the first transistor; forming a first conductive post and a second conductive post, the first conductive post penetrating at least a portion of the stacked structure, and one end of the first conductive post along the first direction being connected to the first transistor; the second conductive post penetrating a portion of the dielectric layer, and one end of the second conductive post along the first direction being connected to the second transistor.

17. The method for fabricating a semiconductor device according to claim 14, characterized in that, After forming the semiconductor layer and before forming the pad structure, the method further includes: forming an interconnect structure that penetrates at least a portion of the semiconductor layer, and the first interconnect structure being connected to a first interconnect structure in the semiconductor layer; forming the pad structure includes: connecting the pad structure to the interconnect structure.

18. A storage system, characterized in that, include: The semiconductor device according to any one of claims 1-13; A controller coupled to the semiconductor device to control the semiconductor device to store data.

19. An electronic device, characterized in that, include: The motherboard and the storage system as described in claim 18, wherein the motherboard is electrically connected to the storage system.

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