Germanium-silicon heterojunction bipolar transistor and manufacturing method thereof

Abstract

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. The germanium-silicon heterojunction bipolar transistor comprises a silicon-based bipolar transistor base structure, a silicon-based bipolar transistor and a silicon-based bipolar transistor, the selective injection collector region is formed in the lightly doped silicon epitaxial collector region; the base region-collector region isolation dielectric layer is formed on the upper sides of the field region dielectric layer and the lightly doped silicon epitaxial collector region; the transition silicon epitaxial collector region is formed on the upper side of the selective injection collector region; the germanium-silicon epitaxial inner base region is formed on the upper side of the transition silicon epitaxial collector region; the heavily doped single crystal emitter region is formed in the germanium-silicon epitaxial inner base region; the emitter region-base region isolation dielectric layer is formed on the upper side of the polycrystalline germanium-silicon outer base region; the stepped silicon oxide isolation layer is formed on the upper side of the germanium-silicon epitaxial inner base region, the upper side and the inner side of the heavily doped polycrystalline germanium-silicon outer base region and the inner side of the emitter region-base region isolation dielectric layer; and a heavily doped polycrystalline silicon emitter region. According to the germanium-silicon heterojunction bipolar transistor and the manufacturing method thereof provided by the embodiment of the invention, the device performance is improved.

Description

A germanium-silicon heterojunction bipolar transistor and its manufacturing method Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a germanium-silicon heterojunction bipolar transistor and its manufacturing method. Background Technology

[0002] The germanium-silicon heterojunction bipolar transistor is a high-performance semiconductor device. By introducing a germanium-silicon (SiGe) alloy into the base region of the transistor to form a heterojunction with the pure silicon in the emitter region, the device's performance, such as speed, radio frequency power, noise, and efficiency, is improved.

[0003] Figure 1 is a schematic diagram of the structure of a germanium-silicon heterojunction bipolar transistor in the prior art. The germanium-silicon heterojunction bipolar transistor includes an intrinsic base region 101 and a connecting base region 102, which are simultaneously grown by a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method. Since the connecting base region 102 is grown simultaneously with the intrinsic base region 101, the doping situation of the connecting base region during the growth process is generally similar to that of the intrinsic base region. However, there are conflicting requirements for boron doping and diffusion in the intrinsic base region 101 and the connecting base region 102. Under the premise of ensuring the requirements of the intrinsic base region first, the boron doping and diffusion of the connecting base region grown simultaneously cannot be fully optimized independently. This results in a considerable portion of the final connecting base region having relatively low doping concentration areas, i.e., areas with high resistance, thereby reducing device performance. Therefore, how to propose a germanium-silicon heterojunction bipolar transistor to overcome the above defects and improve device performance has become an important problem that urgently needs to be solved in this field. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of the present invention provide a germanium-silicon heterojunction bipolar transistor and a method for manufacturing the same, which can at least partially solve the problems existing in the prior art.

[0005] In a first aspect, the present invention provides a germanium-silicon heterojunction bipolar transistor, comprising:

[0006] A basic structure for a silicon-based bipolar transistor; wherein the basic structure includes a substrate, a heavily doped silicon buried layer collector region formed on the substrate, a field region dielectric layer formed on the heavily doped silicon buried layer collector region, and a lightly doped silicon epitaxial collector region; wherein the conductivity type of the heavily doped silicon buried layer collector region and the lightly doped silicon epitaxial collector region is opposite to that of the substrate.

[0007] Selective implantation of a collector region is performed to form within the lightly doped silicon epitaxial collector region;

[0008] A base-collector isolation dielectric layer is formed on the field dielectric layer and the lightly doped silicon epitaxial collector region;

[0009] A transition silicon epitaxial collector region is formed on the upper side of the selectively implanted collector region; wherein the conductivity type of the transition silicon epitaxial collector region is the same as the conductivity type of the lightly doped silicon epitaxial collector region;

[0010] A heavily doped polycrystalline germanium-silicon outer base region is formed on the upper side of the base region-collector region isolation dielectric layer; wherein the conductivity type of the heavily doped polycrystalline germanium-silicon outer base region is opposite to the conductivity type of the heavily doped silicon buried layer collector region;

[0011] A germanium-silicon epitaxial inner base region is formed on the upper side of the transition silicon epitaxial collector region;

[0012] A heavily doped single-crystal emitter region is formed within the inner base region of the germanium-silicon epitaxial layer;

[0013] An emitter-base region isolation dielectric layer is formed on the upper side of the polycrystalline germanium-silicon outer base region;

[0014] A stepped silicon oxide isolation layer is formed on the upper side of the inner base region of the germanium-silicon epitaxial layer, on the upper and inner sides of the heavily doped polycrystalline germanium-silicon outer base region, and on the inner side of the emitter-base region isolation dielectric layer.

[0015] A heavily doped polycrystalline silicon emitter region is formed on the emitter-base region isolation dielectric layer, the stepped silicon oxide isolation layer, and the heavily doped single-crystal emitter region; wherein the conductivity type of the polycrystalline silicon emitter region is the same as the conductivity type of the heavily doped silicon buried layer collector region.

[0016] Furthermore, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0017] The first dielectric outer wall is formed on the outside of the heavily doped polycrystalline silicon emitter region;

[0018] The second dielectric outer wall is formed on the outside of the heavily doped polycrystalline germanium silicon outer base region and the base-collector isolation dielectric layer.

[0019] Furthermore, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0020] An emitter electrode is formed on the upper side of the heavily doped polycrystalline silicon emitter region;

[0021] The base electrode is formed on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

[0022] In a second aspect, the present invention provides a method for manufacturing a germanium-silicon heterojunction bipolar transistor, comprising:

[0023] A silicon-based bipolar transistor (BPT) basic structure is provided, the BPT basic structure including a substrate, a heavily doped silicon buried layer collector region formed on the substrate, and a field region dielectric layer and a lightly doped silicon epitaxial collector region formed on the upper side of the heavily doped silicon buried layer collector region; wherein the conductivity type of the heavily doped silicon buried layer collector region and the lightly doped silicon epitaxial collector region is opposite to that of the substrate.

[0024] On the silicon-based bipolar transistor basic structure, a base-collector isolation dielectric layer, a heavily doped outer base polycrystalline germanium silicon layer with compressive strain, an emitter-base isolation dielectric layer, and a silicon nitride layer are deposited sequentially; wherein, the conductivity type of the heavily doped outer base polycrystalline germanium silicon layer is opposite to the type of the collector region of the heavily doped silicon buried layer;

[0025] A collector region window is formed along the thickness direction of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer, exposing part of the base region-collector region isolation dielectric layer; and ion implantation is performed on the lightly doped silicon epitaxial collector region through the exposed base region-collector region isolation dielectric layer to form a selectively implanted collector region;

[0026] A transition silicon epitaxial collector region and a germanium-silicon epitaxial inner base region are sequentially formed within the collector region window; wherein, a gap exists between the germanium-silicon epitaxial inner base region and the polycrystalline germanium-silicon layer of the heavily doped outer base region;

[0027] The thermal process causes the heavily doped polycrystalline germanium-silicon layer in the outer base region to reflow, and releases and relaxes the compressive strain to fill the gap between the heavily doped polycrystalline germanium-silicon layer in the outer base region and the germanium-silicon epitaxial inner base region.

[0028] A stepped silicon oxide isolation layer is formed inside the emitter-base region isolation dielectric layer, at the exposed portion of the germanium-silicon epitaxial inner base region in the collector region window, and on the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer.

[0029] A heavily doped polycrystalline silicon emitter region with the same conductivity type as the collector region of the heavily doped silicon buried layer is deposited;

[0030] Rapid thermal annealing is performed to allow impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial base region, forming a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region.

[0031] Further, the step of forming a collector region window along the thickness direction of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer, thereby exposing a portion of the base-collector region isolation dielectric layer, includes:

[0032] A collector region window photoresist pattern is formed on the photoresist on the silicon nitride layer using a photolithography process;

[0033] Using the photoresist pattern of the collector region window as a mask, the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer are etched away sequentially to expose the base region-collector region isolation dielectric layer;

[0034] Remove the photoresist pattern from the collector area window to form the collector area window.

[0035] Further, the sequential formation of the transition silicon epitaxial collector region and the germanium-silicon epitaxial inner base region within the collector region window includes:

[0036] A silicon nitride inner wall is formed at the inner edge of the collector window on the upper side of the base region-collector region isolation dielectric layer;

[0037] Remove the base-collector isolation dielectric layer below the collector window to expose the selectively injected collector, and laterally remove the base-collector isolation dielectric layer of a predetermined width below the silicon nitride inner wall;

[0038] A transition silicon epitaxial collector region is formed on the upper side of the selectively implanted collector region, and the thickness of the transition silicon epitaxial collector region is greater than or equal to the thickness of the base region-collector region isolation dielectric layer;

[0039] On the upper side of the transition silicon epitaxial collector region, a germanium-silicon epitaxial inner base region is formed, and the silicon nitride layer and the silicon nitride inner sidewall are removed.

[0040] Further, the formation of a stepped silicon oxide isolation layer inside the emitter-base region isolation dielectric layer, at the exposed portion of the germanium-silicon epitaxial inner base region in the collector region window, and on the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer includes:

[0041] A silicon oxide layer is deposited on the upper side of the emitter-base region isolation dielectric layer, the germanium-silicon epitaxial inner base region, and the heavily doped outer base region polycrystalline germanium-silicon layer, and a recessed region is formed on the upper side of the germanium-silicon epitaxial inner base region;

[0042] A heavily doped emitter region inner sidewall polysilicon layer is deposited; wherein the conductivity type of the heavily doped emitter region inner sidewall polysilicon layer is opposite to that of the substrate;

[0043] Anisotropic dry etching is performed on the polysilicon layer of the inner sidewall of the heavily doped emitter region to form the inner sidewall of the heavily doped polysilicon emitter region.

[0044] The exposed silicon oxide layer is etched away by wet etching using the inner sidewall of the heavily doped polycrystalline silicon emitter region as a mask, forming a stepped silicon oxide isolation layer.

[0045] Furthermore, the deposition forming of a heavily doped polycrystalline silicon emitter region with the same conductivity type as the heavily doped silicon buried layer collector region includes:

[0046] The deposited heavily doped emitter polysilicon layer merges with the inner sidewall of the heavily doped polysilicon emitter region to form a heavily doped emitter polysilicon layer.

[0047] A polysilicon emitter region photoresist pattern is formed on the photoresist on the heavily doped emitter region polysilicon layer using a photolithography process.

[0048] Using the photoresist pattern of the polysilicon emitter region as a mask, the heavily doped emitter region polysilicon layer and the emitter region-base region isolation dielectric layer are etched sequentially.

[0049] Remove the photoresist pattern from the polysilicon emitter region.

[0050] Furthermore, after removing the photoresist pattern from the polycrystalline silicon emitter region and before performing rapid thermal annealing, the method for manufacturing a germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0051] Photolithography is performed on the heavily doped polycrystalline germanium-silicon outer base region to form a photoresist pattern for the heavily doped polycrystalline germanium-silicon outer base region.

[0052] Using the photoresist pattern of the heavily doped polycrystalline germanium silicon outer base region as a mask, the heavily doped polycrystalline germanium silicon outer base region layer and the base region-collector region isolation dielectric layer are etched sequentially.

[0053] Remove the photoresist pattern from the heavily doped polycrystalline germanium silicon outer base region;

[0054] Deposition of the outer wall medium layer;

[0055] After rapid thermal annealing, which allows impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial base region to form a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region, the process further includes:

[0056] The outer wall dielectric layer is etched using anisotropic dry etching to form a first dielectric outer wall and a second dielectric outer wall.

[0057] Furthermore, after forming the first dielectric outer wall and the second dielectric outer wall, the method for manufacturing a germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0058] An emitter electrode is formed on the upper side of the heavily doped polycrystalline silicon emitter region, and a base electrode is formed on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

[0059] The germanium-silicon heterojunction bipolar transistor and its manufacturing method provided in this invention do not include a connection base region that cannot be sufficiently heavily doped in the device structure. The heavily doped polycrystalline germanium-silicon outer base region and the germanium-silicon-carbon epitaxial inner base region are directly connected, thus avoiding the introduction of corresponding parasitic resistance in the connection base region. This effectively reduces the parasitic base region resistance of the germanium-silicon heterojunction bipolar transistor, which can not only increase the maximum frequency under a given cutoff frequency, but also effectively reduce the radio frequency noise figure, thereby improving the overall device performance of the germanium-silicon heterojunction bipolar transistor as a radio frequency device, such as radio frequency power and noise. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0061] Figure 1 is a schematic diagram of the structure of a germanium-silicon heterojunction bipolar transistor in the prior art.

[0062] Figure 2 is a schematic diagram of the structure of a germanium-silicon heterojunction bipolar transistor provided in an embodiment of the present invention.

[0063] Figure 3 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention.

[0064] Figure 4 is a flowchart illustrating a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention.

[0065] Figure 5 is a flowchart illustrating a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention.

[0066] Figure 6 is a flowchart illustrating a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention.

[0067] Figure 7 is a flowchart illustrating a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention.

[0068] Figure 8a is a schematic diagram of the basic structure of an npn bipolar transistor provided in an embodiment of the present invention.

[0069] Figure 8b is a schematic diagram of the structure after deposition of a multilayer structure according to an embodiment of the present invention.

[0070] Figure 8c is a schematic diagram of the structure after forming a photoresist pattern in the collector region window according to an embodiment of the present invention.

[0071] Figure 8d is a schematic diagram of the structure after forming the collector region window according to an embodiment of the present invention.

[0072] Figure 8e is a schematic diagram of the structure after forming the silicon nitride inner wall according to an embodiment of the present invention.

[0073] Figure 8f is a schematic diagram of the structure after removing part of the base region-collector region isolation silicon oxide layer according to an embodiment of the present invention.

[0074] Figure 8g is a schematic diagram of the structure after forming a transition silicon epitaxial collector region according to an embodiment of the present invention.

[0075] Figure 8h is a schematic diagram of the structure after forming the inner base region of germanium-silicon-carbon epitaxial layer according to an embodiment of the present invention.

[0076] Figure 8i is a schematic diagram of the structure after removing the inner wall of silicon nitride according to an embodiment of the present invention.

[0077] Figure 8j is a schematic diagram of the structure after gap filling according to an embodiment of the present invention.

[0078] Figure 8k is a schematic diagram of the structure after forming the inner sidewall of the heavily doped polycrystalline silicon emitter region according to an embodiment of the present invention.

[0079] Figure 81 is a schematic diagram of the structure after forming a heavily doped emitter region polycrystalline silicon layer according to an embodiment of the present invention.

[0080] Figure 8m is a schematic diagram of the structure after forming a heavily doped polycrystalline silicon emitter region according to an embodiment of the present invention.

[0081] Figure 8n is a schematic diagram of the structure after forming a heavily doped polycrystalline germanium silicon outer base region according to an embodiment of the present invention.

[0082] Figure 80 is a schematic diagram of the structure after rapid thermal annealing according to an embodiment of the present invention.

[0083] Figure 8p is a schematic diagram of the structure after forming a silicon oxide outer wall according to an embodiment of the present invention.

[0084] Figure 8q is a schematic diagram of the structure after forming the emitter silicide electrode and the base silicide electrode according to an embodiment of the present invention. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other in any way. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations.

[0086] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0087] It should be noted that the term "including / comprising" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0088] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0089] In existing germanium-silicon heterojunction bipolar transistors, a selective epitaxial growth method using p-type in-situ doped germanium-silicon-carbon is employed to simultaneously grow an intrinsic inner base region and an outer base region, both containing a polysilicon layer cantilever and a connection base region beneath the silicon nitride inner sidewall. The epitaxial inner base region, the core intrinsic region of the device obtained through selective epitaxial growth, roughly comprises a silicon buffer layer, a germanium-silicon-carbon layer, and a silicon capping layer, in that order. The buffer and capping layers are undoped. Even the germanium-silicon-carbon layer further comprises several epitaxial layers, with only the innermost layer being boron-doped. This ensures a sufficiently thin inner base region, minimizing the carrier density over time within the intrinsic region of the germanium-silicon heterojunction bipolar transistor, thereby maximizing the device's cutoff frequency.

[0090] However, since the interconnect base region is grown simultaneously with the intrinsic base region, its doping situation during growth is largely similar to that of the intrinsic base region. Specifically, only the innermost layer is boron-doped, while the other layers are undoped. Although some boron impurities can diffuse from the heavily doped outer polysilicon layer during growth and subsequent thermal processes, there are conflicting requirements for boron doping and diffusion in the intrinsic base region and the interconnect base region to ensure both a sufficiently thin inner base region and minimize boron impurity diffusion during growth and subsequent thermal processes. Therefore, prioritizing the intrinsic base region, the interconnect base region, grown simultaneously, cannot be fully optimized for boron doping and diffusion independently. This results in a significant portion of the final interconnect base region having relatively low doping concentrations, i.e., regions with high resistance. The high resistance of the interconnect base region prevents a sufficient reduction in the parasitic base region resistance of the entire device.

[0091] Germanium-silicon bipolar transistors (BSBs), as representatives of high-performance silicon-based radio frequency semiconductor devices, can achieve very high cutoff frequencies through structural and process optimization of the intrinsic region, including the intrinsic base region. However, if the base region parasitic resistance, one of the most important parasitic parameters, cannot be sufficiently reduced, the final device performance will be greatly reduced. This is not only reflected in the fact that the maximum oscillation frequency, another performance indicator that is equal to or even more important than the cutoff frequency, cannot be sufficiently increased due to the insufficient base region parasitic resistance, thus failing to guarantee that the device can obtain a sufficiently high radio frequency power gain under high-frequency operating conditions, but also that a high base region parasitic resistance will directly cause the degradation of radio frequency noise performance.

[0092] Therefore, this application proposes a germanium-silicon heterojunction bipolar transistor with a structure without a connecting base region, thereby avoiding the conflicting requirements between the intrinsic base region and the connecting base region in terms of boron doping and diffusion, which would lead to a reduction in device performance.

[0093] Figure 2 is a schematic diagram of a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention. As shown in Figure 2, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the present invention includes:

[0094] A basic structure for a silicon-based bipolar transistor; wherein the basic structure includes a substrate 201, a heavily doped silicon buried layer collector region 202 formed on the upper side of the substrate 201, a field region dielectric layer 203 formed on the upper side of the heavily doped silicon buried layer collector region 202, and a lightly doped silicon epitaxial collector region 204; wherein the conductivity type of the heavily doped silicon buried layer collector region 202 and the lightly doped silicon epitaxial collector region 204 is opposite to that of the substrate 201;

[0095] Selective implantation of collector region 205 is formed within lightly doped silicon epitaxial collector region 204;

[0096] A base-collector isolation dielectric layer 206 is formed on the upper side of the field dielectric layer 203 and the lightly doped silicon epitaxial collector region 204;

[0097] A transition silicon epitaxial collector region 207 is formed on the upper side of the selectively implanted collector region 205; wherein, the conductivity type of the transition silicon epitaxial collector region 207 is the same as the conductivity type of the lightly doped silicon epitaxial collector region 204.

[0098] A heavily doped polycrystalline germanium silicon outer base region 208 is formed on the upper side of the base region-collector region isolation dielectric layer 206; wherein, the conductivity type of the heavily doped polycrystalline germanium silicon outer base region 208 is opposite to the conductivity type of the heavily doped silicon buried layer collector region 202.

[0099] The germanium-silicon epitaxial inner base region 209 is formed on the upper side of the transition silicon epitaxial collector region 207;

[0100] A heavily doped single-crystal emitter region 210 is formed within the germanium-silicon epitaxial base region 209;

[0101] The emitter-base region isolation dielectric layer 211 is formed on the upper side of the heavily doped polycrystalline germanium silicon outer base region 208;

[0102] A stepped silicon oxide isolation layer 212 is formed on the upper side of the germanium-silicon epitaxial inner base region 209, on the upper and inner sides of the heavily doped polycrystalline germanium-silicon outer base region 208, and inside the emitter-base region isolation dielectric layer 211.

[0103] A heavily doped polycrystalline silicon emitter region 213 is formed on the emitter-base region isolation dielectric layer 211, the stepped silicon oxide isolation layer 212, and the heavily doped single crystal emitter region 210; wherein, the conductivity type of the heavily doped polycrystalline silicon emitter region 213 is the same as the conductivity type of the heavily doped silicon buried layer collector region 202.

[0104] The dielectric layer can be a silicon oxide layer.

[0105] It should be noted that when the substrate 201 is a p-type lightly doped silicon substrate, the heavily doped silicon buried layer collector region 202 is an n-type heavily doped silicon buried layer collector region, the lightly doped silicon epitaxial collector region 204 is an n-type lightly doped silicon epitaxial collector region, the transition silicon epitaxial collector region 207 is an n-type lightly doped transition silicon epitaxial collector region 207, the heavily doped polycrystalline germanium silicon outer base region 208 is a p-type heavily doped polycrystalline germanium silicon outer base region, and the heavily doped polycrystalline silicon emitter region 213 is an n-type heavily doped polycrystalline silicon emitter region 213.

[0106] When the substrate 201 is an n-type lightly doped silicon substrate, the heavily doped silicon buried layer collector region 202 is a p-type heavily doped silicon buried layer collector region, the lightly doped silicon epitaxial collector region 204 is a p-type lightly doped silicon epitaxial collector region, the transition silicon epitaxial collector region 207 is a p-type lightly doped transition silicon epitaxial collector region 207, the heavily doped polycrystalline germanium silicon outer base region 208 is an n-type heavily doped polycrystalline germanium silicon outer base region, and the heavily doped polycrystalline silicon emitter region 213 is a p-type heavily doped polycrystalline silicon emitter region 213.

[0107] The germanium-silicon heterojunction bipolar transistor provided in this invention does not include a connection base region that cannot be sufficiently heavily doped in its device structure. The heavily doped polycrystalline germanium-silicon outer base region and the germanium-silicon-carbon epitaxial inner base region are directly connected, thus avoiding the introduction of corresponding parasitic resistance in the connection base region. This effectively reduces the parasitic base region resistance of the germanium-silicon heterojunction bipolar transistor, which can not only increase the maximum frequency under a given cutoff frequency, but also effectively reduce the radio frequency noise figure, thereby improving the overall device performance of the germanium-silicon heterojunction bipolar transistor as a radio frequency device, such as radio frequency power and noise.

[0108] As shown in Figure 1, based on the above embodiments, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0109] The first dielectric outer wall 214 is formed on the outside of the heavily doped polycrystalline silicon emitter region 213;

[0110] The second dielectric outer wall 215 is formed on the outside of the heavily doped polycrystalline germanium silicon outer base region 208 and the base-collector isolation dielectric layer 206.

[0111] As shown in Figure 1, based on the above embodiments, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention further includes:

[0112] Emitter electrode 216 is located on the upper side of the heavily doped polycrystalline silicon emitter region;

[0113] Base electrode 217, located on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

[0114] Figure 3 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention. As shown in Figure 3, the method for manufacturing a germanium-silicon heterojunction bipolar transistor according to an embodiment of the present invention includes:

[0115] S301. A silicon-based bipolar transistor basic structure is provided, the silicon-based bipolar transistor basic structure including a substrate, a heavily doped silicon buried layer collector region formed on the substrate, and a field region dielectric layer and a lightly doped silicon epitaxial collector region formed on the upper side of the heavily doped silicon buried layer collector region; wherein, the conductivity type of the heavily doped silicon buried layer collector region and the lightly doped silicon epitaxial collector region is opposite to that of the substrate.

[0116] Specifically, the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention begins with a basic structure including a substrate, a heavily doped silicon buried collector region, a field region dielectric layer, and a lightly doped silicon epitaxial collector region. The heavily doped silicon buried collector region is formed on the substrate, and the field region dielectric layer and the transition silicon epitaxial collector region are formed on the heavily doped silicon buried collector region.

[0117] In this case, the conductivity type of the heavily doped silicon buried layer collector region and the transition silicon epitaxial collector region is opposite to that of the substrate. For example, if the substrate is a p-type lightly doped silicon substrate, then the heavily doped silicon buried layer collector region is an n-type heavily doped silicon buried layer collector region, and the lightly doped silicon epitaxial collector region is an n-type lightly doped silicon epitaxial collector region.

[0118] S302, On the silicon-based bipolar transistor basic structure, a base region-collector region isolation dielectric layer, a heavily doped outer base region polycrystalline germanium silicon layer with compressive strain, an emitter region-base region isolation dielectric layer, and a silicon nitride layer are deposited sequentially; wherein, the conductivity type of the heavily doped outer base region polycrystalline germanium silicon layer is opposite to the type of the collector region of the heavily doped silicon buried layer;

[0119] Specifically, a base-collector isolation dielectric layer, a heavily doped outer base polycrystalline germanium-silicon layer with compressive strain, an emitter-base isolation dielectric layer, and a silicon nitride layer are sequentially deposited on the silicon-based bipolar transistor basic structure. By adjusting the germanium composition of the heavily doped outer base polycrystalline germanium-silicon layer, the compressive strain of the heavily doped outer base polycrystalline germanium-silicon layer can be changed to ensure that the subsequent heavily doped outer base polycrystalline germanium-silicon layer releases and relaxes the compressive strain, thus completely filling the gaps left by the corrosion of the silicon nitride inner sidewall.

[0120] The conductivity type of the heavily doped outer base region polycrystalline germanium-silicon layer with compressive strain is opposite to that of the heavily doped silicon buried layer collector region. For example, if the heavily doped silicon buried layer collector region is an n-type heavily doped silicon buried layer collector region, then the heavily doped outer base region polycrystalline germanium-silicon layer is a p-type heavily doped outer base region polycrystalline germanium-silicon layer.

[0121] S303. A collector region window is formed along the thickness direction of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer, exposing part of the base region-collector region isolation dielectric layer; and ion implantation is performed on the transition silicon epitaxial collector region through the exposed base region-collector region isolation dielectric layer to form a selectively implanted collector region.

[0122] Specifically, a collector region window photoresist pattern is formed on the photoresist on the silicon nitride layer using photolithography. Then, using the collector region window photoresist pattern as a mask, the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium-silicon layer are sequentially etched away to expose the underlying base-collector region isolation dielectric layer, forming the collector region window. After etching, selective ion implantation is performed through the exposed base-collector region isolation dielectric layer, thereby forming a selectively implanted collector region in the lightly doped silicon epitaxial collector region directly opposite the collector region window. After forming the selectively implanted collector region, the collector region window photoresist pattern is removed.

[0123] When the lightly doped silicon epitaxial collector region is an n-type lightly doped silicon epitaxial collector region, n-type ion implantation will be performed to form a selectively implanted collector region.

[0124] S304. A transition silicon epitaxial collector region and a germanium-silicon epitaxial inner base region are sequentially formed within the collector region window; wherein, there is a gap between the germanium-silicon epitaxial inner base region and the polycrystalline germanium-silicon layer of the heavily doped outer base region.

[0125] Specifically, a silicon nitride inner wall is formed at the inner edge of the collector region window on the upper side of the base-collector region isolation dielectric layer. Then, the base-collector region isolation dielectric layer below the collector region window is removed to expose the selectively implanted collector region. The base-collector region isolation dielectric layer of a predetermined width below the silicon nitride inner wall is then removed laterally. A transition silicon epitaxial collector region is then formed on the upper side of the selectively implanted collector region. Finally, a germanium-silicon epitaxial inner base region is formed on the upper side of the transition silicon epitaxial collector region, and the silicon nitride layer and the silicon nitride inner wall are removed, thereby forming a gap between the germanium-silicon epitaxial inner base region and the heavily doped outer base region polycrystalline germanium-silicon layer.

[0126] The preset width is set according to actual needs, and is not limited in this embodiment of the invention. The thickness of the transition silicon epitaxial collector region is equal to the thickness of the base-collector region isolation dielectric layer, or the thickness of the transition silicon epitaxial collector region is greater than the thickness of the base-collector region isolation dielectric layer.

[0127] S305. Based on the thermal process, the heavily doped polycrystalline germanium-silicon outer base region is reflowed, and the compressive strain is released and relaxed to fill the gap between the heavily doped outer base region polycrystalline germanium-silicon layer and the germanium-silicon epitaxial inner base region.

[0128] Specifically, a thermal process is used to maintain the stability of the germanium-silicon-carbon epitaxial inner base region, causing the heavily doped polycrystalline germanium-silicon layer in the outer base region to reflow and fully release and relax the compressive strain, thereby causing the volume of the heavily doped polycrystalline germanium-silicon layer in the outer base region to expand to a certain extent, thereby filling the gap between the heavily doped polycrystalline germanium-silicon layer in the outer base region and the germanium-silicon epitaxial inner base region.

[0129] S306. A stepped silicon oxide isolation layer is formed inside the emitter-base region isolation dielectric layer, on the exposed portion of the germanium-silicon epitaxial inner base region in the collector region window, and on the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer.

[0130] Specifically, a silicon oxide layer is deposited on the upper side of the emitter-base region isolation dielectric layer, the germanium-silicon epitaxial inner base region, and the heavily doped outer base region polycrystalline germanium-silicon layer, and a recessed region is formed on the upper side of the germanium-silicon epitaxial inner base region; then, a heavily doped emitter region inner sidewall polycrystalline silicon layer is deposited; next, anisotropic dry etching is performed on the heavily doped emitter region inner sidewall polycrystalline silicon layer to form the heavily doped polycrystalline silicon emitter region inner sidewall; then, the exposed silicon oxide layer is wet-etched away using the heavily doped polycrystalline silicon emitter region inner sidewall as a mask to form a stepped silicon oxide isolation layer.

[0131] The conductivity type of the heavily doped emitter region inner sidewall polysilicon layer is opposite to that of the substrate. For example, the substrate is a p-type lightly doped silicon substrate, and the heavily doped emitter region inner sidewall polysilicon layer is a p-type heavily doped emitter region inner sidewall polysilicon layer.

[0132] S307, deposited to form a heavily doped polycrystalline silicon emitter region with the same conductivity type as the collector region of the heavily doped silicon buried layer;

[0133] Specifically, after forming a stepped silicon oxide isolation layer, a heavily doped polycrystalline silicon emitter region is deposited on the base region of the germanium-silicon epitaxial layer, the emitter-base region isolation dielectric layer, and the upper side of the stepped silicon oxide isolation layer.

[0134] In this case, the conductivity type of the heavily doped polysilicon emitter region is the same as that of the heavily doped silicon buried collector region. For example, the heavily doped silicon buried collector region is an n-type heavily doped silicon buried collector region, and the heavily doped polysilicon emitter region is an n-type heavily doped polysilicon emitter region.

[0135] S308. Perform rapid thermal annealing to allow impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial base region, forming a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region.

[0136] Specifically, the semiconductor structure formed by the above steps is subjected to rapid thermal annealing (RTA) to allow impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial base region, forming a heavily doped single-crystal emitter region and achieving impurity activation.

[0137] The conductivity type of the heavily doped single-crystal emitter region is the same as that of the heavily doped polycrystalline silicon emitter region. For example, the heavily doped polycrystalline silicon emitter region is an n-type heavily doped polycrystalline silicon emitter region, and the heavily doped single-crystal emitter region is an n-type heavily doped single-crystal emitter region.

[0138] Figure 4 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention. As shown in Figure 4, based on the above embodiments, the step of forming a collector region window along the thickness direction of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium-silicon layer, so that the base region-collector region isolation dielectric layer is partially exposed, includes:

[0139] S401. A collector area window photoresist pattern is formed on the photoresist on the silicon nitride layer by photolithography.

[0140] Specifically, photoresist is spin-coated onto the silicon nitride layer, and then photolithography is performed on the photoresist to form a collector region window photoresist pattern. The collector region window photoresist pattern serves as a mask for subsequent etching of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer.

[0141] S402. Using the photoresist pattern of the collector region window as a mask, the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer are sequentially etched away to expose the base region-collector region isolation dielectric layer.

[0142] Specifically, the silicon nitride layer, the emitter-base isolation dielectric layer, and the heavily doped outer base polycrystalline germanium silicon layer are sequentially etched away using the photoresist pattern of the collector region window as a mask, exposing the underlying base-collector isolation dielectric layer.

[0143] S403. Remove the photoresist pattern from the collector area window to form the collector area window.

[0144] Specifically, the photoresist pattern of the collector area window on the silicon nitride layer is removed to obtain the collector area window.

[0145] Figure 5 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention. As shown in Figure 5, based on the above embodiments, the step of sequentially forming a transition silicon epitaxial collector region and a germanium-silicon epitaxial inner base region within the collector region window includes:

[0146] S501, A silicon nitride inner wall is formed at the inner edge of the collector window on the upper side of the base region-collector region isolation dielectric layer;

[0147] Specifically, a sacrificial silicon nitride layer is first deposited, and then the sacrificial silicon nitride layer is etched by anisotropic dry etching to form an inner wall of silicon nitride at the edge of the collector window.

[0148] S502. Remove the base-collector isolation dielectric layer below the collector window to expose the selectively injected collector, and laterally remove the base-collector isolation dielectric layer of a predetermined width below the silicon nitride inner wall.

[0149] Specifically, using the silicon nitride layer and the silicon nitride inner wall as a mask, anisotropic dry etching is used to remove the exposed base-collector isolation dielectric layer of a predetermined thickness. Then, the remaining thickness of the base-collector isolation dielectric layer is removed by wet etching, while simultaneously transverse etching of the base-collector isolation dielectric layer to remove the base-collector isolation dielectric layer of a predetermined width below the silicon nitride inner wall.

[0150] The preset thickness, for example, is 4 / 5 of the thickness of the base-collector region isolation dielectric layer, and is set according to actual needs; this embodiment of the invention does not limit this. The remaining thickness refers to the thickness remaining after subtracting the preset thickness from the thickness of the base-collector region isolation dielectric layer. The preset width is set according to actual needs; this embodiment of the invention does not limit this. The preset width setting needs to be adapted to the expansion of the heavily doped outer base region polycrystalline germanium-silicon layer so that the heavily doped outer base region polycrystalline germanium-silicon layer can fill the gaps and directly connect with the germanium-silicon epitaxial inner base region during thermal processes.

[0151] S503, A transition silicon epitaxial collector region is formed on the upper side of the selectively implanted collector region, wherein the thickness of the transition silicon epitaxial collector region is greater than or equal to the thickness of the base region-collector region isolation dielectric layer;

[0152] Specifically, on the selectively implanted collector region, a transition silicon epitaxial collector region of a target thickness is selectively grown epitaxially. The target thickness is greater than or equal to the thickness of the base-collector region isolation dielectric layer. The target thickness is set according to actual needs, and this embodiment of the invention does not limit it.

[0153] The conductivity type of the transition silicon epitaxial collector region is the same as that of the substrate. For example, substrate 201 is an n-type lightly doped silicon substrate, and the transition silicon epitaxial collector region is an n-type impurity in-situ doped transition silicon epitaxial collector region.

[0154] S504. On the upper side of the transition silicon epitaxial collector region, a germanium-silicon epitaxial inner base region is formed, and the silicon nitride layer and the silicon nitride inner sidewall are removed.

[0155] Specifically, germanium-silicon-carbon epitaxial inner base region is obtained by selectively growing germanium-silicon-carbon on the upper side of the transition silicon epitaxial collector region using in-situ boron-doped silica. Then, the silicon nitride layer and the silicon nitride inner sidewalls can be removed by wet etching.

[0156] For example, when the substrate is an n-type lightly doped silicon substrate, germanium-silicon-carbon epitaxial inner base region can be obtained by selective epitaxial growth of p-type in-situ boron-doped germanium-silicon-carbon on the upper side of the transition silicon epitaxial collector region.

[0157] Figure 6 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention. As shown in Figure 6, based on the above embodiments, the step of forming a stepped silicon oxide isolation layer inside the emitter-base region isolation dielectric layer, at the exposed portion of the germanium-silicon epitaxial inner base region in the collector region window, and on the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer includes:

[0158] S601. A silicon oxide layer is deposited on the upper side of the emitter-base region isolation dielectric layer, the germanium-silicon epitaxial inner base region, and the heavily doped outer base region polycrystalline germanium-silicon layer, and a recessed region is formed on the upper side of the germanium-silicon epitaxial inner base region.

[0159] Specifically, after the heavily doped polycrystalline germanium-silicon outer base region is reflowed based on a thermal process to fill the gap between the heavily doped polycrystalline germanium-silicon outer base region layer and the germanium-silicon epitaxial inner base region, a silicon oxide layer is deposited on the emitter-base region isolation dielectric layer, the germanium-silicon epitaxial inner base region, and the heavily doped polycrystalline germanium-silicon outer base region layer. The thickness of the silicon oxide layer is less than a preset value to form a thin silicon oxide layer. After the silicon oxide layer is deposited, a recessed region is formed on the upper side of the germanium-silicon epitaxial inner base region within the original collector region window.

[0160] S602. Deposit a heavily doped emitter inner sidewall polysilicon layer in the recessed region; wherein the conductivity type of the heavily doped emitter inner sidewall polysilicon layer is opposite to that of the substrate.

[0161] Specifically, an in-situ heavily doped emitter inner wall polysilicon layer is deposited in the recessed region, that is, a polysilicon layer is deposited in the recessed region, which is subsequently used to form the heavily doped emitter inner wall.

[0162] The conductivity type of the polysilicon layer on the inner sidewall of the heavily doped emitter region is opposite to that of the substrate; for example, if the substrate is a p-type lightly doped silicon substrate, then the polysilicon layer on the inner sidewall of the heavily doped emitter region is an n-type heavily doped emitter region.

[0163] S603. Perform anisotropic dry etching on the polysilicon layer of the inner sidewall of the heavily doped emitter region to form the inner sidewall of the heavily doped polysilicon emitter region.

[0164] Specifically, for the heavily doped emitter region inner sidewall polysilicon layer, an anisotropic dry etching method is used to form the heavily doped polysilicon emitter region inner sidewall.

[0165] S604. Using the inner sidewall of the heavily doped polycrystalline silicon emitter region as a mask, wet etching is used to remove the exposed silicon oxide layer, forming a stepped silicon oxide isolation layer.

[0166] Specifically, using the inner sidewall of the heavily doped polycrystalline silicon emitter region as a shield, the exposed silicon oxide layer, namely the silicon oxide layer on the emitter-base region isolation dielectric layer and the silicon oxide layer on the inner base region of the germanium-silicon-carbon epitaxial layer, is wet-etched away to form a stepped silicon oxide isolation layer.

[0167] Figure 7 is a schematic flowchart of a method for manufacturing a germanium-silicon heterojunction bipolar transistor according to another embodiment of the present invention. As shown in Figure 7, based on the above embodiments, the deposition of the heavily doped polycrystalline silicon emitter region having the same conductivity type as the heavily doped silicon buried layer collector region further includes:

[0168] S701, The deposited heavily doped emitter polysilicon layer merges with the inner sidewall of the heavily doped polysilicon emitter region to form a heavily doped emitter polysilicon layer.

[0169] Specifically, an in-situ heavily doped emitter polysilicon layer is deposited, which merges with the inner sidewall of the heavily doped emitter polysilicon layer to form a heavily doped emitter polysilicon layer.

[0170] For example, an in-situ heavily doped n-type emitter polysilicon layer is deposited, which merges with the inner sidewall of the n-type heavily doped polysilicon emitter region to form an n-type heavily doped emitter polysilicon layer.

[0171] S702. A polysilicon emission region photoresist pattern is formed on the photoresist on the heavily doped emission region polysilicon layer using a photolithography process.

[0172] Specifically, photoresist is spin-coated onto the heavily doped emitter polysilicon layer, and then photolithography is performed on the photoresist to form a polysilicon emitter photoresist pattern. The polysilicon emitter photoresist pattern serves as a mask for subsequent etching of the heavily doped emitter polysilicon layer and the emitter-base isolation dielectric layer.

[0173] S703. Using the photoresist pattern of the polysilicon emitter region as a mask, the heavily doped emitter region polysilicon layer and the emitter region-base region isolation dielectric layer are etched sequentially.

[0174] Specifically, using the photoresist pattern of the polysilicon emitter region as a mask, the exposed heavily doped emitter region polysilicon layer and the underlying emitter-base region isolation dielectric layer are sequentially etched away. Etching away the heavily doped emitter region polysilicon layer forms the heavily doped polysilicon emitter region. After etching away the exposed emitter-base region isolation dielectric layer beneath the heavily doped emitter region polysilicon layer, the emitter-base region isolation dielectric layer of the germanium-silicon heterojunction bipolar transistor is obtained.

[0175] S704. Remove the photoresist pattern from the polysilicon emitter region.

[0176] Specifically, the photoresist pattern of the polysilicon emitter region is removed to expose the heavily doped polysilicon emitter region.

[0177] Based on the above embodiments, further, after removing the photoresist pattern from the polysilicon emitter region and before performing rapid thermal annealing, the following steps are also included:

[0178] Photolithography is performed on the heavily doped polycrystalline germanium-silicon outer base region to form a photoresist pattern for the heavily doped polycrystalline germanium-silicon outer base region.

[0179] Using the photoresist pattern of the heavily doped polycrystalline germanium silicon outer base region as a mask, the heavily doped polycrystalline germanium silicon outer base region layer and the base region-collector region isolation dielectric layer are etched sequentially.

[0180] Remove the photoresist pattern from the heavily doped polycrystalline germanium silicon outer base region;

[0181] Deposition of the outer wall medium layer;

[0182] Specifically, photoresist is spin-coated onto the heavily doped polycrystalline silicon emitter region and the heavily doped outer base region polycrystalline germanium-silicon layer, and then photolithography is performed on the photoresist to form a photoresist pattern for the heavily doped polycrystalline germanium-silicon outer base region. This photoresist pattern serves as a mask for etching the heavily doped outer base region polycrystalline germanium-silicon layer and the base-collector isolation dielectric layer.

[0183] Using the composite photoresist pattern as a mask, the heavily doped outer base region polycrystalline germanium-silicon layer and the base-collector isolation dielectric layer are etched sequentially to obtain the heavily doped polycrystalline germanium-silicon outer base region and the base-collector isolation dielectric layer of the germanium-silicon heterojunction bipolar transistor.

[0184] Remove the composite photoresist pattern to expose the heavily doped polycrystalline silicon emitter region and the heavily doped polycrystalline germanium silicon outer base region.

[0185] An outer wall dielectric layer is deposited on the field region dielectric layer, the heavily doped polycrystalline germanium-silicon outer base region, and the heavily doped polycrystalline silicon emitter region. The outer wall dielectric layer forms the first dielectric outer wall and the second dielectric outer wall. The outer wall dielectric layer can be an outer wall silicon oxide layer.

[0186] After rapid thermal annealing, which allows impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial base region to form a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region, the process further includes:

[0187] The outer wall dielectric layer is etched using anisotropic dry etching to form a first dielectric outer wall and a second dielectric outer wall.

[0188] Specifically, after rapid annealing to form a heavily doped single-crystal emitter region, anisotropic dry etching can be used to etch the outer wall dielectric layer, forming a first dielectric outer wall on the side of the heavily doped polycrystalline silicon emitter region, and a second dielectric outer wall on the side of the heavily doped polycrystalline germanium silicon outer base region and the base-collector region isolation dielectric layer.

[0189] Based on the above embodiments, further comprising, after forming the first medium outer wall and the second medium outer wall, the following:

[0190] An emitter electrode is formed on the upper side of the heavily doped polycrystalline silicon emitter region, and a base electrode is formed on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

[0191] Specifically, a low-resistance metal silicide layer is formed by self-aligning a silicide reaction between a refractory metal and exposed monocrystalline and polycrystalline silicon. An emitter silicide electrode, i.e., the emitter electrode, is formed on the emitter region of the heavily doped polycrystalline silicon, and a base silicide electrode, i.e., the base electrode, is formed on the outer base region of the heavily doped polycrystalline germanium silicon.

[0192] The following describes the manufacturing process of a dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as an example to illustrate the manufacturing method of the germanium-silicon heterojunction bipolar transistor provided in this embodiment of the invention.

[0193] The first step is to obtain the basic structure of an npn-type bipolar transistor. The basic structure of an npn-type bipolar transistor includes a p-type lightly doped silicon substrate 801, an n-type heavily doped silicon buried collector region 802, an n-type lightly doped silicon epitaxial collector region 804, and a field region silicon oxide layer 803. The n-type heavily doped silicon buried collector region 802 is formed on the upper side of the p-type lightly doped silicon substrate 801, and the field region silicon oxide layer 803 and the n-type lightly doped silicon epitaxial collector region 804 are formed on the upper side of the n-type heavily doped silicon buried collector region 802, as shown in Figure 8a.

[0194] The second step is to deposit a multilayer structure. On the silicon-based bipolar transistor base structure, a base-collector isolation silicon oxide layer 805, a p-type in-situ boron-doped polycrystalline germanium-silicon layer 806, an emitter-base isolation silicon oxide layer 807, and a silicon nitride layer 808 are deposited sequentially, as shown in Figure 8b. The p-type in-situ boron-doped polycrystalline germanium-silicon layer exhibits compressive strain, allowing it to expand and fill the gap between the heavily doped polycrystalline germanium-silicon layer and the germanium-silicon epitaxial inner base region during subsequent thermal processes, thus directly connecting the germanium-silicon carbon epitaxial inner base region and the p-type heavily doped polycrystalline germanium-silicon outer base region.

[0195] The third step is to perform photolithography on the collector area window. Photoresist is spin-coated onto the silicon nitride layer 808, and then photolithography is performed on the photoresist to form a photoresist pattern 809 for the collector area window, as shown in Figure 8c.

[0196] Step 4: Forming the collector region window. Using the collector region window photoresist pattern 809 as a mask, the silicon nitride layer 808, the emitter-base region isolation silicon oxide layer 807, and the p-type in-situ boron-doped outer base region polycrystalline germanium silicon layer 806 are sequentially etched away, exposing the underlying base-collector region isolation silicon oxide layer 805, forming the collector region window 810. Before removing the collector region window photoresist pattern 809 after etching, n-type ion implantation (SIC ion implantation) is performed across the exposed base-collector region isolation silicon oxide layer 805, thereby forming a selectively implanted collector region 811, i.e., the SIC region, in the portion of the n-type lightly doped silicon epitaxial collector region 804 directly opposite the collector region window 810. Then, the collector region window photoresist pattern 809 is removed. The resulting structure is shown in Figure 8d.

[0197] Step 5: Forming the silicon nitride inner sidewall. A silicon nitride layer is deposited at the edge of the collector window 810, and then the silicon nitride layer is etched using anisotropic dry etching to form a silicon nitride inner sidewall 812 at the edge of the collector window 810, as shown in Figure 8e. The thickness of the deposited silicon nitride layer is set according to actual needs, and is not limited in this embodiment of the invention.

[0198] Step 6: Remove part of the base-collector region isolation silicon oxide layer. Using the silicon nitride layer 808 and the silicon nitride inner sidewall 812 as a mask, first use anisotropic dry etching to remove the base-collector region isolation silicon oxide layer 805 of a preset thickness, and finally use wet etching to remove the remaining thickness of the base-collector region isolation silicon oxide layer 805, exposing the selectively implanted collector region 811. At the same time, the base-collector region isolation silicon oxide layer 805 of a preset width below the silicon nitride inner sidewall 812 will be etched laterally, as shown in Figure 8f.

[0199] Step 7: Forming the transition silicon epitaxial collector region. On the selectively implanted collector region 811, a transition silicon epitaxial collector region 813, selectively epitaxially doped with n-type impurities in situ, is grown, as shown in Figure 8g. The thickness of the transition silicon epitaxial collector region 813 is greater than or equal to the thickness of the base-collector region isolation silicon oxide layer 805. The thickness of the transition silicon epitaxial collector region 813 is set according to actual needs; this embodiment of the invention does not impose a limitation.

[0200] Step 8: Forming the germanium-silicon-carbon epitaxial inner base region. On the transition silicon epitaxial collector region 813, the germanium-silicon-carbon epitaxial inner base region 814 is selectively epitaxially grown by p-type in-situ boron-doped germanium-silicon-carbon, as shown in Figure 8h.

[0201] Step 9: Remove the silicon nitride inner sidewall. The silicon nitride layer 808 and the silicon nitride inner sidewall 812 are removed by wet etching. After removing the silicon nitride inner sidewall 812, there is a gap between the germanium-silicon-carbon epitaxial inner base region 814 and the p-type in-situ boron-doped outer base region polycrystalline germanium-silicon layer 806, as shown in Figure 8i.

[0202] Step 10: Filling the gaps. Using a thermal process, while maintaining the stability of the germanium-silicon-carbon epitaxial inner base region 814, the p-type in-situ boron-doped polycrystalline germanium-silicon layer 806 with compressive strain undergoes reflow, fully releasing and relaxing the compressive strain. This causes the volume of the p-type in-situ boron-doped polycrystalline germanium-silicon layer 806 to expand, completely filling the gaps left by the etching away of the silicon nitride inner sidewall 812, as shown in Figure 8j.

[0203] Step 11: Forming the inner sidewall of the heavily doped polycrystalline silicon emitter region. A silicon oxide layer 815 is deposited, and then the inner sidewall 816 of the n-type heavily doped polycrystalline silicon emitter region is formed by first depositing an n-type in-situ heavily doped emitter region inner sidewall polycrystalline silicon layer, and then anisotropic dry etching, as shown in Figure 8k. The thickness of the silicon oxide layer 815 is set according to actual needs, and is not limited in this embodiment of the invention.

[0204] Step 12: Forming a heavily doped emitter polysilicon layer. Using the inner sidewall 816 of the n-type heavily doped polysilicon emitter region as a mask, wet etching is used to remove the exposed silicon oxide layer 815, forming a stepped silicon oxide isolation layer 817. Then, an in-situ heavily doped n-type emitter polysilicon layer is deposited, merging with the inner sidewall 816 to form an n-type heavily doped emitter polysilicon layer 818, as shown in Figure 81.

[0205] Step 13: Forming the heavily doped polysilicon emitter region. Photoresist is spin-coated onto the heavily doped emitter region polysilicon layer 818, and then photolithography is performed on the photoresist to form a polysilicon emitter region photoresist pattern. Using the polysilicon emitter region photoresist pattern as a mask, the exposed n-type heavily doped emitter region polysilicon layer and the underlying emitter-base region isolation silicon oxide layer are etched away sequentially to form the n-type heavily doped polysilicon emitter region 819 and the emitter-base region isolation silicon oxide layer 820. Then, the polysilicon emitter region photoresist pattern is removed, as shown in Figure 8m.

[0206] Step 14: Forming the heavily doped polycrystalline germanium-silicon outer base region. Photolithography is performed on the heavily doped polycrystalline germanium-silicon outer base region to form a photoresist pattern. Using this photoresist pattern as a mask, the exposed heavily doped polycrystalline germanium-silicon layer 806 and the underlying base-collector isolation silicon oxide layer 805 are sequentially etched away to form the p-type heavily doped polycrystalline germanium-silicon outer base region 821 and the base-collector isolation silicon oxide layer 822. Then, the photoresist pattern is removed, as shown in Figure 8n.

[0207] Step 15: Perform rapid thermal annealing. Deposit the outer wall silicon oxide layer 823. Then perform rapid thermal annealing, which on the one hand allows the impurities in the n-type heavily doped polycrystalline silicon emitter region 819 to diffuse into the germanium silicon carbon epitaxial inner base region 814 to form the n-type heavily doped single crystal emitter region 824, and on the other hand achieves impurity activation, as shown in Figure 8o.

[0208] Step 16: Forming silicon oxide outer walls. The outer wall silicon oxide layer 823 is etched anisotropically to form a first silicon oxide outer wall 825 on the side of the n-type heavily doped polycrystalline silicon emitter region 819, and a second silicon oxide outer wall 826 on the side of the p-type heavily doped polycrystalline germanium silicon outer base region 821 and the base-collector isolation silicon oxide layer 822, as shown in Figure 8p.

[0209] Step 17: Forming the emitter silicide electrode and the base silicide electrode. A low-resistance metal silicide layer is formed by self-aligning a silicide reaction between a refractory metal and the exposed monocrystalline and polycrystalline silicon. An emitter silicide electrode 827 is formed on the n-type heavily doped polycrystalline silicon emitter region 819, and a base silicide electrode 828 is formed on the p-type heavily doped polycrystalline germanium silicon outer base region 821, as shown in Figure 8q.

[0210] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0211] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0212] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0213] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0214] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0215] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A germanium-silicon heterojunction bipolar transistor, characterized in that, include: A basic structure for a silicon-based bipolar transistor (BPT) includes a substrate, a heavily doped silicon buried layer collector region formed on the substrate, a field region dielectric layer formed on the heavily doped silicon buried layer collector region, and a lightly doped silicon epitaxial collector region. The conductivity types of the heavily doped silicon buried layer collector region and the lightly doped silicon epitaxial collector region are opposite to those of the substrate. A selectively implanted collector region is formed within the lightly doped silicon epitaxial collector region. A base-collector isolation dielectric layer is formed on the field region dielectric layer and the lightly doped silicon epitaxial collector region. A transition silicon epitaxial collector region is formed on the selectively implanted collector region. The conductivity type of the transition silicon epitaxial collector region is the same as that of the lightly doped silicon epitaxial collector region. A heavily doped polycrystalline germanium silicon outer base region is formed on the base region. - Above the collector region isolation dielectric layer; wherein, the conductivity type of the heavily doped polycrystalline germanium-silicon outer base region is opposite to the conductivity type of the heavily doped silicon buried layer collector region; a germanium-silicon epitaxial inner base region is formed above the transition silicon epitaxial collector region; a heavily doped single crystal emitter region is formed within the germanium-silicon epitaxial inner base region; an emitter-base region isolation dielectric layer is formed above the polycrystalline germanium-silicon outer base region; a stepped silicon oxide isolation layer is formed above the germanium-silicon epitaxial inner base region, above and inside the heavily doped polycrystalline germanium-silicon outer base region, and inside the emitter-base region isolation dielectric layer; a heavily doped polycrystalline silicon emitter region is formed above the emitter-base region isolation dielectric layer, the stepped silicon oxide isolation layer, and the heavily doped single crystal emitter region; wherein, the conductivity type of the polycrystalline silicon emitter region is the same as the conductivity type of the heavily doped silicon buried layer collector region.

2. The germanium-silicon heterojunction bipolar transistor according to claim 1, characterized in that, Also includes: The first dielectric outer wall is formed on the outside of the heavily doped polycrystalline silicon emitter region; the second dielectric outer wall is formed on the outside of the heavily doped polycrystalline germanium silicon outer base region and the base-collector isolation dielectric layer.

3. The germanium-silicon heterojunction bipolar transistor according to claim 1, characterized in that, Also includes: An emitter electrode is formed on the upper side of the heavily doped polycrystalline silicon emitter region; The base electrode is formed on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

4. A method for manufacturing a germanium-silicon heterojunction bipolar transistor, characterized in that, include: A silicon-based bipolar transistor (BPT) basic structure is provided, comprising a substrate, a heavily doped silicon buried layer collector region formed on the substrate, a field region dielectric layer formed on the upper side of the heavily doped silicon buried layer collector region, and a lightly doped silicon epitaxial collector region; wherein the conductivity types of the heavily doped silicon buried layer collector region and the lightly doped silicon epitaxial collector region are opposite to those of the substrate; a base-collector region isolation dielectric layer, a heavily doped outer base region polycrystalline germanium silicon layer with compressive strain, an emitter-base region isolation dielectric layer, and a silicon nitride layer are sequentially deposited on the BPT basic structure; wherein the conductivity type of the heavily doped outer base region polycrystalline germanium silicon layer is opposite to that of the heavily doped silicon buried layer collector region; a collector region window is formed along the thickness direction of the silicon nitride layer, the emitter-base region isolation dielectric layer, and the heavily doped outer base region polycrystalline germanium silicon layer, exposing a portion of the base-collector region isolation dielectric layer; and the lightly doped silicon collector region is separated from the lightly doped silicon collector region by the exposed base-collector region isolation dielectric layer. Ion implantation is performed on the epitaxial collector region to form a selectively implanted collector region; a transition silicon epitaxial collector region and a germanium-silicon epitaxial inner base region are sequentially formed within the collector region window; a gap exists between the germanium-silicon epitaxial inner base region and the heavily doped outer base region polycrystalline germanium-silicon layer; the heavily doped outer base region polycrystalline germanium-silicon layer is reflowed based on a thermal process, and the compressive strain is released and relaxed to fill the gap between the heavily doped outer base region polycrystalline germanium-silicon layer and the germanium-silicon epitaxial inner base region; a stepped silicon oxide isolation layer is formed inside the emitter-base region isolation dielectric layer, at the exposed portion of the germanium-silicon epitaxial inner base region in the collector region window, and on the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer; a heavily doped polycrystalline silicon emitter region with the same conductivity type as the heavily doped silicon buried layer collector region is deposited; rapid thermal annealing is performed, allowing impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial inner base region to form a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region.

5. The method according to claim 4, characterized in that, The step of forming a collector window along the thickness direction of the silicon nitride layer, the emitter-base isolation dielectric layer, and the heavily doped outer base polycrystalline germanium silicon layer to expose part of the base-collector isolation dielectric layer includes: forming a collector window photoresist pattern on the photoresist on the silicon nitride layer using a photolithography process; sequentially etching away the silicon nitride layer, the emitter-base isolation dielectric layer, and the heavily doped outer base polycrystalline germanium silicon layer using the collector window photoresist pattern as a mask to expose the base-collector isolation dielectric layer; and removing the collector window photoresist pattern to form the collector window.

6. The method according to claim 4, characterized in that, The step of sequentially forming a transition silicon epitaxial collector region and a germanium-silicon epitaxial inner base region within the collector region window includes: forming a silicon nitride inner sidewall at the inner edge of the collector region window above the base-collector region isolation dielectric layer; removing the base-collector region isolation dielectric layer below the collector region window to expose the selectively implanted collector region, and laterally removing a base-collector region isolation dielectric layer of a predetermined width below the silicon nitride inner sidewall; forming a transition silicon epitaxial collector region above the selectively implanted collector region, wherein the thickness of the transition silicon epitaxial collector region is greater than or equal to the thickness of the base-collector region isolation dielectric layer; forming a germanium-silicon epitaxial inner base region above the transition silicon epitaxial collector region, and removing the silicon nitride layer and the silicon nitride inner sidewall.

7. The method according to claim 4, characterized in that, The formation of a stepped silicon oxide isolation layer on the inner side of the emitter-base isolation dielectric layer, the exposed portion of the germanium-silicon epitaxial inner base region at the collector region window, and the upper side of the heavily doped outer base region polycrystalline germanium-silicon layer includes: depositing a silicon oxide layer on the upper side of the emitter-base isolation dielectric layer, the germanium-silicon epitaxial inner base region, and the heavily doped outer base region polycrystalline germanium-silicon layer, and forming a recessed region on the upper side of the germanium-silicon epitaxial inner base region; depositing a heavily doped emitter inner sidewall polycrystalline silicon layer; wherein the conductivity type of the heavily doped emitter inner sidewall polycrystalline silicon layer is opposite to that of the substrate; performing anisotropic dry etching on the heavily doped emitter inner sidewall polycrystalline silicon layer to form a heavily doped polycrystalline silicon emitter inner sidewall; and using the heavily doped polycrystalline silicon emitter inner sidewall as a mask to wet etch away the exposed silicon oxide layer to form a stepped silicon oxide isolation layer.

8. The method according to claim 7, characterized in that, The deposition of a heavily doped polysilicon emitter region with the same conductivity type as the collector region of the heavily doped silicon buried layer includes: depositing a heavily doped emitter polysilicon layer and merging it with the inner sidewall of the heavily doped polysilicon emitter region to form a heavily doped emitter polysilicon layer; forming a polysilicon emitter region photoresist pattern on the photoresist on the heavily doped emitter polysilicon layer using a photolithography process; sequentially etching the heavily doped emitter polysilicon layer and the emitter-base isolation dielectric layer using the polysilicon emitter region photoresist pattern as a mask; and removing the polysilicon emitter region photoresist pattern.

9. The method according to claim 8, characterized in that, After removing the photoresist pattern of the polycrystalline silicon emitter region and before performing rapid thermal annealing, the process further includes: performing photolithography on the heavily doped polycrystalline germanium-silicon outer base region to form a heavily doped polycrystalline germanium-silicon outer base region photoresist pattern; sequentially etching the heavily doped polycrystalline germanium-silicon outer base region layer and the base-collector region isolation dielectric layer using the heavily doped polycrystalline germanium-silicon outer base region photoresist pattern as a mask; removing the heavily doped polycrystalline germanium-silicon outer base region photoresist pattern; depositing an outer wall dielectric layer; and after performing rapid thermal annealing to allow impurities in the heavily doped polycrystalline silicon emitter region to diffuse into the germanium-silicon epitaxial inner base region to form a heavily doped single-crystal emitter region with the same conductivity type as the heavily doped polycrystalline silicon emitter region, the process further includes: anisotropic dry etching of the outer wall dielectric layer to form a first dielectric outer wall and a second dielectric outer wall.

10. The method according to claim 9, characterized in that, After forming the first dielectric outer wall and the second dielectric outer wall, the method further includes: forming an emitter electrode on the upper side of the heavily doped polycrystalline silicon emitter region and forming a base electrode on the upper side of the heavily doped polycrystalline germanium silicon outer base region.

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