Fin field effect transistor and manufacturing method thereof

Abstract

A fin field effect transistor structure includes a semiconductor substrate, a fin structure protruding from the semiconductor substrate, a gate crossing the fin structure, a source region and a drain region respectively disposed on the fin structure on both sides of the gate, and a gate electrode disposed on the fin structure on both sides of the gate. The source electrode region comprises a first epitaxial layer and a third epitaxial layer which are respectively embedded in the fin-shaped structure, a first non-epitaxial region is defined as the fin-shaped structure between the first epitaxial layer and the third epitaxial layer, and the drain electrode region comprises a second epitaxial layer and a fourth epitaxial layer which are respectively embedded in the fin-shaped structure. A second non-epitaxial region is defined as a fin structure between the second epitaxial layer and the fourth epitaxial layer, a first contact plug is disposed on the third epitaxial layer, and a second contact plug is disposed on the fourth epitaxial layer.

Description

Technical Field

[0001] This invention relates to a fin field-effect transistor, and more particularly to a fin field-effect transistor having multiple epitaxial layers in the source and drain regions. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication process of semiconductor devices typically involves sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements on this semiconductor substrate. Many circuits are typically fabricated on a single semiconductor wafer, and the individual chips are separated by dicing along dicing lines between the integrated circuits. These individual chips are typically packaged separately in multi-chip modules or other types of packages.

[0003] As the feature size of transistor devices continues to shrink to achieve higher circuit density and higher performance, FinFETs are widely used in integrated circuits. FinFET devices have a three-dimensional structure that can improve circuit control, reduce leakage current, and shorten the gate length of transistors.

[0004] However, in terms of manufacturing process, fin field-effect transistors still encounter the problem of incomplete formation of material layers at the drain and source. Summary of the Invention

[0005] In view of this, the present invention provides a method of forming multiple epitaxial layers in the source region and the drain region respectively, so as to solve the problem that it is impossible to fill the epitaxial layer in a large area of ​​groove.

[0006] According to a preferred embodiment of the present invention, a fin field-effect transistor structure includes a semiconductor substrate, a fin structure protruding from the semiconductor substrate, a gate spanning the fin structure, a source region disposed on the fin structure on one side of the gate, wherein the source region includes a first epitaxial layer buried in the fin structure, a third epitaxial layer buried in the fin structure, and the third epitaxial layer and the first epitaxial layer are not connected, a first non-epitaxy region defined as the fin structure between the first epitaxial layer and the third epitaxial layer, a drain region disposed on the fin structure on the other side of the gate, wherein the drain region includes a second epitaxial layer buried in the fin structure, a fourth epitaxial layer buried in the fin structure, and the second epitaxial layer and the fourth epitaxial layer are not connected, a second non-epitaxy region defined as the fin structure between the second epitaxial layer and the fourth epitaxial layer, a first contact plug disposed on the third epitaxial layer and a second contact plug disposed on the fourth epitaxial layer.

[0007] According to another preferred embodiment of the present invention, a method for fabricating a fin field-effect transistor structure includes forming a fin field-effect transistor structure, wherein the fin field-effect transistor structure includes a semiconductor substrate, a fin-shaped structure protruding from the semiconductor substrate, a gate spanning the fin-shaped structure, a source region disposed on the fin-shaped structure on one side of the gate, wherein the source region includes a first epitaxial layer buried in the fin-shaped structure, a third epitaxial layer buried in the fin-shaped structure, and the third epitaxial layer and the first epitaxial layer are not connected, a first non-epitaxy region defined as the fin-shaped structure between the first epitaxial layer and the third epitaxial layer, a drain region disposed on the fin-shaped structure on the other side of the gate, wherein the drain region includes a second epitaxial layer buried in the fin-shaped structure, a fourth epitaxial layer buried in the fin-shaped structure, and the second epitaxial layer and the fourth epitaxial layer are not connected, a second non-epitaxy region defined as the fin-shaped structure between the second epitaxial layer and the fourth epitaxial layer, a first contact plug disposed on the third epitaxial layer and a second contact plug disposed on the fourth epitaxial layer.

[0008] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0009] Figure 1 A top view of a finned field-effect transistor according to a first preferred embodiment of the present invention;

[0010] Figure 2 for Figure 1 The side view drawn along the tangent AA;

[0011] Figure 3 A schematic diagram of a finned field-effect transistor according to a second preferred embodiment of the present invention;

[0012] Figure 4 A schematic diagram of a finned field-effect transistor according to a third preferred embodiment of the present invention;

[0013] Figure 5 A schematic diagram of a finned field-effect transistor according to a fourth preferred embodiment of the present invention;

[0014] Figure 6 A schematic diagram of a finned field-effect transistor according to a fifth preferred embodiment of the present invention;

[0015] Figure 7 A schematic diagram of a finned field-effect transistor according to a sixth preferred embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of a method for fabricating a finned field-effect transistor according to a first preferred embodiment;

[0017] Figure 9 This is a schematic diagram of a finned field-effect transistor as an example of the present invention.

[0018] Symbol Explanation

[0019] 10: Semiconductor substrate

[0020] 12: Fin-like structure

[0021] 14a: First doped well

[0022] 14b: Second doped well

[0023] 16: Epitaxial layer

[0024] 16a: First epitaxial layer

[0025] 16b: Second epitaxial layer

[0026] 16c: Third epitaxial layer

[0027] 16d: Fourth epitaxial layer

[0028] 16e: Fifth epitaxial layer

[0029] 16f: Sixth epitaxial layer

[0030] 18a: First non-extensional region

[0031] 18b: Second non-extensional region

[0032] 18c: Third non-extensional region

[0033] 18d: Fourth non-extensional region

[0034] 20a: First contact plug

[0035] 20b: Second contact plug

[0036] 20c: First dummy contact plug

[0037] 20d: Second dummy contact plug

[0038] 22a: First metal silicide

[0039] 22b: Second metal silicide

[0040] 22c: Third metal silicide

[0041] 22d: Fourth metal silicide

[0042] 24a: Source doped region

[0043] 24b: Drain doped region

[0044] 26a: Single diffusion blocking

[0045] 26b: Single diffusion blocking

[0046] 28: Groove

[0047] 30: Dielectric layer

[0048] 32a: First contact hole

[0049] 32b: Second contact hole

[0050] 100: Fin Field-Effect Transistor

[0051] 200: Fin Field-Effect Transistor

[0052] 300: Fin Field-Effect Transistor

[0053] 400: Fin Field-Effect Transistor

[0054] 500: Fin Field-Effect Transistor

[0055] 600: Fin Field-Effect Transistor

[0056] 700: Fin Field-Effect Transistor

[0057] D: Drain region

[0058] DG1: First Dummy Gate

[0059] DG2: Second Dummy Gate

[0060] L1: First distance

[0061] L2: Second distance

[0062] G: Gate

[0063] S: Source region

[0064] SP: Spacer wall

[0065] X: Horizontal direction

[0066] Y: Vertical direction Detailed Implementation

[0067] Figure 1 A top view of a fin field-effect transistor according to a first preferred embodiment of the present invention. Figure 2 for Figure 1 The side view drawn along the tangent AA.

[0068] like Figure 1 and Figure 2As shown, a fin field-effect transistor 100 includes a semiconductor substrate 10, which may be a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon-germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-coated insulating substrate. In this invention, the semiconductor substrate 10 is preferably a silicon substrate. A fin structure 12 protrudes from the semiconductor substrate 10, a gate G spans the fin structure 12, spacers SP are provided on both sides of the gate G, a source region S is disposed on one side of the fin structure 12 of the gate G, and a drain region D is disposed on the other side of the fin structure 12 of the gate G. The source region S includes a first doped well 14a, a first epitaxial layer 16a, a first non-epitaxy region 18a, and a third epitaxial layer 16c. The first epitaxial layer 16a and the third epitaxial layer 16c are both buried in the fin structure 12. The third epitaxial layer 16c and the first epitaxial layer 16a are not connected. The first non-epitaxy region 18a is defined as the fin structure 12 between the first epitaxial layer 16a and the third epitaxial layer 16c. The first doped well 14a is located in the first non-epitaxy region 18a and below the first epitaxial layer 16a and the third epitaxial layer 16c.

[0069] The drain region D includes a second doped well 14b, a second epitaxial layer 16b, a second non-epitaxy region 18b, and a fourth epitaxial layer 16d. The second epitaxial layer 16b and the fourth epitaxial layer 16d are buried in the fin structure 12 and are not connected. The second non-epitaxy region 18b is defined as the fin structure 12 between the second epitaxial layer 16b and the fourth epitaxial layer 16d. The second doped well 14b is located in the second non-epitaxy region 18b and below the second epitaxial layer 16b and the fourth epitaxial layer 16d.

[0070] A vertical direction Y is perpendicular to the upper surface of the fin structure 12. Along the vertical direction Y, the edge of the first epitaxial layer 16a overlaps with the spacer wall SP, and the edge of the second epitaxial layer 16b overlaps with the spacer wall SP. That is to say, the first epitaxial layer 16a and the second epitaxial layer 16b are adjacent to the gate G. There is no non-epitaxy region between the first epitaxial layer 16a and the gate G, and there is no non-epitaxy region between the second epitaxial layer 16b and the gate G.

[0071] Furthermore, a first contact plug 20a is disposed on the third epitaxial layer 16c, a second contact plug 20b is disposed on the fourth epitaxial layer 16d, a first metal silicide 22a is disposed only between the first contact plug 20a and the third epitaxial layer 16c, and a second metal silicide 22b is disposed only between the second contact plug 20b and the fourth epitaxial layer 16d. There are no metal silicides on the first epitaxial layer 16a, the second epitaxial layer 16b, the first non-epitaxy region 18a, and the second non-epitaxy region 18b. There are also no metal silicides on the third epitaxial layer 16c, which is not covered by the first contact plug 20a, and on the fourth epitaxial layer 16d, which is not covered by the second contact plug 20b. According to a preferred embodiment of the present invention, along the horizontal direction X, the length of the fourth epitaxial layer 16d is greater than that of the second epitaxial layer 16b, and the length of the third epitaxial layer 16c is greater than that of the first epitaxial layer 16a. Therefore, by disposing the second contact plug 20b on the fourth epitaxial layer 16d and the first contact plug 20a on the third epitaxial layer 16c, a greater process window can be provided for the manufacturing process of the contact plug.

[0072] A first dummy gate DG1 is disposed at one end of the fin structure 12 and adjacent to the source region S, and a second dummy gate DG2 is disposed at the other end of the fin structure 12 and adjacent to the drain region S. The first dummy gate DG1 and the second dummy gate DG2 do not have the function of controlling the switching of the transistor, but are only set up to balance the load effect in the manufacturing process.

[0073] In a first preferred embodiment, a first distance L1 is provided between the edge of the gate G and the edge of the source region S, and a second distance L2 is provided between the edge of the gate G and the edge of the drain region D. The second distance L2 is equal to the first distance L1, meaning that the source region S and the drain region D have the same length along the horizontal direction X. Furthermore, depending on whether the fin field-effect transistor 100 is a P-type transistor or an N-type transistor, the doped wells and epitaxial layers will have different conductivity types. For example, when the fin field-effect transistor 100 is a P-type transistor, a first epitaxial layer 16a, a second epitaxial layer 16b, a third epitaxial layer 16c, and a fourth epitaxial layer 16d are preferably silicon-germanium (SiGe) epitaxy, in which P-type dopants can be selectively doped. Simultaneously, the first doped well 14a and the second doped well 14b are preferably N-type in conductivity. On the other hand, when the fin field-effect transistor 100 is an N-type transistor, the first epitaxial layer 16a, the second epitaxial layer 16b, the third epitaxial layer 16c, and the fourth epitaxial layer 16d are preferably silicon phosphide (SiP) epitaxy or silicon carbide (SiC) epitaxy. N-type dopants can be selectively doped into the silicon phosphide and silicon carbide epitaxy. Meanwhile, the first doped well 14a and the second doped well 14b are preferably P-type in terms of conductivity. Furthermore, as can be seen from the above-described component configuration, the fin field-effect transistor 100 has a symmetrical structure.

[0074] When the material of the fin structure 12 is silicon, the larger the area of ​​the first non-epitaxial region 18a and the second non-epitaxial region 18b, that is, the smaller the area of ​​the first epitaxial layer 16a, the second epitaxial layer 16b, the third epitaxial layer 16c and the fourth epitaxial layer 16d, the higher the resistance of the source region S and the drain region D. Thus, the on-resistance of the fin field-effect transistor 100 can be controlled by adjusting the area of ​​the first non-epitaxial region 18a and the second non-epitaxial region 18c.

[0075] Figure 3 The fin field-effect transistor illustrated according to the second preferred embodiment of the present invention uses the same component designations as in the first preferred embodiment for components having the same function and location. The fin field-effect transistor 200 has a symmetrical structure. The difference between the second preferred embodiment and the first preferred embodiment is that the second preferred embodiment further includes a source-doped region 24a and a drain-doped region 24b. The source-doped region 24a is disposed in the first epitaxial layer 16a, the third epitaxial layer 16c, and the first non-epitaxy region 18a. The drain-doped region 24b is disposed in the second epitaxial layer 16b, the fourth epitaxial layer 16d, and the second non-epitaxy region 18b. When the fin field-effect transistor 200 is an N-type transistor, the conduction type of the source-doped region 24a and the drain-doped region 24b is N-type; when the fin field-effect transistor 200 is a P-type transistor, the conduction type of the source-doped region 24a and the drain-doped region 24b is P-type. All other components are the same as in the first preferred embodiment and will not be described again here.

[0076] Figure 4 The fin field-effect transistor illustrated according to the third preferred embodiment of the present invention uses the same component designations as the second preferred embodiment for elements having the same function and location. The fin field-effect transistor 300 has a symmetrical structure. The difference between the third preferred embodiment and the second preferred embodiment is that the third preferred embodiment further includes a first dummy contact plug 20c and a second dummy contact plug 20d. The first dummy contact plug 20c is disposed on the first non-epitaxy region 18a, the second dummy contact plug 20d is disposed on the second non-epitaxy region 18b, a third metal silicide 22c is disposed between the first dummy contact plug 20c and the first non-epitaxy region 18a, and a fourth metal silicide 22d is disposed between the second dummy contact plug 20d and the second non-epitaxy region 18b. The first dummy contact plug 20c and the second dummy contact plug 20d are not connected to other wires and therefore do not have the function of conducting signals. The first dummy contact plug 20c and the second dummy contact plug 20d are set up to balance the load effect in the manufacturing process. Other components are the same as in the first preferred embodiment and will not be described again here.

[0077] Figure 5The fin field-effect transistor illustrated according to the fourth preferred embodiment of the present invention uses the same component designations as the second preferred embodiment for elements having the same function and location. The fin field-effect transistor 400 has a symmetrical structure. The fourth preferred embodiment differs from the second preferred embodiment in that the fourth preferred embodiment does not have a first dummy gate DG1 and a second dummy gate DG2. Furthermore, in the fourth preferred embodiment, single diffusion breakers 26a / 26b are additionally provided in the source region S and drain region D to define the range of the source region S and drain region D. All other components are the same as in the second preferred embodiment and will not be described again here.

[0078] Figure 6 The fin field-effect transistor 500 is illustrated according to a fifth preferred embodiment of the present invention, wherein elements having the same function and location will use the same element designations as in the second preferred embodiment. The fin field-effect transistor 500 has an asymmetric structure. The fifth preferred embodiment differs from the second preferred embodiment in that the first distance L1 from the edge of the gate G to the source region S and the second distance L2 from the edge of the gate G to the drain region D are different; the second distance L2 is greater than the first distance L1. That is, along the horizontal direction X, the length of the drain region D is greater than the length of the source region S. Because the drain region D is longer, it can accommodate more epitaxial layers and can be used as a high-voltage signal input terminal. Therefore, the epitaxial layers in the source region S and the epitaxial layers in the drain region D... The number of epitaxial layers can vary. For example, in the fifth preferred embodiment, the drain region D has three unconnected epitaxial layers: the second epitaxial layer 16b, the fourth epitaxial layer 16d, and the sixth epitaxial layer 16f. The source region S has only two epitaxial layers: the second epitaxial layer 16a and the fourth epitaxial layer 16c. The fin structure 12 between the second epitaxial layer 16b and the sixth epitaxial layer 16f is defined as the second non-epitaxylated region 18b, and the fin structure 12 between the sixth epitaxial layer 16f and the fourth epitaxial layer 16d is defined as the fourth non-epitaxylated region 18d. Other components are the same as in the second preferred embodiment and will not be described again here.

[0079] Figure 7The fin field-effect transistor illustrated in the sixth preferred embodiment of the present invention, wherein elements having the same function and position will use the same element designations as in the second preferred embodiment, the fin field-effect transistor 600 is a symmetrical structure, the sixth preferred embodiment differs from the second preferred embodiment in that: there are three unconnected epitaxial layers in the source region S and the drain region D, but along the horizontal direction X, the length of the drain region is still the same as the length of the source region, that is, the first distance L1 is equal to the second distance L2. In detail, the source region S contains a first epitaxial layer 16a, a third epitaxial layer 16c, and a fifth epitaxial layer 16e, and the drain region D contains a second epitaxial layer 16b, a fourth epitaxial layer 16d, and a sixth epitaxial layer 16f. The fin-like structure 12 between the second epitaxial layer 16b and the sixth epitaxial layer 16f is defined as the second non-epitaxy region 18b, the fin-like structure 12 between the sixth epitaxial layer 16f and the fourth epitaxial layer 16d is defined as the fourth non-epitaxy region 18d, the fin-like structure 12 between the first epitaxial layer 16a and the fifth epitaxial layer 16e is defined as the first non-epitaxy region 16a, and the fin-like structure 12 between the fifth epitaxial layer 16e and the third epitaxial layer 16c is defined as the third non-epitaxy region 16c. Other components are the same as in the second preferred embodiment and will not be described again here.

[0080] Figure 8 The illustration depicts a method for fabricating a finned field-effect transistor according to a first preferred embodiment, wherein components having the same function and location will use the same component designations as in the first preferred embodiment. For example... Figure 8 As shown, firstly, a semiconductor substrate 10 is provided, then the semiconductor substrate 10 is etched to define a fin structure 12 on the semiconductor substrate 10. Subsequently, a gate G, a first dummy gate DG1, and a second dummy gate DG2 are simultaneously formed across the fin structure 12. Then, an ion implantation process is performed to form a first doped well 14a and a second doped well 14b in the fin structure 12 on both sides of the gate G. Afterwards, the fin structure 12 is patterned to form several grooves 28 within the fin structure. Then, as... Figure 2 As shown, an epitaxial fabrication process is performed to form a first epitaxial layer 16a, a second epitaxial layer 16b, a third epitaxial layer 16c, and a fourth epitaxial layer 16d, which are then filled into the groove 28. Next, a dielectric layer 30 is formed to cover the fin-like structure 12. The dielectric layer 30 is then etched to form a first contact hole 32a and a second contact hole 32b, respectively exposing the third epitaxial layer 16c and the fourth epitaxial layer 16d. Then, a first metal silicide 22a and a second metal silicide 22b are formed on the exposed third epitaxial layer 16c and the fourth epitaxial layer 16d. Finally, a first contact plug 20a and a second contact plug 20b are formed. The first contact plug 20a is filled into the first contact hole 32a, and the second contact plug 20b is filled into the second contact hole 32b. This completes the fabrication process. Figure 2 The fin field-effect transistor 100 in the middle.

[0081] Furthermore, regarding the fabrication method of the source doped region 24a and drain doped region 24b in fin field-effect transistors 200, 300, 400, 500, and 600, the source doped region 24a and drain doped region 24b can be formed by ion implantation after the formation of the first epitaxial layer 16a, the second epitaxial layer 16b, the third epitaxial layer 16c, and the fourth epitaxial layer 16d, and selectively forming the fifth epitaxial layer 16e and the sixth epitaxial layer 16f, and before the formation of the dielectric layer 30. The first dummy contact plug 20c and the second dummy contact plug 20d in fin field-effect transistor 300 can be fabricated simultaneously with the first contact plug 20a and the second contact plug 20b using the same fabrication process. In the fin field-effect transistor 400, the single diffusion blocking 26a / 26b can be fabricated by etching the fin structure 12 after it is formed and filling it with insulating material before forming the gate G. The different numbers of epitaxial layers in the fin field-effect transistors 500 and 600 can be achieved by adjusting the number of grooves 28. Furthermore, the different first distance L1 and second distance L2 in the fin field-effect transistor 500 can be achieved by adjusting the position of the gate G.

[0082] Figure 9 The fin field-effect transistor illustrated in this exemplary embodiment of the invention, wherein elements having the same function and location, will use the same element designations as in the first preferred embodiment, such as... Figure 9 As shown, the fin field-effect transistor 700 has no non-epitaxy region, so the epitaxial layer 16 needs to fill the entire source region S and drain region D. As a result, the groove 28 that the epitaxial layer 16 needs to fill will have a large opening, so there will be a problem that the epitaxial layer 16 cannot fill the groove 28 completely.

[0083] The present invention forms multiple grooves in the source and drain regions, so that the opening of each groove is small, allowing the epitaxial layer to fill each groove. Furthermore, as mentioned above, the on-resistance of the fin field-effect transistor can be adjusted by the non-epitaxy region, and also by selectively forming source and drain doped regions. Therefore, the fin field-effect transistor of the present invention has an adjustable on-resistance, which is beneficial for its application in electrostatic discharge (ESD) protection devices.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A fin field-effect transistor structure, comprising: Semiconductor substrate; Fin-like structures protrude from the semiconductor substrate; The gate spans the fin-like structure; A source region is disposed on the fin-like structure on one side of the gate, wherein the source region includes: The first epitaxial layer is embedded in the fin-like structure; A third epitaxial layer is embedded in the fin-like structure, and the third epitaxial layer is not connected to the first epitaxial layer; The first non-epicentric region is defined as the fin-like structure between the first epitaxial layer and the third epitaxial layer; A drain region is disposed on the fin structure on the other side of the gate, wherein the drain region includes: The second epitaxial layer is embedded in the fin-like structure; The fourth epitaxial layer is embedded in the fin-like structure, and the second epitaxial layer and the fourth epitaxial layer are not connected; The second non-epicentric region is defined as the fin-like structure between the second epitaxial layer and the fourth epitaxial layer; The first contact plug is disposed on the third epitaxial layer; as well as The second contact plug is disposed on the fourth epitaxial layer.

2. The fin field-effect transistor structure as described in claim 1, further comprising: A first metal silicide is disposed only between the first contact plug and the third epitaxial layer; and The second metal silicide is disposed only between the second contact plug and the fourth epitaxial layer.

3. The fin field-effect transistor structure as claimed in claim 1, wherein there is no metal silicide on the first epitaxial layer, the second epitaxial layer, the first non-epitaxy region, and the second non-epitaxy region.

4. The fin field-effect transistor structure as described in claim 1, further comprising: A source-doped region is disposed in the first epitaxial layer, the third epitaxial layer, and the first non-epitaxy region; and A drain-doped region is disposed in the second epitaxial layer, the fourth epitaxial layer, and the second non-epitaxy region.

5. The fin field-effect transistor structure as claimed in claim 1, wherein there is a first distance from the edge of the gate to the source region, and a second distance from the edge of the gate to the drain region, the second distance being greater than the first distance.

6. The fin field-effect transistor structure as described in claim 1, further comprising: A fifth epitaxial layer is embedded in the fin-like structure of the source region and disposed between the first epitaxial layer and the third epitaxial layer; the first non-epitaxy region is disposed between the first epitaxial layer and the fifth epitaxial layer; and The sixth epitaxial layer is embedded in the fin structure of the drain region and disposed between the second epitaxial layer and the fourth epitaxial layer, and the second non-epitaxy region is disposed between the second epitaxial layer and the sixth epitaxial layer.

7. The fin field-effect transistor structure as described in claim 1, further comprising: A first dummy gate is disposed at the end of the fin structure; A second dummy gate is disposed at the other end of the fin structure.

8. The fin field-effect transistor structure as claimed in claim 1 further includes two spacer walls disposed on both sides of the gate, wherein the vertical direction is perpendicular to the upper surface of the fin structure, and along the vertical direction, the edge of the first epitaxial layer overlaps with one of the two spacer walls, and along the vertical direction, the edge of the second epitaxial layer overlaps with the other of the two spacer walls.

9. The fin field-effect transistor structure as described in claim 1, further comprising: M fifth epitaxial layers are embedded in the fin structure of the source region and disposed between the first epitaxial layer and the third epitaxial layer, wherein each of the M fifth epitaxial layers does not contact each other, M is an integer and M is greater than or equal to 0; N sixth epitaxial layers are embedded in the fin structure of the drain region and disposed between the second epitaxial layer and the fourth epitaxial layer, wherein each of the N sixth epitaxial layers does not contact each other, N is an integer and N is greater than or equal to 1; wherein M is not equal to N.

10. The fin field-effect transistor structure as described in claim 1, further comprising: A first dummy contact plug is disposed on the first non-extended region; and The second dummy contact plug is disposed on the second non-extended area.

11. A method for fabricating a fin field-effect transistor structure, comprising: Forming a fin field-effect transistor structure, comprising: Semiconductor substrate; Fin-like structures protrude from the semiconductor substrate; The gate spans across the fin-like structure; A source region is disposed on the fin-like structure on one side of the gate, wherein the source region includes: The first epitaxial layer is embedded in the fin-like structure; A third epitaxial layer is embedded in the fin-like structure, and the third epitaxial layer is not connected to the first epitaxial layer; The first non-epicentric region is defined as the fin-like structure between the first epitaxial layer and the third epitaxial layer; A drain region is disposed on the fin structure on the other side of the gate, wherein the drain region includes: The second epitaxial layer is embedded in the fin-like structure; The fourth epitaxial layer is embedded in the fin-like structure, and the second epitaxial layer and the fourth epitaxial layer are not connected; The second non-epicentric region is defined as the fin-like structure between the second epitaxial layer and the fourth epitaxial layer; The first contact plug is disposed on the third epitaxial layer; as well as The second contact plug is disposed on the fourth epitaxial layer.

12. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: The first metal silicide is formed only between the first contact plug and the third epitaxial layer; and The second metal silicide is formed only between the second contact plug and the fourth epitaxial layer.

13. The method for fabricating a fin field-effect transistor structure as described in claim 11, wherein there is no metal silicide on the first epitaxial layer, the second epitaxial layer, the first non-epitaxy region, and the second non-epitaxy region.

14. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: A source doped region is formed in the first epitaxial layer, the third epitaxial layer, and the first non-epitaxy region; and A drain-doped region is formed in the second epitaxial layer, the fourth epitaxial layer, and the second non-epitaxy region.

15. The method for fabricating a fin field-effect transistor structure as claimed in claim 11, wherein there is a first distance from the edge of the gate to the source region, and a second distance from the edge of the drain region of the gate, the second distance being greater than the first distance.

16. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: A fifth epitaxial layer is formed, embedded in the fin-like structure of the source region and disposed between the first and third epitaxial layers, and the first non-epitaxy region is disposed between the first and fifth epitaxial layers; and A sixth epitaxial layer is formed, embedded in the fin structure of the drain region and disposed between the second epitaxial layer and the fourth epitaxial layer, and the second non-epitaxy region is disposed between the second epitaxial layer and the sixth epitaxial layer.

17. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: A first dummy gate is formed and disposed at the end of the fin structure; and A second dummy gate is formed and disposed at the other end of the fin structure.

18. The method for fabricating a fin field-effect transistor structure as claimed in claim 11 further includes two spacer walls disposed on both sides of the gate, wherein the vertical direction is perpendicular to the upper surface of the fin structure, the edge of the first epitaxial layer and one of the two spacer walls overlap along the vertical direction, and the edge of the second epitaxial layer and the other of the two spacer walls overlap along the vertical direction.

19. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: M fifth epitaxial layers are formed, embedded in the fin structure of the source region and disposed between the first epitaxial layer and the third epitaxial layer, wherein each of the M fifth epitaxial layers does not contact each other, M is an integer and M is greater than or equal to 0; N sixth epitaxial layers are formed and embedded in the fin structure of the drain region and disposed between the second epitaxial layer and the fourth epitaxial layer, wherein each of the N sixth epitaxial layers does not contact each other, N is an integer and N is greater than or equal to 1; wherein M is not equal to N.

20. The method for fabricating a fin field-effect transistor structure as described in claim 11, further comprising: A first dummy contact plug is formed and disposed on the first non-extended region; and A second dummy contact plug is formed and disposed on the second non-extended region.

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