SiC MOSFET device with surrounding P + shielding layer and manufacturing method thereof
By introducing a surrounding P+ shielding layer into SiC MOSFET devices, the problems of large reverse transfer capacitance and poor switching performance of SiC MOSFET devices are solved, achieving higher short-circuit withstand capability and lower switching losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN UNIV OF TECH
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-01
AI Technical Summary
SiC MOSFET devices have a large reverse transfer capacitance Crss (=Cgd), resulting in poor switching performance and short-circuit withstand capability.
In SiC MOSFET devices, a surrounding P+ shielding layer is introduced. By wrapping the active region of the device with the surrounding P+ shielding layer, an electrical connection is formed. A silicon carbide P-type trench gate shielding layer is set at the bottom of the gate trench to reduce the gate-drain coupling capacitance and improve the shielding capability of the gate oxide layer.
It reduces the forward saturation current of the device, improves short-circuit capability and switching performance, reduces switching losses, and enhances the on-resistance and reliability of the device.
Smart Images
Figure CN121968639A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics and solid-state electronics, and relates to a SiC MOSFET device with a surrounding P+ shielding layer. This invention also relates to a method for fabricating a SiC MOSFET device with a surrounding P+ shielding layer. Background Technology
[0002] Due to the excellent material properties of SiC, SiC-based power devices are now widely used in automotive electronics, high-speed rail, industrial electromechanical systems, data centers, and other industries. With the booming development of markets such as new energy electric vehicles and photovoltaic inverters, the market demand for SiC-based power devices is rapidly increasing. Currently, commercially successful SiC power semiconductor devices mainly include SiC SBDs and SiC MOSFETs. Among them, SiC MOSFETs, as an important switching device in SiC power devices, have lower losses and lower heat dissipation requirements at the same power compared to Si MOSFETs and SiIGBTs. They also have significant advantages in performance indicators such as current density, operating frequency, reliability, and leakage current, and have great development potential.
[0003] SiC MOSFETs can be classified into planar gate and trench gate types based on their gate structure. Planar gate structures offer simple fabrication, high cell repeatability, and high device reliability. However, they suffer from a significant JFET effect, where the on-current is confined to the JFET region between the two P-type base regions, resulting in a high on-state resistance. Compared to planar gate structures, trench gate structures eliminate the JFET region, increasing channel electron density, reducing resistivity, and improving on-state performance. However, in the blocking state, due to the curvature effect of the electric field corners, a large number of electric field lines accumulate in the oxide layer at the bottom of the gate, leading to poor gate oxide reliability. Another drawback of trench MOSFETs is their large reverse transfer capacitance Crss (=Cgd), which degrades switching performance. Therefore, improving the gate oxide reliability and dynamic characteristics of trench-gate SiC MOSFETs has become a research goal for many researchers. Summary of the Invention
[0004] The purpose of this invention is to provide a SiC MOSFET device with a surrounding P+ shielding layer, which solves the problems of large reverse transfer capacitance Crss (=Cgd) and poor switching performance and short-circuit withstand capability of existing SiC MOSFET devices.
[0005] Another object of the present invention is to provide a method for fabricating a SiC MOSFET device having a surrounding P+ shielding layer. The first technical solution adopted in this invention is a SiC MOSFET device with a surrounding P+ shielding layer, comprising, from bottom to top, a silicon carbide N-type substrate, a silicon carbide N-type epitaxial layer, a silicon carbide N-type current spreading layer, a silicon carbide P-type body region, and a surface N+ region. The silicon carbide N-type current spreading layer, the silicon carbide P-type body region, and the surface N+ region are surrounded by a hollow silicon carbide P-type surrounding P+ region. A gate trench is formed at the center of the structure formed by the silicon carbide N-type current spreading layer, the silicon carbide P-type body region, and the surface N+ region. A silicon carbide P-type trench gate shielding layer is provided at the bottom of the gate trench. The gate trench is filled with trench gate N-type polysilicon.
[0006] The first technical solution of this invention is further characterized by: The silicon carbide P-type surrounding P+ region is connected to the silicon carbide P-type slot grid shielding layer to form an electrical connection.
[0007] The surface of the silicon carbide P-type surrounding P+ region and the surface N+ region together form the source of the device.
[0008] The silicon carbide N-type current extension layer is located within the JFET region, which consists of the silicon carbide P-body region, the silicon carbide P-type surrounding P+ region, and the gate trench.
[0009] The surface inside the gate trench is provided with a trench gate oxide layer.
[0010] The second technical solution of the present invention is further characterized by: The fabrication method of a SiC MOSFET device with a surrounding P+ shielding layer specifically includes the following steps: Step 1: Form a silicon carbide N-type epitaxial layer on the upper surface of a silicon carbide N-type substrate; Step 2: A silicon carbide N-type current spreading layer is formed above the silicon carbide N-type epitaxial layer, and a silicon carbide P-body region is formed above the silicon carbide N-type current spreading layer. Step 3: Form a surface N+ region on the upper surface of the silicon carbide P-body region; Step 4: Etch the gate trench, form a silicon carbide P-type trench gate shielding layer at the bottom of the gate trench, and deposit a trench gate oxide layer on the inner wall of the gate trench to form a trench gate N-type polysilicon.
[0011] The second technical solution of the present invention is further characterized by: In step 1, the doping concentration of the silicon carbide N-type epitaxial layer is 4*10⁻⁶. 15 cm -3 ~7*10 15 cm -3 .
[0012] In step 2, the doping concentration of the silicon carbide N-type current spreading layer is 1*10. 16 cm -3 ~3*10 16cm -3 .
[0013] The beneficial effects of this invention are as follows: The invention utilizes a surrounding P+ shielding layer to enclose the active region of the device. This structure reduces the saturation current output by the device in the forward operating state, thereby improving the device's short-circuit capability. Furthermore, since the injection depth of the surrounding P+ shielding layer enclosing the active region is equal to or greater than that of the trench gate shielding layer located at the bottom of the trench gate, the trench gate shielding layer is connected to the surrounding P+ shielding layer, achieving electrical continuity. This structural feature further reduces the device's forward saturation current. Simultaneously, faster pinch-off in the blocking state further reduces leakage current. Because the trench gate shielding layer is connected to the source through the surrounding P+ shielding layer, it has a better ability to shield the electric field, thereby further protecting the gate oxide layer. At the same time, it reduces the coupling capacitance between the gate and drain, thereby reducing the device's switching losses and improving its switching performance. In the JFET region of the device, a current spreading layer with a higher doping concentration than the drift region is present to reduce the specific on-resistance of the device. The presence of the current spreading layer balances the device's conduction and blocking capabilities. In terms of implementation method, compared to existing technologies, the implementation process of this structure is simpler. Attached Figure Description
[0014] Figure 1(a) is a schematic diagram of the overall structure of the SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 1(b) is a schematic diagram of the internal structure of the SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 2 This is a schematic diagram of the epitaxial layer structure in the SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 3 This is a schematic diagram of the structure of a SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 4 A schematic diagram of the structure of the P-body region in a SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 5 This is a schematic diagram of the surface N+ region in a SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 6 This is a schematic diagram of the gate trench structure in a SiC MOSFET device with a surrounding P+ shielding layer according to the present invention; Figure 7(a) is a schematic diagram of the trench gate N-type polysilicon and the trench gate shielding layer in the SiC MOSFET device with a surrounding P+ shielding layer of the present invention. Figure 7(b) is a schematic cross-sectional view of the structure shown in Figure 7(a) at the dashed line. Figure 8(a) is a schematic diagram of the surrounding P+ region in a SiC MOSFET device with a surrounding P+ shielding layer; Figure 8(b) is a schematic diagram of the cross-section at the dashed line in Figure 8(a); Figure 9 This is a comparison of the output characteristic curves of the conventional structure and the SiC MOSFET device with a surrounding P+ shielding layer of the present invention; Figure 10 This is a comparison of the capacitance characteristic curves of the conventional structure and the SiC MOSFET device with a surrounding P+ shielding layer of the present invention.
[0015] In the figure, 1. Silicon carbide N-type substrate, 2. Silicon carbide N-type epitaxial layer, 3. Silicon carbide N-type current spreading layer, 4. Silicon carbide P-type body region, 5. Surface N+ region, 6. Gate trench, 7. Silicon carbide P-type trench gate shielding layer, 8. Trench gate oxide layer, 9. Trench gate N-type polysilicon, 10. Silicon carbide P-type surrounding P+ region. Detailed Implementation
[0016] The following detailed description is provided in conjunction with specific implementation methods.
[0017] Example 1 The present invention relates to a SiC MOSFET device having a surrounding P+ shielding layer, comprising a silicon carbide N-type substrate 1 and a silicon carbide N-type epitaxial layer 2 located above the silicon carbide N-type substrate 1, and a silicon carbide N-type current spreading layer 3, a silicon carbide P-body region 4, a surface N+ region 5, a gate trench 6, a silicon carbide P-type trench gate shielding layer 7, a trench gate N-type polysilicon 9, and a silicon carbide P-type surrounding P+ region 10 formed on the silicon carbide N-type epitaxial layer 2 by a semiconductor manufacturing process.
[0018] Example 2 The silicon carbide N-type current spreading layer 3 is located within the silicon carbide P-body region 4, within the JFET region formed by the silicon carbide P-type surrounding P+ region 10 and the gate trench 6. Its depth is consistent with the depth of the silicon carbide P-type surrounding P+ region 10. The thickness of the silicon carbide N-type current spreading layer 3 is 1.5~2μm, and the doping concentration is 1*10⁻⁶. 16 cm -3 ~3*10 16 cm -3 .
[0019] Example 3 The silicon carbide P-body region 4 is located between the surface N+ region 5 and the silicon carbide N-type current extension layer 3; the silicon carbide P-type trench gate shielding layer 7 is located at the bottom of the gate trench 6, and the length direction of the silicon carbide P-type trench gate shielding layer 7 is parallel to the length direction of the gate trench 6. The thickness of the silicon carbide P-body region 4 is 0.5~1.0μm.
[0020] Example 4 The surface N+ region 5 is located on the upper surface of the silicon carbide N-type epitaxial layer 2, and forms the source of the device together with the silicon carbide P-type surrounding P+ region 10. The surface N+ region 5 has a thickness of 0.2~0.3μm, is N-type doped, and has a doping concentration of 1*10. 19 cm -3 .
[0021] The gate trench 6 is located at the center of the unit cell. It is formed by mask etching starting from the upper surface of the silicon carbide N-type epitaxial layer 2, with a width of 1~1.5μm and a depth of 1~1.5μm.
[0022] The silicon carbide P-type trench gate shielding layer 7 is located at the bottom of the gate trench 6. The length direction of the silicon carbide P-type trench gate shielding layer 7 is parallel to the length direction of the trench, the thickness is 0.2~0.4μm, and the doping concentration is 1*10. 19 cm -3 .
[0023] The trench gate oxide layer 8 is located on the inner surface of the gate trench 6 and is formed by dry oxidation to form a trench gate oxide layer 8 with a thickness of 50 nm.
[0024] The trench gate N-type polysilicon 9 is used as the filler for the gate trench 6, and its doping type is N-type with a doping concentration of 1*10⁻⁶. 19 cm -3 . Example 5 The silicon carbide P-type surrounding P+ region 10 is located on top of the silicon carbide N-type epitaxial layer 2, extending from the surface of the silicon carbide N-type epitaxial layer 2 to below the silicon carbide P-type trench gate shielding layer 7, and is connected to the silicon carbide P-type trench gate shielding layer 7. The silicon carbide P-type surrounding P+ region 10 is located on top of the silicon carbide N-type epitaxial layer 2, and its thickness is consistent with that of the silicon carbide N-type current spreading layer 3, with a doping concentration of 1*10. 19 cm -3 It is connected to the silicon carbide P-type slot grid shielding layer 7 to form an electrical connection.
[0025] The silicon carbide P-type surrounding P+ region 10 is connected to the silicon carbide P-type trench gate shielding layer 7 to form an electrical connection, and the surface of the silicon carbide P-type surrounding P+ region 10 and the surface N+ region 5 together form the source of the device.
[0026] Example 6 The fabrication method of a SiC MOSFET device with a surrounding P+ shielding layer specifically includes the following steps: Step 1, as follows Figure 2 As shown, the silicon carbide N-type epitaxial layer 2 is located above the silicon carbide N-type substrate 1; specifically, the silicon carbide N-type substrate 1 is a 4H-SiC substrate, and the doping element of the 4H-SiC substrate is N, with a doping concentration of 1*10⁻⁶. 19cm -3 The silicon carbide N-type epitaxial layer 2 is epitaxially grown on the surface of the silicon carbide N-type substrate 1 by chemical vapor deposition (LPCVD), and the doping element is N with a doping concentration of 4*10. 15 cm -3 ~7*10 15 cm -3 The thickness is 10-15 μm. In addition, drain metal needs to be deposited on the lower surface of silicon carbide N-type substrate 1, and Ti / Ni / Al alloy is used as ohmic contact material. Ohmic contact is achieved by annealing at an ambient temperature of 900-1100℃.
[0027] Step 2, as follows Figure 3 As shown, a silicon carbide N-type current spreading layer 3 is formed through ion implantation. The current spreading layer, with a diameter of 1.5–2 μm, is formed by ion implantation. The doping type is N-type, and the doping ions can be phosphorus (P) or nitrogen (N) ions, with a doping concentration of 1*10⁻⁶. 16 cm -3 ~3*10 16 cm -3 .
[0028] Step 3, as follows Figure 4 As shown, a silicon carbide p-body region 4 also needs to be formed within the silicon carbide N-type epitaxial layer 2. The silicon carbide p-body region 4 can be achieved through a high-temperature, high-energy ion implantation process. The silicon carbide p-body region 4 is located in the upper middle part of the silicon carbide N-type epitaxial layer 2. The impurities doped in the silicon carbide p-body region 4 are p-type dopants, such as aluminum (Al) ions. The specific doping concentration can be 1*10⁻⁶. 17 cm -3 ~5*10 17 cm -3 The injection depth is approximately 0.5~1.0μm.
[0029] Step 4, as follows Figure 5 As shown, a high concentration of N-type ions is implanted into the surface of the silicon carbide N-type epitaxial layer 2 to form a surface N+ region 5. The implantation depth is 0.2~0.3μm, and the doping concentration is 1*10⁻⁶. 19 cm -3 .
[0030] Specifically, photolithography is first performed to form SiO2 as an ion implantation mask layer on the surface of the silicon carbide N-type current extension layer 3. Photoresist is then deposited on the surface of SiO2. After photolithography processes such as exposure, development, and hardening, an ion implantation window is formed. A high-energy ion implanter is used to form a 0.2~0.3μm doping window with a doping concentration of 1*10⁻⁶. 19 cm -3 5. Surface N+ region.
[0031] Step 5, as follows Figure 6As shown, the gate trench 6 is etched, and the length direction of the gate trench 6 is parallel to the length direction of the N+ region 5 on the surface.
[0032] Specifically, inductively coupled plasma reactive ion etching (ICP-RIE) was used for trench etching, and a photomask was used for nested etching. This ensured that the length of the etched trenches was consistent with the N+ region 5 on the surface, and the direction was parallel to the length direction of the N+ region 5. The trench width was approximately 1.0~1.5 μm, and the gate trench depth was approximately 1.0~1.5 μm. After trench etching, passivation treatment was required to eliminate the micro-trenches. Argon was used as the primary gas, with SiH4 as the auxiliary gas for passivation. Step 6, as shown in Figure 7(a), involves forming a silicon carbide P-type trench gate shielding layer 7 at the bottom of the gate trench 6 through P-type ion implantation to suppress the concentration of electric field intensity at the bottom corner of the gate trench 6. The length direction of the silicon carbide P-type trench gate shielding layer 7 is parallel to the length direction of the gate trench 6, and the implantation depth is 0.2~0.4μm. After depositing a trench gate oxide layer 8 on the inner wall of the gate trench 6, polysilicon is deposited to form a trench gate N-type polysilicon 9. Figure 7(b) is a cross-section taken at the position of the dashed line in Figure 7(a), which allows for a clearer observation of the positional relationship of each region.
[0033] A SiO2 layer is formed on the silicon carbide surface as an ion implantation mask layer. Photoresist is deposited on the SiO2 surface. After photolithography processes such as exposure, development, and hardening, an ion implantation window is formed, which is consistent with the etching window described above. A high-energy ion implanter is used to form a silicon carbide P-type trench gate shielding layer 7 doped with Al, with a doping concentration of 1*10⁻⁶. 19 cm -3 The thickness is 0.2–0.4 μm.
[0034] After ion implantation, the mask layer is removed and dry oxidation is performed to grow a trench gate oxide layer 8 on the inner wall of the gate trench 6. Then, polysilicon gate fabrication is performed by using a photolithography plate to deposit N-type polysilicon in the gate trench 6 to generate trench gate N-type polysilicon 9.
[0035] Polysilicon was grown using LPCVD, followed by ion implantation, annealing at 900°C, planarization, and then polysilicon etching. After gate oxide growth, annealing was performed to reduce interface states and improve gate oxide quality.
[0036] Step 7, as shown in Figure 8(a), P-type ions are implanted through an ion implantation process to form a silicon carbide P-type surrounding P+ region 10. The silicon carbide P-type surrounding P+ region 10 and the surface N+ region 5 together form the source of the device. The implantation depth of the silicon carbide P-type surrounding P+ region 10 is consistent with that of the silicon carbide N-type current extension layer 3. Figure 8(b) is a cross-section taken at the position of the dashed line in Figure 8(a). It can be clearly observed that the silicon carbide P-type trench gate shielding layer 7 and the silicon carbide P-type surrounding P+ region 10 are electrically connected.
[0037] In addition, after ion implantation, activation annealing is required at a temperature above 1500°C. Argon is used as a protective gas during the annealing process. The purpose is to activate and release the charge of the ions in the interstitial lattice and repair the lattice damage caused by ion implantation.
[0038] At this point, the manufacturing method of SiC MOSFET devices with a surrounding P+ shielding layer is complete, and subsequent processing steps such as interlayer dielectric (ILD) deposition and etching, surface metal interconnection, and passivation layer deposition and etching can be carried out.
[0039] Figure 9 This is a comparison of the output characteristic curves of the traditional structure and the present invention. Compared with the traditional structure, the present invention significantly reduces the saturation current of the device. The saturation current is a key factor affecting the short-circuit capability of the device, as it determines the peak value of the drain-source current during a short circuit. A lower saturation current can improve the short-circuit withstand capability of the device.
[0040] Figure 10 This is a comparison of the capacitance characteristic curves of the conventional structure and the present invention. Compared with the conventional structure, the present invention effectively reduces the gate-drain overlap area, and at the same time, by shorting the P+ shielding layer to the source, it partially reduces the gate-drain coupling capacitance C. GD Converted to gate-source coupling capacitance C GS This reduces the gate-drain capacitance of the device. Since the power consumption of SiC MOSFETs during switching is mainly concentrated in the Miller plateau stage, this invention can effectively reduce the Miller capacitance of the device by using a surrounding P+ shielding layer structure, thereby reducing the device's switching power consumption and optimizing its switching performance.
Claims
1. A SiC MOSFET device having a surrounding P+ shielding layer, characterized in that: The structure includes a silicon carbide N-type substrate (1), a silicon carbide N-type epitaxial layer (2), a silicon carbide N-type current extension layer (3), a silicon carbide P-type body region (4), and a surface N+ region (5) arranged sequentially from bottom to top. The silicon carbide N-type current extension layer (3), silicon carbide P-type body region (4), and surface N+ region (5) are surrounded by a hollow silicon carbide P-type surrounding P+ region (10). A gate trench (6) is formed at the center of the structure formed by the silicon carbide N-type current extension layer (3), silicon carbide P-type body region (4), and surface N+ region (5). A silicon carbide P-type trench gate shielding layer (7) is provided at the bottom of the gate trench (6). The gate trench (6) is filled with trench gate N-type polysilicon (9).
2. The SiC MOSFET device with a surrounding P+ shielding layer according to claim 1, characterized in that: The silicon carbide P-type surrounding P+ region (10) is connected to the silicon carbide P-type slot grid shielding layer (7) to form an electrical connection.
3. The SiC MOSFET device with a surrounding P+ shielding layer according to claim 2, characterized in that: The surface of the silicon carbide P-type surrounding P+ region (10) and the surface N+ region (5) together form the source of the device.
4. The SiC MOSFET device with a surrounding P+ shielding layer according to claim 3, characterized in that: The silicon carbide N-type current extension layer (3) is located within the JFET region consisting of the silicon carbide P-body region (4), the silicon carbide P-type surrounding P+ region (10), and the gate trench (6).
5. The SiC MOSFET device with a surrounding P+ shielding layer according to claim 4, characterized in that: The surface inside the gate trench (6) is provided with a trench gate oxide layer (8).
6. A method for fabricating a SiC MOSFET device with a surrounding P+ shielding layer, characterized in that: Specifically, the steps include the following: Step 1: Form a silicon carbide N-type epitaxial layer (2) on the upper surface of a silicon carbide N-type substrate (1). Step 2: A silicon carbide N-type current spreading layer (3) is formed above the silicon carbide N-type epitaxial layer (2), and a silicon carbide P-body region (4) is formed above the silicon carbide N-type current spreading layer (3). Step 3, form a surface N+ region (5) on the upper surface of the silicon carbide P-body region (4); Step 4: Etch the gate trench (6), form a silicon carbide P-type trench gate shielding layer (7) at the bottom of the gate trench (6), and deposit a trench gate oxide layer (8) on the inner wall of the gate trench (6) to form a trench gate N-type polysilicon (9).
7. The method for fabricating a SiC MOSFET device with a surrounding P+ shielding layer according to claim 6, characterized in that: In step 1, the doping concentration of the silicon carbide N-type epitaxial layer (2) is 4*10⁻⁶. 15 cm -3 ~7*10 15 cm -3 .
8. The method for fabricating a SiC MOSFET device with a surrounding P+ shielding layer according to claim 7, characterized in that: In step 2, the doping concentration of the silicon carbide N-type current extension layer (3) is 1*10. 16 cm -3 ~3*10 16 cm -3 .