Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle
By introducing amorphous SiNx and nanocrystalline Si3N4 layers into 4H-SiC MOSFET devices, combined with the structural design of 3C-SiC layers, the problems of low channel mobility and poor gate oxide reliability are solved, realizing semiconductor devices with high mobility and high breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANHUI YOFC ADVANCED SEMICONDUCTOR CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-05-01
AI Technical Summary
Existing MOSFET devices based on 4H-SiC suffer from low channel mobility and poor gate oxide reliability under high temperature and high electric field conditions.
The semiconductor body structure includes a 4H-SiC layer, an amorphous SiNx layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer stacked sequentially. By setting source and well regions in the 3C-SiC layer and forming a first insulating layer on its surface, the amorphous SiNx layer is used to suppress interface reactions, and the nanocrystalline Si3N4 layer blocks defect propagation, thereby promoting the nucleation and growth of 3C-SiC, reducing the interface state density, and improving the channel mobility and the reliability of the insulating layer.
It improves channel mobility, enhances the reliability of the gate insulating layer, and maintains a high breakdown voltage, thus solving the problem of insufficient device performance in the prior art.
Smart Images
Figure CN121968640A_ABST
Abstract
Description
Semiconductor devices and their fabrication methods, power modules, power conversion circuits and vehicles Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology
[0002] In SiC semiconductor devices, 4H-SiC material is usually used as the substrate and epitaxial layer because it is easier and more stable to grow and prepare at high temperatures (above 1900℃) than 3C-SiC. Compared with 6H-SiC, it has a higher intrinsic carrier concentration and electron mobility. Moreover, 4H-SiC MOS devices have a faster switching speed than 6H-SiC.
[0003] However, existing MOSFET devices based on 4H-SiC suffer from low channel mobility and poor gate oxide reliability under high temperature and high electric field conditions. Summary of the Invention
[0004] This application provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to improve channel mobility and gate insulating layer reliability.
[0005] According to one aspect of this application, a semiconductor device is provided, comprising: a semiconductor body configured with a first conductivity type, said semiconductor body comprising a 4H-SiC layer and an amorphous SiN layer sequentially stacked thereon. x The semiconductor body comprises a layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer; the semiconductor body further comprises a well region and a source region, the source region being configured with a first conductivity type and located within the 3C-SiC layer, the well region being configured with a second conductivity type and located within the 3C-SiC layer, the first conductivity type and the second conductivity type being different; wherein, x is a real number greater than 0; a first insulating layer is disposed on the surface of the 3C-SiC layer.
[0006] Optionally, X is greater than or equal to 1 and less than or equal to 4 / 3.
[0007] Optionally, the angle between the (111) plane of the 3C-SiC layer and the {10-10} plane of the nanocrystalline Si3N4 layer is 20-50 degrees.
[0008] Optionally, the thickness of the 4H-SiC layer is greater than that of the amorphous SiN. x The thickness of the 4H-SiC layer is greater than the thickness of the nanocrystalline Si3N4 layer; the thickness of the 3C-SiC layer is greater than the thickness of the amorphous SiN4 layer. xThe thickness of the 3C-SiC layer is greater than the thickness of the nanocrystalline Si3N4 layer.
[0009] Optionally, the thickness of the 3C-SiC layer is greater than the thickness of the 4H-SiC layer.
[0010] Optionally, the semiconductor body includes a first surface and a second surface disposed opposite to each other; the surface of the 3C-SiC layer away from the 4H-SiC layer is the first surface; the first insulating layer is disposed on the first surface, and the first insulating layer has a first via exposed at least a portion of the source region; the semiconductor device further includes: a polysilicon gate disposed on the side of the first insulating layer away from the first surface, the vertical projection of the polysilicon gate on the semiconductor body overlapping with at least a portion of the well region, and not overlapping with the vertical projection of the first via on the semiconductor body; a second insulating layer disposed on the surface of the semiconductor body... On the side of the polysilicon gate away from the first surface, the second insulating layer is provided with a second via and a third via, the second via exposing a portion of the polysilicon gate; the vertical projection of the third via onto the semiconductor body overlaps with the vertical projection of the first via onto the semiconductor body, the overlapping area exposing at least a portion of the source region; a source electrode is disposed on the side of the second insulating layer away from the semiconductor body and at least fills the third via; a metal gate electrode is disposed on the side of the second insulating layer away from the semiconductor body and at least fills the second via; a drain electrode is disposed on the second surface.
[0011] Optionally, the semiconductor body further includes a first region and a JFET region, the JFET region and the first region being disposed on the first surface, and the well region being in contact with the first region; the first region and the well region have the same conductivity type, and the JFET region and the source region have the same conductivity type; the overlapping region exposes at least a portion of the first region; the semiconductor body further includes a field-limiting ring region disposed within the 3C-SiC layer; the semiconductor body further includes a SiC substrate disposed on the side of the 4H-SiC layer away from the 3C-SiC layer.
[0012] According to another aspect of this application, a power module is provided, characterized in that it includes a substrate and a semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.
[0013] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.
[0014] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.
[0015] According to another aspect of this application, a method for fabricating a semiconductor device is provided, comprising: sequentially forming amorphous SiN on the surface of a 4H-SiC layer. x A semiconductor body is formed by a semiconductor body consisting of a 3C-SiC layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer; wherein the semiconductor body is configured with a first conductivity type, and x is a real number greater than 0; a well region and a source region are formed within the semiconductor body; wherein the source region is configured with a first conductivity type and is located within the 3C-SiC layer, and the well region is configured with a second conductivity type and is located within the 3C-SiC layer, wherein the first conductivity type and the second conductivity type are different; and a first insulating layer is formed on the surface of the 3C-SiC layer.
[0016] Optionally, forming a first insulating layer on the surface of the 3C-SiC layer includes: forming a first insulating layer on the surface of the 3C-SiC layer away from the nanocrystalline Si3N4 layer by an oxidation process.
[0017] Optionally, the oxidation process includes dry oxygen oxidation, wherein the temperature of dry oxygen oxidation is less than or equal to 950 degrees Celsius.
[0018] This application embodiment includes a semiconductor body comprising a 4H-SiC layer and an amorphous SiN layer stacked sequentially. x Layers, nanocrystalline Si3N4 layers, and 3C-SiC layers, amorphous SiN x Layers can suppress SiC / SiN xThe interface reaction absorbs the lattice mismatch stress between the 4H-SiC and 3C-SiC layers. The nanocrystalline Si3N4 layer effectively blocks the propagation of TSD defects in the 4H-SiC layer, promotes the nucleation and growth of 3C-phase SiC, and ensures that the 3C-SiC layer of the semiconductor body has high film quality. Furthermore, due to the higher carrier mobility of the 3C-SiC layer, the location of the source and well regions within the 3C-SiC layer ensures high channel mobility in the semiconductor device. Because the first insulating layer prepared using the 3C-SiC layer has a low interface state density, and the 3C-SiC layer can be prepared at a lower temperature, the carbon residue problem caused by high temperature can be further reduced, further improving the channel mobility of the device and ensuring high reliability of the first insulating layer. Simultaneously, the high breakdown voltage characteristics of the 4H-SiC layer ensure that the semiconductor device has a high breakdown voltage. In summary, the semiconductor device of this application embodiment has high channel mobility, high breakdown voltage, and a highly reliable gate insulating layer.
[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this application; Figure 2 is a flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application; Figure 3 is a schematic diagram of fabricating a 4H-SiC layer provided in an embodiment of this application; Figure 4 is a schematic diagram of fabricating amorphous SiN provided in an embodiment of this application. x Figure 5 is a schematic diagram of the preparation of the 3C-SiC layer provided in the embodiment of this application; Figure 6 is a schematic diagram of the preparation of the source region and the well region provided in the embodiment of this application; Figure 7 is a schematic diagram of the preparation of the first insulating layer provided in the embodiment of this application. Detailed Implementation
[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0024] As mentioned in the background section, existing 4H-SiC-based MOSFET devices suffer from low channel mobility and poor gate insulation layer reliability under high temperature and high electric field conditions. The inventors discovered through research that this problem arises because the channel mobility of 4H-SiC MOSFET devices is only 30 cm⁻¹. 2 The band structure of 4H-SiC determines that the gate insulating layer prepared by 4H-SiC has a high interface state density of about / (V·S). Furthermore, the high temperature required for the formation process of the gate insulating layer will cause the Si at the SiO2 / SiC interface to be selectively oxidized, resulting in carbon residue, which further reduces the channel mobility and leads to poor reliability of the gate insulating layer.
[0025] To address the aforementioned problems, this application provides a semiconductor device. Figure 1 is a schematic diagram of a semiconductor device provided in this application. Referring to Figure 1, the semiconductor device includes: a semiconductor body 10, configured as a first conductivity type, the semiconductor body 10 including a 4H-SiC layer 11 and an amorphous SiN layer sequentially stacked. xThe semiconductor body 10 includes a layer 12, a nanocrystalline Si3N4 layer 13, and a 3C-SiC layer 14; the semiconductor body 10 also includes a well region 102 and a source region 101, the source region 101 being configured with a first conductivity type and located within the 3C-SiC layer 14, and the well region 102 being configured with a second conductivity type and located within the 3C-SiC layer 14, the first conductivity type and the second conductivity type being different; where x is a real number greater than 0; and a first insulating layer 20, which is disposed on the surface of the 3C-SiC layer 14.
[0026] Specifically, the semiconductor device can be a metal-oxide-semiconductor field-effect transistor (MOSFET). One of the first conductivity type and the second conductivity type is N-type, and the other is P-type. For example, the first conductivity type is N-type, and the second conductivity type is P-type. The well region 102 and the source region 101 can be formed by doping the 3C-SiC layer 14. The first insulating layer 20 is a gate insulating layer, exemplarily a silicon oxide layer. The semiconductor device of this application can be either trench-type or planar-type. When the semiconductor device is trench-type, the semiconductor body 10 is provided with a gate trench, which extends from the surface of the 3C-SiC layer 14 away from the 4H-SiC layer 11 into the 3C-SiC layer 14, and the first insulating layer 20 can be located on the sidewall of the gate trench. When the semiconductor device is planar-type, the first insulating layer 20 is disposed on the surface of the 3C-SiC layer 14 away from the 4H-SiC layer 11.
[0027] Due to the significant differences in lattice constants and stacking order between 4H-SiC (hexagonal crystal system) and 3C-SiC (cubic crystal system), defects such as dislocations and stacking faults are easily generated at the interface. Furthermore, the different coefficients of thermal expansion of the two crystal forms can lead to stress differences that cause epitaxial growth cracks or interface delamination. Currently, there are very few techniques for growing 3C-SiC on 4H-SiC, and those that exist are complex and have high defect densities.
[0028] In this embodiment, an amorphous SiN layer is first grown on the 4H-SiC layer 11. x Layer 12 can suppress SiC / SiN x Interfacial reaction. Additionally, amorphous SiN... x Layer 12 can absorb the lattice mismatch stress between the 4H-SiC layer 11 and the 3C-SiC layer 14 through the free volume effect. Then, in amorphous SiN... x A nanocrystalline Si3N4 layer 13 is grown on layer 12, which can effectively block the propagation of TSD defects in the 4H-SiC layer 11. Furthermore, the local compressive stress generated during the amorphous-to-nanocrystalline transformation can promote the nucleation of 3C-phase SiC, which is beneficial to the growth of the 3C-SiC layer 14. Therefore, this embodiment of the application provides an amorphous SiN4 layer on the 4H-SiC layer 11. xAfter layer 12 and nanocrystalline Si3N4 layer 13, a 3C-SiC layer 14 is then set, which can reduce the defects of the 3C-SiC layer 14, so that the 3C-SiC layer 14 has a high film quality and the process is simple.
[0029] Since the channel mobility of 3C-SiC semiconductor devices is 5-10 times that of 4H-SiC MOSFET devices, using a 3C-SiC layer to fabricate the well region 102 and source region 101 can improve the channel mobility of the semiconductor device. The first insulating layer 20 can be prepared by oxidizing the 3C-SiC layer 14. The first insulating layer 20 prepared with 3C-SiC has a low interface state density, ensuring that the semiconductor device has a high channel mobility and the first insulating layer 20 has high reliability. Furthermore, using a 4H-SiC layer 11 and amorphous SiN... x The device employs a stacked epitaxial structure consisting of layer 12, nanocrystalline Si3N4 layer 13, and 3C-SiC layer 14. Simultaneously, the high breakdown voltage of 4H-SiC ensures a high breakdown voltage for the semiconductor device. Furthermore, 3C-SiC can undergo dry oxidation at low temperatures to form the first insulating layer 20, further reducing carbon residue issues caused by high temperatures and improving the device's electron mobility.
[0030] In this embodiment, the semiconductor body 10 includes a 4H-SiC layer 11 and an amorphous SiN layer stacked sequentially. x Layer 12, nanocrystalline Si3N4 layer 13, and 3C-SiC layer 14, amorphous SiN x Layer 12 can suppress SiC / SiN x The interface reaction absorbs the lattice mismatch stress between the 4H-SiC layer 11 and the 3C-SiC layer 14. The nanocrystalline Si3N4 layer 13 effectively blocks the propagation of TSD defects in the 4H-SiC layer 11, promotes the nucleation and growth of 3C phase SiC, and ensures that the 3C-SiC layer 14 of the semiconductor body has high film quality. Furthermore, due to the higher carrier mobility of the 3C-SiC layer 14, the location of the source region 101 and well region 102 within the 3C-SiC layer 14 ensures high channel mobility for the semiconductor device. Because the first insulating layer 20 prepared using the 3C-SiC layer 14 has a low interface state density, and the 3C-SiC layer 14 can be prepared at a lower temperature, the carbon residue problem caused by high temperature can be further reduced, further improving the channel mobility of the device and ensuring high reliability of the first insulating layer 20. Simultaneously, the high breakdown voltage characteristics of the 4H-SiC layer 11 can be utilized to ensure a high breakdown voltage for the semiconductor device. In summary, the semiconductor devices of this application have high channel mobility, high breakdown voltage, and a highly reliable gate insulating layer.
[0031] Based on the above embodiments, optionally, X is greater than or equal to 1 and less than or equal to 4 / 3. This setting can better suppress SiC / SiN x Interfacial reaction, improving amorphous SiN x The film quality of layer 12 ensures the formation of amorphous SiN. x Layer 12 can better absorb the lattice mismatch stress between 4H-SiC layer 11 and 3C-SiC layer 14, thereby improving the film quality of 3C-SiC layer 14.
[0032] Based on the above embodiments, optionally, the angle between the (111) facet of the 3C-SiC layer 14 and the {10-10} facet of the nanocrystalline Si3N4 layer 13 is 20 degrees to 50 degrees.
[0033] Specifically, Si3N4 has a hexagonal crystal structure, which has a lattice mismatch problem with the cubic crystal system 3C-SiC. By setting the angle between the (111) plane of the 3C-SiC layer 14 and the {10-10} plane of the nanocrystalline Si3N4 layer 13 to 20-50 degrees, the atomic arrangement of the two can be periodically aligned, thereby reducing the dangling bond density during the growth of the 3C-SiC layer 14, reducing the interface energy, reducing the defects of the 3C-SiC layer 14, and improving the film quality.
[0034] Based on the above embodiments, optionally, the thickness of the 4H-SiC layer 11 is greater than that of the amorphous SiN. x The thickness of layer 12, the thickness of 4H-SiC layer 14 is greater than the thickness of nanocrystalline Si3N4 layer 13; the thickness of 3C-SiC layer 14 is greater than the thickness of amorphous SiN x The thickness of layer 12 and the thickness of 3C-SiC layer 14 are greater than the thickness of nanocrystalline Si3N4 layer 13.
[0035] Specifically, the 4H-SiC layer 11 is used to improve the breakdown voltage of the semiconductor device, and the 3C-SiC layer 14 is used to form functional regions such as the well region 102 and the source region 101. The 4H-SiC layer 11 and the 3C-SiC layer 14 have a relatively large thickness, and the amorphous SiN... x Layer 12 and nanocrystalline Si3N4 layer 13 have a small thickness, which can ensure that each functional area has a suitable size, the semiconductor device has a high breakdown voltage and a low on-resistance.
[0036] Based on the above embodiments, optionally, the thickness of the 3C-SiC layer 14 is greater than the thickness of the 4H-SiC layer 11.
[0037] Specifically, if the thickness of the 4H-SiC layer 11 is too large, it will increase the on-resistance and size of the device. By setting the thickness of the 3C-SiC layer 14 to be greater than that of the 4H-SiC layer 11, the on-resistance and size of the device can be reduced while ensuring that the device has a high breakdown voltage.
[0038] Based on the above embodiments, optionally, the semiconductor body 10 includes a first surface 01 and a second surface 02 disposed opposite to each other; the surface of the 3C-SiC layer 14 away from the 4H-SiC layer 11 is the first surface 01; a first insulating layer 20 is disposed on the first surface 01, and the first insulating layer 20 is provided with a first via 21, the first via 21 exposing at least a portion of the source region 101; the semiconductor device further includes: a polysilicon gate 30, disposed on the side of the first insulating layer 20 away from the first surface 01, and the vertical projection of the polysilicon gate 30 on the semiconductor body 10 overlaps with at least a portion of the well region 102, but does not overlap with the vertical projection of the first via 21 on the semiconductor body 10; the first A second insulating layer 40 is disposed on the side of the polysilicon gate 30 away from the first surface 01. The second insulating layer 40 is provided with a second via 41 and a third via 42. The second via 41 exposes a portion of the polysilicon gate 30. The vertical projection of the third via 42 onto the semiconductor body 10 overlaps with the vertical projection of the first via 41 onto the semiconductor body 10. The overlapping area exposes at least a portion of the source region 101. A source electrode 50 is disposed on the side of the second insulating layer 40 away from the semiconductor body 10 and is at least filled in the third via 42. A metal gate 60 is disposed on the side of the second insulating layer away from the semiconductor body and is at least filled in the second via. A drain electrode 70 is disposed on the second surface 02.
[0039] Specifically, the metal gate 60 is connected to the polysilicon gate 30, and the source 50 is connected to the source region 101. When the semiconductor body 10 does not include the substrate, the second surface 02 of the semiconductor body 10 is the surface of the 4H-SiC layer 11 away from the 3C-SiC layer 14. When the semiconductor body 10 includes the substrate, the second surface 02 of the semiconductor body 10 is the surface of the substrate away from the 4H-SiC layer 11. When the semiconductor device is operating, a voltage is applied to the source 50 and the metal gate 60. When the voltage difference between the metal gate 60 and the source 50 reaches the threshold voltage, an inversion layer is formed in the well region 102. Current flows through the source 40, the source region 101, the inversion layer, the 3C-SiC layer 14, the nanocrystalline Si3N4 layer 13, and the amorphous SiN4 layer 14. x Layer 12 and 4H-SiC layer 11 reach the drain 70.
[0040] Based on the above embodiments, optionally, the semiconductor body 10 further includes a first region 103 and a JFET region 104, the JFET region 104 and the first region 103 are disposed on the first surface 01, and the well region 102 is in contact with the first region 103; the first region 103 and the well region 102 have the same conductivity type, and the JFET region 104 and the source region 101 have the same conductivity type; the overlapping region exposes at least a portion of the first region 103; the semiconductor body further includes a field-limiting ring region 105, the field-limiting ring region 105 is disposed within the 3C-SiC layer 14; the semiconductor body 10 further includes a SiC substrate 15, the SiC substrate 15 is disposed on the side of the 4H-SiC layer 11 away from the 3C-SiC layer 14.
[0041] Specifically, the overlapping region exposes at least a portion of the first region 103. The first region 103 is connected to the source 50 and also contacts the well region 102. The first region 103 is used to provide potential for the well region 101. The JFET region 14 is a junction field-effect transistor region. The first region 103 and the JFET region 104 are disposed within the 3C-SiC layer 14, and can be formed by doping the 3C-SiC layer 14.
[0042] The field-limiting ring region 105 is used to improve the horizontal breakdown voltage of the semiconductor device. The field-limiting ring region 105 can be formed by doping the 3C-SiC layer 14. The field-limiting ring region 105 is disposed in the terminal region of the semiconductor device, which also includes a third insulating layer 80 disposed on the first surface 01 of the semiconductor body 10. The third insulating layer 80 is a field oxide layer.
[0043] Based on the above embodiments, this application also provides a power module, including a substrate and the semiconductor device described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.
[0044] The power module provided by the technical solution of this application has the same beneficial effects as the semiconductor device described in any embodiment of this application.
[0045] Based on the above embodiments, this application also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.
[0046] The power conversion circuit provided in the embodiments of this application has the same beneficial effects as the semiconductor device described in any embodiment of this application.
[0047] Based on the above embodiments, this application also provides a vehicle, including a load and the power conversion circuit described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0048] The vehicle provided by the technical solution of this application has the same beneficial effects as the semiconductor device described in any embodiment of this application.
[0049] This application also provides a method for fabricating a semiconductor device. Figure 2 is a flowchart of a method for fabricating a semiconductor device provided in this application. Referring to Figure 2, the method for fabricating the semiconductor device includes: S110, sequentially forming amorphous SiN on the surface of a 4H-SiC layer. x A semiconductor body is formed by a layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer; wherein the semiconductor body is set to the first conductivity type, and x is a real number greater than 0.
[0050] Figure 3 is a schematic diagram of the fabrication of a 4H-SiC layer according to an embodiment of this application. Referring to Figure 3, a 4H-SiC layer 11 is epitaxially grown on the surface of a SiC substrate 15. Figure 4 is a schematic diagram of the fabrication of amorphous SiN according to an embodiment of this application. x A schematic diagram of the 4H-SiC layer and the nanocrystalline Si3N4 layer is shown in Figure 4. Amorphous SiN4 is sequentially grown on the surface of the 4H-SiC layer 11 using a CVD process. x Layer 12 and nanocrystalline Si3N4 layer 13 are formed by controlling CVD parameters to create amorphous SiN. x Layer 12 and nanocrystalline Si3N4 layer 13. Figure 5 is a schematic diagram of the preparation of 3C-SiC layer provided in the embodiment of this application. Referring to Figure 5, 3C-SiC layer 14 is epitaxially grown on the surface of nanocrystalline Si3N4 layer 13.
[0051] S120. A well region and a source region are formed within the semiconductor body; wherein the source region is configured with a first conductivity type and is located within the 3C-SiC layer, and the well region is configured with a second conductivity type and is located within the 3C-SiC layer, and the first conductivity type and the second conductivity type are different.
[0052] Figure 6 is a schematic diagram of the source region and well region after preparation according to the embodiment of this application. Referring to Figure 6, the 3C-SiC layer 14 can be doped by using doping processes such as ion implantation to form the source region 101, well region 102, first region 103, JFET region 104 and field confinement ring region 105.
[0053] S130. A first insulating layer is formed on the surface of the 3C-SiC layer.
[0054] Figure 7 is a schematic diagram of the fabrication of the first insulating layer according to an embodiment of this application. Referring to Figure 7, a third insulating layer 80 is substrated on the surface of the semiconductor body 10 in the terminal region. The first insulating layer 20 is formed by oxidizing the 3C-SiC layer 14. Continuing to refer to Figure 1, after forming the first insulating layer 20, a gate polysilicon layer 30, a second insulating layer 40, a source electrode 50, a metal gate electrode 60, and a drain electrode 70 can be formed.
[0055] This application embodiment includes a semiconductor body comprising a 4H-SiC layer and an amorphous SiN layer stacked sequentially. x Layers, nanocrystalline Si3N4 layers, and 3C-SiC layers, amorphous SiN x Layers can suppress SiC / SiN x The interface reaction absorbs the lattice mismatch stress between the 4H-SiC and 3C-SiC layers. The nanocrystalline Si3N4 layer effectively blocks the propagation of TSD defects in the 4H-SiC layer, promotes the nucleation and growth of 3C-phase SiC, and ensures that the 3C-SiC layer of the semiconductor body has high film quality. Furthermore, due to the higher carrier mobility of the 3C-SiC layer, the location of the source and well regions within the 3C-SiC layer ensures high channel mobility in the semiconductor device. Because the first insulating layer prepared using the 3C-SiC layer has a low interface state density, and the 3C-SiC layer can be prepared at a lower temperature, the carbon residue problem caused by high temperature can be further reduced, further improving the channel mobility of the device and ensuring high reliability of the first insulating layer. Simultaneously, the high breakdown voltage characteristics of the 4H-SiC layer ensure that the semiconductor device has a high breakdown voltage. In summary, the semiconductor device of this application embodiment has high channel mobility, high breakdown voltage, and a highly reliable gate insulating layer.
[0056] Based on the above embodiments, optionally, forming a first insulating layer on the surface of the 3C-SiC layer includes: forming a first insulating layer 20 on the surface of the 3C-SiC layer 14 away from the nanocrystalline Si3N4 layer 13 by an oxidation process.
[0057] The first insulating layer 20, prepared by oxidizing the 3C-SiC layer 14, has a low interface state density, which ensures that the semiconductor device has a high channel mobility and the first insulating layer 20 has high reliability.
[0058] Based on the above embodiments, optionally, the oxidation process includes dry oxygen oxidation, wherein the temperature of dry oxygen oxidation is less than or equal to 950 degrees.
[0059] For example, the dry oxidation process temperature can be 900 degrees. By performing dry oxidation on the 3C-SiC layer 14 under lower temperature process conditions to form the first insulating layer 20, the carbon residue problem caused by high temperature can be further reduced, and the channel mobility of the device can be improved.
[0060] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0061] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, include: The semiconductor body, configured as a first conductivity type, comprises a 4H-SiC layer and an amorphous SiN layer stacked sequentially. x The semiconductor body comprises a layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer; the semiconductor body further comprises a well region and a source region, the source region being configured with a first conductivity type and located within the 3C-SiC layer, the well region being configured with a second conductivity type and located within the 3C-SiC layer, the first conductivity type and the second conductivity type being different; wherein, x is a real number greater than 0; a first insulating layer is disposed on the surface of the 3C-SiC layer.
2. The semiconductor device according to claim 1, characterized in that: X is greater than or equal to 1 and less than or equal to 4 / 3.
3. The semiconductor device according to claim 1, characterized in that: The angle between the (111) plane of the 3C-SiC layer and the {10-10} plane of the nanocrystalline Si3N4 layer is 20-50 degrees.
4. The semiconductor device according to claim 1, characterized in that: The thickness of the 4H-SiC layer is greater than that of the amorphous SiN. x The thickness of the 4H-SiC layer is greater than the thickness of the nanocrystalline Si3N4 layer; the thickness of the 3C-SiC layer is greater than the thickness of the amorphous SiN4 layer. x The thickness of the 3C-SiC layer is greater than the thickness of the nanocrystalline Si3N4 layer.
5. The semiconductor device according to claim 1, characterized in that: The thickness of the 3C-SiC layer is greater than the thickness of the 4H-SiC layer.
6. The semiconductor device according to claim 1, characterized in that: The semiconductor body includes a first surface and a second surface disposed opposite to each other; the surface of the 3C-SiC layer away from the 4H-SiC layer is the first surface; the first insulating layer is disposed on the first surface, and the first insulating layer is provided with a first through hole, the first through hole exposing at least a portion of the source region; The semiconductor device further includes: a polysilicon gate disposed on the side of the first insulating layer away from the first surface, wherein the vertical projection of the polysilicon gate onto the semiconductor body overlaps with at least a portion of the well region, but does not overlap with the vertical projection of the first via onto the semiconductor body; a second insulating layer disposed on the side of the polysilicon gate away from the first surface, wherein the second insulating layer has a second via and a third via, wherein the second via exposes a portion of the polysilicon gate; wherein the vertical projection of the third via onto the semiconductor body overlaps with the vertical projection of the first via onto the semiconductor body, and the overlapping area exposes at least a portion of the source region; The source electrode is disposed on the side of the second insulating layer away from the semiconductor body and at least fills the third via; the metal gate electrode is disposed on the side of the second insulating layer away from the semiconductor body and at least fills the second via; and the drain electrode is disposed on the second surface.
7. The semiconductor device according to claim 6, characterized in that: The semiconductor body further includes a first region and a JFET region, the JFET region and the first region being disposed on the first surface, and the well region being in contact with the first region; the first region and the well region have the same conductivity type, and the JFET region and the source region have the same conductivity type; the overlapping region exposes at least a portion of the first region; the semiconductor body further includes a field-limiting ring region, the field-limiting ring region being disposed within the 3C-SiC layer; the semiconductor body further includes a SiC substrate, the SiC substrate being disposed on the side of the 4H-SiC layer away from the 3C-SiC layer.
8. A power module, characterized in that, The device includes a substrate and the semiconductor device according to any one of claims 1-7, wherein the substrate is used to support the semiconductor device.
9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-7, the semiconductor device being electrically connected to the circuit board.
10. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 9, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
11. A method for fabricating a semiconductor device, characterized in that, include: Amorphous SiN is sequentially formed on the surface of the 4H-SiC layer. x A semiconductor body is formed by a semiconductor body consisting of a 3C-SiC layer, a nanocrystalline Si3N4 layer, and a 3C-SiC layer; wherein the semiconductor body is configured with a first conductivity type, and x is a real number greater than 0; a well region and a source region are formed within the semiconductor body; wherein the source region is configured with a first conductivity type and is located within the 3C-SiC layer, and the well region is configured with a second conductivity type and is located within the 3C-SiC layer, wherein the first conductivity type and the second conductivity type are different; and a first insulating layer is formed on the surface of the 3C-SiC layer.
12. The method according to claim 11, characterized in that, Forming a first insulating layer on the surface of the 3C-SiC layer includes: forming a first insulating layer on the surface of the 3C-SiC layer away from the nanocrystalline Si3N4 layer by an oxidation process.
13. The method according to claim 12, characterized in that, The oxidation process includes dry oxygen oxidation, where the temperature is less than or equal to 950 degrees Celsius.