Transistor and preparation method thereof, semiconductor device and electronic equipment

Abstract

The invention discloses a transistor, a preparation method thereof, a semiconductor device and electronic equipment. The transistor includes a channel, a gate structure, a first pole assembly, and a second pole assembly. The gate structure includes a gate electrode. The first pole assembly and the second pole assembly are located on the two sides of the gate structure in the first direction respectively and connected with the channel. The orthographic projection of at least one of the first pole assembly and the second pole assembly on the substrate is overlapped with the orthographic projection of the channel on the first plane; or, the orthographic projection of the first pole assembly and the orthographic projection of the second pole assembly on the first plane are not overlapped with the orthographic projection of the channel on the first plane, and the two ends of the gate structure in the first direction are correspondingly flush with the two ends of the channel in the first direction. According to the transistor and the preparation method thereof, the semiconductor device and the electronic equipment, the distance between the gate electrode and the source / drain electrode can be reduced, and the electrical property of the transistor can be improved.

Description

Technical Field

[0001] This article relates to semiconductor technology, particularly a transistor and its fabrication method, semiconductor devices, and electronic devices. Background Technology

[0002] A transistor consists of a source, a drain, and an intermediate metal-oxide-semiconductor (MOS) capacitor. Some transistors have a lower electric field strength near the drain along the channel direction, exhibiting better performance, reliability, and compatibility, and their fabrication process is relatively simple. Summary of the Invention

[0003] This application provides a transistor, including: The channel extends along the first direction; A gate structure is located on one side, both sides, or on the outer periphery of the channel in a second direction, wherein the second direction is perpendicular to the first direction, and the gate structure includes a gate electrode that is insulated from the channel. The first electrode assembly and the second electrode assembly are respectively located on both sides of the gate electrode in the first direction and are both connected to the channel; At least one of the first electrode assembly and the second electrode assembly has its orthographic projection on the first plane arranged to overlap with the orthographic projection of the channel on the first plane; or... The orthographic projections of the first electrode assembly and the second electrode assembly onto the first plane are configured not to overlap with the orthographic projections of the channel onto the first plane. The gate structure at both ends in the first direction is configured to be flush with the two ends of the channel in the first direction. The first plane is parallel to the first direction and perpendicular to the second direction.

[0004] In some exemplary embodiments, the first electrode assembly, the second electrode assembly, and the gate electrode are all located on the same side of the channel in the second direction.

[0005] In some exemplary embodiments, at least one of the first pole component and the second pole component is configured to have its orthographic projection on the first plane lie within the orthographic projection of the channel on the first plane.

[0006] In some exemplary embodiments, at least one of the first electrode assembly and the second electrode assembly is configured to extend toward the side of the gate electrode away from the first direction and cover the end face of the channel in the first direction.

[0007] In some exemplary embodiments, the first electrode assembly includes a first electrode and a first contact terminal, the second electrode assembly includes a second electrode and a second contact terminal, the first electrode and the second electrode are respectively located at both ends of the channel in the first direction, and the first contact terminal, the second contact terminal and the gate structure are located on the same side of the channel in the second direction; The first contact terminal contacts one end of the first electrode and the channel in the first direction, and the second contact terminal contacts the other end of the second electrode and the channel in the first direction; The orthographic projection of at least one of the first contact terminal and the second contact terminal on the first plane is configured to overlap with the orthographic projection of the channel on the first plane.

[0008] In some exemplary embodiments, the gate structure further includes a first insulating layer configured to cover the end face of the gate electrode on the side away from the channel.

[0009] In some exemplary embodiments, the first insulating layer includes a first dielectric layer and a second dielectric layer stacked together, the first dielectric layer being located on the side of the second dielectric layer closer to the gate electrode, and the first dielectric layer and the second dielectric layer being made of different materials.

[0010] In some exemplary embodiments, the material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon oxide.

[0011] In some exemplary embodiments, the gate structure further includes a gate insulating layer that forms a receiving groove with its opening facing away from the channel, the gate electrode being disposed within the receiving groove, and the first insulating layer being configured to be at least partially located within the receiving groove.

[0012] In some exemplary embodiments, a conductive layer is provided between the first electrode assembly and the channel, and / or between the second electrode assembly and the channel.

[0013] In some exemplary embodiments, the first electrode assembly and the second electrode assembly are configured to extend along the second direction toward the side of the channel close to the gate structure, and the first electrode assembly and the second electrode assembly respectively contact the two ends of the gate structure in the first direction.

[0014] In some exemplary embodiments, the gate structure further includes a second insulating layer located between the gate electrode and the first electrode assembly, and / or between the gate electrode and the second electrode assembly; The material of the second insulating layer includes a low dielectric constant material.

[0015] In some exemplary embodiments, the minimum distance between the first electrode assembly and the gate electrode in the first direction is set to D1, the minimum distance between the second electrode assembly and the gate electrode in the first direction is set to D2, and the extension length of the channel in the first direction is set to L, wherein the ratio of D1 to L is set to be greater than 0 and less than 0.6, and / or the ratio of D2 to L is set to be greater than 0 and less than 0.6.

[0016] In some exemplary embodiments, 0 < D1 < 30 nm, and / or, 0 < D2 < 30 nm.

[0017] This application provides a method for fabricating a transistor, including: Provide substrate; A channel, a gate structure, a first electrode assembly, and a second electrode assembly are formed. The channel extends along a first direction, and the gate structure is located on one side, both sides, or on the outer periphery of the channel in a second direction, which is perpendicular to the first direction. The gate structure includes a gate electrode that is insulated from the channel. The first electrode assembly and the second electrode assembly are respectively located on both sides of the gate electrode in the first direction and are both connected to the channel. The orthographic projection of at least one of the first electrode assembly and the second electrode assembly on a first plane is configured to overlap with the orthographic projection of the channel on the first plane; or, the orthographic projection of the first electrode assembly and the second electrode assembly on the first plane is configured not to overlap with the orthographic projection of the channel on the first plane. The two ends of the gate structure in the first direction are configured to be flush with the two ends of the channel in the first direction. The first plane is parallel to the first direction and perpendicular to the second direction.

[0018] In some exemplary embodiments, the formation of the channel, gate structure, first electrode assembly, and second electrode assembly includes: Channels are formed on the substrate; A gate insulating layer is formed on the channel, and the gate insulating layer has a receiving groove with the opening facing away from the channel; A gate electrode is formed by depositing gate material within the receiving tank. A first insulating layer is formed at the end of the gate material away from the channel; The first and second pole components are formed.

[0019] In some exemplary embodiments, the formation of the channel, gate structure, first electrode assembly, and second electrode assembly includes: A first electrode assembly is formed on the substrate; A channel is formed on the side of the first electrode away from the substrate; A gate insulating layer is formed on the channel, and the gate insulating layer has a receiving groove with the opening facing away from the channel; A gate electrode is formed by depositing gate material in the receiving trench surrounded by the gate insulating layer. A first insulating layer is formed at the end of the gate material away from the channel; A second electrode assembly is formed on the side of the channel away from the substrate.

[0020] In some exemplary embodiments, forming a first insulating layer at one end of the gate material away from the channel includes: The gate material is etched, and the end face of the gate electrode away from the channel is configured to be located on the side of the end face of the gate insulating layer away from the channel close to the channel, forming a first groove; The first insulating layer is formed within the first groove.

[0021] In some exemplary embodiments, forming the first insulating layer within the first groove includes: A first dielectric layer is deposited in the first groove, wherein the end face of the first dielectric layer away from the channel is flush with the end face of the gate insulating layer away from the channel. A second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer constitute the first insulating layer.

[0022] In some exemplary embodiments, a gate insulating layer is formed on the channel, the gate insulating layer having a receiving groove with its opening facing away from the channel, including: The gate insulating layer is formed on one side of the channel in the second direction. A second insulating layer is formed on the channel, the second insulating layer covering both ends of the gate insulating layer in the first direction.

[0023] This application provides a semiconductor device, including the transistor described above, or a transistor obtained by the transistor fabrication method described above.

[0024] This application provides an electronic device, including the semiconductor device described above.

[0025] The transistors of this application embodiment can reduce the distance between the gate electrode and the source / drain electrode, thereby improving the transistor's electrical performance. The transistors of this application embodiment can reduce the channel length and increase the on-state current. In the transistors of this application embodiment, the first and second contact terminals can increase the contact area between the channel and the first / second electrode, lowering the potential barrier and improving ion distribution and concentration, thereby further improving transistor performance. In the transistors of this application embodiment, a first insulating layer is added to the gate electrode, preventing the first or second electrode assembly from misaligning and contacting the gate electrode, solving the gate electrode short-circuit problem, and greatly improving the misalignment margin. In the transistors of this application embodiment, the channel can be a thin film material, allowing for effective control of the gate electrode and greatly reducing the drain-induced barrier lowering (DIBL) effect.

[0026] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0028] Figure 1 A schematic diagram of a transistor in this exemplary embodiment; Figure 2 for Figure 1 A schematic diagram of the channel of a transistor in a transistor; Figure 3 for Figure 1 A first schematic diagram of the transistor fabrication process; Figure 4 for Figure 1 A second schematic diagram of the transistor fabrication process; Figure 5 for Figure 1 A third schematic diagram of the transistor fabrication process; Figure 6 for Figure 1 The fourth schematic diagram of transistor fabrication in the image; Figure 7 This is a schematic diagram illustrating the fabrication of another transistor in this exemplary embodiment; Figure 8 This is a schematic diagram of a method for fabricating a transistor, as illustrated in this exemplary embodiment. Figure 9A schematic diagram of another transistor as an exemplary embodiment of this invention; Figure 10 Another schematic diagram of a transistor for this exemplary embodiment; Figure 11 A schematic diagram of another transistor as an exemplary embodiment of this invention; Figure 12 Another schematic diagram of a transistor for this exemplary embodiment; Figure 13 A schematic diagram of another transistor as an exemplary embodiment of this invention; Figure 14 Another transistor schematic diagram of this exemplary embodiment; Figure 15 for Figure 14 A schematic diagram of the fabrication method of a transistor; Figure 16 This is a schematic diagram of a method for fabricating a transistor, which is an exemplary embodiment of this invention.

[0029] Figure label: 100 - Channel; 200 - Gate structure; 300 - First electrode component; 400 - Second electrode component; 500 - Interlayer dielectric layer; 600 - Substrate; 201 - Gate electrode; 202 - Gate insulating layer; 203 - First insulating layer; 204 - Receiving groove; 205 - Gate material; 206 - First groove; 207 - First dielectric layer; 208 - Second dielectric layer; 209 - Second insulating layer; 301 - First pole; 302 - First contact terminal; 401 - Second pole; 402 - Second contact terminal; 501 - First contact hole; 502 - Second contact hole. Detailed Implementation

[0030] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0031] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0032] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0033] In existing transistors, the source and drain electrodes are typically located on opposite sides of the channel and are both led up through conductive material in the contact hole. The applicant has found that the gap between the gate electrode and the conductive material in the contact hole is large, and the larger the gap, the worse the transistor's electrical performance.

[0034] like Figure 1 This is a schematic diagram of a transistor in an exemplary embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of the channel of a transistor is provided in this exemplary embodiment. Figure 1 and Figure 2As shown, the transistor can be a junctionless field-effect transistor (JFET). The transistor may include a channel 100, a gate structure 200, a first electrode assembly 300, and a second electrode assembly 400. The channel 100 extends along a first direction. The gate structure 200 may be located on one side, both sides, or on the outer periphery of the channel 100 in a second direction, with the second direction perpendicular to the first direction. The gate structure 200 includes a gate electrode 201, which is insulated from the channel 100. The first electrode assembly 300 and the second electrode assembly 400 are respectively located on both sides of the gate structure 200 in the first direction and are both connected to the channel 100. At least one of the first electrode assembly 300 and the second electrode assembly 400 may have its orthographic projection on the first plane P1 overlap with the orthographic projection of the channel 100 on the first plane P1, wherein the first plane P1 is perpendicular to the second direction and parallel to the first direction; or, the orthographic projections of the first electrode assembly 300 and the second electrode assembly 400 on the first plane P1 may not overlap with the orthographic projection of the channel 100 on the first plane P1, and the two ends of the gate structure 200 in the first direction may be flush with the two ends of the channel 100 in the first direction, thereby reducing the minimum distance between the gate electrode 201 and the first electrode assembly 300 or the second electrode assembly 400 in the first direction. Thus, the transistor of this embodiment can reduce the distance between the gate electrode and the source / drain, thereby improving the transistor's electrical performance.

[0035] In some exemplary embodiments, such as Figure 1 and Figure 2 As shown, a channel 100 is disposed on a substrate 600, which is parallel to a first plane P1, and a gate structure 200 is located on the side of the channel 100 away from the substrate 600. However, it is not limited to this. For example, the substrate 600 may be perpendicular to the first plane P1 and perpendicular to a first direction, such that the channel 100 is perpendicular to the substrate 600, and a first electrode assembly 300 or a second electrode assembly 400 may be disposed on the substrate 600.

[0036] In some exemplary embodiments, such as Figure 1 and Figure 2 As shown, the channel 100 can be constructed of a semiconductor thin film material. The gate electrode can generate effective control, greatly reducing the drain-induced barrier lowering (DIBL) effect. DIBL is a phenomenon that leads to a decrease in the device's threshold voltage, affecting device performance. In some exemplary embodiments, the material of the channel 100 can be indium gallium zinc oxide (IGZO), but is not limited to this; for example, it can be silicon or other thin film channel materials, such as amorphous silicon.

[0037] In some exemplary embodiments, such as Figure 1 and Figure 2As shown, the first electrode assembly 300 may include a first electrode 301 and a first contact terminal 302, and the second electrode assembly 400 may include a second electrode 401 and a second contact terminal 402. The extension direction of the channel 100 is parallel to the substrate 600, that is, the substrate 600 is parallel to the first direction. The substrate 600 is located on one side of the channel 100 in the second direction. The first electrode 301 and the second electrode 401 may be located on the substrate 600 and are respectively located at both ends of the channel 100 in the first direction, such that the orthographic projections of the first electrode 301 and the second electrode 401 on the first plane P1 do not overlap with the orthographic projection of the channel 100 on the substrate 600. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto. For example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 can have the same doping type as the channel 100, that is, the first electrode 301 and the second electrode 401 can be made of the same material as the channel 100, both being semiconductor thin film materials. However, this is not limited to this; for example, the first electrode 301 and the second electrode 401 can be made of metallic materials, while the channel 100 is a semiconductor thin film material. In this example, the first electrode 301 and the second electrode 401 have the same doping type or the same metallic conductive material, that is, in this embodiment, the transistor is a junctionless transistor. In this example, the materials of the first electrode 301 and the second electrode 401 can be titanium nitride (TiN) or tungsten (W). The thickness of the first electrode 301 and the thickness of the second electrode 401 are both equal to the thickness of the channel 100. The thickness of the first electrode 301 can be the dimension of the first electrode 301 in the second direction, the thickness of the second electrode 401 can be the dimension of the second electrode 401 in the second direction, and the thickness of the channel 100 can be the dimension of the channel 100 in the second direction.

[0038] In some exemplary embodiments, such as Figure 1As shown, the first contact terminal 302 is located on the side of the first electrode 301 away from the substrate (not shown) in the second direction, and the second contact terminal 402 is located on the side of the second electrode 401 away from the substrate (not shown) in the second direction, such that the gate structure 200 is located between the first contact terminal 302 and the second contact terminal 402. The materials of the first contact terminal 302 and the second contact terminal 402 may be the same, and may both be metallic materials, but are not limited thereto; for example, they may be other conductive materials. For example, a conductive layer (not shown) is provided in the area where the first electrode assembly 300 and / or the second electrode assembly 400 contacts the channel 100. That is, a conductive layer may be provided between the first electrode 301 and the channel 100, and / or between the second electrode 401 and the channel 100, between the first contact terminal 302 and the channel 100, and / or between the second contact terminal 402 and the channel 100. The material of the conductive layer may include indium tin oxide (ITO), but is not limited to this. For example, it may be other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrodes and the channel, which helps to increase the current. The heights of the first contact terminal 302 and the second contact terminal 402 may be the same, both being H1. The heights of the first contact terminal 302 and the second contact terminal 402 may be the dimensions of the first contact terminal 302 and the second contact terminal 402 in the second direction, respectively. In addition, the first electrode assembly 300 and the second electrode assembly 400 may be symmetrically arranged according to the gate structure 200.

[0039] In some exemplary embodiments, such as Figure 1 and Figure 2As shown, the orthographic projection of the first contact terminal 302 on the first plane P1 overlaps with the orthographic projection of the channel 100 on the first plane P1. The end of the first contact terminal 302 near the substrate (not shown) can contact the channel 100 and the first electrode 301, such that a portion of the orthographic projection of the first contact terminal 302 on the first plane P1 lies within the orthographic projection of the channel 100 on the first plane P1, and the other portion lies within the orthographic projection of the first electrode 301 on the first plane P1. Similarly, the orthographic projection of the second contact terminal 402 on the first plane P1 overlaps with the orthographic projection of the channel 100 on the first plane P1. The end of the second contact terminal 402 near the substrate (not shown) can contact the channel 100 and the second electrode 401, such that a portion of the orthographic projection of the second contact terminal 402 on the first plane P1 lies within the orthographic projection of the channel 100 on the first plane P1, and the other portion lies within the orthographic projection of the second electrode 401 on the first plane P1. The first contact terminal 302 is positioned close to the end face of the gate structure 200 and contacts the gate structure 200, while the second contact terminal 402 is also positioned close to the end face of the gate structure 200 and contacts the gate structure 200. This increases the contact area between the first contact terminal 302 and the channel 100, and increases the contact area between the second contact terminal 402 and the channel 100, lowering the potential barrier and improving ion distribution and concentration, thereby further enhancing transistor performance. Currently, in related junctionless field-effect transistors, the gate electrode competes with the source / drain electrode for channel control, resulting in a potential barrier between the gate electrode and the source / drain electrode. This causes a dip in the electric field and electron density at the barrier, leading to a significant reduction in the on-state current. In contrast, the transistor in this example lowers the potential barrier and improves performance by increasing the contact area between the first electrode 301 (source electrode) and / or the second electrode 401 (drain electrode) and the channel 100.

[0040] Figure 3 for Figure 1 A first schematic diagram of the transistor fabrication process. Figure 4 for Figure 1 A second schematic diagram of the transistor fabrication process is shown. Figure 5 for Figure 1 The third schematic diagram of transistor fabrication in the image. Figure 6 for Figure 1 The fourth schematic diagram of transistor fabrication in the figure, in some exemplary embodiments, such as Figures 1 to 6As shown, the orthographic projection of the gate structure 200 onto the first plane P1 lies within the orthographic projection of the channel 100 onto the first plane P1. In addition to the gate electrode 201, the gate structure 200 also includes a gate insulating layer 202. The material of the gate electrode 201 may include polysilicon, titanium nitride (TiN), indium zinc oxide (IZO), or tungsten (W), etc.; the material of the gate insulating layer 202 may include insulating high-dielectric-constant materials or low-dielectric-constant materials, such as silicon oxide, hafnium oxide, etc. A gate insulating layer 202 is disposed on the channel 100 and forms a receiving groove 204 with its opening facing away from the substrate (not shown in the figure). The gate electrode 201 can be located within the receiving groove 204. That is, the gate insulating layer 202 covers the end face of the gate electrode 201 near the channel 100 in the second direction, the end face near the first electrode assembly 300 in the first direction, and the end face near the second electrode assembly 400, so that the gate electrode 201 can be separated from the channel 100, the first electrode assembly 300, and the second electrode assembly 400. The gate insulating layer 202 can be formed by depositing an insulating material thin film, and the thickness of the gate insulating layer 202 can be the thickness of the insulating material thin film.

[0041] In some exemplary embodiments, such as Figures 1 to 6 As shown, the first contact terminal 302 can contact one end face of the gate insulating layer 202 in the first direction, and the second contact terminal 402 can contact the other end face of the gate insulating layer 202 in the first direction. The minimum distance (D1) between the gate electrode 201 and the first contact terminal 302 in the first direction can be equal to the minimum distance (D2) between the gate electrode 201 and the second contact terminal 402 in the first direction, and can be equal to the thickness (H) of the gate insulating layer 202. The height (H2) of the gate structure 200 can be the maximum dimension of the gate structure 200 in the second direction. The height of the first contact terminal 302 can be equal to the height of the second contact terminal 402 and both are equal to H1. The height of the first contact terminal 302 can be the maximum dimension of the first contact terminal 302 in the second direction, and the height of the second contact terminal 402 can be the maximum dimension of the second contact terminal 402 in the second direction, wherein H2≤H1, such that the end face of the gate electrode 201 away from the channel 100 is closer to the channel 100 than the end faces of the first contact terminal 302 and the second contact terminal 402 away from the channel 100.

[0042] In some exemplary embodiments, such as Figures 1 to 6As shown, the gate structure 200 may include a first insulating layer 203, which covers the end face of the gate electrode 201 away from the channel 100. The first insulating layer 203 prevents the first contact terminal 302 and the second contact terminal 402 from contacting the end face of the gate electrode 201 away from the channel 100, as contact between the gate electrode 201 and the first contact terminal 302 or the second contact terminal 402 would cause a gate short circuit. During the fabrication of the first contact terminal 302 and the second contact terminal 402, there may be an offset in a first direction, causing the first contact terminal 302 or the second contact terminal 402 to cross the gate insulating layer 202 and approach the gate electrode 201. The provision of the first insulating layer 203 prevents the first contact terminal 302 and the second contact terminal 402 from contacting the gate electrode 201.

[0043] In some exemplary embodiments, such as Figures 1 to 6 As shown, the first insulating layer 203 can be located within the receiving groove 204, and the end face of the first insulating layer 203 away from the gate electrode 201 can be flush with the end face of the gate insulating layer 202 away from the channel 100. The end of the gate insulating layer 202 away from the channel 100 can protrude from the end face of the gate electrode 201 away from the channel 100. The gate electrode 201 and the gate insulating layer 202 can form a first groove 206, the groove depth of the first groove 206 can be H3, and the first insulating layer 203 can be located within the first groove 206.

[0044] In some exemplary embodiments, such as Figures 1 to 6 As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum distance between the gate electrode 201 and the first contact terminal 302 in the first direction, and D2 can be the minimum distance between the gate electrode 201 and the second contact terminal 402 in the first direction. In some exemplary embodiments, 0 < D1 < 30 nm, and / or 0 < D2 < 30 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 10 nm, so that the current is maintained at 10. -6 On the order of A; when the voltage at the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 20nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 30nm, thus maintaining the current at 10 -12 A-level.

[0045] Figure 7 This is a schematic diagram illustrating the fabrication of another transistor in this exemplary embodiment. In some exemplary embodiments, such as... Figure 7As shown, the first insulating layer 203 can have a multilayer stacked structure. The first insulating layer 203 includes a first dielectric layer 207 and a second dielectric layer 208 stacked in a second direction. The first dielectric layer 207 is located on the side of the second dielectric layer 208 closest to the gate electrode 201. The material of the first dielectric layer 207 may be different from the material of the second dielectric layer 208. The material of the first dielectric layer 207 includes silicon nitride, and the material of the second dielectric layer 208 includes silicon oxide, but is not limited to this. A portion of the first insulating layer 203 is located within the receiving groove 204, and another portion protrudes from the receiving groove 204. The first dielectric layer 207 may be located within a first recess 206. The end face of the first dielectric layer 207 away from the gate electrode 201 may be flush with the end face of the gate insulating layer 202 away from the channel 100. The second dielectric layer 208 is located outside the first recess 206. However, this is not the only possibility. For example, the first insulating layer 203 can have a multi-layer stacked structure, comprising a first dielectric layer 207 and a second dielectric layer 208 stacked in the second direction. The first dielectric layer 207 is located on the side of the second dielectric layer 208 near the gate electrode 201, and both the first dielectric layer 207 and the second dielectric layer 208 are located within the first groove 206. Alternatively, the first insulating layer 203 can also have a multi-layer stacked structure, comprising a first dielectric layer 207 and a second dielectric layer 208 stacked in the second direction. The first dielectric layer 207 is located on the side of the second dielectric layer 208 near the gate electrode 201, with a portion of the first dielectric layer 207 within the first groove 206 and another portion protruding from the first groove 206.

[0046] Figure 8 This is a schematic diagram of a method for fabricating a transistor in an exemplary embodiment. In some exemplary embodiments, a fabrication method can be applied to, for example... Figures 1 to 7 The transistor shown, such as Figure 8 As shown, the preparation method may include: S1: Provide a substrate (not shown in the figure).

[0047] S2: Forming a channel 100 on the substrate. In some exemplary embodiments, such as Figure 3 As shown, forming a channel 100 on a substrate includes forming a channel 100, a first electrode 301, and a second electrode 401 on a substrate (not shown) through a patterning process.

[0048] S3: A gate insulating layer 202 is formed on the channel 100. In some exemplary embodiments, such as Figure 3 As shown, forming a gate insulating layer 202 on the channel 100 includes forming a gate insulating layer 202 on the channel 100 through a patterning process, and the gate insulating layer 202 can form a receiving groove 204.

[0049] S4: Deposit gate material 205 on gate insulating layer 202.

[0050] In some exemplary embodiments, such as Figure 3 As shown, depositing gate material 205 on gate insulating layer 202 includes: filling gate material 205 in receiving trench 204 formed by gate insulating layer 202, gate material 205 filling receiving trench 204, and the end face of gate material 205 away from channel 100 being flush with the end face of gate insulating layer 202 away from channel 100.

[0051] S5: A first insulating layer 203 is formed at the end of the gate material 205 away from the channel 100.

[0052] In some exemplary embodiments, such as Figure 4 , Figure 5 and Figure 7 As shown, a first insulating layer 203 is formed at the end of the gate material 205 away from the channel 100, comprising: Etching of gate material 205 forms gate electrode 201, wherein, as Figure 4 As shown, the top of the gate material 205 is etched so that the end of the gate insulating layer 202 away from the channel 100 protrudes from the gate material 205, forming a first groove 206 with a depth of H3. The etched gate material 205 forms the gate electrode 201. The end face of the gate electrode 201 away from the channel 100 is located on the side of the end face of the gate insulating layer 202 away from the channel 100 in the second direction, which is closer to the channel 100. The end face of the gate electrode 201 away from the channel 100 constitutes the bottom of the first groove 206.

[0053] A first insulating layer 203 is formed within the first groove 206, wherein, as shown in the example Figure 5 As shown, a first insulating material can be filled into the first groove 206 to form a first insulating layer 203. The first insulating layer 203 is completely inside the first groove 206, and the end face of the first insulating layer 203 away from the channel 100 is flush with the end face of the gate insulating layer 202 away from the channel 100.

[0054] In some exemplary embodiments, such as Figure 7 As shown, the first insulating layer 203 may be partially located within the first groove 206. During the fabrication of the first insulating layer 203, a first dielectric layer 207 may first be deposited within the first groove 206. The end face of the first dielectric layer 207 away from the channel 100 is flush with the end face of the gate insulating layer 202 away from the channel 100. Subsequently, a second dielectric layer 208 is formed on the first dielectric layer 207. The second dielectric layer 208 is deposited on the end face of the first dielectric layer 207 away from the channel 100. The first dielectric layer 207 and the second dielectric layer 208 constitute the first insulating layer 203.

[0055] S6: Forms the first pole component and the second pole component.

[0056] In some exemplary embodiments, such as Figure 6 As shown, the first electrode assembly and the second electrode assembly are formed, including: First, an interlayer dielectric layer 500 is deposited on a substrate (not shown in the figure). The interlayer dielectric layer 500 covers the first electrode 301, the second electrode 401, and the gate structure 200, as well as the portion of the channel 100 not covered by the gate structure 200. The material of the interlayer dielectric layer 500 may include an insulating material.

[0057] Subsequently, the interlayer dielectric layer 500 is etched to form a first contact hole 501 and a second contact hole 502. The first contact hole 501 can be connected to... Figure 1 The first contact terminal 302 corresponds to the position of the first contact hole 501, which penetrates the interlayer dielectric layer 500, exposing the top surface of the first electrode 301 and the portion of the channel 100 near the first electrode 301. The second contact hole 502 can be connected to... Figure 1 The second contact terminal 402 is positioned corresponding to the second contact hole 502, which penetrates the interlayer dielectric layer 500, exposing the top surface of the second electrode 401 and the portion of the channel 100 near the second electrode 401. The hole walls of the first contact hole 501 and the second contact hole 502 are exposed at both end faces of the gate structure 200 in the first direction.

[0058] Subsequently, conductive material is filled into the first contact hole 501 and the second contact hole 502. The conductive material in the first contact hole 501 forms the first contact terminal 302, and the conductive material in the second contact hole 502 forms the second contact terminal 402. The first electrode 301 and the first contact terminal 302 form the first electrode assembly, and the second electrode 401 and the second contact terminal 402 form the second electrode assembly. Thus, the following is obtained: Figure 1 The transistor shown.

[0059] Figure 9 This is another schematic diagram of a transistor in this exemplary embodiment. In some exemplary embodiments, such as Figure 9As shown, the channel 100 extends parallel to the substrate and is located on one side of the substrate in the second direction. The first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the same side of the channel 100 in the second direction, that is, the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the side of the channel 100 away from the substrate (not shown in the figure). The orthographic projections of the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 on the first plane are all located within the orthographic projection of the channel 100 on the first plane, which is parallel to the substrate. Exemplarily, the regions of the first electrode assembly and / or the second electrode assembly that contact the channel are provided with a conductive layer. The material of the conductive layer may include indium tin oxide (ITO), but is not limited to this; for example, it may be other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrodes and the channel, which helps to increase the current.

[0060] In some exemplary embodiments, such as Figure 9 As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 and the second electrode 401 may be located on the channel 100 and respectively at both ends of the gate structure 200 in the first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto; for example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is a semiconductor thin film material, such as indium gallium zinc oxide. The gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204. The first electrode 301 may contact one end face of the gate insulating layer 202 in the first direction, and the second electrode 401 may contact the other end face of the gate insulating layer 202 in the first direction. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction can be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and can be equal to the thickness of the gate insulating layer 202. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100.

[0061] In some exemplary embodiments, such as Figure 9As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum spacing between the gate electrode 201 and the first electrode 301 in the first direction, and D2 can be the minimum spacing between the gate electrode 201 and the second electrode 401 in the first direction. In some exemplary embodiments, 0 < D1 < 25 nm, and / or 0 < D2 < 25 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 5 nm, so that the current is maintained at 10. -6 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 15nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 25nm, thus maintaining the current at 10 -12 A-level.

[0062] Figure 10 This is another transistor schematic diagram of this exemplary embodiment. In some exemplary embodiments, such as Figure 10 As shown, the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the same side of the channel 100 in the second direction, that is, the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the side of the channel 100 away from the substrate (not shown in the figure). The orthographic projection of the gate structure 200 on the first plane lies within the orthographic projection of the channel 100 on the first plane, and the orthographic projection portions of the first electrode assembly 300 and the second electrode assembly 400 on the first plane lie within the orthographic projection of the channel 100 on the first plane. The first plane is parallel to the first direction and perpendicular to the second direction. Exemplarily, the regions of the first electrode assembly and / or the second electrode assembly that contact the channel are provided with a conductive layer. The material of the conductive layer may include indium tin oxide (ITO), but is not limited to this; for example, it may be other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrodes and the channel, which helps to increase the current.

[0063] In some exemplary embodiments, such as Figure 10As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 and the second electrode 401 may be located on the channel 100 and respectively at both ends of the gate structure 200 in the first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto; for example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is a semiconductor thin film material, such as indium gallium zinc oxide. The gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204. The first electrode 301 may contact one end face of the gate insulating layer 202 in the first direction, and the second electrode 401 may contact the other end face of the gate insulating layer 202 in the first direction. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction can be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and can also be equal to the thickness of the gate insulating layer 202. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100. At the same time, the first electrode 301 extends in the first direction away from the gate structure 200 such that the first electrode 301 protrudes from the channel 100 in the first direction, and extends towards the substrate (not shown in the figure) such that the first electrode 301 covers one end face of the channel 100 in the first direction; the second electrode 401 extends in the first direction away from the gate structure 200 such that the second electrode 401 protrudes from the channel 100 in the first direction, and extends towards the substrate (not shown in the figure) such that the second electrode 401 covers the other end face of the channel 100 in the first direction. Therefore, the orthographic projections of a portion of the first pole 301 and a portion of the second pole 401 on the first plane are located within the orthographic projection of the channel 100 on the first plane, and the orthographic projections of the other portion of the first pole 301 and the other portion of the second pole 401 on the first plane do not overlap with the orthographic projection of the channel 100 on the first plane. The first plane is parallel to the first direction and perpendicular to the second direction.

[0064] In some exemplary embodiments, such as Figure 10As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum spacing between the gate electrode 201 and the first electrode 301 in the first direction, and D2 can be the minimum spacing between the gate electrode 201 and the second electrode 401 in the first direction. In some exemplary embodiments, 0 < D1 < 25 nm, and / or 0 < D2 < 25 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 5 nm, so that the current is maintained at 10. -6 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 15nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 25nm, thus maintaining the current at 10 -12 A-level.

[0065] Figure 11 This is another schematic diagram of a transistor in this exemplary embodiment. In some exemplary embodiments, such as Figure 11 As shown, the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the same side of the channel 100 in the second direction, that is, the first electrode assembly 300, the second electrode assembly 400, and the gate structure 200 are all located on the side of the channel 100 away from the substrate (not shown in the figure). The orthographic projection of the gate structure 200 on the first plane lies within the orthographic projection of the channel 100 on the first plane, and the first plane is parallel to the first direction and perpendicular to the second direction.

[0066] In some exemplary embodiments, such as Figure 11As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 and the second electrode 401 may be located on the channel and respectively at both ends of the gate structure 200 in the first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto; for example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is a semiconductor thin film material, such as indium gallium zinc oxide. The gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204. The first electrode 301 may contact one end face of the gate insulating layer 202 in the first direction, and the second electrode 401 may contact the other end face of the gate insulating layer 202 in the first direction. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction can be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and can also be equal to the thickness of the gate insulating layer 202. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100. Simultaneously, the orthographic projections of the first electrode 301 and the gate structure 200 on the first plane are both located within the orthographic projection of the channel 100 on the first plane, which is parallel to the first direction and perpendicular to the second direction. The second electrode 401 extends in the first direction away from the gate structure 200, causing the second electrode 401 to protrude from the channel 100 in the first direction, and extends towards the substrate (not shown in the figure), causing the second electrode 401 to cover one end face of the channel 100 in the first direction. Therefore, the orthographic projection of a portion of the second electrode 401 onto the first plane lies within the orthographic projection of the channel 100 onto the first plane, and the orthographic projection of another portion of the second electrode 401 onto the first plane does not overlap with the orthographic projection of the channel 100 onto the first plane. However, this is not the only possibility; for example, the orthographic projections of both the second electrode 401 and the gate structure 200 onto the first plane may lie within the orthographic projection of the channel 100 onto the first plane; the orthographic projection of a portion of the first electrode 301 onto the first plane may lie within the orthographic projection of the channel 100 onto the first plane, and the orthographic projection of another portion of the first electrode 301 onto the first plane may not overlap with the orthographic projection of the channel 100 onto the first plane.

[0067] Figure 12 This is another transistor schematic diagram of this exemplary embodiment. In some exemplary embodiments, such as Figure 12As shown, the first electrode assembly 300 and the second electrode assembly 400 are located on opposite sides of the channel 100 in the first direction, and the gate structure 200 is located on one side of the channel 100 in the first direction. The orthographic projections of the first electrode assembly 300 and the second electrode assembly 400 on the first plane do not overlap with the orthographic projections of the channel 100 on the first plane. The first plane is parallel to the first direction and perpendicular to the second direction. For example, the regions of the first electrode assembly and / or the second electrode assembly that contact the channel are provided with a conductive layer. The material of the conductive layer may include indium tin oxide (ITO), but is not limited to this; for example, it may be other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrodes and the channel, thus helping to increase the current.

[0068] In some exemplary embodiments, such as Figure 12 As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 and the second electrode 401 may be located on a substrate (not shown) and respectively at both ends of the channel 100 in a first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto; for example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is a semiconductor thin film material, such as indium gallium zinc oxide.

[0069] In some exemplary embodiments, such as Figure 12 As shown, the gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204. The two ends of the gate structure 200 in a first direction may be flush with the two ends of the channel 100 in the first direction, respectively. One end of the gate insulating layer 202 in the first direction may be flush with one end of the channel 100 in the first direction, and the other end of the gate insulating layer 202 in the first direction may be flush with the other end of the channel 100 in the first direction. The first electrode 301 and the second electrode 401 both extend in a second direction away from the substrate (not shown). The first electrode 301 may contact one end face of the gate insulating layer 202 in the first direction, and the second electrode 401 may contact the other end face of the gate insulating layer 202 in the first direction. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction may be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and may be equal to the thickness of the gate insulating layer 202. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100.

[0070] In some exemplary embodiments, such as Figure 12As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum spacing between the gate electrode 201 and the first electrode 301 in the first direction, and D2 can be the minimum spacing between the gate electrode 201 and the second electrode 401 in the first direction. In some exemplary embodiments, 0 < D1 < 25 nm, and / or 0 < D2 < 25 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 5 nm, so that the current is maintained at 10. -6 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 15nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 25nm, thus maintaining the current at 10 -12 A-level.

[0071] Figure 13 This is another schematic diagram of a transistor in this exemplary embodiment. In some exemplary embodiments, such as Figure 13 As shown, the first electrode assembly 300 and the second electrode assembly 400 are located on opposite sides of the channel 100 in the first direction, and the gate structure 200 is located on one side of the channel 100 in the second direction. The first electrode assembly 300, the second electrode assembly 400, and the channel 100 may all be located on a substrate (not shown in the figure). The orthographic projections of the first electrode assembly 300 and the second electrode assembly 400 on the first plane do not overlap with the orthographic projection of the channel 100 on the first plane. The first plane is parallel to the first direction and perpendicular to the second direction. For example, the area where the first electrode assembly and / or the second electrode assembly contacts the channel is provided with a conductive layer. The material of the conductive layer may include indium tin oxide (ITO), but is not limited to this. For example, it may be other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrodes and the channel, which helps to increase the current.

[0072] In some exemplary embodiments, such as Figure 13 As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 and the second electrode 401 may be located on a substrate (not shown) and respectively at both ends of the channel 100 in a first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto; for example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is a semiconductor thin film material, such as indium gallium zinc oxide.

[0073] In some exemplary embodiments, such as Figure 13 As shown, the gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204, as well as a second insulating layer 209. The material of the second insulating layer 209 may include a low dielectric constant material. The second insulating layer 209 covers both end faces of the gate insulating layer 202 in the first direction, such that one layer of the second insulating layer 209 can be located between the gate electrode 201 and the first electrode 301, and another layer can be located between the gate electrode 201 and the second electrode 401. Therefore, the capacitance between the gate electrode 201 and the first electrode 301 / second electrode 401 is reduced due to the provision of the second insulating layer 209, thereby not reducing the device switching speed. The two ends of the gate structure 200 in the first direction may be flush with the two ends of the channel 100 in the first direction, respectively. One end of the second insulating layer 209 away from the gate electrode 201 may be flush with one end of the channel 100 in the first direction, and the other end of the second insulating layer 209 away from the gate electrode 201 may be flush with the other end of the channel 100 in the first direction. Both the first electrode 301 and the second electrode 401 extend in a direction away from the substrate (not shown in the figure) along a second direction. The first electrode 301 and the second electrode 401 can contact the end face of the second insulating layer 209 away from the gate electrode 201. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction can be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and can be equal to the sum of the thickness of the gate insulating layer 202 and the thickness of the second insulating layer 209. The thickness of the second insulating layer 209 can be the dimension of the second insulating layer 209 in the first direction. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100.

[0074] In some exemplary embodiments, such as Figure 13 As shown, a method for fabricating a transistor includes forming a channel 100 and a gate insulating layer 202 on a substrate. The process of forming the channel 100 and the gate insulating layer 202 on the substrate includes: first forming the channel 100 on the substrate; then forming the gate insulating layer 202 on the side of the channel 100 away from the substrate; and subsequently forming a second insulating layer 209 on the side of the channel 100 away from the substrate, wherein the second insulating layer 209 covers both ends of the gate insulating layer 202 in a first direction.

[0075] In some exemplary embodiments, such as Figure 13As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum spacing between the gate electrode 201 and the first electrode 301 in the first direction, and D2 can be the minimum spacing between the gate electrode 201 and the second electrode 401 in the first direction. In some exemplary embodiments, 0 < D1 < 25 nm, and / or 0 < D2 < 25 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 5 nm, so that the current is maintained at 10. -6 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 15nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 25nm, thus maintaining the current at 10 -12 A-level.

[0076] Figure 14 This is another schematic diagram of a transistor in this exemplary embodiment. Figure 15 for Figure 14 A schematic diagram of a transistor fabrication method is shown in some exemplary embodiments, such as... Figure 14 and Figure 15 As shown, the first electrode assembly 300 and the second electrode assembly 400 are located on opposite sides of the channel 100 in the first direction, and the gate structure 200 is located on one side of the channel 100 in the second direction. The channel 100 extends along the first direction and is perpendicular to the substrate 600. The substrate 600 is perpendicular to the first direction and the first plane P1 and parallel to the second direction. The first electrode assembly 300 is located on the substrate 600, and the first electrode assembly 300, the channel 100, and the second electrode assembly 400 are arranged sequentially in the direction away from the substrate 600. However, this is not limited to the arrangement of the second electrode assembly 400, which is located on the substrate 600, and the second electrode assembly 400, the channel 100, and the first electrode assembly 300 are arranged sequentially in the direction away from the substrate 600. The orthographic projections of the first electrode assembly 300 and the second electrode assembly 400 onto the first plane P1 do not overlap with the orthographic projection of the channel 100 onto the first plane P1. The first plane P1 is parallel to the first direction and perpendicular to the second direction. For example, the area where the first electrode assembly and / or the second electrode assembly contacts the channel is provided with a conductive layer. The material of the conductive layer may include, but is not limited to, indium tin oxide (ITO), for example, other conductive metal oxides. The conductive layer can reduce the contact barrier between the source / drain electrode and the channel, which helps to increase the current.

[0077] In some exemplary embodiments, such as Figure 14 and Figure 15As shown, the first electrode assembly 300 may include a first electrode 301, and the second electrode assembly 400 may include a second electrode 401. The first electrode 301 may be located on the substrate 600, and the first electrode 301 and the second electrode 401 are respectively located at both ends of the channel 100 in a first direction. The first electrode 301 may be a source electrode, and the second electrode 401 may be a drain electrode, but is not limited thereto. For example, the first electrode 301 may be a drain electrode, and the second electrode 401 may be a source electrode. The first electrode 301 and the second electrode 401 may be made of metallic materials, such as titanium nitride (TiN) or tungsten (W), while the channel 100 is made of a semiconductor thin film material, such as indium gallium zinc oxide.

[0078] In some exemplary embodiments, such as Figure 14 and Figure 15 As shown, the gate structure 200 may include a gate insulating layer 202 forming a receiving trench 204 and a gate electrode 201 located within the receiving trench 204. The two ends of the gate structure 200 in a first direction may be flush with the two ends of the channel 100 in the first direction, respectively. One end of the gate insulating layer 202 in the first direction may be flush with one end of the channel 100 in the first direction, and the other end of the gate insulating layer 202 in the first direction may be flush with the other end of the channel 100 in the first direction. One end of the first electrode 301 and the second electrode 401 in the second direction may be flush with one end of the channel 100 in the second direction. The other ends of the first electrode 301 and the second electrode 401 in the second direction extend towards the side having the gate structure 200 in the second direction. The first electrode 301 may contact one end face of the gate insulating layer 202 in the first direction, and the second electrode 401 may contact the other end face of the gate insulating layer 202 in the first direction. The minimum spacing (D1) between the gate electrode 201 and the first electrode 301 in the first direction can be equal to the minimum spacing (D2) between the gate electrode 201 and the second electrode 401 in the first direction, and can be equal to the thickness of the gate insulating layer 202. The end face of the gate structure 200 away from the channel 100 can be flush with the end faces of the first electrode 301 and the second electrode 401 away from the channel 100.

[0079] In some exemplary embodiments, such as Figure 12 As shown, the extension length of the channel 100 in the first direction is set to L. The ratio of D1 to L can be greater than 0 and less than 0.6, and / or the ratio of D2 to L can be greater than 0 and less than 0.6, wherein D1 can be the minimum spacing between the gate electrode 201 and the first electrode 301 in the first direction, and D2 can be the minimum spacing between the gate electrode 201 and the second electrode 401 in the first direction. In some exemplary embodiments, 0 < D1 < 25 nm, and / or 0 < D2 < 25 nm. In some exemplary embodiments, when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 5 nm, so that the current is maintained at 10. -6On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 15nm, thus maintaining the current at 10 -8 On the order of A; when the voltage of the gate electrode 201 is maintained at 3V, the values ​​of D1 and D2 are both less than 25nm, thus maintaining the current at 10 -12 A-level.

[0080] In some exemplary embodiments, such as Figure 14 and Figure 15 As shown, a method for fabricating a transistor can be applied to, for example... Figure 14 The transistor shown includes: S1: Provide a substrate (not shown in the figure).

[0081] S2: Form a first electrode component 300 on a substrate, for example, a first electrode 301 may be formed.

[0082] S3: A channel 100 is formed on the side of the first electrode 301 away from the substrate 600; S4: A gate insulating layer 202 is formed on the channel 100. Forming the gate insulating layer 202 on the channel 100 includes forming the gate insulating layer 202 on the channel 100 by a patterning process. The gate insulating layer 202 can form a receiving trench 204.

[0083] S5: Deposit gate material on gate insulating layer 202.

[0084] In some exemplary embodiments, depositing gate material on the gate insulating layer 202 includes: filling the receiving trench formed by the gate insulating layer 202 with gate material, the gate material filling the receiving trench, and the end face of the gate material away from the channel 100 being flush with the end face of the gate insulating layer 202 away from the channel 100.

[0085] S6: A first insulating layer 203 is formed at the end of the gate material away from the channel 100.

[0086] In some exemplary embodiments, a first insulating layer 203 is formed at one end of the gate material away from the channel 100, including: The gate material 205 is etched to form a gate electrode 201, and the end face of the gate electrode 201 away from the channel 100 forms a first groove. Subsequently, a first insulating layer 203 is formed in the first groove 206, and the end face of the first insulating layer 203 away from the channel 100 is flush with the end face of the gate insulating layer 202 away from the channel 100.

[0087] S7: Form a second electrode component 400, for example, a second electrode 401 may be formed.

[0088] In some exemplary embodiments, forming the second electrode 401 includes depositing the second electrode 401 on the side of the channel away from the first electrode 301. This results in... Figure 14 The transistor shown.

[0089] Figure 16 This is a schematic diagram of a method for fabricating a transistor in an exemplary embodiment. In some exemplary embodiments, a method for fabricating a transistor, such as... Figure 16 As shown, it includes: Provide substrate; A channel, a gate structure, a first electrode assembly, and a second electrode assembly are formed. The channel extends along a first direction, and the gate structure is located on one side, both sides, or on the outer periphery of the channel in a second direction, which is perpendicular to the first direction. The gate structure includes a gate electrode that is insulated from the channel. The first electrode assembly and the second electrode assembly are respectively located on both sides of the gate electrode in the first direction and are both connected to the channel. The orthographic projection of at least one of the first electrode assembly and the second electrode assembly on a first plane is configured to overlap with the orthographic projection of the channel on the first plane; or, the orthographic projection of the first electrode assembly and the second electrode assembly on the first plane is configured not to overlap with the orthographic projection of the channel on the first plane. The two ends of the gate structure in the first direction are configured to be flush with the two ends of the channel in the first direction. The first plane is parallel to the first direction and perpendicular to the second direction.

[0090] In some exemplary embodiments, a semiconductor device includes the transistor described above, or a transistor obtained by the transistor fabrication method described above.

[0091] In some exemplary embodiments, this application also provides an electronic device including the semiconductor device described above. In some embodiments, the electronic device may include, but is not limited to, storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks.

[0092] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0093] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0094] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0095] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0096] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0098] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A transistor, characterized in that, include: The channel extends along the first direction; A gate structure is located on one side, both sides, or on the outer periphery of the channel in a second direction, wherein the second direction is perpendicular to the first direction, and the gate structure includes a gate electrode that is insulated from the channel. The first electrode assembly and the second electrode assembly are respectively located on both sides of the gate electrode in the first direction and are both connected to the channel; At least one of the first pole assembly and the second pole assembly has its orthographic projection on the first plane arranged to overlap with the orthographic projection of the channel on the first plane; or, The orthographic projections of the first electrode assembly and the second electrode assembly onto the first plane are configured not to overlap with the orthographic projections of the channel onto the first plane. The gate structure at both ends in the first direction is configured to be flush with the two ends of the channel in the first direction. The first plane is parallel to the first direction and perpendicular to the second direction.

2. The transistor according to claim 1, characterized in that, The first electrode assembly, the second electrode assembly, and the gate electrode are all located on the same side of the channel in the second direction.

3. The transistor according to claim 2, characterized in that, The orthographic projection of at least one of the first pole assembly and the second pole assembly onto the first plane is configured to lie within the orthographic projection of the channel onto the first plane.

4. The transistor according to claim 2, characterized in that, At least one of the first electrode assembly and the second electrode assembly is configured to extend toward the side away from the gate electrode in the first direction and cover the end face of the channel in the first direction.

5. The transistor according to claim 1, characterized in that, The first electrode assembly includes a first electrode and a first contact terminal, and the second electrode assembly includes a second electrode and a second contact terminal. The first electrode and the second electrode are respectively located at both ends of the channel in the first direction, and the first contact terminal, the second contact terminal and the gate structure are located on the same side of the channel in the second direction. The first contact terminal contacts one end of the first electrode and the channel in the first direction, and the second contact terminal contacts the other end of the second electrode and the channel in the first direction; The orthographic projection of at least one of the first contact terminal and the second contact terminal on the first plane is configured to overlap with the orthographic projection of the channel on the first plane.

6. The transistor according to claim 1, characterized in that, The gate structure further includes a first insulating layer configured to cover the end face of the gate electrode away from the channel.

7. The transistor according to claim 6, characterized in that, The first insulating layer includes a first dielectric layer and a second dielectric layer stacked together, the first dielectric layer being located on the side of the second dielectric layer closer to the gate electrode, and the first dielectric layer and the second dielectric layer being made of different materials.

8. The transistor according to claim 7, characterized in that, The material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon oxide.

9. The transistor according to claim 6, characterized in that, The gate structure further includes a gate insulating layer, which forms a receiving groove with its opening facing away from the channel. The gate electrode is disposed in the receiving groove, and the first insulating layer is configured to be at least partially located in the receiving groove.

10. The transistor according to claim 1, characterized in that, A conductive layer is provided between the first electrode assembly and the channel, and / or between the second electrode assembly and the channel.

11. The transistor according to claim 1, characterized in that, The first electrode assembly and the second electrode assembly are configured to extend along the second direction toward the side of the channel close to the gate structure, and the first electrode assembly and the second electrode assembly respectively contact the two ends of the gate structure in the first direction.

12. The transistor according to any one of claims 1 to 11, characterized in that, The gate structure further includes a second insulating layer, which is located between the gate electrode and the first electrode assembly, and / or between the gate electrode and the second electrode assembly; The material of the second insulating layer includes a low dielectric constant material.

13. The transistor according to any one of claims 1 to 11, characterized in that, The minimum distance between the first electrode assembly and the gate electrode in the first direction is set to D1, the minimum distance between the second electrode assembly and the gate electrode in the first direction is set to D2, and the extension length of the channel in the first direction is set to L, wherein the ratio of D1 to L is set to be greater than 0 and less than 0.6, and / or the ratio of D2 to L is set to be greater than 0 and less than 0.

6.

14. The transistor according to claim 13, characterized in that, 0 < D1 < 30nm, and / or 0 < D2 < 30nm.

15. A method for fabricating a transistor, characterized in that, include: Provide substrate; A channel, a gate structure, a first electrode assembly, and a second electrode assembly are formed. The channel extends along a first direction, and the gate structure is located on one side, both sides, or on the outer periphery of the channel in a second direction, which is perpendicular to the first direction. The gate structure includes a gate electrode that is insulated from the channel. The first electrode assembly and the second electrode assembly are respectively located on both sides of the gate electrode in the first direction and are both connected to the channel. The orthographic projection of at least one of the first electrode assembly and the second electrode assembly on a first plane is configured to overlap with the orthographic projection of the channel on the first plane. Alternatively, the orthographic projections of the first electrode assembly and the second electrode assembly onto the first plane are configured not to overlap with the orthographic projections of the channel onto the first plane, the gate structure at both ends in the first direction is configured to be flush with the two ends of the channel in the first direction, and the first plane is parallel to the first direction and perpendicular to the second direction.

16. The method for fabricating a transistor according to claim 15, characterized in that, The formation of the channel, gate structure, first electrode assembly, and second electrode assembly includes: Channels are formed on the substrate; A gate insulating layer is formed on the channel, and the gate insulating layer has a receiving groove with the opening facing away from the channel; A gate electrode is formed by depositing gate material within the receiving tank. A first insulating layer is formed at the end of the gate material away from the channel; The first and second pole components are formed.

17. The method for fabricating a transistor according to claim 15, characterized in that, The formation of the channel, gate structure, first electrode assembly, and second electrode assembly includes: A first electrode assembly is formed on the substrate; A channel is formed on the side of the first electrode away from the substrate; A gate insulating layer is formed on the channel, and the gate insulating layer has a receiving groove with the opening facing away from the channel; A gate electrode is formed by depositing gate material in the receiving trench surrounded by the gate insulating layer. A first insulating layer is formed at the end of the gate material away from the channel; A second electrode assembly is formed on the side of the channel away from the substrate.

18. The method for fabricating a transistor according to claim 16 or 17, characterized in that, The formation of a first insulating layer at the end of the gate material away from the channel includes: The gate material is etched, and the end face of the gate electrode away from the channel is configured to be located on the side of the end face of the gate insulating layer away from the channel close to the channel, forming a first groove; The first insulating layer is formed within the first groove.

19. The method for fabricating a transistor according to claim 18, characterized in that, The formation of the first insulating layer within the first groove includes: A first dielectric layer is deposited in the first groove, wherein the end face of the first dielectric layer away from the channel is flush with the end face of the gate insulating layer away from the channel. A second dielectric layer is formed on the first dielectric layer, and the first dielectric layer and the second dielectric layer constitute the first insulating layer.

20. The method for fabricating a transistor according to claim 16 or 17, characterized in that, A gate insulating layer is formed on the channel, the gate insulating layer having a receiving groove with its opening facing away from the channel, including: The gate insulating layer is formed on one side of the channel in the second direction. A second insulating layer is formed on the channel, the second insulating layer covering both ends of the gate insulating layer in the first direction.

21. A semiconductor device, characterized in that, It includes the transistor as described in any one of claims 1 to 14, or the transistor obtained by the method of manufacturing the transistor as described in any one of claims 15 to 20.

22. An electronic device, characterized in that, Including the semiconductor device as described in claim 21.

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