Preparation method of semiconductor structure

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate, forming fin-shaped structures extending in a first direction on the substrate and isolation structures located between the fin-shaped structures, and enabling the fin-shaped structures to protrude out of the isolation structures; depositing an oxide, wherein the oxide covers the surfaces of the fin-shaped structure and the isolation structure; a heat treatment process is performed on the oxide to form an oxide layer. A target layer covering a surface of the oxide layer is formed. Wherein after the heat treatment process is performed on the oxide and before the target layer is formed, surface treatment operation is performed on the oxide layer; and / or the target layer at least comprises a preset target layer, and executing a preset operation when the preset target layer is formed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a semiconductor structure. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and high integration, resulting in increasingly smaller device dimensions. Transistor structures are crucial components of semiconductor architectures, typically formed through processes such as material deposition and etching. During the fabrication of the gate dielectric layer, a thermal processing step is often employed to improve the quality of the resulting material layer. However, this step can easily introduce defects into the subsequently deposited material layer, negatively impacting the semiconductor structure's performance.

[0003] Therefore, there are still many problems in the fabrication process of semiconductor devices that need to be improved. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure. The method includes providing a substrate, forming fin-like structures extending along a first direction and isolation structures located between the fin-like structures on the substrate, depositing an oxide, performing a heat treatment process on the oxide to form an oxide layer and a target layer.

[0005] Among them, the fin-like structure protrudes from the isolation structure, and the oxide covers the surface of the fin-like structure and the isolation structure;

[0006] The target layer covers the surface of the oxide layer;

[0007] Among them, after performing a heat treatment process on the oxide and before forming the target layer, a surface treatment operation is performed on the oxide layer;

[0008] And / or, the target layer includes at least a preset target layer, and a preset operation is performed when the preset target layer is formed.

[0009] In some embodiments, performing a surface treatment operation on the oxide layer after performing a heat treatment process on the oxide layer and before forming the target layer further includes treating the oxide layer with a preset material to form dangling bonds on the surface of the oxide layer.

[0010] In some embodiments, the oxide layer is treated with a preset material to form dangling bonds on the surface of the oxide layer, and further includes treating the oxide layer with a solution containing ammonia and hydrogen peroxide to form hydrogen-oxygen dangling bonds on the surface of the oxide layer.

[0011] In some embodiments, the oxide layer is treated with a preset material to form dangling bonds on the surface of the oxide layer, and further includes treating the oxide layer with a solution containing dilute hydrofluoric acid to form silicon-hydrogen dangling bonds on the surface of the oxide layer.

[0012] In some embodiments, the oxide layer is treated with a preset material to form dangling bonds on the surface of the oxide layer, and further includes connecting the preset dangling bonds to the surface of the oxide layer.

[0013] In some embodiments, forming a target layer includes: forming a seed layer, forming a first target layer on the seed layer, performing a first etching process, and forming a second target layer on the first target layer.

[0014] The seed layer covers the surface of the oxide layer.

[0015] The first target layer covers the surface of the seed layer.

[0016] In the first etching process, the first target layer of a first preset thickness is removed.

[0017] The second target layer covers the surface of the first target layer.

[0018] In some embodiments, the preset target layer is a seed layer; when forming the preset target layer, preset operations are performed, including forming the seed layer for a first duration, forming the first target layer on the seed layer, performing a first etching process, and forming the second target layer on the first target layer.

[0019] The seed layer covers the surface of the oxide layer; and the first duration is longer than the first preset duration.

[0020] The first target layer covers the surface of the seed layer.

[0021] In the first etching process, the first target layer of a first preset thickness is removed.

[0022] The second target layer covers the surface of the first target layer.

[0023] In some embodiments, the preset target layer is a first target layer; when forming the preset target layer, a preset operation is performed, including forming a seed layer, forming the first target layer on the seed layer for a second duration, performing a first etching process, and forming a second target layer on the first target layer.

[0024] The seed layer covers the surface of the oxide layer.

[0025] The first target layer covers the surface of the seed layer; the second duration is longer than the second preset duration.

[0026] In the first etching process, the first target layer of the first preset thickness is removed.

[0027] The second target layer covers the surface of the first target layer.

[0028] In some embodiments, forming fin-like structures extending along a first direction and isolation structures located between the fin-like structures on a substrate includes performing an etching process on the substrate and performing an etching process on the substrate and filling with an isolation material.

[0029] In the etching process, a portion of the substrate is removed to form a fin-like structure on the substrate.

[0030] In the filling and insulating material, an insulating structure is formed between the fin-like structures, with the fin-like structures protruding from the surface of the insulating structure.

[0031] In some embodiments, the oxide layer is made of silicon oxide, and the target layer is made of amorphous silicon.

[0032] The semiconductor structure fabrication method provided in this disclosure includes providing a substrate, forming fin-like structures extending along a first direction and isolation structures located between the fin-like structures on the substrate, depositing an oxide, performing a heat treatment process on the oxide to form an oxide layer and a target layer.

[0033] Among them, the fin-like structure protrudes from the isolation structure, and the oxide covers the surface of the fin-like structure and the isolation structure;

[0034] The target layer covers the surface of the oxide layer;

[0035] Among them, after performing a heat treatment process on the oxide and before forming the target layer, a surface treatment operation is performed on the oxide layer;

[0036] And / or, the target layer includes at least a preset target layer, and a preset operation is performed when the preset target layer is formed.

[0037] In some embodiments, forming fin-like structures extending along a first direction and isolation structures located between the fin-like structures on a substrate includes performing an etching process on the substrate and performing an etching process on the substrate and filling with an isolation material.

[0038] Understandably, performing a thermal treatment process on the oxide after its formation to obtain an oxide layer helps improve the quality of the oxide layer, thereby improving the performance of the final semiconductor structure. However, while using thermal treatment to improve the quality of the oxide layer, some structures on the oxide layer surface that are beneficial for bonding with the target layer formed later are usually eliminated. If the target layer is formed in a conventional manner on this basis, it is very easy to generate a large number of white spots in the final target layer, affecting the electrical performance of the final semiconductor structure. In the embodiments of this disclosure, after performing a thermal treatment process on the oxide, a surface treatment operation is performed on the oxide layer before forming the target layer, and / or the target layer includes at least a preset target layer. Performing a preset operation when forming the preset target layer helps to reduce the generation of defects such as white spots in the target layer to a large extent, and may even result in no white spots. Among them, performing a surface treatment operation helps to reform structures on the surface of the oxide layer that are beneficial for bonding with the target layer formed later, such as dangling bonds. Performing preset operations helps improve the distribution of the target layer on the oxide layer, which is beneficial to improving the growth quality of the target layer, reducing or even eliminating phenomena such as white spots, and improving the electrical and other properties of the final semiconductor structure.

[0039] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0042] Figures 2 to 11 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0043] Figures 12 to 15 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure;

[0044] Figure 16 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure;

[0045] Figure 17 Transmission electron microscope images of semiconductor structures obtained in Experiments 1 to 5 provided for embodiments of this disclosure;

[0046] Figure 18 A schematic diagram illustrating the relationship between processing conditions and target layer thickness in a semiconductor structure provided for different embodiments;

[0047] Figure 19 This disclosure provides a transmission electron microscope image of a preset target layer in a semiconductor structure after performing a preset operation. Detailed Implementation

[0048] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0049] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0050] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] In the fabrication of semiconductor structures, after forming fin-like structures and oxide layers on their surfaces, amorphous silicon layers filling the spaces between the fins are typically obtained through material deposition, etching, and re-deposition. To improve the quality of certain materials, one or more thermal processing steps are often performed after these material layers are formed. However, while thermal processing can improve material quality, it can also negatively impact the subsequent formation of amorphous silicon, causing issues such as white spots.

[0055] Based on this, the technical solution of the present disclosure embodiment is proposed as follows:

[0056] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps:

[0057] Step S101: Provide a substrate, and form fin-like structures extending along a first direction and isolation structures located between the fin-like structures on the substrate, wherein the fin-like structures protrude from the isolation structures;

[0058] Step S102: Deposit oxide, which covers the surface of the fin structure and the isolation structure;

[0059] Step S103: Perform a heat treatment process on the oxide to form an oxide layer;

[0060] Step S104: Form a target layer that covers the surface of the oxide layer; wherein, after performing a heat treatment process on the oxide layer and before forming the target layer, a surface treatment operation is performed on the oxide layer; and / or, the target layer includes at least a preset target layer, and a preset operation is performed when the preset target layer is formed.

[0061] It is understandable that performing a thermal treatment process on the oxide after its formation to obtain an oxide layer helps improve the quality of the oxide layer, thereby improving the performance of the final semiconductor structure. However, while using thermal treatment to improve the quality of the oxide layer, some structures on the oxide layer surface that are beneficial for bonding with the target layer formed later are usually eliminated. If the target layer is formed in a conventional manner on this basis, it is very easy to generate a large number of white spots in the final target layer, affecting the electrical performance of the final semiconductor structure. In the embodiments of this disclosure, after performing a thermal treatment process on the oxide, a surface treatment operation is performed on the oxide layer before forming the target layer, and / or the target layer includes at least a preset target layer. Performing a preset operation when forming the preset target layer helps to reduce the generation of defects such as white spots in the target layer to a large extent, and may even eliminate the generation of white spots. Among them, performing a surface treatment operation helps to reform structures on the surface of the oxide layer that are beneficial for bonding with the target layer formed later, such as dangling bonds. Performing preset operations helps improve the distribution of the target layer on the oxide layer, which is beneficial to improving the growth quality of the target layer, reducing or even eliminating phenomena such as white spots, and improving the electrical and other properties of the final semiconductor structure.

[0062] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0063] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0064] Figures 2 to 11 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 12 to 15 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure; Figure 16A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure;

[0065] Figure 17 Transmission electron microscope images of semiconductor structures obtained in Experiments 1 to 5 provided for embodiments of this disclosure; Figure 18 A schematic diagram illustrating the relationship between processing conditions and target layer thickness in a semiconductor structure provided for different embodiments; Figure 19 This disclosure provides a transmission electron microscope image of a preset target layer in a semiconductor structure after performing a preset operation.

[0066] The preparation method provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0067] First, execute step S101, as follows: Figure 2 and Figure 3 As shown, where, Figure 3 Figure (1) is a schematic diagram of the semiconductor structure during the fabrication process. Figure 3 Figure (2) is Figure 3 An enlarged view of region Q is shown in (1). A substrate 10 is provided, on which fin-like structures 11 extending along a first direction and isolation structures 12 located between the fin-like structures 11 are formed, the fin-like structures 11 protruding from the isolation structures 12. The first direction is parallel to the surface of the substrate 10.

[0068] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0069] In some embodiments, fin-like structures 11 and isolation structures 12 located between the fin-like structures 11 are formed on the substrate 10, including:

[0070] Substrate 10 is provided;

[0071] An etching process is performed on the substrate 10 to remove a portion of the substrate 10 in order to form a fin structure 11 on the substrate 10;

[0072] An insulating material is filled to form an insulating structure 12 between the fin structures 11, the fin structures 11 protruding from the surface of the insulating structure 12.

[0073] In addition to the methods described above, in other embodiments, the fin structure 11 and the isolation structure 12 can also be obtained by forming a material layer on the substrate 10. Specifically, the choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0074] In some embodiments, the material of the isolation structure 12 may include, but is not limited to, oxides, nitrides, oxynitrides, such as silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0075] In actual operation, the materials involved in forming the fin structure 11 and the isolation structure 12 can be grown using one or more thin film deposition processes. Specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.

[0076] Next, proceed with step S102, as follows: Figure 3 As shown, oxide 13a is deposited, which covers the surface of fin structure 11 and isolation structure 12.

[0077] In some embodiments, the material of oxide 13a may include, but is not limited to, at least one or a combination of low dielectric constant materials or high dielectric constant materials.

[0078] In practice, the material of oxide 13a may include, but is not limited to, oxides, such as silicon oxide. However, it is not limited to this. In some embodiments, the material of oxide 13a may also include high-k dielectric materials, which may include, but are not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3).

[0079] In some embodiments, oxide 13a can be formed by a low-temperature atomic layer deposition process.

[0080] In some specific embodiments, the temperature range of the atomic layer deposition process for forming oxide 13a can be between 300°C and 450°C (inclusive), for example, 320°C, 350°C, 370°C, 390°C, 410°C, 430°C, or 450°C.

[0081] Understandably, the oxide 13a formed here is actually a material layer covering the surface of the fin structure 11 and the isolation structure 12. However, due to the limitations of the process conditions, the obtained oxide 13a material layer may have some performance-affecting conditions, such as impurities and defects A, as well as low density.

[0082] Then, proceed with step S103, as follows: Figure 4 As shown, a heat treatment process is performed on oxide 13a to form oxide layer 13.

[0083] In some embodiments, the thickness of the oxide layer 13 can range from [specific range missing]. Left and right (including endpoint values), for example wait.

[0084] In some embodiments, the heat treatment process includes, but is not limited to, at least one or a combination of peak annealing, furnace tube annealing, and other heat treatment processes.

[0085] In some specific embodiments, the heat treatment process can be a peak annealing process with a temperature range between 900°C and 1100°C (inclusive), such as 950°C, 980°C, 1000°C, 1050°C, 1080°C, 1100°C, etc.

[0086] In some embodiments, the time range for heat treatment of oxide 13a using a peak annealing process is between a few milliseconds and a few seconds, such as 50 milliseconds, 500 milliseconds, 1 second, 1.3 seconds, 1.5 seconds, 2 seconds, 2.3 seconds, 2.5 seconds, 3 seconds, etc.

[0087] Understandably, because a relatively low process temperature was used to form oxide 13a, impurities and other defects (see details) are easily generated in the obtained oxide 13a. Figure 3 In addition, there are issues such as low density. In conventional processes, in order to meet production schedules or achieve predetermined production efficiency, no additional specific processing operations are usually performed on the obtained oxide 13a. As a result, defects such as impurities A are retained. In addition, the density may also be low, which can easily have an adverse effect on the performance of the final semiconductor structure.

[0088] In this embodiment of the present disclosure, performing a heat treatment process after the oxide 13a formation step helps to reduce or eliminate defects A such as impurities contained in the oxide 13a, which helps to improve the quality and density of the oxide layer 13 obtained after the step, thereby improving the performance of the final semiconductor structure.

[0089] Next, proceed to step S104, as follows: Figures 7 to 10 , Figures 12 to 15 and Figure 16 As shown, a target layer 144 is formed covering the surface of the oxide layer 13, wherein a surface treatment operation is performed on the oxide layer 13 after a heat treatment process is performed on the oxide 13a and before the target layer 14 is formed; and / or, the target layer 14 includes at least a preset target layer, and a preset operation is performed when the preset target layer is formed.

[0090] In some embodiments, the material of the target layer 14 includes amorphous silicon (A-Si).

[0091] In some embodiments, the target layer 14 may be used as a pseudo gate layer of a semiconductor structure.

[0092] It should be noted that the preparation method provided in this embodiment can not only obtain amorphous silicon with good performance on the oxide layer 13 after heat treatment, but also obtain a material layer with good performance and other components on the oxide layer 13. Specifically, the specific composition of the material can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0093] Understandably, in this embodiment of the present disclosure, performing a heat treatment process on oxide 13a after its formation helps to effectively improve the quality of the oxide layer 13 obtained after this operation step. For example, it can improve the density and purity of the oxide layer 13, thereby improving the performance of the final semiconductor structure. However, it should be noted that while using heat treatment to improve the quality of oxide layer 13, some structures on the surface of oxide layer 13 that are beneficial for bonding with the target layer 14 formed later are also easily repaired. At this time, the number of dangling bonds, such as Si-H / -OH bonds, on the surface of the obtained oxide layer 13 will be significantly reduced, that is, the number of attachment sites on the surface of oxide layer 13 for attaching the target layer material to be formed later will be significantly reduced. This will increase the incubation time required for material layer growth during the formation of target layer 14.

[0094] Building upon the above, if the target layer is formed using conventional methods, it is highly likely that the target layer will not grow completely when filling the trenches between adjacent fin structures. This can result in gaps (e.g., at the contact point between the oxide layer and the target layer, corresponding to white spots), unclear boundaries of the target layer on the oxide layer, and large gaps in the trenches (e.g., in the middle of the trench between adjacent fin structures), leading to defects such as white spots. These defects will adversely affect subsequent manufacturing processes, ultimately impacting electrical properties and yield.

[0095] In order to improve the above situation, this disclosure provides a variety of ways to improve the situation where the surface of the oxide layer 13 is changed by the heat treatment process, which is not conducive to the growth of the target layer 14.

[0096] In some embodiments, such as Figure 5 and Figure 6 As shown, after performing a heat treatment process on oxide 13a and before forming target layer 14, the surface treatment operation on oxide layer 13 includes:

[0097] The oxide layer 13 is treated with a pre-selected material to form dangling bonds on the surface of the oxide layer 13.

[0098] In some embodiments, such as Figure 5 As shown, the oxide layer 13 is treated with a preset material to form dangling bonds on the surface of the oxide layer 13, including:

[0099] The oxide layer 13 is wet-treated with a solution containing ammonia and hydrogen peroxide to form hydrogen-oxygen dangling bonds on the surface of the oxide layer 13.

[0100] In some embodiments, the volume ratio of ammonia (NH4OH): hydrogen peroxide (H2O2): water (H2O) ranges from (0.5–3):(1–4.5):(25–150) (inclusive), such as 1:2:50 or 2:3:100. The treatment time ranges from 55s to 65s (inclusive), such as 56s, 57s, 58s, 59s, 60s, 61s, 62s, 63s, 64s, etc.

[0101] In some embodiments, the solution containing ammonia and hydrogen peroxide may include an SC1 solution, which is short for Stand Clean 1 solution. SC1 is a mixed solution composed of deionized water, hydrogen peroxide, and ammonia. The concentration can be a commercially available standard ratio, and the treatment temperature can be room temperature, 40°C, or 60°C, etc.

[0102] When the oxide layer 13 is treated with a solution containing ammonia and hydrogen peroxide, there is virtually no loss in the thickness of the oxide layer 13. After the deposition process of the target layer 14 is completed, the thickness relationship between the material layers obtained is the same as that obtained by conventional techniques. There is no performance degradation of the semiconductor structure due to the loss of oxide layer 13 thickness, and the entire production process does not require targeted adjustments due to thickness changes, which helps maintain the stability of the production process. In addition, when the oxide layer 13 is treated with a solution containing ammonia and hydrogen peroxide, the solution also removes particulate matter on the surface of the oxide layer 13, which helps to further improve the performance of the final target layer 14.

[0103] In other embodiments, such as Figure 6 As shown, the oxide layer 13 is treated with a predetermined material to form dangling bonds on the surface of the oxide layer 13, including:

[0104] The oxide layer 13 is wet-treated with a solution containing dilute hydrofluoric acid (HF) to form silicon-hydrogen dangling bonds on the surface of the oxide layer 13.

[0105] Continue to refer to Figure 6 It can be seen that when the surface of oxide layer 13 is treated with a solution containing dilute hydrofluoric acid (HF), the reaction process can include four stages: a1 to a4. In stage a1, HF molecules attack Si-O bonds. In stage a2, water molecules in the structure obtained in stage a1 are released. In stage a3, the Si-F bonds formed in the previous stage lead to the polarization of Si-Si antibonds. When HF attacks the above antibonds, SiFx will be released, thus reaching stage a4, which is the stage of silicon-hydrogen dangling bond formation.

[0106] Figure 6 In some embodiments, the volume ratio of water to stock hydrofluoric acid in the dilute hydrofluoric acid (HF) solution used to treat the oxide layer 13 ranges from (150 to 250):(0.5 to 1.5) (inclusive), for example: 150:0.5, 150:0.8, 150:1, 200:0.5, 200:0.8, 200:1, 250:0.5, 250:0.8, 250:1, etc. The temperature conditions used can include room temperature or other suitable temperatures, which can be flexibly selected according to actual conditions and are not specifically limited here. The treatment time ranges from 5s to 25s (inclusive), for example: 5s, 8s, 10s, 15s, 18s, 20s, 22s, 25s, etc.

[0107] In some embodiments, a surface treatment operation at room temperature with a volume ratio of 200:1 (H2O:HF) and a time range of 10–20 seconds can be used to help prevent excessive thickness loss of the oxide layer 13 or insufficient surface treatment. At this time, the etching rate of the dilute hydrofluoric acid solution on the oxide layer 13 is approximately [missing information]. The thickness of oxide layer 13 lost during the entire process is less than [amount missing]. For example

[0108] It is understandable that, compared with the previous embodiment, in this embodiment, since the preset material used to perform the surface treatment operation is a dilute hydrofluoric acid solution, a certain thickness of oxide layer 13 will be lost during the process. Therefore, in the step of forming oxide layer 13, an oxide layer 13 with a greater thickness than that in the previous embodiment can be formed.

[0109] In some embodiments, when the preset material used to perform the surface treatment operation is a dilute hydrofluoric acid solution, the difference between the thickness of the treated oxide layer 13 and the thickness of the oxide layer 13 treated with a solution containing ammonia and hydrogen peroxide ranges from... Between (including endpoint values), for example: When the thickness range of the oxide layer 13 in this embodiment meets the above conditions, it helps the various parameters of the obtained oxide layer 13 to meet the requirements of the target parameters (e.g., MTS, module target parameters, etc.) needed in the production process.

[0110] In any of the above embodiments, whether the oxide layer 13 is treated with a solution containing ammonia and hydrogen peroxide or a solution containing dilute hydrofluoric acid, the gap size of the target layer 14 at the midpoint of the groove between two adjacent fin structures 11 can be effectively reduced. Simultaneously, it also significantly improves the yield.

[0111] In some other embodiments, the oxide layer 13 is treated with a pre-selected material to form dangling bonds on the surface of the oxide layer 13, including:

[0112] A pre-set dangling key is attached to the surface of oxide layer 13.

[0113] In some embodiments, the preset dangling key may include any suitable dangling key, which can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0114] In some specific embodiments, the dangling bonds connected to the surface of the oxide layer 13 may include, but are not limited to, nitrogen-hydrogen (NH) dangling bonds.

[0115] In any of the above embodiments, such as Figures 7 to 10As shown, target layer 14 is formed, including:

[0116] Seed layer 14a is formed, which covers the surface of oxide layer 13 (see details). Figure 7 );

[0117] A first target layer 141 is formed on the seed layer 14a, and the first target layer 141 covers the surface of the seed layer 14a (see details). Figure 8 );

[0118] Perform a first etching process to remove the first target layer 141 of a first preset thickness (see details). Figure 9 );

[0119] A second target layer 142 is formed on the first target layer 141, and the second target layer 142 covers the surface of the first target layer 141 (see details). Figure 10 ).

[0120] In some embodiments, after the formation of the first target layer 141 and the first etching process are completed, and before the process for forming the second target layer 142 is performed, the method may further include:

[0121] The residual gases in the reaction chamber are purged to prevent them from adversely affecting the properties of the subsequently formed materials.

[0122] As can be seen, in this embodiment, the target layer 14 is obtained using a deposition-etch-deposition (DED) process. The thickness of the material removed in the etching step can be determined by considering factors such as the thickness of the formed material and its growth characteristics, and is not specifically limited here.

[0123] In some embodiments, to obtain a higher quality target layer 14, the deposition and etching cycles may be performed multiple times, such as 2, 3, 5, a dozen, several dozen, or even more times, and a deposition process is performed again after these cycles. In the embodiments of this disclosure, the specific number of cycles used is not specifically limited, and the operator can flexibly choose according to the actual situation.

[0124] In some embodiments, the precursor used in forming the seed layer 14a may include silane (Si2H6), and the precursor used in forming the first target layer 141 and the second target layer 142 may include silane (SiH4).

[0125] Understandably, because the surface treatment operation performed after the formation of oxide layer 13 and before the formation of target layer 14 creates dangling bonds on the surface of oxide layer 13, the number of attachment sites on oxide layer 13 increases significantly. As a result, during the formation of target layer 14, seed layer 14a can be better connected with the dangling bonds formed on the surface of oxide layer 13 after the above operation, so that seed layer 14a can be formed better and more uniformly on the surface of oxide layer 13. This helps to improve the growth quality of target layer 14 in the final semiconductor structure, reduce or even eliminate the occurrence of white spots, and improve the electrical and other properties of the final semiconductor structure.

[0126] To verify whether surface treatment of the oxide layer 13 after heat treatment with the preset material would reduce the occurrence of defects such as white spots in the target layer 14, the following experiment was conducted:

[0127] Experiment 1: Atomic Layer Deposition Oxide Layer + Heat Treatment Process (ANN (Spike Annealing)) + DED

[0128] Experiment 2: Atomic layer deposition oxide layer + heat treatment process (FUR ANN, furnace tube annealing (950℃, 30min)) + DED

[0129] Experiment 3: Atomic Layer Deposition of Oxide Layer + DED

[0130] Experiment 4: Atomic layer deposition oxide layer + (ANN, (spike, peak annealing)) + wet dilute hydrofluoric acid (DHF) + DED

[0131] Experiment 5: Atomic layer deposition oxide layer + (ANN, (spike, peak annealing)) + wet SC1 + DED

[0132] The semiconductor structures obtained in Experiments 1 to 5 were obtained using transmission electron microscopy (TEM). Figure 17 The results are shown in the figure.

[0133] It can be seen that, in experiments 1 and 2, where the oxide layer 13 was formed using the same atomic layer deposition process but without surface treatment, the target layer 14 had a relatively long incubation time during growth due to the material contained in it. This resulted in a smaller size for the target layer 14, making it prone to over-etching. The final target layer 14 exhibited obvious defects such as white spots, and the gaps in the middle of the trenches between adjacent fin structures 11 (which can be understood as the unfilled portion of the target layer 14) also had a large size, indicating that the target layer 14 did not completely fill the trenches. In Experiment 3 (which can be used as a reference group), the oxide layer 13 was also formed by atomic layer deposition. However, without any heat treatment process, the target layer 14 obtained basically did not show defects such as white spots. Moreover, the gap in the middle position of the groove between two adjacent fin structures 11 (which can be understood as the part not filled by the target layer 14) was much smaller than that in Experiments 1 and 2, and was not very obvious. This shows that the oxide layer 13 obtained by heat treatment process does have an adverse effect on the growth of the target layer 14, resulting in defects such as white spots, and the gap size in the middle position of the groove between two adjacent fin structures 11 is relatively large.

[0134] In Experiments 4 and 5, the use of pre-selected materials (such as dilute hydrofluoric acid or SC1) after heat treatment and before forming the target layer 14 increased the number of adhesion sites on the surface of the oxide layer 13 and made their distribution more uniform. This resulted in virtually no defects such as white spots in the final target layer 14. Furthermore, the gap at the midpoint of the groove between two adjacent fin-like structures 11 (which can be understood as the portion not filled by the target layer 14) was significantly smaller than in Experiment 3. This demonstrates that the preparation method provided in this embodiment can obtain a high-quality oxide layer 13 while simultaneously achieving a well-grown target layer 14 through heat treatment, significantly reducing the occurrence of defects such as white spots in the target layer 14.

[0135] In addition, to verify the inference that SC1 / HF can increase the number of attachment sites and reduce the incubation time during the growth of target layer 14, a control experiment was designed using non-production wafers (NPWs). We prepared three non-production wafers (NPWs) (film stack: Sub+1K (1000 Å thick oxide layer) with thermal processing), where the first NPW underwent wet SC1 treatment, the second underwent wet DHF treatment, and the last was left untreated, followed by amorphous silicon deposition. The results showed that, as Figure 18As shown, the target layer 14 treated with SC1 / DHF grew thicker, which proves that the inference that SC1 / HF reduces the incubation time during material growth is correct, and SC1 / HF does indeed have the ability to supplement the number of attachment sites.

[0136] In addition to providing surface treatment operations to improve the growth quality of the target layer 14, this disclosure also provides other methods to obtain a better target layer 14, such as extending the growth time of the preset target layer L. After these operations, the target layer 14 can have good quality, better coverage and filling capabilities, and can meet production requirements even when the process node is scaled down.

[0137] It should be noted that the following technical solutions can be implemented alone to obtain a target layer 14 of good quality, but are not limited thereto. They can also be combined with the surface treatment operation provided in any of the above embodiments to work together. Specifically, they can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0138] In some embodiments, such as Figures 12 to 15 As shown, the preset target layer L is seed layer 14a; when forming the preset target layer L, preset operations are performed, including:

[0139] A seed layer 14a is formed for a first duration, and the seed layer 14a covers the surface of the oxide layer 13; wherein, the first duration is longer than a first preset duration (see details). Figure 12 );

[0140] A first target layer 141 is formed on the seed layer 14a, and the first target layer 141 covers the surface of the seed layer 14a (see details). Figure 13 );

[0141] Perform a first etching process to remove the first target layer 141 of a first preset thickness (see details). Figure 14 );

[0142] A second target layer 142 is formed on the first target layer 141, and the second target layer 142 covers the surface of the first target layer 141 (see details). Figure 15 ).

[0143] Here, the first preset duration can be understood as the time taken to grow the seed layer 14a in conventional processes after obtaining the oxide layer 13 using atomic layer deposition (ALD). In this embodiment, an operation with a first duration longer than the first preset duration can effectively increase the uniformity of the distribution of the seed layer 14a on the oxide layer 13. This embodiment can effectively compensate for the problem of prolonged incubation time during seed layer 14a growth caused by the execution of heat treatment processes by extending the growth time of the seed layer 14a, so that the obtained target layer 14 can have good quality, such as reducing the occurrence of problems like white spots.

[0144] In other embodiments, such as Figure 16 As shown, the preset target layer L is the first target layer 141; when forming the preset target layer L, preset operations are performed, including:

[0145] Seed layer 14a is formed, and seed layer 14a covers the surface of oxide layer 13;

[0146] A first target layer 141 is formed on the seed layer 14a using a second duration, and the first target layer 141 covers the surface of the seed layer 14a; wherein the second duration is longer than a second preset duration;

[0147] Perform a first etching process to remove the first target layer 141 of a first preset thickness;

[0148] A second target layer 142 is formed on the first target layer 141, and the second target layer 142 covers the surface of the first target layer 141.

[0149] Here, the second preset duration can be understood as the time taken to grow the first target layer 141 in conventional processes after obtaining the oxide layer 13 using atomic layer deposition. This embodiment effectively compensates for the problem of uneven distribution of the seed layer 14a on the oxide layer 13 due to the extended incubation time during the formation of the seed layer 14a caused by the heat treatment process, by extending the growth time of the first target layer 141. This ensures that in the blank areas on the oxide layer 13 where the seed layer 14a has not formed, the first target layer 141 has a sufficiently long growth time, thus providing sufficient conditions for the formation of the material contained in the first target layer 141 in the blank areas. This allows the obtained target layer 14 to have good quality, such as reducing the occurrence of problems like white spots.

[0150] from Figure 19 The growth results of the target layer 14 show that even without surface treatment operations, performing preset operations (such as extending the growth time) on the target layer L alone can also obtain a target layer 14 with good growth effect, reducing the occurrence of problems such as white spots, and the gap size is also significantly reduced.

[0151] It should be noted that the method for preparing the semiconductor structure provided in this disclosure can be applied to any semiconductor device including the structure, and no further limitations are imposed here.

[0152] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided on which fin-like structures extending along a first direction and isolation structures located between the fin-like structures are formed; the fin-like structures protrude from the isolation structures. An oxide is deposited, which covers the surfaces of the fin structure and the isolation structure; The oxide is subjected to a heat treatment process to form an oxide layer; and A target layer is formed covering the surface of the oxide layer; Specifically, after performing a heat treatment process on the oxide and before forming the target layer, a surface treatment operation is performed on the oxide layer; And / or, the target layer includes at least a preset target layer, and a preset operation is performed when the preset target layer is formed.

2. The preparation method according to claim 1, characterized in that, After performing a heat treatment process on the oxide and before forming the target layer, the surface treatment operation on the oxide layer includes: The oxide layer is treated with a preset material to form dangling bonds on the surface of the oxide layer.

3. The preparation method according to claim 2, characterized in that, The oxide layer is treated with a predetermined material to form dangling bonds on the surface of the oxide layer, including: The oxide layer is treated with a solution containing ammonia and hydrogen peroxide to form hydrogen-oxygen dangling bonds on the surface of the oxide layer.

4. The preparation method according to claim 2, characterized in that, The oxide layer is treated with a predetermined material to form dangling bonds on the surface of the oxide layer, including: The oxide layer is treated with a solution containing dilute hydrofluoric acid to form silicon-hydrogen dangling bonds on the surface of the oxide layer.

5. The preparation method according to claim 2, characterized in that, The oxide layer is treated with a predetermined material to form dangling bonds on the surface of the oxide layer, including: A pre-set dangling key is attached to the surface of the oxide layer.

6. The preparation method according to any one of claims 1-5, characterized in that, Forming the target layer includes: A seed layer is formed, which covers the surface of the oxide layer; A first target layer is formed on the seed layer, and the first target layer covers the surface of the seed layer; Perform a first etching process to remove a first target layer of a first preset thickness; A second target layer is formed on the first target layer, and the second target layer covers the surface of the first target layer.

7. The preparation method according to claim 1, characterized in that, The preset target layer is a seed layer; When forming the preset target layer, preset operations are performed, including: A seed layer is formed over a first duration, the seed layer covering the surface of the oxide layer; wherein the first duration is longer than a first preset duration; A first target layer is formed on the seed layer, and the first target layer covers the surface of the seed layer; Perform a first etching process to remove a first target layer of a first preset thickness; A second target layer is formed on the first target layer, and the second target layer covers the surface of the first target layer.

8. The preparation method according to claim 1, characterized in that, The preset target layer is the first target layer; When forming the preset target layer, preset operations are performed, including: A seed layer is formed, which covers the surface of the oxide layer; A first target layer is formed on the seed layer for a second duration, and the first target layer covers the surface of the seed layer; wherein the second duration is greater than a second preset duration; Perform a first etching process to remove a first target layer of a first preset thickness; A second target layer is formed on the first target layer, and the second target layer covers the surface of the first target layer.

9. The preparation method according to claim 1, characterized in that, Forming fin-like structures extending along a first direction and isolation structures located between the fin-like structures on the substrate includes: An etching process is performed on the substrate to remove a portion of the substrate in order to form the fin structure on the substrate; An insulating material is filled to form an insulating structure between the fin-like structures, the fin-like structures protruding from the surface of the insulating structure.

10. The preparation method according to claim 1, characterized in that, The oxide layer is made of silicon oxide, and the target layer is made of amorphous silicon.

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