Semiconductor device and method for manufacturing polycrystalline opening thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device at a polycrystal opening, the semiconductor device comprises a substrate, an epitaxial layer of a first doping type, a plurality of bases of a second doping type, a well region, a source region, a grid electrode, a first doping buried layer, a second doping buried layer and a source electrode metal layer, a groove is etched in the epitaxial layer, the bases are arranged in the epitaxial layer, and the source electrode metal layer is arranged in the groove. The side edges of the well region and the source region are connected with the base; the grid electrode is formed by polycrystalline silicon which is filled in the groove and is provided with a dug hole; the first doped buried layer and the second doped buried layer are formed at the bottom end of the grid electrode, the first doped buried layer and the second doped buried layer are not connected to the base electrode, the first doped buried layer is of a first doping type, the second doped buried layer is of a second doping type different from the first doping type, and the source electrode metal layer is connected with the base electrode, the source electrode region and the second doped buried layer. The problems caused by the charge storage / accumulation effect can be effectively solved, the device is not easily influenced by the groove, and the design window and the process window of the device can be larger.

Description

Technical Field

[0001] This application relates to the field of semiconductor power devices, and in particular to semiconductor devices and methods for manufacturing the same in polycrystalline openings. Background Technology

[0002] TrenchMOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor) is a transistor structure that is an advanced technology developed from the traditional PlanarMOS (Plane Metal-Oxide-Semiconductor Field-Effect Transistor). TrenchMOS technology achieves higher integration and better electrical performance by etching deep trenches on the surface of semiconductor material and forming transistors on the sidewalls of the trenches.

[0003] Trench MOSFETs embed the gate into the substrate, forming a vertical channel. Compared to Planar MOSFETs, this reduces the area occupied by the gate, allowing for a smaller cell pitch. This increases the area of ​​the chip through which current flows, resulting in more efficient use of the chip area. For the same chip area, a smaller cell size allows for more cells to be connected in parallel, increasing cell and channel density and reducing on-resistance. The gate width of a Trench MOSFET is much smaller than that of a planar structure, significantly reducing the parasitic gate-drain capacitance Cgd (Miller capacitance), thus drastically lowering switching losses.

[0004] However, under high drain voltage, a large electric field exists at the bottom of the trench, which can easily cause breakdown, affecting the device's voltage resistance and reliability. Summary of the Invention

[0005] In order to improve the device's resistance to pressure and extend its service life, this application provides a semiconductor device and a method for manufacturing the same in a polycrystalline opening.

[0006] The first aspect of this application provides a semiconductor device employing the following technical solution: A semiconductor device, comprising: Substrate; A first-doped epitaxial layer is formed on the upper surface of the substrate, and the epitaxial layer is etched with trenches; Multiple bases of the second doping type are disposed within the epitaxial layer; A well region and a source region are disposed within the epitaxial layer, with the sides of the well region and the source region connected to the base. The gate is formed of polysilicon filling a trench, the bottom end of the gate penetrating the well region and the source region, and the polysilicon has a hole. A first doped buried layer and a second doped buried layer are formed at the bottom of the gate. The first doped buried layer and the second doped buried layer are not connected to the base. The first doped buried layer is of a first doping type, and the second doped buried layer is of a second doping type different from the first doping type. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base and source regions. The source metal layer is also formed in the hole so that the source metal layer penetrates the well region and the source region and connects to the second doped buried layer.

[0007] By adopting the above technical solution, a unique P-type and N-type region with a trench bottom structure is formed, effectively reducing the on-resistance of the device while improving its withstand voltage and reliability. Repeated switching of the device leads to charge accumulation, increasing parasitic capacitance and reducing switching speed. Furthermore, repeated switching increases the on-resistance, affecting power consumption. Therefore, this application effectively solves the problems caused by charge storage / accumulation effects by grounding through a second doped buried layer. Additionally, injecting only at the bottom of the trench affects the device's turn-on and turn-off performance due to the trench depth and morphology. By injecting the base on both sides of the first and second doped buried layers, the device is less affected by the trench, allowing for a larger design and process window.

[0008] Optionally, the hole cuts through the polysilicon laterally but does not cut through it longitudinally, so that the hole is in the shape of a first window.

[0009] By employing the above technical solution, the polysilicon gate is laterally cut away while remaining continuous vertically, forming a first window-shaped via. This design effectively reduces the parasitic capacitance of the polysilicon gate, especially the parasitic capacitance between the gate and source, thereby reducing switching losses and improving the device's switching speed. Simultaneously, this via design can also improve the electric field distribution of the gate, further enhancing the device's reliability and voltage resistance.

[0010] Optionally, the perforation does not cut through the polycrystalline silicon in either the lateral or longitudinal direction, so that the perforation is in the shape of a second window, and multiple sets of perforations in the polycrystalline silicon are arranged in parallel in the lateral direction.

[0011] By adopting the above technical solution, the hollowing out of polycrystalline silicon can maintain the integrity of polycrystalline silicon and avoid lateral and longitudinal fractures, thereby ensuring the stability of the polycrystalline silicon structure.

[0012] Optionally, the perforation does not cut through the polycrystalline silicon in either the lateral or longitudinal direction, so that the perforation is in the shape of a second window, and the perforations in the multiple sets of polycrystalline silicon are staggered in the lateral direction.

[0013] By adopting the above technical solution, the electric field distribution within polysilicon can be effectively optimized, avoiding localized breakdown problems caused by electric field concentration. Simultaneously, the laterally staggered perforations further improve the device's heat dissipation performance, ensuring the device's stability and reliability under high-frequency operating conditions.

[0014] Optionally, the polysilicon is not cut through in the transverse direction, but is cut in the longitudinal direction to make the hole a long groove.

[0015] By employing the above technical solution, a long trench-shaped via is formed in the polysilicon beneath the gate, effectively reducing electric field concentration beneath the gate and improving the device's reliability and high-voltage withstand capability. Simultaneously, this structural design optimizes the current path, further reducing on-resistance and enhancing the overall device performance.

[0016] Optionally, the well region includes a first conductive channel region and a second conductive channel region arranged from bottom to top, wherein the first conductive channel region is a first doping type, the second conductive channel region is a second doping type, and the source region is a first doping type; Wherein, the doping concentration of the base is higher than that of the first conductive channel region, and the doping concentration of the second conductive channel region is lower than that of the source region, and the second conductive channel region constitutes an internal negative feedback resistor between the first conductive channel region and the source region.

[0017] By adopting the above technical solution, the second conductive channel region can be equivalent to a negative feedback resistor connected in series with the source electrode of the insulated gate semiconductor chip. When VGS is applied to the gate electrode and source electrode of the insulated gate semiconductor chip from the outside, the resistor can achieve voltage division, improve the gate-source withstand voltage performance, and reduce the risk of the gate oxide layer being broken down.

[0018] Optionally, it also includes an insulating layer disposed between the epitaxial layer and the source metal layer; it also includes a passivation layer disposed on the upper surface of the source metal layer, and a resin layer disposed on the upper surface of the passivation layer, the passivation layer having a thickness of 0.1um-20um, and the resin layer having a thickness of 1um-50um.

[0019] By adopting the above technical solutions, the insulating layer can effectively isolate the epitaxial layer from the source metal layer, preventing electrical short circuits and improving the reliability and stability of the device. The passivation layer covers the upper surface of the source metal layer, further enhancing the device's moisture resistance and oxidation resistance, and extending its service life. The resin layer, as a protective layer, not only provides physical protection but also improves the device's heat dissipation performance, ensuring stable operation of the device under long-term use.

[0020] The second aspect of this application provides a method for manufacturing a semiconductor device with a polycrystalline opening, which employs the following technical solution: A method for manufacturing a semiconductor device with a polycrystalline opening includes the following steps: S10. Provide a substrate, wherein an epitaxial layer of a first doping type is formed on the upper surface of the substrate; S20. Ions are implanted into the epitaxial layer for the first time to form multiple bases of the second doping type in the epitaxial layer; S30. Ions are implanted into the epitaxial layer for a second time to form a well region and a source region in the epitaxial layer, wherein the sides of the well region and the source region are connected to the base. S40. Etch the epitaxial layer to form a trench that penetrates the well region and the source region, wherein the trench is not connected to the base. S50. Ions are implanted into the epitaxial layer for the third time to form a first doped buried layer and a second doped buried layer sequentially at the bottom of the trench. The first doped buried layer is of a first doping type, and the second doped buried layer is of a second doping type different from the first doping type. The first doped buried layer and the second doped buried layer are not connected to the base. S60. Polysilicon is deposited in the trench to form a gate, wherein the polysilicon has a hole. S70. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base and source regions; the source metal layer is also formed in the hole of the polysilicon, so that the source metal layer passes through the well region and the source region and is connected to the second doped buried layer.

[0021] Optionally, step S60 includes: S61. The polycrystalline silicon is cut through laterally but not longitudinally to form a first window-shaped hole; or, S61. The polysilicon is not cut through in either the transverse or longitudinal direction to form a second window-shaped hole; multiple sets of holes within the polysilicon are arranged parallel to each other in the transverse direction; or, S61. The polysilicon is not cut through in either the transverse or longitudinal direction to form a second window-shaped perforation; multiple sets of perforations within the polysilicon are staggered in the transverse direction; or, S61. Do not cut through the polycrystalline silicon in the transverse direction, but dig the polycrystalline silicon in the longitudinal direction to form a long groove-shaped hole.

[0022] Optionally, step S30 includes: S31. Ions are implanted into the epitaxial layer to form a first conductive channel region of the second doping type; S32. Ions are implanted into the epitaxial layer to form a second conductive channel region of the first doping type, and the first conductive channel region and the second conductive channel region are combined to form a well region. S33. Ions are implanted into the epitaxial layer to form a source region of the first doping type; The base region has a higher doping concentration than the first conductive channel region, and the second conductive channel region has a lower doping concentration than the source region, so as to form an internal negative feedback resistor between the first conductive channel region and the source region, thereby realizing gate-source breakdown voltage.

[0023] In summary, this application includes at least one of the following beneficial technical effects: 1. This application can effectively solve the problem caused by charge storage / accumulation effect by grounding through the second doped buried layer; at the same time, if the injection is only done at the bottom of the trench, the performance of device conduction and turn-off will be affected by the depth and morphology of the trench. However, by injecting the base on both sides of the first doped buried layer and the second doped buried layer, the device is less affected by the trench, and the design window and process window of the device can be larger. 2. By introducing a first conductive channel region, a second conductive channel region, and a source region structure, the risk of gate oxide layer breakdown is reduced. At the same time, voltage division is achieved through the second conductive channel region to improve gate-source breakdown voltage performance and further improve device reliability. 3. Ensure effective connection between the source metal layer and the second doped buried layer, the base and source regions, reduce contact resistance, and improve device reliability and electrical performance. Attached Figure Description

[0024] Figure 1 This is a partial structural schematic diagram of a semiconductor device according to some preferred embodiments of this application, wherein... Figure 1 (A) is a schematic diagram showing the connection between the source metal layer and the base and the source region. Figure 1 (B) is a schematic diagram of the connection between the source metal layer and the second doped buried layer; Figure 2 This is a schematic diagram of the semiconductor device drilling in some preferred embodiments of this application, wherein... Figure 2 (A) is a top view of a semiconductor device. Figure 2 (B) is a sectional view along line BB in (A). Figure 2 (C) is a sectional view along line CC in (A); Figure 3 This is a schematic diagram of the semiconductor device drilling in some preferred embodiments of this application, wherein... Figure 3 (A), (B), and (C) represent variations of different embodiments; Figure 4 This is a schematic diagram illustrating the provision of a substrate and the growth of an epitaxial layer on the substrate during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 5 This is a schematic diagram of the formation of a base in the epitaxial layer during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 6This is a schematic diagram of the formation of a well region and a source region in the epitaxial layer during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 7 This is a schematic diagram of trenches formed by etching downwards on the upper surface of the epitaxial layer during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 8 This is a schematic diagram of forming a first doped buried layer and a second doped buried layer at the bottom of a trench during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 9 This is a schematic diagram illustrating the activation of the semiconductor device after forming a protective layer during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 10 This is a schematic diagram showing the formation of oxide layers on the upper surface of the epitaxial layer and the inner surface of the trench during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 11 This is a schematic diagram of polysilicon deposition in a trench during the fabrication of a semiconductor device according to some preferred embodiments of this application; Figure 12 This is a schematic diagram illustrating the etching of polysilicon to form vias during the fabrication of a semiconductor device according to some preferred embodiments of this application, wherein... Figure 12 (A) is a top view of a semiconductor device. Figure 12 (B) is a sectional view along line BB in (A). Figure 12 (C) is a sectional view along line CC in (A); Figure 13 This is a schematic diagram illustrating the provision of insulating layers within vias and on the upper surface of the epitaxial layer during the fabrication of a semiconductor device according to some preferred embodiments of this application. Figure 13 (A) is a top view of a semiconductor device. Figure 13 (B) is a sectional view along line BB in (A). Figure 13 (C) is a sectional view along line CC in (A); Figure 14 This is a schematic diagram illustrating the etching of an insulating layer to form contact holes and grounding holes during the fabrication of a semiconductor device according to some preferred embodiments of this application. Figure 14 (A) is a top view of a semiconductor device. Figure 14 (B) is a sectional view along line BB in (A). Figure 14 (C) is a sectional view along line CC in (A); Figure 15 This is a schematic diagram illustrating the formation of conductive layers at the bottom of contact holes and grounding holes during the fabrication of a semiconductor device according to some preferred embodiments of this application. Figure 15 (A) is a top view of a semiconductor device. Figure 15 (B) is a sectional view along line BB in (A). Figure 15(C) is a sectional view along line CC in (A); Figure 16 This is a schematic diagram illustrating the formation of a source metal layer, a passivation layer, a resin layer, and a drain metal layer during the fabrication of a semiconductor device according to some preferred embodiments of this application. Figure 16 (A) is a schematic diagram showing the connection between the source metal layer and the base and the source region. Figure 16 (B) is a schematic diagram of the connection between the source metal layer and the second doped buried layer.

[0025] Explanation of reference numerals in the attached figures: 10. Substrate; 20. Epitaxial layer; 21. Trench; 30. Base; 40. First conductive channel region; 41. Second conductive channel region; 42. Source region; 50. First doped buried layer; 51. Second doped buried layer; 60. Mask; 61. Protective layer; 62. Oxide layer; 70. Gate; 71. Hole; 72. Insulating layer; 73. Contact hole; 74. Grounding hole; 75. Conductive layer; 80. Source metal layer; 81. Passivation layer; 82. Resin layer; 83. Drain metal layer. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments for understanding the inventive concept of the present invention, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art under the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

[0027] It should be noted that if directional indicators (such as up, down, left, right, front, back, etc.) are involved in the embodiments of the present invention, these directional indicators are only used to explain the relative positional relationships and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. To better understand the technical solution of the present invention, the manufacturing method of the semiconductor device with polycrystalline openings of the present invention will be described and explained in further detail below, but this is not intended to limit the scope of protection of the present invention.

[0028] In specific applications of the variations, the source of the example can be used as the drain, and the drain of the example can be used as the source. The source and drain represent the relative flow direction of electrons. When the source described in the specification is used as the source, the drain described in the specification must be used as the drain; when the drain described in the specification is used as the drain, the drain described in the specification must be used as the source. For ease of understanding of the technical solution of this application, the specification and the scope of protection still use "source" and "drain," but in fact, they are not limited to source and drain, but rather use a first electrode and a second electrode that represent two different potential poles. Therefore, those skilled in the art can interchange the "source" and "drain" of the semiconductor device after understanding the technical solution of this invention, and the scope of protection of this invention naturally includes such equivalent interchange.

[0029] Furthermore, the first doping type in this application is the opposite of the second doping type. When the first doping type is N-type, the second doping type is P-type; when the first doping type is P-type, the second doping type is N-type. The embodiments in this application are described with the first doping type being N-type and the second doping type being P-type.

[0030] The accompanying drawings only illustrate the commonalities among multiple embodiments; differences or distinctions are described in text or presented in comparison with the drawings. Based on industry characteristics and the nature of the technology, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination thereof described below can characterize the same embodiment, or whether multiple mutually exclusive technical features can only characterize different variations of the embodiment.

[0031] Figures 1 to 3 This is a schematic diagram of the semiconductor device of this application; Figures 4 to 16 This is a partial cross-sectional schematic diagram of the corresponding component during the manufacturing process of the semiconductor device of this application (corresponding to steps S10 to S70).

[0032] The semiconductor device provided in the embodiments of this application refers to... Figure 1 (A) and Figure 1 (B) includes a substrate 10, an epitaxial layer 20, a base 30, a well region, a source region 42, a first doped buried layer 50, a second doped buried layer 51, a gate 70, and a source metal layer 80. The substrate 10 can be made of SiC or other suitable materials. The epitaxial layer 20 is formed on the upper surface of the substrate 10 and is of the first doping type, i.e., an N-type epitaxial layer 20.

[0033] In this embodiment, multiple parallel P+ bases 30 are formed by implanting P-type ions into the epitaxial layer 20.

[0034] The well region and source region 42 are disposed within the epitaxial layer 20, with their sides connected to the base 30. Specifically, the well region includes a first conductive channel region 40 and a second conductive channel region 41 from bottom to top. The first conductive channel region 40 is of the second doping type, and the second conductive channel region 41 is of the first doping type. The source region 42 is disposed above the second conductive channel region 41. Simultaneously, the doping concentration of the base 30 is higher than that of the first conductive channel region 40, and the doping concentration of the second conductive channel region 41 is lower than that of the source region 42, thus forming an internal negative feedback resistor between the first conductive channel region 40 and the source region 42 to achieve gate-source breakdown voltage.

[0035] Specifically, the base region 30 is a P+ region, the first conductive channel region 40 is a P- region, the second conductive channel region 41 is an N- region, and the source region 42 is an N+ region.

[0036] The epitaxial layer 20 is etched to form a trench 21 penetrating the well region and the source region 42. Ions are sequentially implanted into the trench 21 to form a first doped buried layer 50 and a second doped buried layer 51. The first doped buried layer 50 and the second doped buried layer 51 are not connected to the base 30. The first doped buried layer 50 is of a first doping type, and the second doped buried layer 51 is of a second doping type different from the first doping type. Specifically, the first doped buried layer 50 is an N-type region, and the second doped buried layer 51 is a P-type region.

[0037] In this embodiment, the first doped buried layer 50 has a structure that is thin in the middle and thick at both sides, while the second doped buried layer 51 is distributed in a ring shape. This structure can form an effective electric field shield at the bottom of the trench 21, reduce the concentration of large electric fields at the bottom of the trench 21, improve the device's voltage resistance and reliability, and further enhance the electric field dispersion effect at the bottom of the trench 21, effectively reducing the local electric field strength and improving the device's breakdown voltage and reliability. In other embodiments, the first doped buried layer 50 and the second doped buried layer 51 can also have other shapes.

[0038] The trench 21 has an oxide layer 62 on its inner wall and is filled with polysilicon to form a gate 70. The gate 70 is disposed between the bases 30 and its bottom end penetrates the well region and the source region 42.

[0039] Reference Figure 1 (A) and Figure 1 (B) A source metal layer 80 is formed on the upper surface of the epitaxial layer 20 to connect the base 30 and the source region 42. The source metal layer 80 also penetrates the well region and the source region 42 to connect to the second doped buried layer 51.

[0040] Reference Figure 2 (A) Figure 2 (B) and Figure 2(C) Specifically, after filling the trench 21 with polysilicon, a mask 60 is formed, and a hole 71 is formed by opening a hole in the polysilicon. Metal is filled in the hole 71 to form a source metal layer 80. The source metal layer 80 connects the base 30 and the source region 42 and passes through the well region and the source region 42 to connect to the second doped buried layer 51.

[0041] The hole 71 can take different forms, forming various layouts of the hole 71. The hole 71 methods include, but are not limited to, those described in this embodiment. Modifications can be made based on this embodiment in terms of size, shape (square, circular, hexagonal, etc.), position, number, and relative positional relationship of adjacent holes, but all of these modifications fall within the scope of this patent. Possible modifications are shown in the following embodiments.

[0042] Reference Figure 2 (A) In this embodiment, the via 71 is cut through the polysilicon laterally but not longitudinally, so that the via 71 is in the shape of a first window. This allows the polysilicon gate to be cut through laterally while remaining continuous in the longitudinal direction, forming a first window-shaped via. This design can effectively reduce the parasitic capacitance of the polysilicon gate, especially the parasitic capacitance between the gate and the source, thereby reducing switching losses and improving the switching speed of the device. At the same time, this via design can also improve the electric field distribution of the gate, further improving the reliability and voltage resistance of the device.

[0043] Reference Figure 3 (A) In another embodiment, the perforation 71 does not cut through the polycrystalline silicon in either the lateral or longitudinal direction, so that the perforation 71 is in the shape of a second window, and the perforations 71 in multiple sets of polycrystalline silicon are arranged in parallel in the lateral direction. This allows the perforations in the polycrystalline silicon to maintain the integrity of the polycrystalline silicon, avoid lateral and longitudinal breakage, and thus ensure the stability of the polycrystalline silicon structure.

[0044] Reference Figure 3 (B) In another embodiment, the perforation 71 does not cut through the polysilicon in either the lateral or longitudinal direction, so that the perforation 71 is in the shape of a second window, and multiple sets of perforations 71 in the polysilicon are arranged in a staggered manner in the lateral direction. This structure can effectively optimize the electric field distribution in the polysilicon and avoid local breakdown problems caused by electric field concentration. At the same time, the laterally staggered perforations can further improve the heat dissipation performance of the device and ensure the stability and reliability of the device under high-frequency operating conditions.

[0045] Reference Figure 3 (C) In another embodiment, the via 71 does not cut through the polysilicon laterally, but cuts through the polysilicon longitudinally to make the via 71 into an elongated groove shape. This structure allows the polysilicon below the gate to form an elongated groove, thereby effectively reducing the electric field concentration phenomenon below the gate and improving the reliability and high voltage resistance of the device. At the same time, this structural design can also optimize the current path, further reduce the on-resistance, and improve the overall performance of the device.

[0046] Reference Figure 1 (A) and Figure 1 (B) An insulating layer 72 is provided between the source metal layer 80 and the sidewall of the trench 21 and between the source metal layer 80 and the upper surface of the epitaxial layer 20. The insulating layer 72 can effectively isolate the epitaxial layer 20 and the source metal layer 80, prevent electrical short circuits, and improve the reliability and stability of the device.

[0047] In addition, conductive layers 75 are provided between the second doped buried layer 51 and the source metal layer 80, and between the source region 42 and the base 30 and the source metal layer 80. The conductive layer 75 may be a silicide layer or a titanide layer, and the material of the source metal layer 80 includes, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0048] In addition, a passivation layer 81 is disposed on the upper surface of the source metal layer 80, a resin layer 82 is disposed on the upper surface of the passivation layer 81, and a drain metal layer 83 is disposed on the lower surface of the substrate 10.

[0049] Optionally, the passivation layer 81 has a thickness of 0.1µm-20µm, and the material of the passivation layer 81 includes, but is not limited to, SiO2, SiN and combinations thereof; the resin layer 82 has a thickness of 1µm-50µm, and the material of the passivation layer 81 may include at least one of polyimide, polyamide and polybenzoxazole, with a preferred thickness range of 10-15µm in this embodiment; the drain metal layer 83 has a material including, but is not limited to, Ti / Ni / Ag / Pd / Au, and alloys or combinations thereof.

[0050] This application creates P-type and N-type regions at the bottom of the trench 21 with a unique structure, effectively reducing the on-resistance of the device while improving its breakdown voltage and reliability. The base 30 forms a P-type region at the bottom of the trench 21, protecting the bottom of the trench 21 and preventing breakdown caused by high electric fields. The combination of the base 30 with the subsequent P-type and N-type regions at the bottom of the trench 21 further optimizes the electric field distribution, improving the device's breakdown voltage and reliability.

[0051] The method for manufacturing a semiconductor device with a polycrystalline opening provided in this application includes the following steps: Reference Figure 4 S10, a substrate 10 is provided, wherein an epitaxial layer 20 of a first doping type is formed on the upper surface of the substrate 10.

[0052] Optionally, an N-type epitaxial layer 20 is used, and the substrate 10 material can be SiC or other suitable materials. The growth of the epitaxial layer 20 can be achieved by chemical vapor deposition (CVD) or other suitable methods to ensure the uniformity and doping concentration of the epitaxial layer 20.

[0053] Reference Figure 5 S20, ions are implanted into the epitaxial layer 20 for the first time to form a plurality of bases 30 of the second doping type in the epitaxial layer 20.

[0054] Optionally, a P+ base 30 is formed by implanting P-type ions. The formation of the base 30 can be achieved by various methods, such as ion implantation or diffusion. Specifically, a mask 60 is formed on the epitaxial layer 20, and then the desired openings are formed on the mask 60 by photolithography and etching processes. Finally, multiple parallel P+ bases 30 are formed by ion implantation.

[0055] Reference Figure 6 S30, a second ion implantation is performed on the epitaxial layer 20 to form a well region and a source region 42 within the epitaxial layer 20, the sides of the well region and the source region 42 being connected to the base 30. S30 further includes: S31. Ions are implanted into the epitaxial layer 20 to form a first conductive channel region 40 of the second doping type.

[0056] S32. Ions are implanted into the epitaxial layer 20 to form a second conductive channel region 41 of the first doping type, and the first conductive channel region 40 and the second conductive channel region 41 are combined to form a well region.

[0057] S33. Ions are implanted into the epitaxial layer 20 to form a source region 42 of the first doping type.

[0058] The base 30 has a higher doping concentration than the first conductive channel region 40, and the second conductive channel region 41 has a lower doping concentration than the source region 42, so as to form an internal negative feedback resistor between the first conductive channel region 40 and the source region 42, thereby realizing gate-source breakdown voltage.

[0059] Preferably, a self-aligned region is formed between adjacent bases 30, and the first conductive channel region 40 and the second conductive channel region 41 are formed in the self-aligned region using a self-aligned process. The first conductive channel region 40 and the second conductive channel region 41 are lightly doped regions, and the source region 42 is a heavily doped region.

[0060] Optionally, the base 30 is a P+ region, the first conductive channel region 40 is a P- region, the second conductive channel region 41 is an N- region, and the source region 42 is an N+ region.

[0061] Specifically, firstly, a P-region window is defined in the self-aligned region. Under certain target temperatures, different energies and doses, B11 ions are injected multiple times through the P-region window under high-temperature conditions to advance the P-region. Then, the injected ions form N-regions, and high-concentration ion implantation is performed in the N-regions to form N+ regions.

[0062] Reference Figure 7 S40, Etch the epitaxial layer 20 to form a trench 21 that penetrates the well region and the source region 42, the trench 21 being not connected to the base 30.

[0063] Optionally, the groove 21 can be flat-bottomed or round-bottomed, and the sidewall angle of the groove 21 is generally 80-91°, preferably 86°. The connection between the bottom and the sidewall of the groove 21 can be arc-shaped to reduce stress concentration.

[0064] Reference Figure 8 S50, ions are implanted into the epitaxial layer 20 for the third time to form a first doped buried layer 50 and a second doped buried layer 51 in sequence at the bottom of the trench 21. The first doped buried layer 50 is a first doping type, and the second doped buried layer 51 is a second doping type different from the first doping type. The first doped buried layer 50 and the second doped buried layer 51 are not connected to the base 30.

[0065] In this embodiment, the first doped buried layer 50 is N-type and the second doped buried layer 51 is P-type.

[0066] In this embodiment, step S50 further includes: S51. A mask 60 is formed on the upper surface of the epitaxial layer 20, the mask 60 also covering the sidewall of the trench 21.

[0067] Specifically, the mask 60 extends to the bottom of the arc of the trench 21.

[0068] S52. Ions are implanted to form a first doped buried layer 50 at the bottom of the trench 21. By controlling the implantation angle, the first doped buried layer 50 has a structure that is thin in the middle and thick on both sides.

[0069] Optionally, an injection angle of 10-20° can be used to form a thicker N-type region on both sides of the bottom of the trench 21, while a thinner N-type region is formed in the center.

[0070] S53. Ion implantation forms a second doped buried layer 51 within the first doped buried layer 50. Through vertical implantation, the second doped buried layer 51 is distributed in a ring shape.

[0071] Optionally, a vertical injection angle can be used to create a ring-shaped distribution of P-type ions at the bottom of trench 21.

[0072] The design of N-type and P-type regions includes, but is not limited to, that described in this embodiment. Modifications can be made based on this embodiment in terms of size, shape, position, and relative positional relationship between the two regions, but all of these modifications fall within the scope of this patent.

[0073] S60. Polysilicon is deposited into the trench 21 to form a gate 70, the polysilicon having a via. Before step S60, the method further includes: Reference Figure 9 S57. Using photolithography or sputtering, a protective layer 61 is formed on the upper surface of the epitaxial layer 20 and the inner wall of the trench 21, and then the internal structure of the semiconductor device is activated at high temperature. The protective layer 61 includes, but is not limited to, a photoresist protective layer 61, a carbon protective layer 61, and an aluminum nitride protective layer 61. In this embodiment, the activation temperature range is 1400-2100℃, with a preferred range of 1700-1800℃. After activation, the protective layer 61 is removed.

[0074] S58. The surface of the epitaxial layer 20 is oxidized at high temperature, and then the sacrificial oxide layer on the surface is removed.

[0075] Reference Figure 10 S59. An oxide layer is formed on the surface by means of thermal oxidation or chemical vapor deposition.

[0076] Step S60 includes: Reference Figure 11 S61. A layer of polysilicon is deposited in the trench 21 and on the upper surface of the epitaxial layer 20. Then, the polysilicon in the trench 21 is retained by an etching process. The polysilicon in the trench 21 forms the required gate 70.

[0077] Reference Figure 12 (A) Figure 12 (B) and Figure 12 (C), S62, forming a mask 60 to form a hole 71 for opening a hole in the polysilicon.

[0078] The hole 71 can take different forms, forming various layouts of the hole 71. The hole 71 methods include, but are not limited to, those described in this embodiment. Modifications can be made based on this embodiment in terms of size, shape (square, circular, hexagonal, etc.), position, number, and relative positional relationship of adjacent holes, but all of these modifications fall within the scope of this patent. Possible modifications are shown in the following embodiments.

[0079] Reference Figure 12 (A) In this embodiment, the hole 71 cuts through the polysilicon in the horizontal direction but does not cut through the polysilicon in the vertical direction so that the hole 71 is in the shape of a first window.

[0080] Reference Figure 3 (A) In another embodiment, the hole 71 does not cut through the polysilicon in either the lateral or longitudinal direction so that the hole 71 is in the shape of a second window, and the holes 71 in the multiple sets of polysilicon are arranged in parallel in the lateral direction.

[0081] Reference Figure 3(B) In another embodiment, the hole 71 does not cut through the polysilicon in either the lateral or longitudinal direction so that the hole 71 is in the shape of a second window, and the holes 71 in the polysilicon are arranged alternately in the lateral direction.

[0082] Reference Figure 3 (C) In another embodiment, the hole 71 does not cut through the polysilicon in the transverse direction, but cuts the polysilicon in the longitudinal direction to make the hole 71 into a long groove shape.

[0083] S70, a source metal layer 80 is formed on the upper surface of the epitaxial layer 20 to connect the base 30 and the source region 42; the source metal layer 80 is also formed in the hole of the polysilicon, so that the source metal layer 80 passes through the well region and the source region 42 and is connected to the second doped buried layer 51.

[0084] Step S70 includes: Reference Figure 13 (A) Figure 13 (B) and Figure 13 (C), S71, forming an insulating layer 72 inside the hole 71 and on the upper surface of the epitaxial layer 20.

[0085] Optionally, the insulating layer 72 may be made of materials including but not limited to silicon dioxide, silicon nitride, or combinations thereof, and may be formed by chemical vapor deposition (CVD) or other suitable methods.

[0086] Reference Figure 14 (A) Figure 14 (B) and Figure 14 (C), S72, Forming a mask 60 on the upper surface of the insulating layer 72, etching the insulating layer 72 above the base 30 and source region 42 to form a contact hole 73, and etching the insulating layer 72 in the trench 21 to form a grounding hole 74.

[0087] Reference Figure 15 (A) Figure 15 (B) and Figure 15 (C), S721, depositing metal at the bottom of the contact hole 73 and the grounding hole 74 to form a conductive layer 75.

[0088] Optionally, silicon or titanium can be deposited, followed by high-temperature annealing to form a silicide or titanium layer, removing excess metal, and the silicide or titanium layer forming a conductive layer 75.

[0089] Reference Figure 16 (A) and Figure 16 (B), S73, fill the contact hole 73 and the ground hole 74 with metal to form a source metal layer 80, the source metal layer 80 connecting the base 30 and the source region 42 and connecting the second doped buried layer 51 through the well region and the source region 42.

[0090] Optionally, the material of the source metal layer 80 includes, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0091] Following step S73, the following also includes: S74. A passivation layer 81 is provided on the upper surface of the source metal layer 80, and the thickness of the passivation layer 81 is 0.1um-20um.

[0092] Optionally, the material of the passivation layer 81 includes, but is not limited to, SiO2, SiN, and combinations thereof.

[0093] S75. A resin layer 82 is provided on the upper surface of the passivation layer 81, and the thickness of the resin layer 82 is 1um-50um.

[0094] Optionally, the material of the passivation layer 81 may include at least one of polyimide, polyamide and polybenzoxazole, and the preferred thickness range in this embodiment is 10-15 μm.

[0095] S76. Thinning of substrate 10, the thickness of substrate 10 after thinning is 80um-250um.

[0096] In this embodiment, the preferred thickness range is 150-200 μm.

[0097] S77. A drain metal layer 83 is formed on the lower surface of the substrate 10.

[0098] The material of the drain metal layer 83 includes, but is not limited to, Ti / Ni / Ag / Pd / Au, and their alloys or combinations.

[0099] In the prior art, repeated switching of a device will lead to charge accumulation, increasing the parasitic capacitance of the device and reducing the switching speed. At the same time, after repeated switching, the on-resistance of the device increases, affecting the power consumption of the device. Therefore, this application can effectively solve the problems caused by the charge storage / accumulation effect by grounding through the second doped buried layer 51. In addition, if the injection is only done at the bottom of the trench 21, the performance of the device's turn-on and turn-off will be affected by the depth and morphology of the trench 21. However, by injecting the base 30 on both sides of the first doped buried layer 50 and the second doped buried layer 51, the device is less affected by the trench 21, and the design window and process window of the device can be larger.

[0100] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate (10); A first doped epitaxial layer (20) is formed on the upper surface of the substrate (10), and the epitaxial layer (20) is etched with trenches (21). Multiple bases (30) of the second doped type are disposed within the epitaxial layer (20); A well region and a source region (42) are disposed within the epitaxial layer (20), and the sides of the well region and the source region (42) are connected to the base (30). The gate (70) is formed of polysilicon filled in the trench (21), the bottom end of the gate (70) extends through the well region and the source region (42), and the polysilicon has a hole (71). A first doped buried layer (50) and a second doped buried layer (51) are formed at the bottom of the gate (70). The first doped buried layer (50) and the second doped buried layer (51) are not connected to the base (30). The first doped buried layer (50) is of the first doping type, and the second doped buried layer (51) is of the second doping type, which is different from the first doping type. A source metal layer (80) is formed on the upper surface of the epitaxial layer (20) to connect the base (30) and the source region (42). The source metal layer (80) is also formed in the hole (71) so that the source metal layer (80) penetrates the well region and the source region (42) and is connected to the second doped buried layer (51).

2. A semiconductor device according to claim 1, characterized in that: The hole (71) cuts through the polycrystalline silicon in the transverse direction, but does not cut through the polycrystalline silicon in the longitudinal direction, so that the hole (71) is in the shape of a first window.

3. A semiconductor device according to claim 1, characterized in that: The hole (71) does not cut through the polysilicon in either the horizontal or vertical direction so that the hole (71) is in the shape of a second window, and multiple sets of holes (71) in the polysilicon are arranged in parallel in the horizontal direction.

4. A semiconductor device according to claim 1, characterized in that: The perforation (71) does not cut through the polycrystalline silicon in either the transverse or longitudinal direction so that the perforation (71) is in the shape of a second window, and the perforations (71) in the polycrystalline silicon are arranged alternately in the transverse direction.

5. A semiconductor device according to claim 1, characterized in that: The hole (71) does not cut through the polysilicon in the transverse direction, but cuts the polysilicon in the longitudinal direction so that the hole (71) is in the shape of a long groove.

6. A semiconductor device according to claim 1, characterized in that, The well region includes a first conductive channel region (40) and a second conductive channel region (41) arranged from bottom to top. The first conductive channel region (40) is of the first doping type, the second conductive channel region (41) is of the second doping type, and the source region (42) is of the first doping type. The base (30) has a higher doping concentration than the first conductive channel region (40), and the second conductive channel region (41) has a lower doping concentration than the source region (42). The second conductive channel region (41) forms an internal negative feedback resistor between the first conductive channel region (40) and the source region (42).

7. A semiconductor device according to claim 1, characterized in that, It also includes an insulating layer (72) disposed between the epitaxial layer (20) and the source metal layer (80); it also includes a passivation layer (81) disposed on the upper surface of the source metal layer (80), and a resin layer (82) disposed on the upper surface of the passivation layer (81), the passivation layer (81) having a thickness of 0.1um-20um, and the resin layer (82) having a thickness of 1um-50um.

8. A method for manufacturing a semiconductor device with a polycrystalline opening, for producing the semiconductor device according to any one of claims 1-7, characterized in that, Includes the following steps: S10. Provide a substrate (10) having an epitaxial layer (20) of a first doping type formed on the upper surface of the substrate (10). S20. Ions are implanted into the epitaxial layer (20) for the first time to form a plurality of bases (30) of the second doping type in the epitaxial layer (20). S30. Ions are implanted into the epitaxial layer (20) for the second time to form a well region and a source region (42) in the epitaxial layer (20), the sides of the well region and the source region (42) being connected to the base (30). S40. Etch the epitaxial layer (20) to form a trench (21) that penetrates the well region and the source region (42), the trench (21) being not connected to the base (30). S50. Ions are implanted into the epitaxial layer (20) for the third time to form a first doped buried layer (50) and a second doped buried layer (51) in sequence at the bottom of the trench (21). The first doped buried layer (50) is of the first doping type, and the second doped buried layer (51) is of the second doping type, which is different from the first doping type. The first doped buried layer (50) and the second doped buried layer (51) are not connected to the base (30). S60. Polysilicon is deposited in the trench (21) to form a gate (70), the polysilicon having a hole (71). S70, a source metal layer (80) is formed on the upper surface of the epitaxial layer (20) to connect the base (30) and the source region (42); the source metal layer (80) is also formed in the hole (71) of the polysilicon, so that the source metal layer (80) passes through the well region and the source region (42) and is connected to the second doped buried layer (51).

9. The method for manufacturing a semiconductor device with a polycrystalline opening according to claim 8, characterized in that, Step S60 includes: S61, the polycrystalline silicon is cut horizontally but not vertically to form a first window-shaped hole (71); or, S61, The polysilicon is not cut through in either the transverse or longitudinal direction to form a second window-shaped hole (71), and multiple sets of holes (71) in the polysilicon are arranged parallel in the transverse direction; or, S61, The polysilicon is not cut through in either the transverse or longitudinal direction to form a second window-shaped hole (71), and multiple sets of holes (71) in the polysilicon are staggered in the transverse direction; or, S61. Do not cut through the polycrystalline silicon in the transverse direction, but cut the polycrystalline silicon in the longitudinal direction to form a long groove-shaped hole (71).

10. The method for manufacturing a semiconductor device with a polycrystalline opening according to claim 8, characterized in that, Step S30 includes: S31. Ions are implanted into the epitaxial layer (20) to form a first conductive channel region (40) of the second doping type. S32. Ions are implanted in the epitaxial layer (20) to form a second conductive channel region (41) of the first doping type, and the first conductive channel region (40) and the second conductive channel region (41) are combined to form a well region; S33. Ions are implanted into the epitaxial layer (20) to form a source region (42) of the first doping type. The base (30) has a higher doping concentration than the first conductive channel region (40), and the second conductive channel region (41) has a lower doping concentration than the source region (42), so as to form an internal negative feedback resistor between the first conductive channel region (40) and the source region (42) to realize gate-source breakdown voltage.

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