Array substrate and display panel

Abstract

The invention relates to an array substrate and a display panel. The array substrate comprises a substrate; the transistor is arranged on one side of the substrate and comprises an active layer, a first conductive structure, a first electrode and a second electrode, and the active layer comprises a channel region, a first conductor region and a second conductor region; the orthographic projection of the first conductive structure on the substrate is at least partially overlapped with the orthographic projection of the channel region on the substrate, the first pole is in contact with the first conductor region, and the second pole is in contact with the second conductor region; the shielding layer is arranged on one side, deviating from the substrate, of the transistor and is provided with a plurality of through holes; a first gap is formed between the orthographic projection of the first electrode on the substrate and the orthographic projection of the first conductive structure on the substrate, a second gap is formed between the orthographic projection of the second electrode on the substrate and the orthographic projection of the first conductive structure on the substrate, and the first gap and the second gap are located in the orthographic projection of the shielding layer on the substrate. Therefore, according to the array substrate and the display panel provided by the invention, the electrical performance of the transistor can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared to liquid crystal displays, OLED technology offers advantages such as low power consumption, low cost, self-emissiveness, wide viewing angle, and fast response time. In related technologies, the display panel includes a shift register and pixel circuitry. The shift register is used to input gate scan signals to the pixel circuitry. The shift register may include transistors. However, the electrical performance of the transistors in the aforementioned display panel needs improvement. Summary of the Invention

[0003] Therefore, it is necessary to provide an array substrate and a display panel that can improve the electrical performance of transistors.

[0004] In a first aspect, embodiments of this application provide an array substrate, the array substrate comprising:

[0005] substrate;

[0006] A transistor is disposed on one side of a substrate. The transistor includes an active layer, a first conductive structure, a first electrode, and a second electrode. The active layer includes a channel region, a first conductive region, and a second conductive region, which are located on opposite sides of the channel region. The first conductive structure, the first electrode, and the second electrode are disposed on the side of the active layer away from the substrate. The orthographic projection of the first conductive structure on the substrate at least partially overlaps with the orthographic projection of the channel region on the substrate. The first electrode is in contact with the first conductive region, and the second electrode is in contact with the second conductive region.

[0007] A shielding layer is provided on the side of the transistor away from the substrate and has multiple through holes;

[0008] There is a first gap between the orthographic projection of the first electrode on the substrate and the orthographic projection of the first conductive structure on the substrate, and a second gap between the orthographic projection of the second electrode on the substrate and the orthographic projection of the first conductive structure on the substrate. The first gap and the second gap are located within the orthographic projection of the shielding layer on the substrate.

[0009] In one embodiment, the array substrate includes a first insulating layer and a first via and a second via that penetrate the first insulating layer. The first insulating layer is located on the side of the first conductive structure away from the substrate, and a first electrode and a second electrode are disposed on the side of the first insulating layer away from the substrate. The first electrode contacts the first conductive region through the first via, and the second electrode contacts the second conductive region through the second via.

[0010] Preferably, the orthographic projection of at least one of the first via and the second via on the substrate overlaps with the orthographic projection of the shielding layer on the substrate;

[0011] Preferably, the orthographic projection of at least one of the first via and the second via on the substrate is located within the orthographic projection of the shielding layer on the substrate.

[0012] Preferably, the active layer is made of an oxide semiconductor.

[0013] In one embodiment, the orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the first conductive structure on the substrate;

[0014] Preferably, the first conductive structure is configured as the gate of a transistor.

[0015] In one embodiment, the array substrate includes a first region, the orthographic projection of the first region on the substrate is located within the orthographic projection of the active layer on the substrate; the orthographic projections of the first conductive structure, the end of the first via facing the substrate and the end of the second via facing the substrate, as well as the first gap and the second gap, are all located within the orthographic projection of the first region on the substrate.

[0016] The plurality of through holes includes a first through hole located on the outer periphery of the first region.

[0017] In one embodiment, the plurality of vias includes a second via located within the first region; the orthographic projection of the second via on the substrate is located within the orthographic projection of the first conductive structure on the substrate.

[0018] Preferably, the dimension of the second via along the direction from the first conductive region to the second conductive region is smaller than the dimension of the first conductive structure along the direction from the first conductive region to the second conductive region;

[0019] Preferably, the dimension of the second via along the direction perpendicular to the first conductive region to the second conductive region is smaller than the dimension of the first conductive structure along the direction perpendicular to the first conductive region to the second conductive region.

[0020] In one embodiment, the diameter of the second through hole is less than or equal to the diameter of the first through hole.

[0021] In one embodiment, the orthographic projections of all vias on the substrate do not overlap with the orthographic projections of the first region on the substrate.

[0022] In one embodiment, the array substrate includes a second region, which is disposed adjacent to the first region; the orthographic projection of the second region on the substrate lies within the orthographic projection of the active layer on the substrate.

[0023] At least one through hole is located in the second region.

[0024] In one embodiment, the array substrate includes a display area and a border area disposed adjacent to each other; transistors and a shielding layer are located in the border area; the array substrate includes a first electrode layer, the first electrode layer being at least located in the display area, and the first electrode layer located in the display area includes a plurality of first electrodes;

[0025] The shielding layer and the first electrode layer are made of the same material and layer; or...

[0026] A portion of the first electrode layer is located in the border area, and the first electrode layer located in the border area is disposed on the side of the shielding layer away from the substrate; the first electrode layer located in the border area is provided with multiple hollow holes, the orthographic projection of the through hole on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the hollow hole on the substrate is located within the orthographic projection of the shielding layer on the substrate.

[0027] Secondly, embodiments of this application provide a display panel, including the display panel of the first aspect.

[0028] The array substrate and display panel provided in this application embodiment, by setting the first gap and the second gap within the orthogonal projection of the shielding layer on the substrate, that is, by using the shielding layer to shield the active layer corresponding to the first gap and the second gap, is beneficial to blocking light from shining on the active layer corresponding to the first gap and the second gap, thereby mitigating the adverse effects of external light on the active layer, and thus improving the electrical performance of the transistor. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a top view of the array substrate provided in an embodiment of this application.

[0031] Figure 2 This is a partial cross-sectional view of the array substrate provided in an embodiment of this application.

[0032] Figure 3 Another partial cross-sectional view of the array substrate provided in an embodiment of this application.

[0033] Figure 4 Another partial cross-sectional view of the array substrate provided in an embodiment of this application.

[0034] Figure 5 A top view of a transistor provided in an embodiment of this application.

[0035] Figure 6This is a top view of the shielding layer provided in an embodiment of this application.

[0036] Figure 7 A top view of the shielding layer and transistor provided in an embodiment of this application.

[0037] Figure 8 Another top view of the shielding layer provided in an embodiment of this application.

[0038] Figure 9 Another top view of the shielding layer and transistor provided in an embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100, Array substrate; 100a, Display area; 100b, Bezel area; 101, Shift register; 110, Transistor; 111, First conductive structure; 112, Second conductive structure; 113, Active layer; 1131, First conductive region; 1132, Second conductive region; 1133, Channel region; 1141, First electrode; 1142, Second electrode; 121, First via; 122, Second via; 130, Shielding layer; 132, Through hole; 1321, First through hole ; 1322, Second through hole; 140, First electrode layer; 141, Hole hole; 150, Substrate; 161, First insulating layer; 162, Second insulating layer; 163, Third insulating layer; 164, Fourth insulating layer; 165, Fifth insulating layer; 171, First conductive layer; 172, Second conductive layer; 173, Third conductive layer; d1, First gap; d2, Second gap; A1, First region; A2, Second region; X, First direction; Y, Second direction; Z, Third direction. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0042] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the process of developing this application, the inventors discovered the following problem in the related technology: the display panel includes a shift register and a pixel circuit, and the shift register is used to input a gate scan signal to the pixel circuit. The shift register includes a transistor, which can be an oxide thin-film transistor (Oxide-TFT), that is, the active layer of the transistor is an oxide semiconductor material.

[0045] However, when oxide semiconductor materials are exposed to light, they generate photogenerated carriers. These photogenerated carriers can disrupt the normal switching characteristics of the device, generate leakage current, and cause discrete conduction of the transistor.

[0046] In view of at least one of the above-mentioned problems, embodiments of this application provide an array substrate and a display panel that can improve the electrical performance of transistors.

[0047] The following will combine Figures 1-9 The array substrate and display panel provided in the embodiments of this application will be described.

[0048] See Figure 2 This application provides an array substrate 100, which includes a substrate 150 that provides support for subsequent layers. In some examples, the substrate 150 may be a rigid substrate, for example, the material of the substrate 150 may be glass. In other examples, the substrate 150 may be a flexible substrate, and the material of the substrate 150 may include at least one selected from polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0049] See Figure 2The array substrate 100 includes a transistor 110, which is disposed on one side of the substrate 150. The transistor 110 includes an active layer 113, a first conductive structure 111, a first electrode 1141, and a second electrode 1142. The active layer 113 includes a channel region 1133, a first conductive region 1131, and a second conductive region 1132. The first conductive region 1131 and the second conductive region 1132 are located on both sides of the channel region 1133. The first conductive structure 111, the first electrode 1141, and the second electrode 1142 are disposed on both sides of the channel region 1133. Both electrodes 1142 are disposed on the side of the active layer 113 away from the substrate 150; the orthographic projection of the first conductive structure 111 on the substrate 150 and the orthographic projection of the channel region 1133 on the substrate 150 at least partially overlap, for example, the orthographic projection of the first conductive structure 111 on the substrate 150 and the orthographic projection of the channel region 1133 on the substrate 150 partially overlap or completely overlap, the first electrode 1141 is in contact with the first conductive region 1131, and the second electrode 1142 is in contact with the second conductive region 1132.

[0050] See Figure 2 The array substrate 100 includes a shielding layer 130, which is disposed on the side of the transistor 110 facing away from the substrate 150. The shielding layer 130 can reduce the amount of external light illuminating the active layer 113. In addition, the shielding layer 130 can also block water vapor and hydrogen on the side of the shielding layer 130 facing away from the substrate 150, which helps to reduce the intrusion of water vapor and hydrogen into the transistor 110. This embodiment mainly uses the shielding layer 130 blocking light as an example for explanation. Ambient light irradiates the array substrate 100 from the active layer 113 towards the substrate 150. The shielding layer 130 is provided with a plurality of through holes 132. When the array substrate 100 is in a high-temperature process, the through holes 132 can discharge the gas generated by the high temperature in the organic film layer located between the shielding layer 130 and the substrate 150, preventing the shielding layer 130 from bulging due to the inability to discharge gas. For example, the fourth insulating layer 164 can be a planarization layer made of organic material. The fourth insulating layer 164 can contact the shielding layer 130.

[0051] See Figure 3 and Figure 4A first gap d1 exists between the orthographic projection of the first electrode 1141 on the substrate 150 and the orthographic projection of the first conductive structure 111 on the substrate 150. A second gap d2 exists between the orthographic projection of the second electrode 1142 on the substrate 150 and the orthographic projection of the first conductive structure 111 on the substrate 150. The active layer 113 corresponding to the first gap d1 and the second gap d2 is not blocked by the upper first electrode 1141, second electrode 1142, and first conductive structure 111, allowing light to easily reach the active layer 113 corresponding to the first gap d1 and the second gap d2, thus adversely affecting the active layer 113 and consequently the electrical performance of the transistor 110. This application places the first gap d1 and the second gap d2 within the orthographic projection of the shielding layer 130 onto the substrate 150. Specifically, the shielding layer 130 is used to shield the active layer 113 corresponding to the first gap d1 and the second gap d2. This effectively blocks light from reaching the active layer 113, mitigating the adverse effects of external light on the active layer 113 and thus improving the electrical performance of the transistor 110. In this case, the orthographic projections of the first gap d1 and the second gap d2 onto the substrate 150 do not overlap with the orthographic projection of the via 132 onto the substrate 150.

[0052] In some embodiments, the first conductive structure 111 may be configured as the gate of transistor 110.

[0053] See Figure 2 In some embodiments, the array substrate 100 includes a second conductive structure 112 located between the active layer 113 and the substrate 150, wherein the orthographic projection of the second conductive structure 112 on the substrate 150 at least partially coincides with the orthographic projection of the channel region 1133 on the substrate 150. Exemplarily, the second conductive structure 112 may be configured as the gate of a transistor 110.

[0054] It should be noted that at least one of the first conductive structure 111 and the second conductive structure 112 is configured as a gate. When both the first conductive structure 111 and the second conductive structure 112 are configured as gates, the transistor 110 has a top-bottom dual-gate structure, and the first conductive structure 111 and the second conductive structure 112 are electrically connected. When the transistor 110 has a top-gate structure, the first conductive structure 111 is configured as the gate of the transistor 110, and the second conductive structure 112 is electrically connected to the first electrode 1141. When the transistor 110 has a bottom-gate structure, the second conductive structure 112 is configured as the gate of the transistor 110, and the first conductive structure 111 is electrically connected to the first electrode 1141.

[0055] It should be noted that, see Figure 2 and Figure 5The array substrate 100 includes a first conductive layer 171 and a second conductive layer 172. A first conductive structure 111 is located on the first conductive layer 171, and the orthographic projection of the first conductive structure 111 on the substrate 150 lies within the orthographic projection of the active layer 113 on the substrate 150. This means that the portion of the first conductive layer 171 overlapping with the active layer 113 along the thickness direction of the substrate 150 is constructed as the first conductive structure 111. A first electrode 1141 and a second electrode 1142 are located on the second conductive layer 172. The orthographic projections of the first electrode 1141 and the second electrode 1142 on the substrate 150 lie within the orthographic projection of the active layer 113 on the substrate 150. This means that the portion of the second conductive layer 172 overlapping with the active layer 113 along the thickness direction of the substrate 150 is constructed as the first electrode 1141 and the second electrode 1142. The region where the active layer 113 is projected onto the substrate 150 is region A of the active layer 113. A first conductive layer 171 located within region A of the active layer 113 is configured as a first conductive structure 111, and a second conductive layer 172 located within region A of the active layer 113 is configured as a first electrode 1141 and a second electrode 1142. The array substrate 100 includes a third conductive layer 173, and the third conductive layer 173 located within region A of the active layer 113 is configured as a second conductive structure 112.

[0056] See Figure 5 In some embodiments, along the thickness direction of the substrate 150, the orthographic projection of the first conductive structure 111 is located on both sides of the orthographic projection of the first electrode 1141 along the second direction Y, and the orthographic projection of the second conductive structure 112 is located on both sides of the orthographic projection of the first electrode 1141 along the second direction Y. That is, the orthographic projection of the gate of the transistor 110 is located on both sides of the orthographic projection of the first electrode 1141 along the second direction Y. Therefore, the length of the channel region 1133 is 2L, and the width of the channel region 1133 is W. The orthographic projection of the second electrode 1142 is located on the side of the orthographic projection of the gate that is opposite to the orthographic projection of the first electrode 1141. In the active layer 113, the channel region 1133 is located on both sides of the first conductive region 1131 along the second direction Y, and the second conductive region 1132 is located on the side of the channel region 1133 that is opposite to the first conductive region 1131.

[0057] In some embodiments, the active layer 113 is made of oxide semiconductor. When the oxide semiconductor is exposed to light, photogenerated carriers are generated. These photogenerated carriers can disrupt the normal switching characteristics of the transistor 110, causing discrete conduction of the transistor 110. This application uses a shielding layer 130 to shield the active layer 113 corresponding to the first gap d1 and the second gap d2, which helps to block light from illuminating the active layer 113 corresponding to the first gap d1 and the second gap d2, thereby helping to prevent discrete conduction of the transistor 110.

[0058] For example, oxide semiconductors may include at least one of indium oxide (InO), indium gallium oxide (IGO), indium tin gallium oxide (ITGO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO).

[0059] See Figure 1 In some embodiments, the array substrate 100 includes a first insulating layer 161 located on the side of the first conductive structure 111 facing away from the substrate 150. A first electrode 1141 and a second electrode 1142 are disposed on the side of the first insulating layer 161 facing away from the substrate 150. The first insulating layer 161 is provided with a first via 121 and a second via 122. The first electrode 1141 contacts the first conductive region 1131 through the first via 121, and the second electrode 1142 contacts the second conductive region 1132 through the second via 122. One of the first electrode 1141 and the second electrode 1142 is the source electrode, and the other is the drain electrode.

[0060] See Figure 2 In some embodiments, the array substrate 100 includes a second insulating layer 162 located between the active layer 113 and the first conductive layer 171. The first via 121 and the second via 122 may also penetrate the second insulating layer 162.

[0061] See Figure 4 In some embodiments, the orthographic projection of the first via 121 on the substrate 150 overlaps with the orthographic projection of the shielding layer 130 on the substrate 150. Thus, the first via 121 and the shielding layer 130 are designed to overlap along the thickness direction of the substrate 150, so that the shielding layer 130 can shield at least a portion of the active layer 113 corresponding to the first via 121, thereby expanding the coverage area of ​​the shielding layer 130. The orthographic projection range of the shielding layer 130 is not just exactly matched with the first gap d1, but is designed to extend beyond the boundary of the first gap d1 toward the first via 121, and further extend to a portion of the orthographic projection area of ​​the first via 121. Even if the shielding layer 130 is offset due to process errors, its extended portion can still better cover the boundary of the first gap d1 toward the first via 121, which can better prevent light from shining onto the active layer 113 corresponding to the first gap d1.

[0062] In some embodiments, the orthographic projection of the first via 121 on the substrate 150 is located within the orthographic projection of the shielding layer 130 on the substrate 150. In this way, the shielding layer 130 can completely shield the active layer 113 corresponding to the first via 121. Even if the shielding layer 130 is offset due to process error, its extended portion can still cover the boundary of the first gap d1 facing the first via 121, which can better prevent light from shining onto the active layer 113 corresponding to the first gap d1.

[0063] See Figure 4 In some embodiments, the orthographic projection of the second via 122 on the substrate 150 overlaps with the orthographic projection of the shielding layer 130 on the substrate 150. Thus, the second via 122 and the shielding layer 130 are designed to overlap along the thickness direction of the substrate 150, so that the shielding layer 130 can shield at least a portion of the active layer 113 corresponding to the second via 122, thereby expanding the coverage area of ​​the shielding layer 130. The orthographic projection range of the shielding layer 130 is not just exactly matched with the second gap d2, but is designed to extend beyond the boundary of the second gap d2 toward the second via 122, and further extend to a portion of the orthographic projection area of ​​the second via 122. Even if the shielding layer 130 is offset due to process errors, its extended portion can still better cover the boundary of the second gap d2 toward the second via 122, which can better prevent light from shining onto the active layer 113 corresponding to the second gap d2.

[0064] In some embodiments, the orthographic projection of the second via 122 on the substrate 150 is located within the orthographic projection of the shielding layer 130 on the substrate 150. In this way, the shielding layer 130 can completely shield the active layer 113 corresponding to the second via 122. Even if the shielding layer 130 is offset due to process error, its extended portion can still better cover the boundary of the second gap d2 facing the second via 122, which can better prevent light from shining onto the active layer 113 corresponding to the second gap d2.

[0065] See Figure 4 In some embodiments, the orthographic projection of the shielding layer 130 on the substrate 150 overlaps with the orthographic projection of the first conductive structure 111 on the substrate 150. Thus, the first conductive structure 111 and the shielding layer 130 are designed to overlap along the thickness direction of the substrate 150, enabling the shielding layer 130 to shield at least a portion of the active layer 113 corresponding to the first conductive structure 111, thereby expanding the coverage area of ​​the shielding layer 130. The shielding layer 130 is designed to extend beyond the boundaries of the first gap d1 and the second gap d2 toward the first conductive structure 111, and further extend to a portion of the orthographic projection area of ​​the first conductive structure 111. Even if the shielding layer 130 shifts due to process errors, its extended portion can still effectively cover the boundaries of the first gap d1 and the second gap d2 toward the first conductive structure 111, thus effectively preventing light from shining onto the active layer 113 corresponding to the first gap d1 and the second gap d2.

[0066] See Figure 5In some embodiments, there are multiple first vias 121, which are spaced apart along a first direction to form a row of first vias 122. The first electrode 1141 contacts the first conductive region 1131 through the multiple first vias 121. There are also multiple second vias 122, which are arranged in two rows along a second direction. Each row of second vias 122 includes multiple second vias 122 spaced apart along the first direction. The two rows of second vias 122 are located on opposite sides of the row of first vias 121 along the second direction Y. The second electrode 1142 contacts the second conductive region 1132 through the multiple second vias 122.

[0067] It should be noted that, see Figure 5 The active layer 113 is located in region A, which includes a first region A1 and a second region A2. The first region A1 and the second region A2 are arranged adjacent to each other. The orthographic projection of the second region A2 on the substrate 150 is located within the orthographic projection of the active layer 113 on the substrate 150. Figure 5 In this design, the second region A2 is located on both sides of the first region A1. When transistor 110 is turned on, the potential difference between the source and drain drives the migration of charge carriers in the first region A1. Therefore, the active layer 113 in the first region A1 is the core pathway for charge carrier transport. If photogenerated charge carriers are generated in the active layer 113 in the first region A1, they can directly participate in conduction and form leakage current. In addition, since the active layer 113 in the second region A2 does not have an effective electric field to drive the directional movement of charge carriers, when light shines on the active layer 113 in the second region A2, only randomly moving charge carriers are generated. The photogenerated charge carriers only undergo thermal motion / recombination and cannot form a detectable leakage current. Because there is no electric field acceleration, very few charge carriers can diffuse to the first region A1, and their contribution to the overall leakage current is negligible. Therefore, this application mainly optimizes the placement of the via 132 in the first region A1. The boundaries of the first region A1 along the second direction Y are K1 and K2, respectively. K1 and K2 are fitted by the outermost contours of all first vias 121 and all second vias 122 along the second direction Y. The boundaries of the first region A1 along the first direction X are K3 and K4, respectively. K3 and K4 are also the boundaries of the active layer 113 along the first direction X.

[0068] Equivalent to, see Figure 5 The array substrate 100 includes a first region A1, the orthographic projection of the first region A1 on the substrate 150 is located within the orthographic projection of the active layer 113 on the substrate 150; the orthographic projections of the first conductive structure 111, the end of the first via 121 facing the substrate 150 and the end of the second via 122 facing the substrate 150, as well as the first gap d1 and the second gap d2, are all located within the orthographic projection of the first region A1 on the substrate 150.

[0069] See Figure 5 and Figure 6 In some embodiments, the plurality of through holes 132 include a first through hole 1321, which is located on the outer periphery of the first region A1. Thus, the first through hole 1321 is located outside the first region A1 and not inside it. The first through hole 1321 can be used to discharge the gas generated by the underlying organic film layer in the high-temperature process. Even if light shines through the first through hole 1321 to the active layer 113 of the second region A2, the contribution to the overall leakage current is negligible. Therefore, the design of the first through hole 1321 outside the first region A1 does not need to consider the correspondence with the active layer 113, making the design of the first through hole 1321 simpler and more flexible.

[0070] See Figure 5 and Figure 7 For example, the array substrate 100 includes a second region A2, and at least one through-hole 132 is located in the second region A2. In this way, the space of the second region A2 can be fully utilized to set the through-hole 132, which is beneficial to set more through-holes 132, thereby improving the effect of the shielding layer 130 in venting the gas generated by the underlying organic film layer in the high-temperature process.

[0071] See Figure 7 In some embodiments, the plurality of vias 132 include a second via 1322, which is located within the first region A1. The orthographic projection of the second via 1322 onto the substrate 150 lies within the orthographic projection of the first conductive structure 111 onto the substrate 150. Since the second via 1322 is located within the first region A1, light passing through the second via 1322 and illuminating the active layer 113 of the first region A1 will result in a significant leakage current. By setting the orthographic projection of the second via 1322 onto the substrate 150 within the orthographic projection of the first conductive structure 111 onto the substrate 150, external light passing through the second via 1322 will illuminate the first conductive structure 111, causing the light to be blocked by the first conductive structure 111 and unable to continue illuminating the active layer 113 of the first region A1. In addition, by adding a second via 1322 to the first region A1, the range of via 132 is wider, which is beneficial to improving the effect of the shielding layer 130 in venting the gas generated by the underlying organic film layer during the high-temperature process.

[0072] For example, there are multiple second through holes 1322, and the multiple second through holes 1322 are spaced apart within the first region A1.

[0073] For example, the first direction X can be a direction perpendicular to the first conductive region 1131 to the second conductive region 1132. The second direction Y can be a direction perpendicular to the first conductive region 1131 to the second conductive region 1132. The third direction Z can be the thickness direction of the substrate. Any two of the first, second, and third directions intersect, for example, they are perpendicular to each other.

[0074] In some embodiments, the size of the second via 1322 along the direction from the first conductive region 1131 to the second conductive region 1132 (i.e., the second direction Y) is smaller than the size of the first conductive structure 111 along the direction from the first conductive region 1131 to the second conductive region 1132. This is beneficial because the orthographic projection of the second via 1322 on the substrate 150 can fall completely within the range of the orthographic projection of the first conductive structure 111 along the second direction Y, and the second via 1322 can not exceed the boundary of the first conductive structure 111 along the second direction Y. This is beneficial because it helps to prevent light from shining through the second via 1322 onto the active layer 113 located in the first region A1.

[0075] In some embodiments, the size of the second via 1322 along the direction perpendicular to the first conductive region 1131 to the second conductive region 1132 (i.e., along the first direction X) is smaller than the size of the first conductive structure 111 along the direction perpendicular to the first conductive region 1131 to the second conductive region 1132. This is beneficial because the orthographic projection of the second via 1322 on the substrate 150 can fall completely within the range of the orthographic projection of the first conductive structure 111 along the first direction X, and the second via 1322 can not exceed the boundary of the first conductive structure 111 along the first direction X. This is beneficial because it helps to prevent light from shining through the second via 1322 onto the active layer 113 located in the first region A1.

[0076] In some embodiments, the second through hole 1322 ( Figure 6 The aperture of the hole is smaller than that of the first through hole 1321. Figure 6 Since the first through-hole 1321 is located outside the first region A1, even if light shines through the first through-hole 1321 to the active layer 113 of the second region A2, its contribution to the overall leakage current is negligible. Therefore, the aperture of the first through-hole 1321 outside the first region A1 can be set to be larger, which is beneficial to improving the effect of the shielding layer 130 in venting the gas generated by the organic film layer below in the high-temperature process. In addition, the aperture of the second through-hole 1322 located inside the first region A1 can be set to be smaller, which is beneficial to prevent light from shining through the second through-hole 1322 to the active layer 113 located in the first region A1.

[0077] In other embodiments, the second through hole 1322 ( Figure 6 The diameter of the hole is equal to that of the first through hole 1321 ( Figure 6 The aperture of each through hole 132 is adjusted to make the aperture of each through hole more consistent, which can reduce the design difficulty of each through hole 132.

[0078] See Figure 8 and Figure 9In some embodiments, the orthographic projection of each via 132 on the substrate 150 does not overlap with the orthographic projection of the first region A1 on the substrate 150. Thus, by not providing vias 132 on the shielding layer 130 located in the first region A1, the shielding layer 130 can completely shield the active layer 113 of the first region A1, which can better improve the light blocking effect of the shielding layer 130 and better prevent light from shining on the active layer 113 of the first region A1. In addition, it makes the shape of the shielding layer 130 of the first region A1 simple.

[0079] See Figure 1 In some embodiments, the array substrate 100 includes a display area 100a and a border area 100b disposed adjacently. Exemplarily, the border area 100b is located on the outer periphery of the display area 100a. The display area 100a can be used to display an image. The border area 100b can be located on at least one side of the display area 100a. For example, the border area 100b can surround the outer periphery of the display area 100a, and the border area 100b can form a "black border" surrounding the outer periphery of the display area 100a. A transistor 110 and a shielding layer 130 are located in the border area 100b; the array substrate 100 includes a first electrode layer 140 (… Figure 4 The first electrode layer 140 is located at least in the display area 100a, and the first electrode layer 140 located in the display area 100a includes a plurality of first electrodes.

[0080] For example, the first electrode can be the anode of a light-emitting device.

[0081] In some embodiments, the shielding layer 130 located in the border area and the first electrode layer 140 located in the display area are disposed in the same layer and made of the same material. In this way, the shielding layer 130 and the first electrode layer 140 can be fabricated at the same time, which helps to simplify the fabrication process and reduce the fabrication cost of the shielding layer 130 and the first electrode layer 140.

[0082] In this application's embodiments, "same layer, same material" refers to a base film layer formed from the same material. After patterning and / or other processing of the base film layer, different parts of the base film layer are formed into various structural film layers. The processing techniques for the different structural film layers can be the same or different, and the different structural film layers can have the same or different thicknesses, and can also be on the same horizontal plane or different horizontal planes.

[0083] See Figure 4In other embodiments, a portion of the first electrode layer 140 is located in the border region 100b, and the first electrode layer 140 located in the border region 100b is disposed on the side of the shielding layer 130 away from the substrate 150. Thus, the first electrode layer 140 extends to the border region 100b and extends to the side of the shielding layer 130 away from the substrate 150. The first electrode layer 140 located in the border region 100b and the shielding layer 130 can simultaneously play the role of blocking light, thereby better preventing light from shining on the active layer 113.

[0084] See Figure 4 In some examples, a plurality of perforations 141 are provided on the first electrode layer 140 located in the border area 100b. The orthographic projection of the through hole 132 on the substrate 150 is located within the orthographic projection of the first electrode layer 140 on the substrate 150, and the orthographic projection of the perforation 141 on the substrate 150 is located within the orthographic projection of the shielding layer 130 on the substrate 150. Thus, by providing a plurality of perforations 141 on the first electrode layer 140 located in the border area 100b, it is beneficial for the organic film layer located below the shielding layer 130 to exhaust air during high-temperature processes. In addition, the perforations... Hole 141 and through hole 132 are offset along the thickness direction of substrate 150. Hole 141 and shielding layer 130 are directly opposite each other along the thickness direction. Through hole 132 and first electrode layer 140 are directly opposite each other along the thickness direction. This allows light passing through hole 141 to be blocked by shielding layer 130, preventing it from reaching active layer 113. Furthermore, through hole 132 is blocked by first electrode layer 140, making it difficult for light to pass through. This ensures good exhaust effect while preventing light from reaching active layer 113. In other examples, multiple holes 141 are provided on the first electrode layer 140 in border area 100b. The orthographic projection of through hole 132 on substrate 150 overlaps with the orthographic projection of hole 141 on substrate 150. For example, the orthographic projection of through hole 132 on substrate 150 and the orthographic projection of hole 141 on substrate 150 can coincide. In other examples, the first electrode layer 140 located in the border area 100b may not have a cutout hole 141.

[0085] In other embodiments, the array substrate 100 includes a third insulating layer 163. Figure 4 The third insulating layer 163 is located between the border area 100b and the display area 100a. The third insulating layer 163 is located on the side of the shielding layer 130 facing away from the substrate 150. The first electrode layer 140 is located on the side of the third insulating layer 163 facing away from the substrate 150. The orthographic projection of the first electrode layer 140 on the substrate 150 does not overlap with the orthographic projection of the border area 100b on the substrate 150. That is, the first electrode layer 140 does not extend to the border area 100b.

[0086] For example, the third insulating layer 163 may be a planarization layer.

[0087] See Figure 4 In some embodiments, the array substrate 100 may include a fourth insulating layer 164, which is located on the side of the first electrode 1141 and the second electrode 1142 away from the substrate 150. A shielding layer 130 is located on the side of the fourth insulating layer 164 away from the substrate 150.

[0088] For example, the fourth insulating layer 164 may be a planarization layer.

[0089] See Figure 4 In some embodiments, the array substrate 100 may include a fifth insulating layer 165, which is located between the third conductive layer 173 and the active layer 113.

[0090] In some embodiments, the array substrate 100 includes pixel circuitry disposed on one side of the substrate 150 and located in the display area 100a. A shift register 101 is used to input gate scan signals to the pixel circuitry.

[0091] For example, any one of the first conductive layer 171, the second conductive layer 172, the third conductive layer 173, the shielding layer 130, and the first electrode layer 140 may be made of metals such as titanium, silver, copper, aluminum, molybdenum, aluminum, and manganese, or alloys, or conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), zinc gallium oxide, titanium tantalum oxide, tin oxide, cadmium oxide, and indium oxide, or any one or more of these.

[0092] For example, the shielding layer 130 and the first electrode layer 140 may be made of at least a metal material with a light-shielding function to achieve their light-blocking function.

[0093] For example, the shielding layer 130 can be a stacked structure, such as Ti layer / Al layer / Ti layer, or Mo layer / Ti layer, or Cu layer / Mn layer / Cu layer.

[0094] In some embodiments, the shielding layer 130 may be connected to a fixed potential, for example, to a VSS (low voltage) signal or a VDD (high voltage) signal.

[0095] The following describes the display panel provided in the embodiments of this application.

[0096] This application provides a display panel, which includes the array substrate 100 described in the above embodiment. The display panel may further include a light-emitting functional part and a second electrode. The light-emitting functional part is located on the array substrate 100, on the side of the first electrode facing away from the substrate 150, and the second electrode is located on the side of the light-emitting functional part facing away from the substrate 150. The first electrode, the light-emitting functional part, and the second electrode are collectively constructed as a light-emitting device, that is, the light-emitting device may include a first electrode, a light-emitting functional part, and a second electrode sequentially stacked along a direction away from the substrate 150. The first electrode may be located on the side of the light-emitting functional part facing the substrate 150. Pixel circuitry is used to drive the light-emitting device to emit light.

[0097] In some embodiments, one of the first electrode and the second electrode can be an anode, and the other can be a cathode. This application describes an embodiment where the first electrode is an anode and the second electrode is a cathode. The first electrode can be electrically connected to the pixel circuit.

[0098] In some embodiments, the light-emitting functional unit includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 100. The light-emitting functional unit may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0099] In some embodiments, there may be multiple light-emitting devices, which may be arranged in an array. The multiple light-emitting devices may include a first light-emitting device, a second light-emitting device, and a third light-emitting device that emit different colors. The multiple light-emitting devices include, but are not limited to, red, green, and blue light-emitting devices. In other examples, the multiple light-emitting devices may also include white light-emitting devices.

[0100] The following describes the display device provided in the embodiments of this application.

[0101] This application provides a display device, which may include a display panel. The display device can be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0102] For example, the display panel can be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Light Emitting Diode (LED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, a Mini Light Emitting Diode (MiniLED) display panel, a Micro Light Emitting Diode (Micro LED) display panel, or a Liquid Crystal Display (LCD) display panel, etc. This application uses an OLED display panel as an example for illustration.

[0103] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: substrate; A transistor is disposed on one side of the substrate. The transistor includes an active layer, a first conductive structure, a first electrode, and a second electrode. The active layer includes a channel region, a first conductive region, and a second conductive region, which are located on opposite sides of the channel region. The first conductive structure, the first electrode, and the second electrode are disposed on the side of the active layer away from the substrate. The orthographic projection of the first conductive structure on the substrate at least partially coincides with the orthographic projection of the channel region on the substrate. The first electrode is in contact with the first conductive region, and the second electrode is in contact with the second conductive region. A shielding layer is disposed on the side of the transistor away from the substrate and has multiple through holes; Wherein, there is a first gap between the orthographic projection of the first electrode on the substrate and the orthographic projection of the first conductive structure on the substrate, and there is a second gap between the orthographic projection of the second electrode on the substrate and the orthographic projection of the first conductive structure on the substrate, and the first gap and the second gap are located within the orthographic projection of the shielding layer on the substrate.

2. The array substrate according to claim 1, characterized in that, The array substrate includes a first insulating layer and at least a first via and a second via penetrating the first insulating layer. The first insulating layer is located on the side of the first conductive structure opposite to the substrate. The first electrode and the second electrode are disposed on the side of the first insulating layer opposite to the substrate. The first electrode contacts the first conductive region through the first via, and the second electrode contacts the second conductive region through the second via. Preferably, the orthographic projection of at least one of the first via and the second via on the substrate overlaps with the orthographic projection of the shielding layer on the substrate; Preferably, the orthographic projection of at least one of the first via and the second via on the substrate is located within the orthographic projection of the shielding layer on the substrate; Preferably, the active layer is made of an oxide semiconductor.

3. The array substrate according to claim 1 or 2, characterized in that, The orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the first conductive structure on the substrate; Preferably, the first conductive structure is configured as the gate of the transistor.

4. The array substrate according to claim 2, characterized in that, The array substrate includes a first region, the orthographic projection of the first region on the substrate is located within the orthographic projection of the active layer on the substrate; the orthographic projections of the first conductive structure, the end of the first via facing the substrate and the end of the second via facing the substrate, as well as the first gap and the second gap, are all located within the orthographic projection of the first region on the substrate. The plurality of through holes includes a first through hole, which is located on the outer periphery of the first region.

5. The array substrate according to claim 4, characterized in that, The plurality of through holes includes a second through hole, which is located within the first region; the orthographic projection of the second through hole on the substrate is located within the orthographic projection of the first conductive structure on the substrate; Preferably, the dimension of the second via along the direction from the first conductive region to the second conductive region is smaller than the dimension of the first conductive structure along the direction from the first conductive region to the second conductive region; Preferably, the dimension of the second via along the direction perpendicular to the first conductor region to the second conductor region is smaller than the dimension of the first conductive structure along the direction perpendicular to the first conductor region to the second conductor region.

6. The array substrate according to claim 5, characterized in that, The diameter of the second through hole is less than or equal to the diameter of the first through hole.

7. The array substrate according to claim 4, characterized in that, The orthographic projections of all the vias on the substrate do not overlap with the orthographic projections of the first region on the substrate.

8. The array substrate according to claim 4, characterized in that, The array substrate includes a second region, which is disposed adjacent to the first region; the orthographic projection of the second region on the substrate is located within the orthographic projection of the active layer on the substrate. At least one of the through holes is located in the second region.

9. The array substrate according to claim 1 or 2, characterized in that, The array substrate includes a display area and a border area disposed adjacent to each other; the transistor and the shielding layer are located in the border area; the array substrate includes a first electrode layer, the first electrode layer being located at least in the display area, and the first electrode layer located in the display area includes a plurality of first electrodes; The shielding layer and the first electrode layer are made of the same layer and the same material; or... A portion of the first electrode layer is located in the frame area, and the first electrode layer located in the frame area is disposed on the side of the shielding layer away from the substrate; the first electrode layer located in the frame area is provided with a plurality of perforations, the orthographic projection of the perforations on the substrate is located within the orthographic projection of the first electrode layer on the substrate, and the orthographic projection of the perforations on the substrate is located within the orthographic projection of the shielding layer on the substrate.

10. A display panel, characterized in that, Includes the display panel described in any one of claims 1-9 above.

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