Epitaxial method for improving width of transition region of overweight B-doped substrate double-layer low-resistance silicon epitaxial wafer and epitaxial wafer thereof

Abstract

The invention provides an epitaxial method for improving the width of a transition region of a double-layer low-resistance silicon epitaxial wafer of an overweight B-doped substrate and the epitaxial wafer obtained by the epitaxial method. The method mainly comprises the step of sequentially arranging a P-type epitaxial inner layer, an N-type buffer layer and a P-type epitaxial outer layer on the B-doped substrate. The method has the advantages that compared with an existing direct epitaxial process, the phenomenon that impurities such as B in the overweight B-doped substrate are diffused to the epitaxial layer can be remarkably reduced by optimizing the epitaxial structure and the process design, and the electrical parameter stability of the epitaxial layer is improved; compared with a traditional epitaxial scheme adopting a P-type buffer layer or an intrinsic Si buffer layer, the epitaxial structure has the advantages that the width of the transition region is greatly reduced, the transition region is steeped, and the voltage resistance and the electrical parameter consistency of the component are improved.

Description

An epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on an ultra-heavily boron-doped substrate and the epitaxial wafer thereof. Technical Field

[0001] This invention belongs to the field of silicon epitaxial technology, specifically an epitaxial method for improving the width of the transition region of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate, and the epitaxial wafer thereof. Background Technology

[0002] In the field of semiconductor device manufacturing, epitaxial growth is a core technology. By growing an epitaxial layer with specific doping type, concentration, and thickness on a substrate surface, the electrical performance of the device can be controlled to meet the chip performance requirements of different application scenarios. Among them, epitaxial structures based on boron-doped p-type silicon substrates are widely used in the fabrication of various semiconductor devices such as power devices and integrated circuits.

[0003] Currently, epitaxial processes based on boron-doped P-type silicon substrates are mainly divided into two categories, but both types of processes have significant technical defects that severely restrict the performance improvement of semiconductor devices, as detailed below:

[0004] The first type is direct epitaxy, which involves directly growing a P-type or N-type epitaxial layer on a boron-doped P-type silicon substrate (such as a heavily boron-doped P++ substrate). While this process is simple and efficient, the significant difference in doping concentration between the substrate and the epitaxial layer causes boron to diffuse into the epitaxial layer during growth, resulting in a relatively wide and gradual transition region. This widening and smoothing of the transition region severely affects the electrical isolation performance of the device, distorting the electric field distribution within the device and significantly reducing the voltage withstand capability of the final component, thus failing to meet the core requirement of high voltage withstand for high-voltage semiconductor devices.

[0005] The second type is epitaxial processing with a buffer layer. To improve the defects of direct epitaxy, this process adds a buffer layer between the substrate and the epitaxial layer. The buffer layer is usually a P-type buffer layer or an intrinsic Si buffer layer. However, this improvement still fails to completely solve the problem of diffusion of high-concentration boron impurities in the substrate.

[0006] In summary, existing epitaxial processes based on boron-doped p-type silicon substrates all suffer from insurmountable defects, either resulting in insufficient device breakdown voltage or increased power consumption. They fail to balance high breakdown voltage with excellent current-carrying capacity, severely limiting their application in mid-to-high-end semiconductor devices. Therefore, there is an urgent need for an epitaxial process solution that can address these technical problems, overcome existing technological bottlenecks, and improve the overall performance of semiconductor devices. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide an epitaxial method and epitaxial wafer for improving the width of the transition region of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate.

[0008] To achieve the above objectives, this application adopts the following technical solution: an epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate, comprising the steps of sequentially depositing a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer on a boron-doped substrate. By introducing an additional inversion low-resistivity buffer layer into the inner layer of the epitaxial wafer before performing epitaxial growth in the outer layer region, this optimized process design can effectively compensate for the P-type impurities introduced by the substrate self-doping effect and the low-resistivity inner layer region. This process not only significantly reduces the transition gradient of impurity distribution but also greatly compresses the transition region width between the inner and outer layers, thereby significantly improving the overall performance and structural integrity of the device.

[0009] Furthermore, the specific methods include the following steps:

[0010] S1. Pre-treat the reaction chamber of the epitaxial equipment by introducing HCl for etching;

[0011] S2. Load the B-doped substrate material into the epitaxial equipment reaction chamber 1 after the treatment in step S1; introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the first P-type epitaxial inner layer.

[0012] S3. Take out the epitaxial wafer prepared in S2 and put it into the epitaxial equipment reaction chamber 2 after the treatment in step S1. Introduce PH3 and SiHCl3 into the epitaxial equipment reaction chamber 2 to grow the second N-type buffer layer.

[0013] S4. Take out the epitaxial wafer prepared in S3 and put it into the epitaxial equipment reaction chamber 1 after the treatment in step S1. Introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the third P-type epitaxial outer layer.

[0014] Furthermore, the growth temperature in S2, S3, and S4 is 1110-1150℃, and the growth rate is 3.5-3.7μm / min.

[0015] Furthermore, the resistivity of the boron-doped substrate material is 0.001 ohm·cm - 0.003 ohm·cm.

[0016] Furthermore, in step S1, the etching temperature is 1160-1180℃, the etching time is 25-35s, and the HCl flow rate is 50-70slm.

[0017] Furthermore, in step S2, the concentration of B2H6 introduced is 15000-25000ppm, the flow rate of B2H6 is 158-162sccm, and the flow rate of SiHCl3 introduced is 11-13slm.

[0018] Furthermore, the resistivity of the inner layer of the epitaxial wafer in step S2 is 0.1 ohm·cm, and the growth time is stopped when the inner layer thickness reaches 3 μm.

[0019] Furthermore, in step S3, the concentration of PH3 introduced is 2500-3500 ppm, the flow rate of PH3 is 150-250 sccm, and the flow rate of SiHCl3 introduced is 11-13 slm.

[0020] Furthermore, the resistivity of the N-type buffer layer in step S3 is 0.1 ohm·cm, and the growth time is stopped when the thickness of the N-type buffer layer reaches 0.1μm-0.3μm.

[0021] Furthermore, in step S4, the concentration of B2H6 introduced is 15000-25000ppm, the flow rate of B2H6 is 48-52sccm, the flow rate of SiHCl3 introduced is 11-13slm, and the growth time is stopped when the thickness of the outer layer reaches 2.3μm.

[0022] The specific operational steps and related parameter settings described above have been carefully designed and optimized, and these steps and parameters have a significant synergistic effect. By strictly controlling each step of the operation process, it can be effectively ensured that the thickness of the final transition layer is precisely controlled within the range of 0.1-0.3 μm. If the thickness of the transition layer exceeds this specified range, an additional PN junction structure may be introduced between the inner and outer layers of the product. The formation of this structure will greatly change the electrical characteristics of the product, thereby seriously affecting its electrical parameter performance and causing the overall function to fail to meet the design requirements.

[0023] The epitaxial wafer obtained by the above preparation method has a structure in which a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer are sequentially grown on a B-doped substrate, and the thickness of the N-type buffer layer is 0.1-0.3 μm.

[0024] In summary, by adopting the above technical solutions, this application achieves the following beneficial effects: Compared with existing direct epitaxial processes, this invention, through optimizing the epitaxial structure and process design, can significantly reduce the diffusion of impurities such as B in the heavily B-doped substrate to the epitaxial layer, effectively reducing impurity contamination of the epitaxial layer and improving the stability of the electrical parameters of the epitaxial layer; Compared with traditional epitaxial schemes using P-type buffer layers or intrinsic Si buffer layers, this invention significantly reduces the width of the transition region, making the transition region steeper, thereby improving the withstand voltage of the device. Attached Figure Description

[0025] Figure 1 is a schematic diagram of the structure of the epitaxial wafer in Embodiment 1 of the present invention.

[0026] Figure 2 is a comparative diagram of longitudinal extension resistance test in Comparative Example 1. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention. It should also be noted that the HCl and SiHCl3 introduced in the present invention are both high-purity gases, and B2H6 and PH3 are directly purchased existing products. Unless otherwise specified, all other gases used are existing technologies.

[0028] Example 1: The present invention provides an epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate, comprising the steps of sequentially depositing a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer on the boron-doped substrate. The specific steps are as follows:

[0029] S1. Pre-treat the reaction chamber of the epitaxial equipment by introducing HCl for etching;

[0030] S2. Load the B-doped substrate material into the epitaxial equipment reaction chamber 1 after the treatment in step S1; introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the first P-type epitaxial inner layer.

[0031] S3. Take out the epitaxial wafer prepared in S2 and put it into the epitaxial equipment reaction chamber 2 after the treatment in step S1. Introduce PH3 and SiHCl3 into the epitaxial equipment reaction chamber 2 to grow the second N-type buffer layer.

[0032] S4. Take out the epitaxial wafer prepared in S3 and put it into the epitaxial equipment reaction chamber 1 after the treatment in step S1. Introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the third P-type epitaxial outer layer.

[0033] Furthermore, in steps S2, S3, and S4, the growth temperature is 1110℃, and the growth rate is 3.5 μm / min; in step S1, the etching temperature is 1160℃, the etching time is 25 s, and the HCl flow rate is 50 slm; in step S2, the B2H6 concentration is 15000 ppm, the B2H6 flow rate is 158 sccm, the SiHCl3 flow rate is 11 slm, and the growth time is until the inner layer thickness reaches 3 μm; in step S3, the PH3 concentration is 2500 ppm, the PH3 flow rate is 150 sccm, and the SiHCl3 flow rate is 11 slm; in step S4, the B2H6 concentration is 15000 ppm, the B2H6 flow rate is 48 sccm, the SiHCl3 flow rate is 11 slm, and the growth time is until the outer layer thickness reaches 2.3 μm.

[0034] The resistivity of the boron-doped substrate material in the epitaxial wafer prepared by the above steps is 0.003 ohm·cm, the resistivity of the inner layer of the epitaxial wafer prepared in step S2 is 0.1 ohm·cm, the resistivity of the N-type buffer layer is 0.1 ohm·cm, and the thickness of the N-type buffer layer reaches 0.3 μm. The resulting epitaxial wafer structure is shown in Figure 1.

[0035] Example 2: The present invention provides an epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate, comprising the steps of sequentially depositing a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer on a boron-doped substrate. The specific steps are as follows:

[0036] S1. Pre-treat the reaction chamber of the epitaxial equipment by introducing HCl for etching;

[0037] S2. Load the B-doped substrate material into the epitaxial equipment reaction chamber 1 after the treatment in step S1; introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the first P-type epitaxial inner layer.

[0038] S3. Take out the epitaxial wafer prepared in S2 and put it into the epitaxial equipment reaction chamber 2 after the treatment in step S1. Introduce PH3 and SiHCl3 into the epitaxial equipment reaction chamber 2 to grow the second N-type buffer layer.

[0039] S4. Remove the epitaxial wafer prepared in S3 and place it into the epitaxial equipment reaction chamber 1 after the treatment in step S1. Introduce B2H6 and SiHCl3 into the reaction chamber 1 to grow the third P-type epitaxial outer layer.

[0040] Furthermore, in steps S2, S3, and S4, the growth temperature is 1150℃, and the growth rate is 3.7 μm / min; in step S1, the etching temperature is 1180℃, the etching time is 35 s, and the HCl flow rate is 70 slm; in step S2, the B2H6 concentration is 25000 ppm, the B2H6 flow rate is 162 sccm, the SiHCl3 flow rate is 13 slm, and the growth time is until the inner layer thickness reaches 3 μm; in step S3, the PH3 concentration is 3500 ppm, the PH3 flow rate is 250 sccm, and the SiHCl3 flow rate is 13 slm; in step S4, the B2H6 concentration is 20000 ppm, the B2H6 flow rate is 52 sccm, the SiHCl3 flow rate is 13 slm, and the growth time is until the outer layer thickness reaches 2.3 μm.

[0041] The resistivity of the boron-doped substrate material in the epitaxial wafer prepared by the above steps is 0.001 ohm·cm, the resistivity of the inner layer of the epitaxial wafer in step S2 is 0.1 ohm·cm, the resistivity of the N-type buffer layer is 0.1 ohm·cm, and the thickness of the N-type buffer layer reaches 0.1 μm.

[0042] Example 3: The present invention provides an epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on a heavily boron-doped substrate, comprising the steps of sequentially depositing a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer on a boron-doped substrate. The specific steps are as follows:

[0043] S1. Pre-treat the reaction chamber of the epitaxial equipment by introducing HCl for etching;

[0044] S2. Load the B-doped substrate material into the epitaxial equipment reaction chamber 1 after the treatment in step S1; introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the first P-type epitaxial inner layer.

[0045] S3. Take out the epitaxial wafer prepared in S2 and put it into the epitaxial equipment reaction chamber 2 after the treatment in step S1. Introduce PH3 and SiHCl3 into the epitaxial equipment reaction chamber 2 to grow the second N-type buffer layer.

[0046] S4. Take out the epitaxial wafer prepared in S3 and put it into the epitaxial equipment reaction chamber 1 after the treatment in step S1. Introduce B2H6 and SiHCl3 into the epitaxial equipment reaction chamber 1 to grow the third P-type epitaxial outer layer.

[0047] Furthermore, in steps S2, S3, and S4, the growth temperature is 1130℃, and the growth rate is 3.6 μm / min; in step S1, the etching temperature is 1170℃, the etching time is 30 s, and the HCl flow rate is 60 slm; in step S2, the B2H6 concentration is 20000 ppm, the B2H6 flow rate is 160 sccm, the SiHCl3 flow rate is 12 slm, and the growth time is until the inner layer thickness reaches 3 μm; in step S3, the PH3 concentration is 3000 ppm, the PH3 flow rate is 190 sccm, and the SiHCl3 flow rate is 12 slm; in step S4, the B2H6 concentration is 20000 ppm, the B2H6 flow rate is 50 sccm, the SiHCl3 flow rate is 12 slm, and the growth time is until the outer layer thickness reaches 2.3 μm.

[0048] The resistivity of the boron-doped substrate material of the epitaxial wafer prepared by the above steps is 0.002 ohm·cm, the resistivity of the inner layer of the epitaxial wafer prepared by step S2 is 0.1 ohm·cm, the resistivity of the N-type buffer layer is 0.1 ohm·cm, and the thickness of the N-type buffer layer reaches 0.2 μm.

[0049] Comparative Example 1 is provided to illustrate the technical effects obtained by the present invention. Comparative Example 1 is a growth process without a buffer layer, which includes the following steps:

[0050] S1. Pre-treat the reaction chamber of the EP200 epitaxial equipment by introducing HCl for etching. The HCl flow rate is 60 slm, the etching temperature is 1170℃, and the etching time is 30 s.

[0051] S2. Prepare the B-doped substrate material. Load the substrate material into the reaction chamber of the EP200 epitaxial equipment after the treatment in step S1. Introduce B2H6 and SiHCl3 at a concentration of 20000ppm into the reaction chamber of the EP200 epitaxial equipment. The flow rate of B2H6 is 160sccm and the flow rate of SiHCl3 is 12slm. Grow a low-resistivity inner layer with a thickness of 2.3μm under the conditions of growth temperature of 1130℃ and growth rate of 3.6μm / min.

[0052] S3. Introduce B2H6 and SiHCl3 at a concentration of 20000ppm into the reaction chamber of the EP200 epitaxial equipment. The flow rate of B2H6 is 50sccm and the flow rate of SiHCl3 is 12slm. Grow a low-resistivity outer layer with a thickness of 3μm at a growth temperature of 1130℃ and a growth rate of 3.6μm / min.

[0053] The extended resistance of the epitaxial wafers obtained in each embodiment and comparative example was tested, and the results are shown in Figure 2. In the figure, the horizontal axis represents the test thickness, and the vertical axis represents the volume resistivity. The steepness or gentleness of the curve between 0-2.3 μm on the horizontal axis represents the width of the transition zone between the inner and outer layers of the product. The steeper the curve, the smaller the width of the transition zone, and the better the product performance. As can be seen from the curves in the figure, the width of the transition zone of the epitaxial wafers obtained in Examples 1 to 3 is better than that of the conventional process.

[0054] Meanwhile, the present invention also provides Comparative Examples 2-3, which have the same preparation steps as the embodiments of the present invention, but different key condition parameters, to illustrate the technical effects obtained by the present invention, as shown in Table 1:

[0055] Key parameters for each experimental group: Transition zone width / Test method: Example 1: See Example 1, 0.62 μm / Spread resistance test; Example 2: See Example 2, 0.5 μm / Spread resistance test; Example 3: See Example 3, 0.61 μm / Spread resistance test; Comparative Example 2: Steps S2, S4, S6, growth temperature 1100℃, growth rate 3.4 μm / min, 0.76 μm / Spread resistance test; Comparative Example 3: Steps S2, S4, S6, growth temperature 1160℃, growth rate 3.8 μm / min, 0.73 μm / Spread resistance test. surface

[0056] The epitaxial wafer prepared by the method of this invention has a transition region width of less than 0.7 μm, while the transition region width of existing P-type buffer layers is generally greater than 2 μm. Since the buffer layer is an intrinsic silicon layer, the transition region is prone to bulging, hindering current flow. Therefore, the epitaxial wafer of this invention has a relatively steep transition region, making it a core process support for high-end semiconductor devices such as power devices and special devices. When applied to low-voltage power devices, it can significantly reduce on-resistance, reduce power loss, and improve the device's current carrying capacity and energy efficiency. When adapted to TVS devices, it can accelerate transient response speed and enhance surge voltage suppression performance. When used in BCD processes, it can optimize high- and low-voltage compatible integration, improving chip integration density and stability. Its advantages in both current-carrying and voltage-resistance characteristics meet the stringent performance requirements of high-end semiconductor devices, helping products to be stably applied in high-reliability scenarios.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An epitaxial method for improving the transition region width of a bilayer low-resistivity silicon epitaxial wafer on an ultra-heavily boron-doped substrate, characterized in that, The process includes the steps of sequentially depositing a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer on a B-doped substrate.

2. The method according to claim 1, characterized in that, The resistivity of the boron-doped substrate material is 0.001 ohm·cm to 0.003 ohm·cm.

3. The method according to claim 1, characterized in that, The process includes the following steps: S1, pre-treating the epitaxial equipment reaction chamber by introducing HCl for etching at a temperature of 1160-1180℃ for 25-35 seconds at a flow rate of 50-70 slm; S2, loading the boron-doped substrate material into the epitaxial equipment reaction chamber 1 after step S1; introducing B2H6 and SiHCl3 into the reaction chamber 1 to grow the first P-type epitaxial inner layer, with a B2H6 concentration of 15000-25000 ppm, a flow rate of 158-162 sccm, and a SiHCl3 flow rate of 11-13 slm; S3, removing the epitaxial wafer prepared in S2 and loading it into the epitaxial equipment reaction chamber 2 after step S1. In the epitaxial reaction chamber 2, PH3 and SiHCl3 are introduced to grow the second N-type buffer layer. The concentration of PH3 is 2500-3500 ppm, the flow rate of PH3 is 150-250 sccm, and the flow rate of SiHCl3 is 11-13 slm. In step S4, the epitaxial wafer prepared in step S3 is taken out and placed into the epitaxial reaction chamber 1 after the treatment in step S1. B2H6 and SiHCl3 are introduced into the reaction chamber 1 to grow the third P-type epitaxial outer layer.

4. The method according to claim 2, characterized in that, The growth temperature in S2, S3, and S4 is 1110-1150℃, and the growth rate is 3.5-3.7μm / min.

5. The method according to claim 3, characterized in that, The resistivity of the inner layer of the epitaxial wafer described in step S2 is 0.1 ohm·cm, and the growth time is stopped when the inner layer thickness reaches 3 μm.

6. The method according to claim 3, characterized in that, The resistivity of the N-type buffer layer in step S3 is 0.1 ohm·cm, and the growth time is stopped when the thickness of the N-type buffer layer reaches 0.1 μm-0.3 μm.

7. The method according to claim 2, characterized in that, In step S4, the concentration of B2H6 introduced is 15000-25000ppm, the flow rate of B2H6 is 48-52sccm, the flow rate of SiHCl3 introduced is 11-13slm, and the growth time is stopped when the thickness of the outer layer reaches 2.3μm.

8. A boron-doped epitaxial wafer, characterized in that, The epitaxial wafer structure consists of a P-type epitaxial inner layer, an N-type buffer layer, and a P-type epitaxial outer layer sequentially grown on a B-doped substrate, obtained by the preparation method described in claims 1-7.

9. The epitaxial wafer according to claim 8, characterized in that, The thickness of the N-type buffer layer is 0.1-0.3 μm.

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