LDMOS device and manufacturing method thereof

Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a source region; a drain region; a gate electrode; at least part of the drift region is located between the source region and the drain region; the field oxide layer is located on the drift region; the low-K dielectric layer is located on the grid electrode and the field oxide layer, and the dielectric constant of the low-K dielectric layer is smaller than that of the field oxide layer; the field plate layer is located on the low-K dielectric layer and extends to the position above the source electrode region, and the field plate layer is made of a conductive material; the source end metal connecting wire is used for short-circuiting the field plate layer and the source electrode region through a contact hole, so that the potential of the field plate layer is the same as that of the source electrode region; and the drain end metal connecting wire is electrically connected with the drain electrode region. The drain end metal connecting wire can have a larger area so as to reduce the on resistance of the device. And the low-K dielectric layer is arranged between the field plate layer and the grid electrode, so that the parasitic capacitance Cgd of the grid electrode can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an LDMOS device, and also to a method for manufacturing an LDMOS device. Background Technology

[0002] As a core device in BCD (Bipolar-CMOS-DMOS) technology, LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) typically requires low on-resistance and high voltage withstand capability. The design of the field plate structure is crucial to LDMOS, as it directly affects the voltage withstand capability and gate parasitic capacitance Cgd of the LDMOS device.

[0003] An exemplary LDMOS field plate structure involves a metal field plate on the field oxide layer, which is shorted to the same metal interconnect as the source region of the LDMOS via a contact hole. However, since the metal field plate is a certain distance from the source region, this metal interconnect occupies a large area. If the aforementioned metal interconnect and the drain metal interconnect are located on the same metal layer, the space for the drain metal interconnect will be squeezed, forcing the drain metal interconnect area to be smaller, which is detrimental to reducing the on-resistance of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide an LDMOS device with a large wiring space for the drain metal interconnect and its manufacturing method.

[0005] An LDMOS device includes: a source region; a drain region; a gate; a drift region, at least partially located between the source region and the drain region; a field oxide layer located on the drift region; a low-k dielectric layer located on the gate and the field oxide layer, wherein the dielectric constant of the low-k dielectric layer is less than the dielectric constant of the field oxide layer; a field plate layer located on the low-k dielectric layer and extending above the source region, wherein the field plate layer is made of a conductive material; a source metal interconnect connecting the field plate layer and the source region through a contact hole, such that the potential of the field plate layer is the same as the potential of the source region; and a drain metal interconnect electrically connected to the drain region.

[0006] In the aforementioned LDMOS device, because the field plate extends above the source region, the area of ​​the source metal interconnect that shorts the field plate and the source region through the target contact hole can be relatively small. This allows for a larger wiring space for the drain metal interconnect, resulting in a larger drain metal interconnect area and reduced on-resistance. Furthermore, by placing a low-k dielectric layer between the field plate and the gate, the gate parasitic capacitance Cgd can be effectively reduced.

[0007] In one embodiment, the field plate layer is made of metal and / or alloy.

[0008] In one embodiment, the low-k dielectric layer and the field plate layer completely cover the gate, and the low-k dielectric layer extends onto the source region.

[0009] In one embodiment, the height difference between the bottom of the contact hole on the field plate layer and the bottom of the contact hole on the source region is less than 1000 Å.

[0010] In one embodiment, the contact hole includes a first contact hole located on the field plate layer and a second contact hole located on the source region, or the contact hole is a large hole with one part located on the field plate layer and the other part located on the source region.

[0011] In one embodiment, the gate is located above the region between the source region and the drain region.

[0012] In one embodiment, the source region, drain region, and drift region have a first conductivity type, and the doping concentration of the source region and drain region is greater than the doping concentration of the drift region. The LDMOS device further includes: a second conductivity type well region, in which the source region is located; the first conductivity type and the second conductivity type are opposite conductivity types; a body lead region, having a second conductivity type, located in the second conductivity type well region, and the doping concentration of the body lead region is greater than the doping concentration of the second conductivity type well region; the body lead region is electrically connected to the source metal interconnect through a body contact hole.

[0013] In one embodiment, the field oxide layer extends from the edge of the drain region to the gate.

[0014] In one embodiment, the orthographic projection of the contact hole onto the upper surface of the source region falls entirely within the upper surface of the source region.

[0015] In one embodiment, the LDMOS device further includes a sidewall located on the side of the gate.

[0016] In one embodiment, the low-k dielectric layer and the field plate layer are patterned using the same photomask.

[0017] In one embodiment, the thickness of the low-k dielectric layer is less than the thickness of the field oxygen layer.

[0018] A method for manufacturing an LDMOS device includes: obtaining a wafer having a drift region, a source region, a drain region, a gate, and a field oxide layer, wherein the drift region is at least partially located between the source region and the drain region, and the field oxide layer is formed on the drift region; forming a low-k dielectric layer on the gate and the field oxide layer, wherein the dielectric constant of the low-k dielectric layer is less than the dielectric constant of the field oxide layer; forming a conductive field plate layer on the low-k dielectric layer; patterning the field plate layer and the low-k dielectric layer, wherein the patterned field plate layer extends above the source region; and forming an interlayer dielectric on the wafer. A dielectric layer is formed; the interlayer dielectric layer is patterned to form a target contact hole and a drain contact hole, the target contact hole being formed on the source region and the field plate layer, and the drain contact hole being formed on the drain region; conductive material is filled in the target contact hole and the drain contact hole; a source metal interconnect and a drain metal interconnect are formed on the interlayer dielectric layer, the source metal interconnect short-circuiting the field plate layer and the source region through the target contact hole, such that the potential of the field plate layer is the same as the potential of the source region, and the drain metal interconnect is electrically connected to the drain region through the drain contact hole.

[0019] In the above-described LDMOS device manufacturing method, the field plate layer extends above the source region. Therefore, the area of ​​the source metal interconnect that shorts the field plate layer and the source region through the target contact hole can be small, thereby allowing the drain metal interconnect to have a larger wiring space and a larger area, thus reducing the on-resistance of the device. Furthermore, by providing a low-k dielectric layer between the field plate layer and the gate, the gate parasitic capacitance Cgd can be effectively reduced. Attached Figure Description

[0020] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0021] Figure 1 This is a schematic diagram of an exemplary LDMOS field plate structure.

[0022] Figure 2 This is a schematic diagram of the structure of an LDMOS device in one embodiment of this application.

[0023] Figure 3 This is a schematic diagram of the structure of an LDMOS device in another embodiment of this application.

[0024] Figure 4 This is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of this application.

[0025] Figures 5a to 5e This is a schematic cross-sectional view of the wafer during the manufacturing process using the manufacturing method of an LDMOS device according to an embodiment of this application.

[0026] Figure 6 This is a flowchart of a sub-step of step S410 in one embodiment of this application. Detailed Implementation

[0027] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0033] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0034] Figure 1 An exemplary LDMOS field plate structure is shown, including a drift region 112, a P-well 114, a drain region 122, a source region 124, a body lead-out region 126, a gate 132, a field oxide layer 142, a metal field plate 144, a contact hole 152, a contact hole 154, a source metal interconnect 162, and a drain metal interconnect 164. Figure 1 In the field plate structure shown, the metal field plate 144 is located above the field oxide layer 142, causing a step difference (i.e., a different depth at the bottom of the contact hole) between the contact hole 154 and other contact holes in other areas (such as contact hole 152). This leads to problems such as insufficient hole etching windows in the process. Furthermore, in Figure 1 In the field plate structure shown, the source metal interconnect 162 of M1 (first metal layer) short-circuit the source region 124 with the metal field plate 144. The source metal interconnect 162 needs to extend from above the source region 124 to above the metal field plate 144. The source metal interconnect 162 occupies a large amount of device area, which results in a small lead-out area of ​​the drain metal interconnect 164 of M1, which is not conducive to reducing the on-resistance of the device.

[0035] This application proposes an LDMOS device with a novel field plate structure. Figure 2 This is a schematic diagram of an LDMOS device according to an embodiment of this application, including a drain region 222, a source region 224, a drift region 212, a gate 232, a field oxide layer 242, a low-k dielectric layer 243, a field plate layer 244, a drain metal interconnect 262, and a source metal interconnect 264. The drift region 212 is at least partially located between the source region 224 and the drain region 222, and the gate 232 is located above the region between the source region 224 and the drain region 222. The field oxide layer 242 is located on the drift region 212. Figure 2 In the illustrated embodiment, gate 232 is located between field oxide layer 242 and source region 224. A low-k dielectric layer 243 is located on gate 232 and field oxide layer 242, and the dielectric constant of the material of low-k dielectric layer 243 is less than the dielectric constant of the material of field oxide layer 242 (silicon dioxide). In one embodiment of this application, the dielectric constant of the material of low-k dielectric layer 243 is <4 and ≥2. In one embodiment of this application, the material of low-k dielectric layer 243 is silicon oxynitride. A conductive field plate layer 244 is located on low-k dielectric layer 243 and extends above source region 224. In one embodiment of this application, the material of field plate layer 244 is metal and / or alloy. A source-side metal interconnect 264 shorts field plate layer 244 and source region 224 through target contact hole 254, such that the potential of field plate layer 244 is the same as the potential of source region 224. The drain metal connection 262 is electrically connected to the drain region 222 through the drain contact hole 252. The drain region 222, source region 224, and drift region 212 have the same conductivity type, denoted as the first conductivity type. Figure 2In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0036] In the aforementioned LDMOS device, since the field plate layer 244 extends above the source region 224, the area of ​​the source metal interconnect 264, which shorts the field plate layer 244 and the source region 224 through the target contact hole 254, can be relatively small. This allows the drain metal interconnect 262 to have a larger wiring space, and the drain metal interconnect 262 can have a larger area, for example, like... Figure 2 The layer extends above the field plate layer 244 to reduce the on-resistance of the device. Furthermore, by providing a low-k dielectric layer 243 between the field plate layer 244 and the gate 232, the gate parasitic capacitance Cgd can be effectively reduced.

[0037] The target contact hole 254, which shorts the source region 224 and the field plate layer 244, can be used in addition to... Figure 2 The large holes shown, one part located on the field plate layer 244 and the other part on the source region 224, can also be used as follows: Figure 3 The conventional contact holes shown include a first target contact hole 254a located on the field plate layer 244 and a second target contact hole 254b located on the source region 224. Figure 2 In the illustrated embodiment, the orthographic projection of the target contact hole 254 onto the upper surface of the source region falls entirely within the upper surface of the source region. Figure 3 In the embodiment shown, the orthographic projections of the first target contact hole 254a and the second target contact hole 254b onto the upper surface of the source region fall completely within the upper surface of the source region.

[0038] In one embodiment of this application, the low-k dielectric layer 243 and the field plate layer 244 completely cover the gate 232 to improve the effect of shielding the gate parasitic capacitance. In another embodiment of this application, the low-k dielectric layer 243 extends onto the source region 224. The low-k dielectric layer 243 and the field plate layer 244 can be patterned using the same photomask, therefore the projected shapes of the low-k dielectric layer 243 and the field plate layer 244 are identical.

[0039] Because the thickness of the low-k dielectric layer 243 is much smaller than the thickness of the field oxygen layer 242, the step difference of the target contact hole 254 (and the step difference between the first target contact hole 254a and the second target contact hole 254b) is relatively smaller than that of the target contact hole 254. Figure 1 The step difference between contact hole 154 and contact hole 152 shown is much smaller. In one embodiment of this application, the height difference between the bottom of the contact hole on the field plate layer 244 and the bottom of the contact hole on the source region 224 is less than 1000 Å.

[0040] exist Figure 2In the illustrated embodiment, the LDMOS device further includes a second conductivity type well region 214 and a body exit region 226. The source region 224 and the body exit region 226 are located within the second conductivity type well region 214. The body exit region 226 has a second conductivity type, and its doping concentration is greater than that of the second conductivity type well region 214. The body exit region 226 is electrically connected to the source metal interconnect 264 through a body contact hole 256.

[0041] exist Figure 2 In the embodiment shown, the drain region 222 and the source region 224 are N+ regions, and the body lead-out region 226 is a P+ region.

[0042] In one embodiment of this application, the field oxide layer 242 extends from the edge of the drain region 222 to the gate 232, covering a portion of the area near one edge of the gate 232. In another embodiment of this application, the LDMOS device further includes a metal silicide area block (SAB) layer. Accordingly, metal silicides are formed on the surfaces of the drain region 222, the source region 224, the body lead-out region 226, and the gate 232. The purpose of the metal silicide is to form an ohmic contact to reduce contact resistance. Self-aligned metal silicide (salicide) is a relatively simple and convenient contact metallization process. During the fabrication of semiconductor devices, some areas require a salicide process, while others require a non-self-aligned metal silicide (non-salicide) process. For devices requiring a non-salicide process, the properties of salicide are utilized, and the areas requiring non-salicide are covered with a material that does not react with metal. This material used to cover non-salicide devices is called SAB.

[0043] In one embodiment of this application, the metal silicide can be made of CoSi. x NiSi x PtSi x Or a combination of these compounds.

[0044] In one embodiment of this application, the metal silicide barrier layer includes an oxide layer, such as silicon oxide. Further, the metal silicide barrier layer may also be a multilayer structure, for example, including an oxide layer, a nitride layer, and an oxide oxy ...

[0045] In one embodiment of this application, the thickness of the low-k dielectric layer 243 is less than half the thickness of the field oxide layer 242.

[0046] In one embodiment of this application, the gate 232 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the material of the gate 232.

[0047] In one embodiment of this application, a gate dielectric layer is further provided at the bottom of the gate 232. In one embodiment of this application, the gate dielectric layer may include conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may include a generally higher dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric material may include, but is not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0048] In one embodiment of this application, the LDMOS device further includes a sidewall 234 located on the side of the gate 232.

[0049] This application provides a method for manufacturing an LDMOS device, which can be used to manufacture the LDMOS device described in any of the above embodiments. Figure 4 This is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of this application, including the following steps:

[0050] S410, to obtain a wafer with a drift region, source region, drain region, gate and field oxide layer formed.

[0051] The drift region 212 is at least partially located between the source region 224 and the drain region 222, and the field oxygen layer 242 is formed on the drift region 212. The structure after step S410 is shown in [reference needed]. Figure 5d .

[0052] S420 forms a low-k dielectric layer on the gate and the field oxide layer.

[0053] A low-k dielectric layer is deposited on the wafer, the dielectric constant of which is less than that of the field oxide layer 242 material (silicon dioxide). In one embodiment of this application, the low-k dielectric is silicon oxynitride.

[0054] S430 forms a field plate layer of conductive material on a low-k dielectric layer.

[0055] A conductive material is formed on a low-k dielectric layer as a field plate. In one embodiment of this application, the conductive material is a metal and / or an alloy.

[0056] S440, patterned low-k dielectric layer and field plate layer.

[0057] The low-k dielectric and the conductive material thereon are etched and photolithographically formed using a field plate photolithography method to obtain the low-k dielectric layer 243 and the field plate layer 244. See also... Figure 5e The field plate layer 244 obtained after etching extends above the source region 224.

[0058] S450 forms an interlayer dielectric layer on the wafer.

[0059] An interlayer dielectric (ILD) layer is deposited. The interlayer dielectric can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric can also be boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS), or boron-doped tetraethoxysilane (BTEOS), etc.

[0060] S460, a patterned interlayer dielectric layer, forms the target contact hole and drain contact hole.

[0061] The target contact hole 254 and the drain contact hole 252 are formed by photolithography and etching of the interlayer dielectric layer using a contact hole photolithography plate.

[0062] S470, fill the target contact hole and drain contact hole with conductive material.

[0063] Fill each contact hole with metal and / or alloy. In one embodiment of this application, step S470 forms a tungsten plug in each contact hole.

[0064] S480 forms source-end and drain-end metal interconnects on the interlayer dielectric layer.

[0065] The structure of the LDMOS device after step S480 can be referred to Figure 2 (or Figure 3 ), Figure 2 and Figure 3 The interlayer dielectric layer is omitted. The source metal interconnect 264 short-circuits the field plate layer 244 and the source region 224 through the target contact hole 254, so that the potential of the field plate layer 244 is the same as the potential of the source region 224. The drain metal interconnect 262 is electrically connected to the drain region 222 through the drain contact hole 252 (conductive material in it).

[0066] In the above-described LDMOS device manufacturing method, the field plate layer 244 extends above the source region 224. Therefore, the area of ​​the source metal interconnect 264, which shorts the field plate layer 244 and the source region 224 through the target contact hole 254, can be relatively small. This allows the drain metal interconnect 262 to have a larger wiring space and a larger area, thereby reducing the on-resistance of the device. Furthermore, by providing a low-k dielectric layer 243 between the field plate layer 244 and the gate 232, the gate parasitic capacitance Cgd can be effectively reduced.

[0067] Figure 6 This is a flowchart of a sub-step of step S410 in one embodiment of this application. Step S410 may specifically include:

[0068] S412, Obtain a wafer having a drift region of a first conductivity type and a well region of a second conductivity type formed.

[0069] Reference Figure 5a In one embodiment of this application, a drift region 212 and a second conductivity type well region 214 can be formed in the substrate of the wafer by photolithography and ion implantation.

[0070] In one embodiment of this application, the substrate is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 5a In the illustrated embodiment, the substrate is made of monocrystalline silicon.

[0071] S414 forms the gate on the wafer.

[0072] In one embodiment of this application, after forming a gate dielectric layer on the upper surface of the wafer, polysilicon is deposited on the gate dielectric layer, and then photolithography and etching are performed on the deposited polysilicon to form the gate 236, as shown below. Figure 5b .

[0073] S416 forms the source region, drain region, and body lead-out region.

[0074] In one embodiment of this application, spacer deposition is performed, followed by etching of the spacer material to form a sidewall 234 on the side of the gate 236. Subsequently, a source region 224, a drain region 222, and a body lead-out region 226 are formed via self-aligned implantation, as shown below. Figure 5cThe source region 224 and the body lead-out region 226 are formed in the second conductivity type well region 214. The source region 224 and the drain region 222 have a first conductivity type, and the body lead-out region 226 has a second conductivity type.

[0075] S418 forms a field oxygen layer.

[0076] An oxide layer is deposited and photolithographically and etched to form a field oxide layer 242. Then, metal silicides are formed on the silicon and polysilicon surfaces not covered by the SAB (i.e., the upper surfaces of the drain region 222, source region 224, and body lead-out region 226, and a portion of the upper surface of the gate 236) to form ohmic contacts, such as... Figure 5d As shown.

[0077] The manufacturing method of the LDMOS device in this application is based on the same inventive concept as the LDMOS device. For details not specifically described in the manufacturing method of the LDMOS device, please refer to the above introduction of the LDMOS device.

[0078] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0079] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An LDMOS device, characterized in that, include: Source region; Drain region; Gate; The drift region is at least partially located between the source region and the drain region; An oxygen layer is located on the drift region; A low-k dielectric layer is located on the gate and the field oxide layer, wherein the dielectric constant of the low-k dielectric layer is less than the dielectric constant of the field oxide layer; A field plate layer is located on the low-k dielectric layer and extends above the source region; the field plate layer is made of a conductive material. The source metal connection short-circuits the field plate layer and the source region through the target contact hole, so that the potential of the field plate layer is the same as the potential of the source region. The drain terminal metal wire is electrically connected to the drain region.

2. The LDMOS device according to claim 1, characterized in that, The material of the field plate layer is metal and / or alloy.

3. The LDMOS device according to claim 2, characterized in that, The low-k dielectric layer and the field plate layer completely cover the gate, and the low-k dielectric layer extends to the source region.

4. The LDMOS device according to claim 1, characterized in that, The height difference between the bottom of the target contact hole located on the field plate layer and the bottom of the target contact hole located on the source region is less than 1000 Å.

5. The LDMOS device according to claim 1, characterized in that, The target contact hole includes a first contact hole located on the field plate layer and a second contact hole located on the source region, or The target contact hole is a large hole, partly located on the field plate layer and partly located on the source region.

6. The LDMOS device according to claim 1, characterized in that, The gate is located above the region between the source region and the drain region.

7. The LDMOS device according to claim 1, characterized in that, The source region, drain region, and drift region have a first conductivity type, and the doping concentration of the source region and drain region is greater than the doping concentration of the drift region. The LDMOS device further includes: The source region is located in the second conductivity type well region; the first conductivity type and the second conductivity type are opposite conductivity types; The body lead-out region has a second conductivity type and is located in the second conductivity type well region. The doping concentration of the body lead-out region is greater than that of the second conductivity type well region. The body lead-out region is electrically connected to the source end metal interconnect through a body contact hole.

8. The LDMOS device according to claim 1, characterized in that, The field oxide layer extends from the edge of the drain region to the gate.

9. A method for manufacturing an LDMOS device, comprising: Obtain a wafer having a drift region, a source region, a drain region, a gate, and a field oxide layer, wherein the drift region is at least partially located between the source region and the drain region, and the field oxide layer is formed on the drift region; A low-k dielectric layer is formed on the gate and the field oxide layer, wherein the dielectric constant of the low-k dielectric layer is less than the dielectric constant of the field oxide layer; A field plate layer of conductive material is formed on the low-k dielectric layer; The field plate layer and the low-k dielectric layer are patterned, and the patterned field plate layer extends above the source region; An interlayer dielectric layer is formed on the wafer; The interlayer dielectric layer is patterned to form target contact holes and drain contact holes. The target contact holes are formed on the source region and the field plate layer, and the drain contact holes are formed on the drain region. The target contact hole and the drain contact hole are filled with conductive material; Source metal interconnects and drain metal interconnects are formed on the interlayer dielectric layer. The source metal interconnects short-circuit the field plate layer and the source region through the target contact hole, so that the potential of the field plate layer is the same as the potential of the source region. The drain metal interconnects are electrically connected to the drain region through the drain contact hole.

10. The method for manufacturing an LDMOS device according to claim 1, characterized in that, The step of obtaining a wafer with a drift region, source region, drain region, gate and field oxide layer includes: Obtain a wafer having a drift region of a first conductivity type and a well region of a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; The gate is formed on the wafer; The source region and drain region, as well as the body lead-out region, are formed; the source region and body lead-out region are formed in the second conductivity type well region, the source region and drain region have a first conductivity type, and the body lead-out region has a second conductivity type; The field oxygen layer is formed.

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