Image sensing structure, sensor and preparation method

Abstract

The invention discloses an image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, and the method comprises the steps: carrying out the epitaxy of a P-type first semiconductor layer on the back surface of a substrate, etching a first groove, then filling a first photosensitive layer, carrying out the epitaxy of a buffer layer according to the needs, continuing to carry out the epitaxy of a P-type second semiconductor layer, etching a second groove, and then filling a second photosensitive layer. The P-type semiconductor material layer extends outwards, a third semiconductor layer continues to extend outwards, the groove is etched, then the first photosensitive layer is filled, the three photosensitive material layers are stacked together to form a photosensitive area with multiple quantum wells, and the P-type semiconductor material layer between the adjacent photosensitive areas forms a self-isolation structure. The respective defects are avoided, and the maximum advantages are exerted; the shape of the photosensitive layer is changed by etching the shape of the groove to obtain more quantum wells, and better isolation performance is obtained through the buffer layer, so that the image sensor with high sensitivity and high stability can be prepared.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors and relates to an image sensor fabrication technology, specifically to an image sensing structure, sensor, and fabrication method. Background Technology

[0002] Image sensors are photoelectric conversion devices widely used in consumer electronics, security monitoring, automotive electronics, machine vision, and many other fields. Back-illuminated (BSI) image sensors offer advantages such as higher sensitivity, better wiring layout, and the ability to record at high speeds, and are often used in fields where high pixel performance of image sensors is required.

[0003] However, in traditional BSI front-end fabrication processes, high-energy ion implantation (IMP) is required to fabricate the diode structure to form the photosensitive region, which leads to substrate surface damage. Uneven ion implantation can also cause crosstalk between different pixels, hindering further performance improvements in BSI image sensors; therefore, it is necessary to further develop new photosensitive region structures and fabrication processes.

[0004] In existing technologies, some techniques form quantum wells by epitaxially growing semiconductor structures with different doped elements, and then use deep trench isolation (DTI) technology to form an isolation structure to obtain an image sensor. In this type of technology, the electron concentration in the photosensitive region is increased by forming quantum wells. However, this technology still faces many challenges. Ideally, this technology should first fabricate a high-quality quantum well structure and then etch DTI for isolation. However, the practical problem is that the deep etching of DTI (usually reactive ion etching, RIE) will generate huge lattice damage and high temperatures. This harsh process will directly destroy the already grown quantum well structure that is extremely sensitive to lattice integrity, introducing a large number of defects, which become the main source of dark current, completely negating the advantages of quantum wells. If DTI is made first and then the quantum well material is epitaxially grown, the sidewalls of DTI will become nucleation sites for epitaxy, leading to polycrystalline growth or the generation of a large number of dislocations. The quantum well cannot form a single-crystal structure on the trench sidewalls, and the performance deteriorates sharply.

[0005] Furthermore, the thermal expansion coefficients of the DTI filler material (usually silicon dioxide) differ significantly from those of silicon. After cooling during processing, the DTI exerts tensile stress on the surrounding silicon substrate. This stress alters the band structure of the semiconductor material (piezoelectric effect). If the quantum well region is too close to the DTI, this non-uniform stress can distort the quantum well's barrier and potential well, causing variations in its band structure at different locations on the chip, severely compromising the uniformity of device performance. Stress concentration points (especially the sharp corners at the bottom of the DTI) are prone to becoming dislocation initiation points. These dislocations multiply and extend into the quantum well region during subsequent processes, becoming unavoidable GR centers (Generation-Recombination centers), leading to a significant increase in dark current and white defects. Therefore, it is necessary to further develop these existing technologies to leverage the advantages of quantum well technology while avoiding the aforementioned drawbacks. Summary of the Invention

[0006] The primary objective of this invention is to provide an image sensing structure that combines existing quantum trap technology with self-isolation technology. This not only avoids the shortcomings of each technology but also achieves better isolation performance while obtaining a high concentration of charge carriers, thus preventing current crosstalk.

[0007] A second objective of this invention is to provide an image sensing structure that, based on the aforementioned technology, employs a photosensitive region formed by sequentially stacking a first photosensitive layer, a second photosensitive layer, and a third first photosensitive layer. The second photosensitive layer has a cross-section that is wider in the middle and narrower at the top and bottom, forming a circle or near-circular shape, while the first photosensitive layer has a cross-section that is wider in the middle and narrower at the top and bottom, forming a rhombus or near-rhombus shape. This allows the invention to possess far more quantum wells than existing technologies, thereby improving the sensor's sensitivity.

[0008] A third objective of this invention is to provide an image sensing structure that, based on the above, inserts a buffer layer into the self-isolation structure to further improve isolation performance.

[0009] The fourth objective of this invention is to provide a method for fabricating an image sensing structure or an image sensor, using a feasible and low-cost process to fabricate the aforementioned image sensing structure.

[0010] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides an image sensing structure, including... Substrate; A P-type semiconductor material layer is formed on the substrate; and Photosensitive regions are formed in a spaced manner within a P-type semiconductor material layer, and the P-type semiconductor material layers between the photosensitive regions form a self-isolation structure. The photosensitive region is formed by stacking multiple N-type doped photosensitive layers, and the band gaps of adjacent photosensitive layers are different, so as to form multiple quantum wells.

[0011] In the above image sensing structure, the photosensitive region is formed by stacking an N-type doped first photosensitive layer, a second photosensitive layer, and a third photosensitive layer in sequence. The band gap of the second photosensitive layer is smaller than that of the first photosensitive layer, making the second photosensitive layer a potential well and the first photosensitive layer a potential barrier.

[0012] In the above image sensing structure, the cross-section of the second photosensitive layer is a circle or a near-circular shape that is wider in the middle and narrower at the top and bottom, and the cross-section of the first photosensitive layer is a rhombus or a near-rhombus shape that is wider in the middle and narrower at the top and bottom.

[0013] In the above image sensing structure, a buffer layer for improving isolation performance is inserted into the self-isolation structure. The buffer layer is a P-type semiconductor material layer that can raise the potential barrier.

[0014] In the above image sensing structure, the doping elements of the first and second photosensitive layers are selected from group V elements.

[0015] In a second aspect, the present invention provides an image sensor, comprising the image sensing structure described above, a grid structure formed on the self-isolation structure, and a filter layer formed on the photosensitive area between adjacent grid structures.

[0016] Thirdly, the present invention provides a method for preparing an image sensing structure, comprising the following steps: A substrate is provided having a plurality of shallow trench isolation structures therein, and the shallow trench isolation structures are exposed by thinning the back side of the substrate. A first semiconductor layer is formed by epitaxially forming a first P-type semiconductor material on the back side of the thinned substrate; A plurality of spaced first grooves are etched in the first semiconductor layer, and N-type semiconductor material is filled in the first grooves to form a first photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form a second semiconductor layer; Several second grooves extending to the first photosensitive layer are etched in the second semiconductor layer, and N-type semiconductor material is filled in the second grooves to form the second photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form the third semiconductor layer; Several third grooves extending to the second photosensitive layer are etched in the third semiconductor layer, and N-type semiconductor material is filled in the third grooves to form the first photosensitive layer; The first photosensitive layer, the second photosensitive layer, and the first photosensitive layer are stacked together to form a photosensitive region with multiple quantum wells. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked together to form a P-type semiconductor material layer. The P-type semiconductor material layers between adjacent photosensitive regions form a self-isolation structure.

[0017] In the above method for fabricating the image sensing structure, etching a plurality of spaced first grooves within the first semiconductor layer includes the following steps: Epitaxially extending a first hard mask layer on a first semiconductor layer; An opening is created by dry etching the first hard mask layer and the first semiconductor layer; A rhomboid groove is formed by etching along the (111) crystal direction using anisotropic wet etching.

[0018] In the above-mentioned method for fabricating the image sensing structure, before the second semiconductor layer is formed by epitaxially forming the first P-type semiconductor material, the following steps are also included: A buffer layer is formed by epitaxially forming a second P-type semiconductor material on a first semiconductor layer filled with a first photosensitive layer.

[0019] In the above-mentioned method for preparing the image sensing structure, the first groove is a rhombus or rhombus-like groove that is wider in the middle and narrower at the top and bottom, and the second groove is a circular or circular groove that is wider in the middle and narrower at the top and bottom.

[0020] In the above method for fabricating the image sensing structure, etching a plurality of second grooves extending to the first photosensitive layer within the second semiconductor layer includes the following steps: A second hard mask layer is epitaxially grown on the second semiconductor layer; An opening is created by dry etching the second hard mask layer; The second semiconductor layer is etched alternately by dry etching and anisotropic wet etching to form a circular profile groove.

[0021] In the above-mentioned method for preparing the image sensing structure, both the first photosensitive layer and the second photosensitive layer are doped semiconductor materials, and the doping concentration is not lower than the simplified doping concentration.

[0022] In the above-mentioned method for fabricating the image sensing structure, group III elements are incorporated into the epitaxial process of the first and second photosensitive layers to adjust the energy level size and form a quantum well.

[0023] Fourthly, the present invention provides a method for manufacturing an image sensor, comprising the following steps: A substrate is provided having a plurality of shallow trench isolation structures therein, and the shallow trench isolation structures are exposed by thinning the back side of the substrate. A first semiconductor layer is formed by epitaxially forming a first P-type semiconductor material on the back side of the thinned substrate; A plurality of spaced first grooves are etched in the first semiconductor layer, and N-type semiconductor material is filled in the first grooves to form a first photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form a second semiconductor layer; Several second grooves extending to the first photosensitive layer are etched in the second semiconductor layer, and N-type semiconductor material is filled in the second grooves to form the second photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form the third semiconductor layer; Several third grooves extending to the second photosensitive layer are etched in the third semiconductor layer, and N-type semiconductor material is filled in the third grooves to form a first photosensitive layer; wherein, the first photosensitive layer, the second photosensitive layer and the first photosensitive layer are stacked together to form a photosensitive region with multiple quantum wells, and the homogeneous first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked together to form a P-type semiconductor material layer, and the P-type semiconductor material layer between adjacent photosensitive regions forms a self-isolation structure; A grid structure is fabricated on a self-isolating structure; A filter layer is fabricated on the photosensitive area between adjacent grid structures.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows: Compared with existing technologies, this invention combines self-isolation technology with quantum well technology. By first epitaxially layering a P-type semiconductor material and then filling it with an N-type doped semiconductor material to form the photosensitive region, it avoids the problem of deep trench isolation (DTI) affecting the photosensitive region. An unexpected technical effect is that it not only avoids the etching damage and interface states that occur in the silicon crystal during the etching process of DTI (these defects become recombination centers for charge carriers, leading to a significant increase in dark current), but also allows the formation of a PN junction between the N-type photosensitive region and the P-type semiconductor material layer. The built-in electric field of this PN junction creates a potential barrier, effectively "confining" photogenerated charge carriers within their respective photosensitive regions. This potential isolation is a bulk self-isolation technology, more thorough than the interface isolation of DTI.

[0025] This invention uses a second photosensitive layer with a cross-section that is wider in the middle and narrower at the top and bottom, forming a circle or near-circular shape. The first photosensitive layer has a cross-section that is wider in the middle and narrower at the top and bottom, forming a rhombus or near-rhombus shape. An unexpected technical effect is that the change in the cross-sectional dimensions of the first and second photosensitive layers results in different actual quantum well widths at different vertical positions within the device. Taking the first photosensitive layer as an example, the central region of the first photosensitive layer is equivalent to a relatively wide quantum well, where the ground state energy level E1 of the electron... wide The energy level is relatively low; the upper and lower regions of the first photosensitive layer are equivalent to a narrow quantum well, where the electron's ground state energy level E1 is relatively low. narrowThe thickness variation creates a "potential energy funnel": this variation in thickness results in a non-uniform distribution of electron potential energy within the quantum well plane. Electrons in the middle (wider well) region have lower energy, while those at the edges (narrower well) have higher energy. This effectively creates a "potential energy funnel" or "potential energy depression" within the plane. Photons are absorbed throughout the entire first photosensitive layer (regardless of thickness), generating electron-hole pairs. Electrons generated in the narrow well region (higher energy level), due to their higher energy, rapidly relax to the lower energy levels in the middle wide well region by emitting phonons (lattice vibrations). This "potential energy funnel" effect helps drive and concentrate photogenerated electrons in the widest central region of the quantum well, allowing for more efficient collection of these electrons and potentially improving the photocurrent collection efficiency while reducing the recombination probability of charge carriers before reaching the extraction point. The second photosensitive layer also exhibits a similar effect due to its circular cross-section, resulting in a significantly larger number of quantum wells in this invention compared to the number of quantum wells generated by simply reducing the two-dimensional size in existing technologies.

[0026] The present invention inserts a buffer layer within the self-isolation structure to improve isolation performance. An unexpected technical effect is that, after inserting different p-type dopant elements into the self-isolation structure to form a buffer layer, N-type dopant is formed. + / P + / P + Structure. This is equivalent to two back-to-back PN junctions, with the photosensitive region N... + With the P of the buffer layer + Forming a heterogeneous PN junction, the P buffer layer + With self-isolation structure P + In the formation of a homojunction, the heavily doped p-type layer of the buffer layer leads to a significant increase in the valence band top, which indirectly raises the conduction band bottom, increasing the energy difference that electrons need to cross. Furthermore, without a buffer layer, uneven doping or the presence of defect levels in the self-isolation structure can create continuous leakage paths within the band gap. Inserting a highly doped, high-quality buffer layer is equivalent to inserting a band gap abrupt change in the leakage path. This abrupt, towering barrier "cuts off" any possible continuous leakage channels formed through defect levels, forcing electrons to overcome a very high and steep barrier to leak, thus greatly improving isolation performance. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an image sensor according to Embodiment 1 of the present invention.

[0028] Figure 2 This is a schematic diagram of another image sensor in Embodiment 2 of the present invention.

[0029] Figure 3 This is a flowchart of the image sensing structure preparation method in Embodiment 5 of the present invention.

[0030] Figure 4 This is a schematic diagram of the substrate provided in step S100 of Embodiment 5 of the present invention.

[0031] Figure 5 This is a schematic diagram of the thinning process on the back side of the substrate in step S100 of embodiment 5 of the present invention.

[0032] Figure 6 This is a schematic diagram of step S200 of embodiment 5 of the present invention, in which a first semiconductor layer is formed by epitaxially growing a first P-type semiconductor material on the back side of the thinned substrate.

[0033] Figure 7 This is a schematic diagram of the epitaxial growth of a first hard mask layer on a first semiconductor layer in step S311 of embodiment 5 of the present invention.

[0034] Figure 8 This is a schematic diagram of step S312 of embodiment 5 of the present invention, in which the first opening is made by dry etching the first hard mask layer and the first semiconductor layer.

[0035] Figure 9 This is a schematic diagram of etching the rhomboid groove in step S313 of embodiment 5 of the present invention.

[0036] Figure 10 This is a schematic diagram of step S323 of embodiment 5 of the present invention, in which N-type semiconductor material is filled into the first groove to form a first photosensitive layer.

[0037] Figure 11 This is a schematic diagram of step S400 in Embodiment 5 of the present invention, in which the first P-type semiconductor material is epitaxially stretched to form a second semiconductor layer.

[0038] Figure 12 This is a schematic diagram of the epitaxial growth of a second hard mask layer on the second semiconductor layer in step S511 of embodiment 5 of the present invention.

[0039] Figure 13 This is a schematic diagram of step S513 of embodiment 5 of the present invention, in which several second grooves extending to the first photosensitive layer are etched in the second semiconductor layer.

[0040] Figure 14 This is a schematic diagram of step S500 of embodiment 5 of the present invention, in which an N-type semiconductor material is filled into the second groove to form a second photosensitive layer.

[0041] Figure 15 This is a schematic diagram of step S600 in Embodiment 5 of the present invention, in which the first P-type semiconductor material is further epitaxially stretched to form a third semiconductor layer.

[0042] Figure 16 This is a schematic diagram of step S700 in Embodiment 5 of the present invention, in which an N-type semiconductor material is filled into the third groove to form a first photosensitive layer.

[0043] Figure 17 This is a schematic diagram of step M400 in Embodiment 6 of the present invention, in which a second P-type semiconductor material is epitaxially formed on a first semiconductor layer filled with a first photosensitive layer to form a buffer layer.

[0044] Figure 18 This is a schematic diagram of step M500 in Embodiment 6 of the present invention, in which a second semiconductor layer is formed by epitaxially growing a first P-type semiconductor material on a buffer layer.

[0045] Figure 19 This is a schematic diagram of step M600 in Embodiment 6 of the present invention, in which N-type semiconductor material is filled into the second groove to form a second photosensitive layer.

[0046] Figure 20 This is a schematic diagram of step M700 in Embodiment 6 of the present invention, in which the first P-type semiconductor material is epitaxially stretched to form a third semiconductor layer.

[0047] Figure 21 This is a schematic diagram of step M800 in Embodiment 6 of the present invention, in which an N-type semiconductor material is filled into the third groove to form a first photosensitive layer.

[0048] Figure 22 This is a schematic diagram comparing the number of quantum wells and electron concentration of the image sensing structure of the present invention with that of a certain image sensor in the prior art. Figure 22 Figure A shows a schematic diagram of the number of quantum wells and electron concentration in a certain existing technology. Figure 22 Figure B is a schematic diagram of the number of quantum wells and electron concentration in Example 2. In each schematic diagram, the steps (or platforms) between the dashed lines on both sides represent the size of the energy level.

[0049] 100 - Substrate, 110 - Front side, 120 - Back side, 130 - Shallow trench isolation structure, 140 - Etch stop layer, 150 - Metal interconnect layer; 200 - P-type semiconductor material layer, 210 - first semiconductor layer, 220 - second semiconductor layer, 230 - third semiconductor layer, 240 - isolation structure; 310 - First hard mask layer; 320 - Second hard mask layer; 400 - Photosensitive area, 410 - First photosensitive layer, 411 - First groove, 412 - First opening; 420 - Second photosensitive layer; 421 - Second groove; 500-grid structure; 600-Buffer Layer; 710 - Blue filter element, 720 - Green filter element, 730 - Red filter element. Detailed Implementation

[0050] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0051] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0053] Example 1: As Figure 1 As shown, this embodiment provides an image sensing structure, including... Substrate 100; A p-type semiconductor material layer 200 is formed on the substrate 100; and Photosensitive regions 400 are formed in a spaced manner within the P-type semiconductor material layer 200, and the P-type semiconductor material layer 200 between the photosensitive regions 400 forms a self-isolating structure 240; The photosensitive region 400 is formed by stacking multiple N-type doped photosensitive layers, and the band gaps of adjacent photosensitive layers are different to form multiple quantum wells.

[0054] This invention combines self-isolation technology with quantum well technology. By first epitaxially growing a P-type semiconductor material layer 200 and then filling it with an N-type doped semiconductor material to form the photosensitive region 400, it avoids the problem of deep trench isolation (DTI) affecting the photosensitive region 400. An unexpected technical effect is that it not only avoids the etching damage and interface states that occur in the silicon crystal during the etching process of DTI (these defects become recombination centers for charge carriers, leading to a significant increase in dark current), but also forms a PN junction between the N-type photosensitive region 400 and the P-type semiconductor material layer 200. The built-in electric field of this PN junction creates a potential barrier, effectively "confining" photogenerated charge carriers within their respective photosensitive regions 400. This potential isolation is a bulk self-isolation technology, more thorough than the interface isolation of DTI.

[0055] The principle of forming a quantum well in this embodiment is as follows: When photosensitive layers are stacked alternately, the difference in band gap caused by heavy doping between adjacent layers will generate a band shift at the heterojunction interface. Typically, the material with the narrower band gap (such as the second photosensitive layer 420) will act as a potential well, while the material with a relatively wider band gap (such as the first photosensitive layer 410) will act as a potential barrier. In this way, electrons are confined within the second photosensitive layer 420 in the vertical direction. If the thickness of the second photosensitive layer 420 is thin enough to be comparable to the de Broglie wavelength of electrons (typically on the nanometer scale), the movement of electrons in the vertical direction will be quantized, forming discrete energy levels, thus creating a quantum well.

[0056] When quantum well technology is combined with the self-isolation technology of this invention, the photosensitive region 400 (N-type) and the self-isolation structure 240 (P-type) are in direct contact, forming a PN junction. In the depletion region of the PN junction, the energy bands are drastically bent. For electrons attempting to move laterally from the N-type photosensitive region 400 to adjacent pixels, they need to overcome a high potential barrier formed by the built-in electric field, namely the PN junction barrier. Through lateral electrical isolation, each pixel unit (photosensitive region 400) is effectively surrounded, preventing photogenerated electrons from diffusing to adjacent photosensitive regions 400 and causing crosstalk.

[0057] In a more preferred embodiment, see as follows: Figure 1 As shown, the photosensitive region 400 is formed by stacking an N-type doped first photosensitive layer 410, a second photosensitive layer 420, and the first photosensitive layer 410 in sequence. The first photosensitive layer 410 is epitaxially formed using a first type of N-type semiconductor material, and the second photosensitive layer 420 is epitaxially formed using a second type of N-type semiconductor material. The band gap of the second type of N-type semiconductor material is smaller than that of the first type of N-type doped semiconductor material, making the second photosensitive layer 420 a potential well and the first photosensitive layer 410 a potential barrier, thereby forming a quantum well. A very high concentration of electron flow is obtained in the second photosensitive layer 420, which greatly improves the sensitivity of the image sensor.

[0058] In a more preferred embodiment, see as follows: Figure 1 As shown, the cross-section of the second photosensitive layer 420 is a circle or near-circular shape that is wider in the middle and narrower at the top and bottom, while the cross-section of the first photosensitive layer 410 is wider in the middle and narrower at the top and bottom. Figure 1 Both ends of the middle have sharp corners that form a rhombus or rhombus-like shape (referred to as a rhombus or rhombus-like cross section).

[0059] In the quantum well of the above embodiment, electrons are confined within a very thin layer. This confinement leads to the quantization of their energy, forming discrete energy levels (such as the ground state E1, the first excited state E2, etc.). The width of the quantum well directly determines the position of the energy levels; the wider the well, the lower the energy level (the smaller the energy), and the narrower the spacing between the energy levels. Conversely, the narrower the well, the stronger the quantization effect, and the higher the energy level. In this embodiment, by designing the cross-sectional shape of the first photosensitive layer 410 and the second photosensitive layer 420, the present invention provides a larger confined area in the middle wide portion, enhancing the confinement capability of charge carriers (electrons), thereby allowing each quantum well to accommodate more electrons. At the same time, the narrow top and bottom structure helps reduce interfacial stress and improve interlayer lattice matching. In particular, in the first photosensitive layer 410, a rhombic cross-section can be formed by anisotropic etching of the crystal planes, resulting in almost no interfacial stress. The second photosensitive layer 420 adopts a circular cross-section, which helps to reduce the interfacial state density and improve the quality and stability of the quantum well. Overall, this cross-sectional design increases the effective width of each quantum well and reduces carrier leakage, thereby achieving a higher electron concentration with the same number of stacked layers. Compared to existing technologies that obtain the number of quantum wells simply by varying the size of the same doping material, the structure of this invention can more efficiently utilize the quantum well effect to obtain a far greater number of quantum wells than existing technologies, thus improving the responsivity of the photosensitive region 400.

[0060] Existing technologies obtain more quantum wells by changing the size of the doped layers, but this method may be limited by interlayer compatibility and interface defects, resulting in a limited number of quantum wells. This invention employs alternating stacking of a first photosensitive layer 410 and a second photosensitive layer 420. Due to the different lattice constants and band shifts of the first and second photosensitive layers 410 and 420, this stacking can form multiple quantum well structures, and the alternating stacking allows for the integration of more quantum well layers within a unit volume, thereby directly increasing the number of quantum wells; compared to existing technologies, more quantum wells can be obtained.

[0061] Taking the first photosensitive layer 410 as an example, the middle region of the first photosensitive layer 410 is equivalent to a relatively wide quantum well, where the ground state energy level E1 of the electron is... wide The area above and below the first photosensitive layer 410 is relatively low; it corresponds to a narrow quantum well, where the ground state energy level E1 of the electron is relatively low. narrowThe thickness of the first photosensitive layer 410 is relatively high, thus forming a "potential energy funnel". This variation in thickness results in a non-uniform distribution of electron potential energy within the quantum well plane. Electrons in the middle (wide well) region have lower energy, while electrons in the edge (narrow well) region have higher energy. This effectively creates a "potential energy funnel" or "potential energy depression" for electrons within the plane. Photons are absorbed throughout the entire first photosensitive layer 410 (regardless of thickness), generating electron-hole pairs. Electrons generated in the narrow well region (high energy level), due to their higher energy, will rapidly relax to the lower energy level in the middle wide well region by emitting phonons (lattice vibrations). This "potential energy funnel" effect helps drive and concentrate photogenerated electrons in the widest central region of the quantum well, allowing for more efficient collection of these electrons, which may improve the collection efficiency of photocurrent and reduce the recombination probability of charge carriers before reaching the extraction point. The second photosensitive layer 420 also exhibits a similar effect due to its circular cross-section, resulting in a significantly greater number of quantum wells in this invention compared to the number of quantum wells generated by simply reducing the two-dimensional size in the prior art.

[0062] In some embodiments, the first photosensitive layer 410 and the second photosensitive layer 420 are doped with different elements, but both are selected from group V elements. Common group V elements include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb). For example, the first photosensitive layer 410 is a silicon material doped with antimony (Sb) (abbreviated as Si-Sb); the second photosensitive layer 420 is a silicon material doped with arsenic (As) (abbreviated as Si-As). The doping concentration of the first photosensitive layer 410 and the second photosensitive layer 420 is not lower than the simplified doping concentration, and both are heavily doped or close to heavily doped, that is, the doping concentration is 1×10⁻⁶. 18 cm 3 Left or right or above, preferably, the doping concentration range is 10 × 10 18 cm 3 Up to 10×10 21 cm 3 .

[0063] In some embodiments, the two first photosensitive layers 410 have the same or similar thickness, both around 40-50 nm, and the second photosensitive layer 420 has a thickness of around 50-70 nm. If the thickness of the first photosensitive layer 410 and the second photosensitive layer 420 is too small, it will not be enough to form a larger number of quantum wells. If the thickness is too large, it will reduce the quantization effect and will not be able to obtain more quantum wells. The above range is the optimal choice to obtain the largest number of quantum wells.

[0064] Example 2: As Figure 2As shown, based on Embodiment 1, a buffer layer 600 for improving isolation performance is inserted into the self-isolation structure 240. The buffer layer 600 is a P-type semiconductor material layer capable of raising the potential barrier. Optimally, the buffer layer 600 is inserted into the self-isolation structure 240 corresponding to the lower part of the second photosensitive layer 420. Research has found that when the first photosensitive layer 410 and the second photosensitive layer 420 have a large number of quantum wells, and the electron concentration in the quantum wells is too high, the Fermi level will be pushed up, causing the PN junction depletion region between the photosensitive region 400 and the self-isolation structure 240 to narrow, effectively reducing the potential barrier height. This lowers the PN junction barrier, making it easier for electrons to tunnel directly through the thinned barrier, resulting in severe inter-pixel leakage.

[0065] In this embodiment, after inserting different types of P-type dopant elements into the self-isolation structure 240 to form a buffer layer 600, an "N" structure is formed. + / P + / P + The structure is equivalent to two back-to-back PN junctions, with a photosensitive region of 400 N. + With buffer layer 600 P + Forming a heterogeneous PN junction, with a 600 P buffer layer. + With self-isolation structure 240 P + The formation of a homojunction and the heavily doped p-type layer 600 in the buffer layer significantly raises the valence band top, indirectly further increasing the conduction band bottom and increasing the energy difference electrons need to cross. Furthermore, without the buffer layer 600, the uneven doping or defect levels in the self-isolation structure 240 might create continuous leakage paths in the band gap. Inserting a highly doped, high-quality buffer layer 600 is equivalent to inserting a band gap abrupt change in the leakage path. This abrupt, towering barrier "cuts off" any possible continuous leakage channels formed through defect levels, forcing electrons to overcome a very high and steep barrier to leak, greatly improving isolation performance.

[0066] In some embodiments, such as Figure 2 As shown, the buffer layer 600 is disposed within the self-isolating structure 240 near the bottom of the second photosensitive layer to achieve a better isolation effect.

[0067] The doping elements of the P-type semiconductor material layer 200 and the buffer layer 600 used to form the self-isolation structure 240 are both selected from group III elements. Common group III elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). For example, the P-type semiconductor material layer 200 is a gallium (Ga)-doped silicon material (referred to as Si-Ga); the buffer layer 600 is a boron (B)-doped silicon material (referred to as Si-B). When the self-isolation structure 240 uses Si-Ga and the buffer layer 600 uses Si-B, a sandwich structure is formed. There is a valence band shift ΔEv1 at the Ga / B interface (buffer layer-self-isolation structure interface) and a valence band shift ΔEv2 at the B / i-Si interface (buffer layer-photosensitive region interface, i-Si represents photosensitive region 400). The total potential barrier that holes need to overcome to flow from photosensitive region 400 to isolation region is... The height, ΔEv1 + ΔEv2, is much greater than the barrier of a single interface. This "double barrier" structure can more effectively block the diffusion of holes. The doping concentration of B can be controlled within a more optimized range than that of Ga, ensuring sufficient band tail effect while reducing lattice damage. The quality of the B / i-Si interface is usually better than that of the Ga / i-Si interface (self-isolation structure-photosensitive region interface), reducing the interface state density and thus cutting off the leakage path through interface defects. The presence of the buffer layer 600 provides a gradual band transition, reducing the local electric field strength and suppressing tunneling current. Therefore, inserting the buffer layer 600 is actually adding a buffer gate between the self-isolation structure 240 and the photosensitive region 400, preventing the PN junction depletion region between the photosensitive region 400 and the self-isolation structure 240 from becoming too narrow due to excessive electron concentration in the photosensitive region 400, thereby improving isolation performance.

[0068] Example 3: As Figure 1 As shown, this embodiment provides an image sensor, including the image sensing structure of Embodiment 1, a grid structure formed on the self-isolation structure 240, and a filter layer formed on the photosensitive area 400 between adjacent grid structures; the grid structure is any metal grid structure in the prior art; after forming the metal grid structure, filter elements are formed between the metal grid structures on the surface of the photosensitive area 400. The filter elements may include a blue filter element 710, a green filter element 720, and a red filter element 730 as shown in the figure. It should be noted that the filter elements include a color filter and a microlens located on the surface of the color filter. Since the surface of the microlens is convex, the blue filter element 710, the green filter element 720, and the red filter element 730 shown in the figure all have convex surfaces.

[0069] Example 4: Figure 2As shown, this embodiment provides an image sensor, including the image sensing structure in embodiment 2, a grid structure formed on the self-isolation structure 240, and a filter layer formed on the photosensitive area 400 between adjacent grid structures; to form the basic structure of the image sensor; the grid structure is any metal grid structure in the prior art; after the metal grid structure is formed, a filter element located on the surface of the photosensitive area 400 is formed between the metal grid structures.

[0070] Example 5, as Figure 3 As shown, this embodiment provides a method for fabricating an image sensing structure, including the following steps: S100, a substrate 100 is provided, the substrate 100 having a plurality of shallow trench isolation structures 130, and the back side 120 of the substrate 100 is thinned to expose the shallow trench isolation structures 130. S200, A first semiconductor layer 210 is formed by epitaxially forming a first P-type semiconductor material on the back side of the thinned substrate; S300: A plurality of spaced first grooves 411 are etched in the first semiconductor layer 210, and N-type semiconductor material is filled in the first grooves 411 to form a first photosensitive layer 410. S400, Continue epitaxial growth of the first P-type semiconductor material to form the second semiconductor layer 220; S500: A plurality of second grooves 421 extending to the first photosensitive layer 410 are etched in the second semiconductor layer 220, and N-type semiconductor material is filled in the second grooves 421 to form the second photosensitive layer 420. S600, Continue epitaxial growth of the first P-type semiconductor material to form the third semiconductor layer 230; S700: A plurality of third grooves extending to the second photosensitive layer 420 are etched in the third semiconductor layer 230, and N-type semiconductor material is filled in the third grooves to form the first photosensitive layer 410. The first photosensitive layer 410, the second photosensitive layer 420 and the first photosensitive layer 410 are stacked together to form a photosensitive region 400 with multiple quantum wells. The first semiconductor layer 210, the second semiconductor layer 220 and the third semiconductor layer 230 are stacked together to form a P-type semiconductor material layer 200. The P-type semiconductor material layers 200 between adjacent photosensitive regions 400 form a self-isolation structure 240.

[0071] In this embodiment, a first P-type semiconductor material is epitaxially grown in stages, with each stage followed by trenching and filling with N-type semiconductor material. This forms a first photosensitive layer 410, a second photosensitive layer 420, and the first photosensitive layer 410 stacked together to form a photosensitive region 400 with multiple quantum wells. The first P-type semiconductor material grown in three stages forms a P-type semiconductor material layer, and the P-type semiconductor material layers between adjacent photosensitive regions 400 form a self-isolating structure 240. An unexpected technical advantage is that this fabrication process completely avoids the damage to the photosensitive region 400 caused by deep etching during the fabrication of the self-isolating structure 240 using DTI technology. The problem is that the photosensitive region 400 fabricated by this invention can reach the optimal level of the epitaxial semiconductor process itself, thus providing a technical foundation for obtaining high-quality devices. In addition, an unexpected technical effect is that this invention avoids the problem that the large difference in the thermal expansion coefficients between the DTI filling material (usually silicon dioxide) and silicon causes tensile stress on the surrounding silicon substrate after the process cooling. This stress will change the band structure of the semiconductor material (piezoelectric effect). This non-uniform stress will distort the barrier and potential well of the quantum well, causing its band structure to vary at different locations on the chip, which will seriously damage the uniformity of device performance.

[0072] In step S100, the substrate 100 may be constructed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, or an indium phosphide (InP) substrate. Alternatively, the substrate 100 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon-germanium on insulator. Therefore, the type and thickness of the substrate 100 should not limit the scope of protection of this disclosure.

[0073] like Figure 4 As shown, the substrate 100 has a front side 110 and a back side 120. The shallow trench isolation structure 130 (STI) can be fabricated in the front end of line (FEOL) process by a combination of etching and deposition processes. Of course, it can also be fabricated by other methods known to those skilled in the art. The filling material of the shallow trench isolation structure 130 (STI) can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or combinations thereof.

[0074] like Figure 4As shown, the front-end process also includes forming an etch stop layer 140 covering the shallow trench isolation structure 130 on the substrate 100, and fabricating a metal interconnect layer 150 after forming the etch stop layer 140. The metal interconnect layer 150 includes an interlayer dielectric (IMD) layer and metal lines formed within the interlayer dielectric layer. Figure 4 (Not shown in the text) The signal of the photodiode is brought out using metal circuits; specifically, an interlayer dielectric (IMD) is first prepared on the etch stop layer 140 by a deposition process. The interlayer dielectric can be a low dielectric material layer, such as tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicon glass (OSG), SiOC) and / or any suitable low-k dielectric material; then, metal circuits are prepared in the interlayer dielectric layer as the metal connection part of the device.

[0075] Of course, this embodiment only illustrates one method. As long as the metal interconnect structure can be formed reasonably, there are no restrictions on the thickness of the etch stop layer 140 and the interlayer dielectric layer. They can be adjusted according to specific process requirements.

[0076] like Figure 5 As shown, in step S100, at least one of dry etching, wet etching, chemical mechanical polishing, and planarization processes can be used to thin the back side 120 of the substrate 100 to expose the shallow trench isolation structure 130. The thinning is optimal to just expose the bottom of the shallow trench isolation structure 130. The shallow trench isolation structure 130 itself can be prepared according to existing technology without special limitations. The spacing between the shallow trench isolation structures 130 is determined according to the size of the photosensitive area 400 designed later.

[0077] In step S200, a first semiconductor layer 210 is formed by epitaxially forming a first P-type semiconductor material on the back side 120 of the thinned substrate 100, as shown in the figure. Figure 6As shown, the first P-type semiconductor material can be formed using any of the following deposition methods, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). This deposition process avoids problems such as crystal structure damage, temperature rise, and electric field effects caused by ion implantation. In this embodiment, a first semiconductor layer 210 can be formed on the back side 120 of the thinned substrate 100 using chemical vapor deposition. The first P-type semiconductor material can be silicon doped with any one of group III elements, such as boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). For example, the first P-type semiconductor material is gallium-doped silicon (Si-Ga) with a heavily doped concentration.

[0078] The thickness of the first semiconductor layer 210 affects the thickness of the subsequent first photosensitive layer 410. Therefore, if the thickness is too large or too small, it will be impossible to form the ideal number of quantum wells. Therefore, the thickness of the first semiconductor layer 210 is 30 nanometers to 100 nanometers, with a preferred range of 50-60 nanometers.

[0079] In some embodiments, in step S300, a plurality of spaced first grooves 411 are etched within the first semiconductor layer 210, resulting in the following: Figure 9 As shown.

[0080] In some embodiments, the first groove 411 is a rhombus-shaped groove. It should be noted that the rhombus-shaped groove of this invention is a groove in the etching field, not a geometrically complete rhombus-shaped groove in the prior art. The rhombus-shaped groove of this invention has a flat bottom, a top opening of approximately the same width as the bottom, and symmetrically protruding sides forming sharp angles, resembling a rhombus. Its cross-section can be simply viewed as a rectangle joined at both ends by an isosceles triangle, with the two isosceles triangles arranged mirror-symmetrically around the center of the rectangle. When the first groove 411 is a rhombus-shaped groove, the filled first photosensitive layer 410 also has a rhombus cross-section. When it contacts the second photosensitive layer 420 to form a quantum well, the middle region of the first photosensitive layer 410 is equivalent to a relatively wide quantum well, where the electron's ground state energy level E1... wide The area above and below the first photosensitive layer 410 is relatively low; it corresponds to a narrow quantum well, where the ground state energy level E1 of the electron is relatively low. narrowThe thickness variation creates a "potential energy funnel": this variation in thickness results in a non-uniform distribution of electron potential energy within the quantum well plane. Electrons in the middle (wider well) region have lower energy, while those at the edges (narrower well) have higher energy. This effectively creates a "potential energy funnel" or "potential energy depression" within the plane. Photons are absorbed throughout the entire first photosensitive layer 410 (regardless of thickness), generating electron-hole pairs. Electrons generated in the narrow well region (higher energy level), due to their higher energy, rapidly relax to the lower energy level in the middle wide well region by emitting phonons (lattice vibrations). This "potential energy funnel" effect helps drive and concentrate photogenerated electrons in the widest central region of the quantum well, allowing for more efficient collection of these electrons, potentially improving the photocurrent collection efficiency and reducing the recombination probability of charge carriers before reaching the extraction point. The second photosensitive layer 420, due to its circular cross-section, also exhibits a similar effect, resulting in a significantly greater number of quantum wells in this invention compared to the number of quantum wells generated by simply reducing the two-dimensional size in existing technologies.

[0081] For example, the present invention provides a process for forming a rhomboid groove, comprising the following steps: S311, Epitaxially extending a first hard mask layer 310 on the first semiconductor layer 210, such as Figure 7 As shown.

[0082] The first hard mask layer 310 is used as a blocking mask when the subsequent dry etching and wet etching are combined to form the rhomboid groove. Therefore, the first hard mask layer 310 can be made of common hard mask materials in the prior art, such as silicon dioxide, carbon-doped silicon oxide, silicon nitride, amorphous carbon, titanium nitride, etc. The processes used include plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, spin coating, chemical vapor deposition or physical vapor deposition.

[0083] The thickness of the first hard mask can be a conventional thickness. For example, in this embodiment, a 1-2 nanometer thick silicon dioxide layer is used as the first hard mask layer 310 by plasma-enhanced chemical vapor deposition.

[0084] S312, the first opening 412 is opened by dry etching the first hard mask layer 310 and the first semiconductor layer 210, such as... Figure 8 As shown.

[0085] The first opening 412 can be formed by etching processes such as reactive ion etching (RIE), low temperature etching, and high aspect ratio etching (HARP). The specific process type and parameter range are selected according to the size of the first opening 412.

[0086] Generally speaking, the first opening 412 cannot be etched through the first semiconductor layer 210, and a certain margin needs to be left, such as a 3-5 nanometer thickness margin.

[0087] S313. Anisotropic wet etching is used to etch along the (111) crystal orientation to form a rhombic groove as the first groove 411, as shown in the figure. Figure 9 As shown.

[0088] For example, a diamond-shaped groove is formed by wet etching with TMAH (tetramethylammonium hydroxide). By utilizing the anisotropy of TMAH, grooves determined by the crystal structure are etched in the exposed silicon region (first semiconductor layer 210) to form a diamond-shaped groove with a special shape. After subsequent filling with semiconductor material, the special shape of the diamond-shaped groove provides more quantum wells.

[0089] The etching principle is as follows: TMAH etches the (100) crystal plane of a silicon substrate at an extremely fast rate, but the etching rate of the (111) crystal plane is extremely slow (typically more than 100 times slower than the (100) crystal plane). When etching through a window on a (100) crystal plane silicon wafer, rapid longitudinal (depth) etching and lateral etching occur simultaneously, forming a groove that gradually widens downwards. When it encounters the (111) crystal plane, the etching rate drops sharply. Eventually, the etching stops at the wedge-shaped groove formed by the two (111) crystal planes. Because TMAH etching offers high selectivity between the (111) and (100) crystal planes, this process is not only precise and controllable, but also effectively avoids the damage and defects caused by traditional dry etching. For a (100) crystal plane silicon wafer, the angle between the (111) plane and the surface is 54.74°, so the sidewall angle of the formed V-shaped groove is 54.74°, which is the typical shape of a rhomboid groove.

[0090] It should be noted that the etching solution usually uses a TMAH aqueous solution with a concentration of 5% to 25%. The concentration affects the etching rate and surface roughness. High concentration (>20%) of TMAH can obtain a smoother etched surface, but too high a concentration makes it difficult to control the size accurately. Therefore, 20-25% is commonly used to achieve a better balance between the smoothness of the etched surface and the accuracy of size control.

[0091] It should be noted that the higher the temperature, the faster the etching rate, but more precise control is required; the best anisotropic performance is achieved at 80-90℃.

[0092] This invention combines dry etching and wet etching, making full use of the selectivity of silicon-based semiconductor crystal surface etching. This results in a near-defect-free perfect state of the rhomboid groove cross-section formed in this embodiment. When forming quantum wells, there are fewer defects and a greater effective number of quantum wells. An unexpected technical effect is that the heterojunction interface formed with the self-isolation structure 240 is also perfect, which greatly improves the isolation performance of the self-isolation structure 240. At the same time, the sharp-edged rhomboid groove will also cause stress concentration when epitaxially extending the first photosensitive layer 410. Therefore, silicon stress technology can be used to improve the carrier concentration of the first photosensitive layer 410.

[0093] In step S300, an N-type semiconductor material is filled into the first groove 411 to form a first photosensitive layer 410, as shown below. Figure 10 As shown; specifically including the following steps: S321. Remove the first hard mask layer 310 by dry etching or wet etching. The dry etching is based on fluorine chemistry. The wet etching can be done by hot phosphoric acid or diluted hydrofluoric acid.

[0094] S322, epitaxial N-type semiconductor material, until the first groove 411 is filled; Epitaxial processes include chemical vapor deposition (CVD) and its enhancement technologies, mainly atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal annealing chemical vapor deposition (RTCVD), ultra-high vacuum chemical vapor deposition (UHV / CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0095] For example, SiH2Cl2, SiH4 (silane) or SiCl4 are typically used as silicon sources for selective epitaxy using atmospheric pressure chemical vapor deposition (APCVD). The dopant gas and silicon source gas are introduced into the reaction chamber together. The dopant molecules decompose on the growth surface, and the doped atoms directly enter the silicon lattice positions that are growing, thus achieving in-situ doped epitaxy.

[0096] The N-type semiconductor material is specifically silicon doped with any one of the elements such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). For example, in this embodiment, the N-type semiconductor material forming the first photosensitive layer 410 is antimony (Sb)-doped silicon (abbreviated as Si-Sb), with a doping concentration of heavily doped or near-heavily doped. For example, the doping concentration is 1 × 10⁻⁶. 18 cm 3 Left or right or above, preferably, the doping concentration range is 10 × 10 18 cm 3 Up to 10×10 21 cm 3 .

[0097] S323. Planarization is achieved through CMP (Chemical Mechanical Polishing) process, remaining on the surface of the first semiconductor layer 210, thus completing the filling of the first photosensitive layer 410 within the first groove 411, as shown in the figure. Figure 10 As shown.

[0098] In step S400, a second semiconductor layer 220 is formed by epitaxially forming a first P-type semiconductor material on the first semiconductor layer 210 filled with the first photosensitive layer 410, as shown in the figure. Figure 11 As shown, the thickness of the material of the second semiconductor layer 220 is approximately the same as that of the first semiconductor layer 210, or the same thickness can be used. The epitaxial process is the same as that of the first semiconductor layer 210 in step S200.

[0099] In step S500, several second grooves 421 extending to the first photosensitive layer 410 are etched within the second semiconductor layer 220, resulting in the following: Figure 13 As shown, the specific steps include: S511, Epitaxial growth of a second hard mask layer 320 on the second semiconductor layer 220, as shown in the figure. Figure 12 As shown; the second hard mask layer 320 and the first hard mask layer 310 have the same material and thickness, and the epitaxial process and control parameters are the same as those for the epitaxy of the first hard mask layer 310 in step S311.

[0100] S512. The opening is opened by dry etching of the second hard mask layer 320. The opening can be opened by using processes such as reactive ion etching (RIE), low temperature etching, and high aspect ratio etching (HARP).

[0101] S513. The second semiconductor layer 220 is etched alternately by dry etching and anisotropic wet etching (related processes in the prior art can be used) to form a circular profiled groove. After removing the second hard mask layer 320, the second groove 421 is obtained, as shown in the figure. Figure 13 As shown, the removal process of the second hard mask layer 320 is the same as the process of removing the first hard mask in step S321.

[0102] The present invention provides an exemplary process as follows: Step 1: Dry etching for initial shaping By utilizing the anisotropy of dry etching, the main depth and basic vertical sidewalls of the groove are rapidly etched on the second semiconductor layer 220 through reactive ion etching (RIE) or deep reactive ion etching (DRIE), defining the location and main dimensions of the groove.

[0103] Step 2: Wet etching for rounded corner finishing By utilizing the isotropic or controllable anisotropy of wet etching, the sharp corners left in the first step are rounded off, forming the desired circular cross-section.

[0104] Etching is performed using a TMAH solution with added surfactant. This method allows for the precise formation of bevels at specific angles (e.g., 54.74°) and the rounding of concave corners by controlling the etching rate along the crystallographic direction during further etching.

[0105] The surfactant in the TMAH solution with added surfactant can be a nonionic surfactant (NC-200), which is a surfactant containing 100% polyoxyethylene alkyl phenyl ether. The volume ratio of the surfactant added is about 0.1%, and the concentration of the TMAH solution is 10-25 wt%; for example, it can be 10 wt%, 20 wt%, and 25 wt%.

[0106] Step 3: Cycling and Fine-tuning Depending on the desired final groove depth and fillet radius, the dry etching-wet etching cycle can be repeated.

[0107] Re-dry etching: used to narrow sidewalls or deepen specific areas, while also creating new tiny sharp corners at the root of already formed rounded corners.

[0108] Second wet etching: round off these newly generated sharp corners again; By repeatedly using dry shaping to create sharp edges and then using wet rounding to eliminate them, the curvature radius, sidewall inclination, and depth-to-width ratio of the final groove are adjusted to make it infinitely close to the ideal circular cross-section of the design.

[0109] In step S500, an N-type semiconductor material is filled into the second groove 421 to form a second photosensitive layer 420, as shown in the figure. Figure 14 As shown.

[0110] The material of the second photosensitive layer 420 is selected from silicon doped with any one of the elements such as nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi), but it is different from the type of the first photosensitive layer 410 in order to form a quantum well. In this embodiment, the first photosensitive layer 410 is a potential well, and the second photosensitive layer 420 is a potential barrier. The appropriate doping element can be selected according to the energy level change after doping with different elements. The doping concentration is also heavily doped or close to heavily doped. For example, the doping concentration is 1×10⁻⁶. 18 cm 3 Left or right or above, preferably, the doping concentration range is 10 × 10 18 cm 3 Up to 10×10 21 cm 3The second photosensitive layer 420 is a silicon material doped with arsenic (As) (abbreviated as Si-As).

[0111] In heavily doped silicon, the two core factors determining its relative conduction band bottom energy are the bandgap narrowing effect and electron affinity. The bandgap narrowing effect is that heavy doping reduces the bandgap width, causing the conduction band bottom to drop. The electron affinity is that the doping atoms themselves may fine-tune the electron affinity of silicon (i.e., the energy difference between the vacuum level and the conduction band bottom); usually, bandgap narrowing is the dominant factor.

[0112] In this embodiment, the donor level of antimony (Sb) is approximately 0.039 eV, and that of arsenic (As) is approximately 0.049 eV. During heavy doping of the silicon substrate, the donor level of antimony (Sb) is lower than that of arsenic (As), meaning it is closer to the conduction band bottom. The donor level affects the degree of ionization; the shallower Sb level results in a lower ionization energy, meaning that at the same temperature, more electrons will be excited to the conduction band in Sb-doped silicon, resulting in a higher electron concentration. However, heavy doping leads to a reduction in the band gap, causing a decrease in the conduction band bottom. The doping atoms themselves may fine-tune the electron affinity of silicon; and band gap narrowing is the dominant factor at medium to high doping concentrations (e.g., 10). 18 -10 19 cm -3 The bandgap narrowing of Si-As is greater than that of Si-Sb. Therefore, Si-As has the largest conduction band bottom and the lowest energy level, naturally becoming a potential well; Si-Sb is called a potential barrier. Thus, when the first photosensitive layer 410 and the second photosensitive layer 420 are chosen as Si-Sb and Si-As respectively, it is necessary to dope with a group III element (such as B) to adjust the bandgap narrowing, so that the bandgap width of the second photosensitive layer 420 is smaller than that of the first photosensitive layer 410. For example, the second photosensitive layer 420 is doped with the same concentration of B as As, while the first photosensitive layer 410 is not doped or lightly doped with B, making its bandgap width smaller than that of the first photosensitive layer 410.

[0113] In step S600, the first P-type semiconductor material is further epitaxially grown to form a third semiconductor layer 230. The epitaxial process is the same as that of the first semiconductor layer 210 in step S200. The thickness of the third semiconductor layer 230 is approximately the same as that of the first semiconductor layer 210. The result after epitaxy is as follows: Figure 15 As shown.

[0114] In step S700, several third grooves extending to the second photosensitive layer 420 are etched within the third semiconductor layer 230. The etching process and the shape of the third grooves are the same as those in step S300 for the first groove 411. Filling the third grooves with N-type semiconductor material to form the first photosensitive layer 410 is also the same as in step S300. The completed structure is as follows: Figure 16As shown, the first photosensitive layer 410, the second photosensitive layer 420 and the first photosensitive layer 410 are stacked together to form a photosensitive region 400 with multiple quantum wells. The homogeneous first semiconductor layer 210, second semiconductor layer 220 and third semiconductor layer 230 are stacked together to form a P-type semiconductor material layer 200. The P-type semiconductor material layers 200 between adjacent photosensitive regions 400 form a self-isolation structure 240.

[0115] Example 6; This example provides another method for preparing an image sensing structure, including the following steps: M100 provides a substrate 100 having a plurality of shallow trench isolation structures 130 therein, and thinning the back side 120 of the substrate 100 to expose the shallow trench isolation structures 130; the result is as follows Figure 5 As shown; for specific process details, please refer to step S100.

[0116] M200, a first semiconductor layer 210 is formed by epitaxially forming a first P-type semiconductor material on the back side 120 of the thinned substrate 100; the result is as follows Figure 6 As shown; for specific process details, please refer to step S200.

[0117] M300, etching a plurality of spaced first grooves 411 within the first semiconductor layer 210, and filling the first grooves 411 with N-type semiconductor material to form a first photosensitive layer 410; the result is as follows Figure 10 As shown; for specific process details, please refer to step S300.

[0118] M400, a buffer layer 600 is formed by epitaxially bonding a second P-type semiconductor material onto the first semiconductor layer 210 filled with the first photosensitive layer 410, as shown in the figure. Figure 17 As shown. The second P-type semiconductor material is selected from silicon material doped with any one of the group II elements such as boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl), and is different from the first P-type semiconductor material. For example, the second P-type semiconductor material is boron (B) doped silicon material (referred to as Si-B), and the doping concentration is heavily doped; the doping process is the same as the formation process of the first semiconductor layer 210 in step S200; the thickness of the buffer layer 600 is 2 nanometers to 20 nanometers.

[0119] When the first photosensitive layer 410 and the second photosensitive layer 420 contain a large number of quantum wells, and the electron concentration in the quantum wells is too high, the Fermi level will be pushed up, causing the depletion region of the PN junction between the photosensitive region 400 and the self-isolation structure 240 to become narrower, and the barrier height to be effectively reduced. This results in a lower PN junction barrier, making it easier for electrons to tunnel directly through the thinned barrier, leading to severe inter-pixel leakage.

[0120] In this embodiment, after inserting different types of P-type dopant elements into the self-isolation structure 240 to form a buffer layer 600, N is formed. + / P+ / P + The structure is equivalent to two back-to-back PN junctions, with a photosensitive region of 400 N. + With buffer layer 600 P + Forming a heterogeneous PN junction, with a 600 P buffer layer. + With self-isolation structure 240 P + The formation of a homojunction and the heavily doped p-type layer of the buffer layer 600 lead to a significant increase in the valence band top, which indirectly raises the conduction band bottom, increasing the energy difference that electrons need to cross. Furthermore, without the buffer layer 600, the inhomogeneous doping or defect levels in the self-isolating structure 240 might create continuous leakage paths in the band gap. Inserting a highly doped, high-quality buffer layer 600 is equivalent to inserting a band gap abrupt change in the leakage path. This abrupt, towering barrier "cuts off" any possible continuous leakage channels formed through defect levels, forcing electrons to overcome a very high and steep barrier to leak, which is extremely difficult in practice.

[0121] M500, a second semiconductor layer 220 is formed by epitaxially forming a first P-type semiconductor material on the buffer layer 600; such as Figure 18 As shown, the specific process is described in step S400.

[0122] M600, etching several second grooves 421 extending to the first photosensitive layer 410 within the second semiconductor layer 220, and filling the second grooves 421 with N-type semiconductor material to form the second photosensitive layer 420; the result is as follows Figure 19 As shown, the specific process is described in step S500.

[0123] M700, continue epitaxy of the first P-type semiconductor material to form the third semiconductor layer 230; the result is as follows Figure 20 As shown, the specific process is described in step S600.

[0124] M800, etching several third grooves extending to the second photosensitive layer 420 within the third semiconductor layer 230, and filling the third grooves with N-type semiconductor material to form the first photosensitive layer 410; the result is as follows Figure 21 As shown, the specific process is described in step S700.

[0125] The first photosensitive layer 410, the second photosensitive layer 420 and the first photosensitive layer 410 are stacked together to form a photosensitive region 400 with multiple quantum wells. The first semiconductor layer 210, the second semiconductor layer 220 and the third semiconductor layer 230 are stacked together to form a P-type semiconductor material layer 200. The P-type semiconductor material layers 200 between adjacent photosensitive regions 400 form a self-isolation structure 240.

[0126] Example 7; This example provides a method for fabricating an image sensor, which, based on Example 5, further includes the following steps: S800, A grid structure is fabricated on the self-isolation structure 240; The metal grid structure is fabricated on the self-isolation structure 240 using an epitaxial process, which can be achieved using the corresponding process in the existing technology.

[0127] S900, a filter layer is fabricated on the photosensitive area 400 between adjacent grid structures.

[0128] After forming the metal grid structure, filter elements are formed between the metal grid structures on the surface of the photosensitive region 400. The filter elements may include, for example, Figure 1 The blue filter element 710, green filter element 720, and red filter element 730 are shown. It should be noted that the filter element includes a color filter and microlenses located on the surface of the color filter. Because the surface of the microlenses is convex, therefore... Figure 1 The blue filter element 710, green filter element 720 and red filter element 730 shown all have a raised surface shape.

[0129] Example 8; This example provides a method for fabricating an image sensor, which, based on Example 6, further includes the following steps: M910, A grid structure is fabricated on the self-isolation structure 240; The metal grid structure is fabricated on the self-isolation structure 240 using an epitaxial process, which can be achieved using the corresponding process in the existing technology.

[0130] M920, a filter layer is fabricated on the photosensitive area 400 between adjacent grid structures.

[0131] After forming the metal grid structure, filter elements are formed between the metal grid structures on the surface of the photosensitive region 400. The filter elements may include, for example, Figure 2 The blue filter element 710, green filter element 720, and red filter element 730 are shown. It should be noted that the filter element includes a color filter and microlenses located on the surface of the color filter. Because the surface of the microlenses is convex, therefore... Figure 2 The blue filter element 710, green filter element 720 and red filter element 730 shown all have a raised surface shape.

[0132] A certain existing technology uses Si-P layers, Si-As layers, Si-Sb layers, and Si-P layers stacked sequentially to form the photosensitive region. Deep trench isolation (DTI) technology is used to fabricate the isolation layer, and the number of quantum wells is obtained by reducing the two-dimensional size of the top Si-P layer. (See schematic diagram below.) Figure 22As shown in Figure A, in this embodiment of the invention, the first photosensitive layer 410, the second photosensitive layer 420, and the first photosensitive layer 410 are stacked sequentially, and the number of quantum wells obtained by the above-mentioned special shape is set as follows. Figure 22 As shown in Figure B, it can be seen that the number of quantum wells and the electron concentration in the quantum wells of the present invention are much higher than those of a certain prior art.

[0133] The above embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Although the invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of the invention do not depart from the spirit and scope of the invention and should be covered within the scope of the claims of the invention.

Claims

1. An image sensing structure, characterized in that, include Substrate; A P-type semiconductor material layer is formed on the substrate; as well as Photosensitive regions are formed in a spaced manner within a P-type semiconductor material layer, and the P-type semiconductor material layers between the photosensitive regions form a self-isolation structure. The photosensitive region is formed by stacking multiple N-type doped photosensitive layers, and the band gaps of adjacent photosensitive layers are different to form multiple quantum wells.

2. The image sensing structure according to claim 1, characterized in that, The photosensitive region is formed by stacking an N-type doped first photosensitive layer, a second photosensitive layer, and a third photosensitive layer in sequence. The band gap of the second photosensitive layer is smaller than that of the first photosensitive layer, making the second photosensitive layer a potential well and the first photosensitive layer a potential barrier.

3. The image sensing structure according to claim 2, characterized in that, The cross-section of the second photosensitive layer is a circle or near-circular shape that is wider in the middle and narrower at the top and bottom, while the cross-section of the first photosensitive layer is a rhombus or near-rhombus shape that is wider in the middle and narrower at the top and bottom.

4. The image sensing structure according to claim 2, characterized in that, A buffer layer is inserted into the self-isolation structure to improve isolation performance. The buffer layer is a P-type semiconductor material layer that can raise the potential barrier.

5. The image sensing structure according to claim 2, characterized in that, The doping elements of the first and second photosensitive layers are selected from group V elements.

6. An image sensor, characterized in that, It includes the image sensing structure as described in any one of claims 1-5, the grid structure formed on the self-isolation structure, and the filter layer formed on the photosensitive area between adjacent grid structures.

7. A method for fabricating an image sensing structure, characterized in that, Includes the following steps: A substrate is provided having a plurality of shallow trench isolation structures therein, and the shallow trench isolation structures are exposed by thinning the back side of the substrate. A first semiconductor layer is formed by epitaxially forming a first P-type semiconductor material on the back side of the thinned substrate; A plurality of spaced first grooves are etched in the first semiconductor layer, and N-type semiconductor material is filled in the first grooves to form a first photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form a second semiconductor layer; Several second grooves extending to the first photosensitive layer are etched in the second semiconductor layer, and N-type semiconductor material is filled in the second grooves to form the second photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form the third semiconductor layer; Several third grooves extending to the second photosensitive layer are etched in the third semiconductor layer, and N-type semiconductor material is filled in the third grooves to form the first photosensitive layer; The first photosensitive layer, the second photosensitive layer, and the first photosensitive layer are stacked together to form a photosensitive region with multiple quantum wells. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked together to form a P-type semiconductor material layer. The P-type semiconductor material layers between adjacent photosensitive regions form a self-isolation structure.

8. The method for fabricating the image sensing structure according to claim 7, characterized in that, Etching a plurality of spaced-apart first grooves within a first semiconductor layer includes the following steps: Epitaxially extending a first hard mask layer on a first semiconductor layer; An opening is created by dry etching the first hard mask layer and the first semiconductor layer; A rhomboid groove is formed by etching along the (111) crystal direction using anisotropic wet etching.

9. The method for fabricating the image sensing structure according to claim 7, characterized in that, Before the second semiconductor layer is formed from the epitaxial first P-type semiconductor material, the following is also included: A buffer layer is formed by epitaxially forming a second P-type semiconductor material on a first semiconductor layer filled with a first photosensitive layer.

10. The method for fabricating the image sensing structure according to claim 7, characterized in that, The first groove is a rhombus or rhombus-like groove that is wider in the middle and narrower at the top and bottom, and the second groove is a circular or circular groove that is wider in the middle and narrower at the top and bottom.

11. The method for fabricating the image sensing structure according to claim 7, characterized in that, Etching a plurality of second grooves extending to the first photosensitive layer within the second semiconductor layer includes the following steps: A second hard mask layer is epitaxially grown on the second semiconductor layer; An opening is created by dry etching the second hard mask layer; The second semiconductor layer is etched alternately by dry etching and anisotropic wet etching to form a circular or near-circular cross-sectional groove.

12. The method for fabricating the image sensing structure according to claim 7, characterized in that, Both the first and second photosensitive layers are doped semiconductor materials, with a doping concentration not lower than the simplified doping concentration.

13. The method for fabricating the image sensing structure according to claim 7, characterized in that, During the epitaxial process of the first and second photosensitive layers, group III elements are doped to adjust the energy level size and form a quantum well.

14. A method for fabricating an image sensor, characterized in that, Includes the following steps: A substrate is provided having a plurality of shallow trench isolation structures therein, and the shallow trench isolation structures are exposed by thinning the back side of the substrate. A first semiconductor layer is formed by epitaxially forming a first P-type semiconductor material on the back side of the thinned substrate; A plurality of spaced first grooves are etched in the first semiconductor layer, and N-type semiconductor material is filled in the first grooves to form a first photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form a second semiconductor layer; Several second grooves extending to the first photosensitive layer are etched in the second semiconductor layer, and N-type semiconductor material is filled in the second grooves to form the second photosensitive layer; Continue epitaxy of the first P-type semiconductor material to form the third semiconductor layer; Several third grooves extending to the second photosensitive layer are etched in the third semiconductor layer, and N-type semiconductor material is filled in the third grooves to form a first photosensitive layer; wherein, the first photosensitive layer, the second photosensitive layer and the first photosensitive layer are stacked together to form a photosensitive region with multiple quantum wells, and the homogeneous first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked together to form a P-type semiconductor material layer, and the P-type semiconductor material layer between adjacent photosensitive regions forms a self-isolation structure; A grid structure is fabricated on a self-isolating structure; A filter layer is fabricated on the photosensitive area between adjacent grid structures.

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