Solar cell and photovoltaic module

Abstract

The invention relates to a solar cell and a photovoltaic module, and the solar cell comprises a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first conductive layer, and a second conductive layer. A first conductive layer is arranged on one surface of the first semiconductor layer deviating from the silicon substrate; at least part of the first conductive layer comprises alternating amorphous conductive layers and microcrystalline conductive layers; a second conductive layer is arranged on one surface, deviating from the silicon substrate, of the second semiconductor layer; the second conductive layer is an amorphous conductive layer. According to the scheme, the amorphous conducting layers and the microcrystalline conducting layers are alternately arranged on the first semiconductor layer, the contact resistance and the optical transmittance of the cell can be better balanced, and therefore the overall performance of the cell is improved, the second conducting layer is arranged to be the amorphous conducting layer, the characteristic that the optical transmittance of the amorphous conducting layer is better is utilized, and the performance of the cell is improved. Therefore, the purpose of balancing the optical and electrical properties of the conductive layer of the second area is achieved.

Description

A solar cell and a photovoltaic module Technical Field

[0001] This invention relates to the field of solar photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells are devices that directly convert light energy into electrical energy. Related technologies involve first fabricating a patterned passivation layer and a doped polycrystalline silicon layer on the surface of the solar cell, then depositing another passivation layer and a doped amorphous silicon layer on the entire back side of the solar cell. Next, the partially doped amorphous silicon layer above the doped polycrystalline silicon is opened up, and then a transparent conductive layer and electrodes are used to conduct electricity of different electrical properties, thus enabling the solar cell to generate electricity.

[0003] Currently, the conductive layer on the surface of solar cells has poor performance, making it difficult to achieve a balance between the optical and electrical properties of solar cells. Summary of the Invention

[0004] In view of this, the present invention proposes a solar cell and a photovoltaic module, which aims to partially or completely solve the technical problem that the conductive layer of existing solar cells is difficult to balance optical and electrical performance.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: In a first aspect, an embodiment of the present invention provides a solar cell, the solar cell comprising: a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first conductive layer, and a second conductive layer; the first semiconductor layer and the second semiconductor layer are alternately disposed on a first surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer have different electrical properties; a first conductive layer is disposed on the side of the first semiconductor layer facing away from the silicon substrate; at least a portion of the first conductive layer comprises alternating amorphous conductive layers and microcrystalline conductive layers; a second conductive layer is disposed on the side of the second semiconductor layer facing away from the silicon substrate; the second conductive layer is an amorphous conductive layer.

[0006] In a second aspect, embodiments of the present invention provide a photovoltaic module, the photovoltaic module including a cover plate, a back plate, and a solar cell disposed between the cover plate and the back plate; the solar cell includes the solar cell as described above.

[0007] In this embodiment, the amorphous conductive layer can form good contact with the first semiconductor layer. The amorphous conductive layer on the first semiconductor layer can collect charge carriers, and the collected charge carriers can be transported laterally through the internal lateral transport effect of the microcrystalline conductive layer on the first conductive layer. Therefore, the design of the first conductive layer including alternating amorphous and microcrystalline conductive layers utilizes the charge carrier collection effect of the amorphous conductive layer and the higher charge carrier concentration and better conductivity of the microcrystalline conductive layer, resulting in better contact between the first conductive layer and the metal electrode and reducing the series resistance of the battery. Furthermore, due to the low charge carrier concentration of the amorphous conductive layer, it has high transmittance in the long wavelength range, increasing transmittance and improving the photoelectric conversion efficiency of the battery. In summary, alternating amorphous and microcrystalline conductive layers on the first semiconductor layer can better balance the contact resistance and optical transmittance of the battery, thereby improving the overall performance of the battery. The second semiconductor layer has a high doping concentration, resulting in excellent conductivity.

[0008] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0010] Figure 1 shows a cross-sectional structural schematic diagram of a solar cell according to an embodiment of the present invention; Figure 2 shows a surface structural schematic diagram of an amorphous conductive layer according to an embodiment of the present invention; Figure 3 shows a surface structural schematic diagram of a microcrystalline conductive layer according to an embodiment of the present invention; Figure 4 shows an interface schematic diagram of an amorphous conductive layer according to an embodiment of the present invention; Figure 5 shows an enlarged schematic diagram of the surface structure of an amorphous conductive layer according to an embodiment of the present invention; Figure 6 shows a schematic diagram of a pyramid structure according to an embodiment of the present invention; Figure 7 shows a schematic diagram of another pyramid structure according to an embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures: 10-First semiconductor layer; 20-Second semiconductor layer; 22-Passivation layer; 21-Doped polycrystalline silicon layer; 30-Silicon substrate; 41-First conductive layer; 42-Second conductive layer; 50-Pyramid structure; 51-Pyramid ridge; 52-Sloping surface; 31-First region; 32-Second region; 33-Platform region; 34-Slope region; 35-Bottom region. Detailed Implementation

[0012] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0013] Referring to Figure 1, which shows a cross-sectional structural schematic diagram of a solar cell provided in an embodiment of the present invention, the present invention discloses a solar cell comprising: a silicon substrate 30, a first semiconductor layer 10, a second semiconductor layer 20, a first conductive layer 41, and a second conductive layer 42; the first semiconductor layer 10 and the second semiconductor layer 20 are alternately disposed on a first surface of the silicon substrate 30; the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties; the first semiconductor layer 10 has a first conductive layer 41 disposed on the side facing away from the silicon substrate; at least a portion of the first conductive layer 41 includes alternating amorphous conductive layers and microcrystalline conductive layers; the second semiconductor layer 20 has a second conductive layer 42 disposed on the side facing away from the silicon substrate 30; the second conductive layer 42 is an amorphous conductive layer.

[0014] In this embodiment of the invention, referring to FIG1, the solar cell can be a hybrid heterojunction back-contact (HIBC) cell. Specifically, in the solar cell, one of the first surface and the second surface is the front side of the silicon substrate 30, and the other of the first surface and the second surface is the back side of the silicon substrate 30. One of the first semiconductor layer 10 and the second semiconductor layer 20 can be an N-type semiconductor layer, and the other of the first semiconductor layer 10 and the second semiconductor layer 20 can be a P-type semiconductor layer. The first semiconductor layer 10 and the second semiconductor layer 20 are disposed on the same surface of the silicon substrate 30 (such as the first surface). In some embodiments, the scheme is illustrated by the first semiconductor layer 10 being a P-type doped crystalline silicon layer and the second semiconductor layer 20 being an N-type doped polycrystalline silicon layer. In addition, for the HIBC cell, a combination of low-temperature passivation process and high-temperature passivation process is used, and the theoretical efficiency of the cell can reach up to 29.2%. Due to the low mobility and high sheet resistance of the silicon substrate, a conductive layer needs to be added between the silicon substrate and the metal electrode.

[0015] Referring to Figure 1, in some embodiments, a first semiconductor layer 10 and a second semiconductor layer 20 are disposed on a first surface of a silicon substrate 30. Since the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties, alternating P-regions and N-regions can be formed on the first surface of the solar cell. The P-region is the hole transport region of the solar cell, corresponding to the first region 31; the N-region is the electron transport region of the solar cell, corresponding to the second region 32. The current collector electrode is typically a fine grid electrode, used to extract charge carriers from the solar cell. The bus electrode is typically a main grid electrode, used to combine the charge carriers transported by multiple current collector electrodes together.

[0016] Specifically, in this embodiment of the invention, a first conductive layer 41 is disposed on the side of the first semiconductor layer 10 facing away from the silicon substrate. At least a portion of the first conductive layer 41 includes alternating amorphous conductive layers and microcrystalline conductive layers. When the annealing temperature and time meet certain conditions, the conductive layer crystallizes and transforms into a microcrystalline conductive layer. The difference between the amorphous conductive layer and the microcrystalline conductive layer lies in the degree of atomic arrangement order, electrical properties, and optical characteristics.

[0017] For amorphous conductive layers, the atomic arrangement is long-range disordered (lacking crystalline periodic structure), resulting in a smoother surface. Dopants in amorphous conductive layers are often in an inactive state, relying primarily on oxygen vacancies for conduction. This leads to lower carrier concentration, lower conductivity, and higher transmittance over long wavelengths. Furthermore, the interface between the amorphous conductive layer and the first semiconductor layer is less prone to oxidation, resulting in superior contact.

[0018] Regarding the microcrystalline conductive layer, some of the dopants in the layer are in an activated state. The microcrystalline conductive layer conducts electricity through the combined action of oxygen vacancies and electrons contributed by the dopants, resulting in a high carrier concentration and higher conductivity. This facilitates lateral carrier collection, strengthens long-wavelength absorption, and reduces long-wavelength transmittance. The contact resistance between the microcrystalline conductive layer and the first semiconductor layer is relatively high.

[0019] Referring to Figure 2, which shows the surface morphology of the amorphous conductive layer, and to Figure 3, which shows the surface morphology of the microcrystalline conductive layer.

[0020] In practical applications, the amorphous conductive layer can form good contact with the first semiconductor layer 10. Charge carriers can be collected through the amorphous conductive layer on the first semiconductor layer 10, and then transported laterally through the internal lateral transport effect of the microcrystalline conductive layer on the first conductive layer 41. Therefore, the design of the first conductive layer 41, which includes alternating amorphous and microcrystalline conductive layers, utilizes the carrier collection effect of the amorphous conductive layer and the higher carrier concentration and better conductivity of the microcrystalline conductive layer, resulting in better contact between the first conductive layer 41 and the metal electrode, thus reducing the series resistance of the battery.

[0021] Furthermore, amorphous conductive layers have low carrier concentrations and high transmittance in the long wavelength range, while microcrystalline conductive layers have high carrier concentrations and slightly lower transmittance in the long wavelength range. Therefore, alternating amorphous and microcrystalline conductive layers on the first semiconductor layer can better balance the battery's contact resistance and optical transmittance, thereby improving the overall performance of the battery.

[0022] Furthermore, a second conductive layer 42 is provided on the side of the second semiconductor layer 20 that is opposite to the silicon substrate 30. The second conductive layer 42 is an amorphous conductive layer.

[0023] In practical applications, the second semiconductor layer 20 of the HIBC battery has a high doping concentration, resulting in excellent conductivity. Therefore, the second conductive layer 42 on the second semiconductor layer 20 does not simply aim for the lowest contact resistance, but rather prioritizes optimizing optical performance while ensuring good ohmic contact. The second region 32, where the second semiconductor layer 20 is located, is a polished surface. Due to the electrical shading phenomenon in the second region 32, its area is often small, so its optical benefits need to be maximized. Since the first region 31, where the first semiconductor layer 10 is located, has a rough textured surface structure, and the conductive layers of the first region 31 and the second region 32 in the battery are fabricated simultaneously, the contact resistance of the second conductive layer 42 on the second semiconductor layer 20 is inherently low. Setting the second conductive layer 42 as an amorphous conductive layer utilizes the better optical transmittance of amorphous conductive layers, thereby achieving the goal of balancing the optical and electrical properties of the conductive layer in the second region 32.

[0024] Referring to Figure 4, which shows a schematic diagram of the interface of the second conductive layer in the second region 32, and referring to Figure 5, which shows an enlarged schematic diagram of the surface structure of the second conductive layer.

[0025] Optionally, referring to Figure 1, the thickness of the second conductive layer is greater than the thickness of the first conductive layer.

[0026] The first conductive layer 41 and the second conductive layer 42 are fabricated simultaneously. The second conductive layer 42 is a conductive layer disposed on the second semiconductor layer 20 located in the second region 32 (N region), and the first conductive layer 41 is a conductive layer disposed on the first semiconductor layer 10 located in the first region 31 (P region). The surface of the second semiconductor layer 20 is polished and flat, allowing for uniform deposition of the conductive layer during vapor deposition, easily forming a thicker and more uniform film. The surface of the first semiconductor layer 20 is textured and rough, resulting in a thinner average thickness of the conductive layer formed during vapor deposition.

[0027] Regarding the design where the thickness of the second conductive layer 42 is greater than that of the first conductive layer 41, since the second region 32 (N-region) is a polished surface and the doping concentration of the second semiconductor layer 20 is high, the contact resistance between the second semiconductor layer 20 and the second conductive layer 42 is low. Therefore, the thicker second conductive layer 42 can effectively reduce its lateral resistance, compensate for the relatively weak conductivity of amorphous materials, and ensure efficient lateral current transmission. The thinner first conductive layer 41 facilitates interface contact; furthermore, the alternating amorphous and microcrystalline structure of the first conductive layer 41 balances electrical and optical properties, thus eliminating the need for increased thickness to improve performance. A thinner first conductive layer 41 is sufficient to meet its transmission requirements, while also reducing material costs and parasitic light absorption.

[0028] Optionally, referring to FIG1, in the region where the first semiconductor layer 10 is located, the portion near the second semiconductor layer 20 includes a ramp region 34 and a platform region 33; the ramp region 34 is further away from the second semiconductor layer 20 than the platform region 33; the portion of the second semiconductor layer 20 near the platform region 33 forms a stacked structure with a portion of the first semiconductor layer 10.

[0029] In some embodiments, the first conductive layer 41 located on the slope region 34 is an amorphous conductive layer.

[0030] In some embodiments, the first conductive layer 41 located on the platform region 33 is an amorphous conductive layer.

[0031] In some embodiments, the conductive layer located on the stacked structure is a second conductive layer 42.

[0032] In this embodiment of the invention, for a HIBC battery, the N-region (second region 32) and the P-region (first region 31) are alternately arranged on the first surface of the solar cell. In this embodiment of the invention, the platform region 33 and the ramp region 34 are located between the N-region and the P-region, and the ramp region 34 is located between the first region 31 and the platform region 33.

[0033] In this design, the height of the platform region 33 relative to the silicon substrate 30 is greater than the height of the slope region 34 relative to the silicon substrate 30. Alternatively, the thickness of the platform region 33 corresponding to the silicon substrate 30 is greater than the thickness of the slope region 34 corresponding to the silicon substrate 30. This creates a height difference between the platform region 33 and the slope region 34. The height of the slope region 34 can decrease uniformly along the second direction Y (perpendicular to the first direction X), thus forming a slope surface. Furthermore, it can be seen that a portion of the second semiconductor layer 20 near the platform region 33 forms a stacked structure with a portion of the first semiconductor layer 10.

[0034] Specifically, the first conductive layer 41 located on the slope region 34 is an amorphous conductive layer, and the first conductive layer 41 located on the platform region 33 is an amorphous conductive layer. The slope region 34 and the platform region 33 are polished surfaces. The amorphous conductive layer has a better passivation effect, resulting in a low carrier concentration, which can control the leakage current and reduce leakage. That is, the embodiment of the present invention can utilize the characteristics of low carrier concentration and weak lateral transport capability of the amorphous conductive layer to effectively limit the leakage current and avoid affecting the battery efficiency due to excessive leakage current.

[0035] Furthermore, hot spot risk refers to the situation where, when a battery is partially shaded, the shaded portion transforms from a power generation unit into a power consumption unit. If the current cannot flow smoothly, it will accumulate near the shading point and be converted into heat energy, leading to high-temperature burnout of the battery. The first conductive layer 41 on the slope region 34 and the platform region 33 is an amorphous conductive layer. Although the conductivity of the amorphous conductive layer is poor, it is not an insulator and still possesses a certain degree of conductivity. By setting the amorphous conductive layer on the slope region 34 and the platform region 33, when local shading occurs, the amorphous conductive layer allows some current to bypass the shading point, thereby preventing the extreme accumulation of current and heat at the shading point and thus playing a role in preventing hot spots.

[0036] Furthermore, the conductive layer located on the stacked structure is the second conductive layer 42, which utilizes the characteristics of the amorphous conductive layer itself having lower contact resistance and better optical transmittance, thereby achieving the purpose of balancing the optical and electrical properties of the conductive layer in the second region 32.

[0037] Optionally, the thickness of the first conductive layer is 20nm-100nm; in some embodiments, the thickness of the first conductive layer located on the slope region is 5nm-50nm.

[0038] In some embodiments, the thickness of the second conductive layer is 20nm-100nm.

[0039] In practical applications, the thickness of the first conductive layer can be selected according to actual needs. For example, the thickness of the first conductive layer can be any value among 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0040] In practical applications, the thickness of the first conductive layer located on the slope region can be selected according to actual needs. For example, the thickness of the first conductive layer located on the slope region can be any value among 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm.

[0041] In practical applications, the thickness of the second conductive layer can be selected according to actual needs. For example, the thickness of the second conductive layer can be any value among 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm.

[0042] Optionally, referring to Figures 1, 6 and 7, at least a portion of the first surface of the silicon substrate 30 has a pyramid structure 50, a first semiconductor layer 10 is conformally deposited on the surface of the silicon substrate 30, and a first conductive layer 41 is conformally deposited on the side of the first semiconductor layer 10 away from the silicon substrate 30; the thickness of the first conductive layer 41 located at the pyramid ridge 51 of the pyramid structure 50 is greater than the thickness of the first conductive layer 41 located at the slope 52 of the pyramid structure 50.

[0043] In Figure 7, the pyramid structure 50 has four edges 51: AO, BO, CO, and DO. The pyramid structure 50 also has four faces 52: AOD, BOA, COB, and DOC, formed by two adjacent edges 41 emanating from the apex O. It should be noted that this embodiment does not limit the number of edges 51 and faces 52 included in a single pyramid structure 50. In some embodiments, a single pyramid structure 50 may have ≥3 edges 51 and ≥3 faces 52.

[0044] In this embodiment, at least a portion of the surface region of the silicon substrate 30 has a pyramid structure 50. The first semiconductor layer 10 is conformally deposited on the surface of the silicon substrate 30, such that at least a portion of the surface region of the first semiconductor layer 10 has a pyramid structure 50. The first conductive layer 41 is conformally deposited on the side of the first semiconductor layer 10 away from the silicon substrate 30, such that at least a portion of the surface region of the first conductive layer 41 has a pyramid structure 50. The function of the pyramid structure 50 is to increase the light trapping effect on the surface of the battery cell, reduce the reflection of light on the battery surface, increase the utilization rate of light by the battery, and improve the battery performance.

[0045] Among them, the pyramid structure 50 can be obtained in an alkaline bath by texturing. The required solution is a potassium hydroxide solution with a concentration of 3±0.5% and a texturing additive, the solution temperature is 82±2 degrees Celsius, the process time is 600±30 seconds, the etching amount is 0.6±0.1g, and the reflectivity is 10±1%.

[0046] In practical applications, under the same process conditions, a thinner conductive layer has a lower carrier concentration and higher sheet resistance, resulting in weaker resonant absorption of light and reduced parasitic absorption of light. A thicker conductive layer has an even higher carrier concentration and lower sheet resistance, resulting in stronger resonant absorption of light and increased parasitic absorption of light. At the same time, a thicker conductive layer has lower transmission resistance, which is beneficial for the lateral transport of carriers, and lower contact resistance, which is beneficial for electrical transport with the collector electrode, thus facilitating the collection of carriers by the collector electrode of the solar cell.

[0047] Parasitic absorption refers to the phenomenon where a transparent conductive layer, originally designed to conduct current rather than absorb photons, inevitably absorbs a portion of the incident light and converts this light energy into unusable heat energy instead of electrical energy. This process directly reduces the battery's short-circuit current and ultimately its photoelectric conversion efficiency. The thicker the conductive layer, the more it affects the layer's penetration of certain wavelengths of light, leading to an enhanced parasitic absorption phenomenon.

[0048] Resonant absorption refers to the phenomenon where, when light shines on a conductive layer, the electromagnetic field of the light wave drives the free electrons in the material to oscillate synchronously. Resonance occurs when the frequency of the incident light matches the natural frequency of the collective oscillation of the free electrons. When the resonance condition is met, the conductive layer exhibits abnormally strong absorption of light of a specific wavelength (resonant wavelength), thus blocking that wavelength of light from entering the absorption layer and causing significant current loss. The resonant absorption phenomenon is weaker when the conductive layer is thinner and stronger when the conductive layer is thicker.

[0049] In this embodiment of the invention, the thickness of the first conductive layer 41 located at the ridge 51 of the pyramid structure 50 can be set to be greater than the thickness of the first conductive layer 41 located at the inclined surface 52 of the pyramid structure 50. For the exposed surface of the pyramid structure 50, the area occupied by the ridge 51 is much smaller than the area occupied by the inclined surface 52. Therefore, for a pyramid structure 50, the area of ​​the ridge 51 on its surface is much smaller than the area of ​​the inclined surface 52. Similarly, for the surface of the first conductive layer 41 on the first semiconductor layer 10, the area of ​​the first conductive layer 41 at the ridge 51 is much smaller than the area of ​​the first conductive layer 41 at the inclined surface 52. Furthermore, since the thickness of the first conductive layer 41 located at the ridge 51 is greater than the thickness of the first conductive layer 41 located at the inclined surface 52 of the pyramid structure 50, the proportion of the thicker first conductive layer 41 on the first semiconductor layer 10 is relatively small, while the proportion of the thinner first conductive layer 41 is relatively large. It can be understood that although the first conductive layer 41 at the ridge is thicker and has the effects of resonant absorption and parasitic absorption, the relative area of ​​the ridge 51 is small, resulting in less resonant absorption and parasitic absorption of incident light. At the inclined surface 52, the thinning of the first conductive layer 41 optimizes the resonant absorption and parasitic absorption of the first conductive layer 41, and the relatively large area of ​​the inclined surface is more conducive to the light utilization efficiency of the battery surface. Through the contact between the electrode and the first conductive layer 41, better contact resistance and lateral transmission current are provided at the thicker ridge, making full use of the selective advantages of the battery conductive layer, thereby improving the overall light utilization efficiency and current transmission efficiency of the battery.

[0050] Therefore, for the conductive region where the first semiconductor layer 10 is located, the portion of the first conductive layer 41 with a larger thickness accounts for a smaller proportion, while the portion of the first conductive layer 41 with a smaller thickness accounts for a larger proportion. This reduces the proportion of the thicker portion of the first conductive layer 41 on the battery. Thus, the larger proportion of the thinner portion of the first conductive layer 41 in this design reduces parasitic absorption and resonant absorption phenomena of the first conductive layer 41, lowering the parasitic absorption defects and resonant absorption defects caused by the thicker portion of the first conductive layer 41, thereby improving the light utilization rate of the solar cell and enhancing its performance. The larger proportion of the thinner portion of the first conductive layer 41 also allows for a larger area for light to pass through, improving the optical performance of the solar cell. Furthermore, the first conductive layer 41 at the ridge is thicker, ensuring the basic thickness of the first conductive layer 41 and improving its conductivity.

[0051] Optionally, the difference between the thickness of the first conductive layer located at the ridge of the pyramid structure and the thickness of the first conductive layer located on the slope of the pyramid structure is 2nm-10nm.

[0052] In practical applications, the above thickness difference can be selected according to actual needs. For example, the above thickness difference can be any value among 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm.

[0053] Optionally, in some embodiments, the first conductive layer and the second conductive layer are single-layer structures.

[0054] In some embodiments, the first conductive layer and the second conductive layer are stacked structures.

[0055] In some embodiments, the stacked structure includes an indium tin oxide layer and a doped metal oxide layer; the doping element of the doped metal oxide layer includes one or more of aluminum, gallium, zinc, and tantalum; the metal oxide includes any one of zinc oxide, indium oxide, tin oxide, and cadmium oxide.

[0056] In this embodiment of the invention, for the case where the first conductive layer and the second conductive layer are both stacked structures, the stacked structure includes an indium tin oxide layer and a doped metal oxide layer. Current verification results show that the indium tin oxide layer can be used as the bottom and top layers in the stacked structure, and the middle layer of the stacked structure is selected as a doped metal oxide layer. This can ensure better contact performance, such as ensuring low contact resistance and high metal pull force; at the same time, it can reduce the consumption of indium-containing target material and reduce battery cost. Specifically, in a preferred embodiment, the layer in contact with N-type / P-type doped silicon in the stacked structure is an indium tin oxide layer, the middle layer is a doped zinc oxide layer or a tin oxide layer, and the top layer is a material with good contact with the electrode, which is a doped indium oxide layer or an indium tin oxide layer.

[0057] Optionally, the In / O atom ratio of the second conductive layer is less than that of the first conductive layer.

[0058] The In / O atomic ratio refers to the ratio of the number of indium (In) atoms to the number of oxygen (O) atoms in an indium tin oxide (InTO) thin film (a commonly used conductive layer material).

[0059] In this embodiment of the invention, data shows that the In / O atomic ratio of the first conductive layer 41 on the first region 31 (P region) is approximately 0.41, while the In / O atomic ratio of the second conductive layer 42 on the second region 32 (N region) is approximately 0.3. The In / O atomic ratio of the second conductive layer is less than that of the first conductive layer. This is because oxygen vacancy conduction is one of the important mechanisms for the conductive layers in both the N and P regions.

[0060] The In / O atom ratio of the first conductive layer 41 on the first region 31 is relatively large, resulting in a higher carrier concentration, better conductivity, and better contact in the first region 31. This can improve electrical performance and reduce the lateral resistance of the P-region conductive layer and the contact resistance with the metal.

[0061] The high In / O atomic ratio of the first conductive layer 41 on the P-region results in a higher carrier concentration, better conductivity, and easier contact with the microcrystalline P. In the second region 32, due to the higher doping concentration of its second semiconductor layer 20, although the carrier concentration of the second conductive layer 20 is lower, the contact between the two is still very good. Therefore, the second conductive layer 20 can utilize its light transmittance to enhance the utilization rate of long-wavelength light. Specifically, for the electrode-covered area, it can enhance the utilization rate of long-wavelength light incident from the front; for the non-electrode-covered area, it can enhance the utilization rate of long-wavelength light incident from the back.

[0062] Optionally, the region where the first semiconductor layer is located includes a bottom region 35, a ramp region 34, and a platform region 33; the ramp region 34 is located between the bottom region 35 and the platform region 33; for a first sub-region in the bottom region 35 that is close to the ramp region 34, and a second sub-region in the bottom region 35 that is far from the ramp region 34; the In / O atomic ratio of the first conductive layer 41 in the first sub-region is smaller than the In / O atomic ratio of the first conductive layer 41 in the second sub-region.

[0063] In this embodiment of the invention, during the electrode printing process, the printing process aims to ensure that the electrode paste completely covers the surface of the conductive layer and forms good contact at the interface between the conductive layer and the paste. However, during the process, due to the fluidity of the paste, it tends to flow towards the first sub-region, making the first sub-region the paste expansion region.

[0064] In the first sub-region, a lower In / O ratio means a lower carrier concentration and weaker conductivity, preventing harmful interdiffusion or reactions between the electrode and the conductive layer, thus stabilizing the contact resistance and avoiding contact performance degradation. Furthermore, the lower In / O ratio in the first sub-region reduces the absorption of long-wavelength photons, allowing more infrared light to pass through, thereby improving battery performance.

[0065] Optionally, referring to FIG1, the first semiconductor layer 10 includes an intrinsic amorphous silicon layer and a doped crystalline silicon layer stacked sequentially; the intrinsic amorphous silicon layer is in contact with the silicon substrate 30; the second semiconductor layer 20 includes a passivation layer 22 disposed on the silicon substrate 30, a doped polycrystalline silicon layer 21 disposed on the passivation layer 22, and a portion of the first semiconductor layer 10 disposed on the doped polycrystalline silicon layer 21.

[0066] One of the first semiconductor layer 10 and the second semiconductor layer 20 is an N-type semiconductor layer, and the other of the first semiconductor layer 10 and the second semiconductor layer 20 is a P-type semiconductor layer. In some embodiments, the scheme is illustrated by taking the first semiconductor layer 10 as a P-type doped crystalline silicon layer and the second semiconductor layer 20 as an N-type doped polycrystalline silicon layer.

[0067] In this embodiment, the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties. In one embodiment, the first semiconductor layer 10 includes a doped crystalline silicon layer, and the second semiconductor layer 20 includes a doped polycrystalline silicon layer. The doped crystalline silicon layer can be any one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon. The second semiconductor layer 20 forms the N-region, providing electron transport for the solar cell; the first semiconductor layer 10 forms the P-region, providing hole transport for the solar cell.

[0068] The passivation layer 22 serves a passivation function, and its thickness is 0.5nm-5nm, preferably 1.2nm-2nm. The passivation layer 22 is made of any one of silicon oxide, aluminum oxide, silicon nitride, silicon carbide, and magnesium oxide.

[0069] This application also provides a photovoltaic module, which includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet. The battery string includes a plurality of solar cells connected in series by interconnecting elements. The solar cells include the aforementioned solar cells.

[0070] This application does not specifically limit whether the photovoltaic module includes other structures. For example, the photovoltaic module may also include: a first encapsulating film disposed between the cover plate and the solar cell, and a second encapsulating film disposed between the back sheet and the solar cell.

[0071] In summary, in this embodiment, the amorphous conductive layer can form good contact with the first semiconductor layer. The amorphous conductive layer on the first semiconductor layer can collect charge carriers, and the collected charge carriers can be transported laterally through the internal lateral transport effect of the microcrystalline conductive layer on the first conductive layer. Therefore, the design of the first conductive layer including alternating amorphous and microcrystalline conductive layers utilizes the charge carrier collection effect of the amorphous conductive layer and the higher charge carrier concentration and better conductivity of the microcrystalline conductive layer, resulting in better contact between the first conductive layer and the metal electrode and reducing the series resistance of the battery. Furthermore, because the amorphous conductive layer has a low charge carrier concentration, it has high transmittance in the long wavelength range, while the microcrystalline conductive layer has a high charge carrier concentration and slightly lower transmittance in the long wavelength range. In conclusion, alternating amorphous and microcrystalline conductive layers on the first semiconductor layer can better balance the contact resistance and optical transmittance of the battery, thereby improving the overall performance of the battery. The second semiconductor layer has a high doping concentration, resulting in excellent conductivity.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0073] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0074] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, The solar cell includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first conductive layer, and a second conductive layer; the first semiconductor layer and the second semiconductor layer are alternately disposed on a first surface of the silicon substrate; the first semiconductor layer and the second semiconductor layer have different electrical properties; a first conductive layer is disposed on the side of the first semiconductor layer facing away from the silicon substrate; at least a portion of the first conductive layer includes alternating amorphous conductive layers and microcrystalline conductive layers; a second conductive layer is disposed on the side of the second semiconductor layer facing away from the silicon substrate; the second conductive layer is an amorphous conductive layer.

2. The solar cell according to claim 1, characterized in that, The thickness of the second conductive layer is greater than the thickness of the first conductive layer.

3. The solar cell according to claim 1, characterized in that, In the region where the first semiconductor layer is located, the portion near the second semiconductor layer includes a ramp region and a plateau region; the ramp region is further away from the second semiconductor layer than the plateau region; the portion of the second semiconductor layer near the plateau region forms a stacked structure with a portion of the first semiconductor layer; the first conductive layer located on the ramp region is an amorphous conductive layer; or, the first conductive layer located on the plateau region is an amorphous conductive layer; or, the conductive layer located on the stacked structure is a second conductive layer.

4. The solar cell according to claim 3, characterized in that, The thickness of the first conductive layer is 20nm-100nm; and / or, the thickness of the first conductive layer located on the slope region is 5nm-50nm; the thickness of the second conductive layer is 20nm-100nm.

5. The solar cell according to claim 1, characterized in that, At least a portion of the first surface of the silicon substrate has a pyramidal structure, the first semiconductor layer is conformally deposited on the surface of the silicon substrate, and the first conductive layer is conformally deposited on the side of the first semiconductor layer away from the silicon substrate. The thickness of the first conductive layer located at the ridge of the pyramid structure is greater than the thickness of the first conductive layer located on the slope of the pyramid structure.

6. The solar cell according to claim 5, characterized in that, The difference between the thickness of the first conductive layer located at the ridge of the pyramid structure and the thickness of the first conductive layer located on the slope of the pyramid structure is 2nm-10nm.

7. The solar cell according to claim 1, characterized in that, The first conductive layer and the second conductive layer are single-layer structures; and / or, the first conductive layer and the second conductive layer are stacked structures; and / or, the stacked structure includes an indium tin oxide layer and a doped metal oxide layer. The doping element of the doped metal oxide layer includes one or more of aluminum, gallium, zinc, and tantalum; the metal oxide includes any one of zinc oxide, indium oxide, tin oxide, and cadmium oxide.

8. The solar cell according to claim 1, characterized in that, The In / O atom ratio of the second conductive layer is smaller than that of the first conductive layer.

9. The solar cell according to claim 1, characterized in that, The region where the first semiconductor layer is located includes a bottom region, a ramp region, and a plateau region; the ramp region is located between the bottom region and the plateau region; there is a first sub-region in the bottom region that is close to the ramp region, and a second sub-region in the bottom region that is far from the ramp region; the In / O atomic ratio of the first conductive layer in the first sub-region is less than the In / O atomic ratio of the first conductive layer in the second sub-region.

10. The solar cell according to claim 1, characterized in that, The first semiconductor layer includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked sequentially; the intrinsic amorphous silicon layer is in contact with the silicon substrate; the second semiconductor layer includes a passivation layer disposed on the silicon substrate, a doped polycrystalline silicon layer disposed on the passivation layer, and a portion of the first semiconductor layer disposed on the doped polycrystalline silicon layer.

11. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting elements; the solar cells include the solar cells as described in any one of claims 1 to 10.

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