Chip-to-wafer advanced packaging method

Abstract

The invention provides a chip-to-wafer advanced packaging method, which comprises the following steps that a carrier wafer and a wafer to be cut are provided, and the wafer to be cut is provided with a plurality of predefined chip units; bonding the back surface of the wafer to be cut with the front surface of the carrier wafer through a temporary bonding process to form a bonded whole; taking the carrier wafer as a process bearing substrate, performing a plasma etching cutting process on the bonded whole, and cutting the to-be-cut wafer into independent chips; carrying out a bonding pretreatment process on the cut chip; and performing a de-bonding process on the carrier wafer and the chips so as to separate the independent chips. By utilizing the method, the manufacturing cost can be reduced by optimizing the technological process, better product performance is realized, and the best realization effect of chip-to-wafer fusion / hybrid bonding advanced packaging is obtained.

Description

Advanced chip-to-wafer packaging methods Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to an advanced chip-to-wafer packaging method. Background Technology

[0002] In the current context of semiconductor technology development, advanced packaging technology has become one of the keys to continuing Moore's Law. As the functionality of integrated circuits continues to improve, traditional packaging methods are gradually failing to meet the demands of high-performance computing and multi-functional integration. Currently, advanced packaging technology is gradually evolving from traditional wire bonding and micro-bump bonding to fusion bonding and hybrid bonding technologies.

[0003] Existing wafer-to-wafer (W2W) fused bonding and hybrid bonding technologies are widely used in the packaging field. However, these technologies have some limitations. For example, wafer-to-wafer packaging requires consistency in wafer size and chip size and is typically limited to connections between silicon-based semiconductors of the same generation, making heterogeneous integration, especially between compound semiconductors and silicon-based semiconductors, difficult. Furthermore, wafer-to-wafer packaging methods cannot perform pre-screening of chips. During multi-layer chip stacking, the presence of defective chips leads to an accumulation of yield losses, ultimately affecting the overall yield of the stacked chips. Summary of the Invention

[0004] The purpose of this invention is to reduce the overall manufacturing cost of advanced packaging by replacing some high-cost and technologically immature processes through process optimization, thereby achieving better product performance and optimal results.

[0005] To this end, the present invention provides an advanced chip-to-wafer packaging method, comprising the following steps: providing a carrier wafer and a wafer to be diced, the wafer to be diced having multiple predefined chip units; bonding the back side of the wafer to be diced to the front side of the carrier wafer through a temporary bonding process to form a bonded whole; using the carrier wafer as a process carrier substrate, performing a plasma etching dicing process on the bonded whole to divide the wafer to be diced into individual chips; performing a pre-bonding processing process on the diced chips; and performing a debonding process on the carrier wafer and the chips to separate the individual chips.

[0006] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the temporary bonding process is fusion bonding, specifically including: forming a dielectric material layer on the front side of the carrier wafer and / or the back side of the wafer to be cut; performing planarization treatment on the surface of the dielectric material layer; performing plasma activation and hydrophilic treatment on the surface of the dielectric material layer; and bonding the back side of the wafer to be cut to the front side of the carrier wafer through the dielectric material layer.

[0007] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the dielectric material layer includes at least one of SiO2, SiN, and SiCN.

[0008] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the debonding process includes: introducing an etching solution into the gap between adjacent chips, wherein the etching solution has a higher etching selectivity for the material constituting the dielectric material layer than for other material layers, so as to dissolve the dielectric material layer between the chip and the carrier wafer, thereby achieving debonding.

[0009] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the etching solution is a buffered oxide etching solution or a diluted hydrofluoric acid solution.

[0010] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the thickness of the etch solution layer is less than the thickness of the semiconductor material layer in the chip.

[0011] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the temporary bonding process is to use temporary bonding adhesive for bonding, and the debonding process includes debonding the temporary bonding adhesive by ultraviolet light irradiation or heat baking to achieve debonding.

[0012] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, the method further includes cleaning the carrier wafer after debonding to remove residual temporary bonding adhesive, and recoating the surface of the carrier wafer with adhesive for reuse.

[0013] Furthermore, preferably, in the chip-to-wafer advanced packaging method of the present invention, when the carrier wafer is used as a process carrier substrate for plasma etching and / or bonding pretreatment processes, process equipment and process formulations adapted to standard-size wafers are used.

[0014] By utilizing this invention, manufacturing costs can be reduced through process optimization, better product performance can be achieved, and the best implementation effect of advanced packaging from chip to wafer fusion / hybrid bonding can be obtained. Attached Figure Description

[0015] Figure 1 is a schematic diagram showing the relative structural relationships of the wafer, blue film, and ring frame in conventional chip-to-wafer advanced packaging methods.

[0016] Figure 2 is a photograph showing the formation of bubbles in the blue film present in conventional chip-to-wafer advanced packaging methods after plasma etching.

[0017] Figure 3 is a schematic diagram illustrating the mechanism by which the blue film present in conventional chip-to-wafer advanced packaging methods releases gas under plasma bombardment.

[0018] Figure 4 is a schematic diagram showing the process steps in conventional chip-to-wafer advanced packaging methods that may be affected by the material of the blue film / ring frame during wafer-to-chip plasma etching and chip-to-wafer hybrid bonding processes.

[0019] Figure 5 is a schematic diagram illustrating the chip-to-wafer advanced packaging process flow according to a preferred embodiment of the present invention.

[0020] Figure 6 is a schematic diagram showing the structural relationship between the film layers of the wafer to be diced and the carrier wafer in the chip-to-wafer advanced packaging process of a preferred embodiment of the present invention.

[0021] Figure 7 is a schematic diagram showing the position and thickness of the etching solution drop in the chip-to-wafer advanced packaging process according to a preferred embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0023] Figures 1 to 4 are schematic diagrams illustrating specific details related to conventional chip-to-wafer advanced packaging methods. Figure 1 shows the relative structural relationship between the wafer, blue film, and ring frame; Figure 2 shows a real-world image of bubbles forming on the blue film after plasma etching; Figure 3 illustrates the mechanism of gas release from the blue film under plasma bombardment; and Figure 4 shows process steps that may be affected by the materials of the blue film / ring frame.

[0024] Chip-to-wafer (D2W) packaging technology has emerged as an upgrade to fusion bonding and hybrid bonding, overcoming the limitations of existing technologies. While improving flexibility, D2W packaging effectively enables heterogeneous and heterogeneous integration. Furthermore, by performing yield screening at the chip level, D2W technology avoids the accumulation of defective chips, thus ensuring a high yield for the final stacked chips. Therefore, D2W fusion bonding and hybrid bonding packaging methods have broader development prospects and advantages.

[0025] Compared to wafer-to-wafer advanced packaging technologies, chip-to-wafer advanced packaging technologies are still under development, especially in wafer-to-chip dicing. Currently, packaging and testing companies commonly use a combination of laser dicing and mechanical dicing for wafer-to-chip dicing. However, laser dicing can cause surface recasting, resulting in uneven chip edges; while mechanical dicing is prone to generating particles, leading to poor surface cleanliness. Both of these issues affect bonding quality, thereby impacting the final bond strength and electrical connectivity.

[0026] To overcome these problems, modern wafer-to-chip dicing technology has increasingly adopted plasma dicing, a method based on dry plasma etching technology in fabs, which has been widely used and is mature. Compared with traditional dicing techniques, plasma dicing offers higher cleanliness, avoiding remelting or particle contamination, thus providing a good foundation for subsequent chip-to-wafer fusion bonding and hybrid bonding.

[0027] However, this cutting method also presents new challenges. In existing wafer-to-chip dicing processes, the bottom of the chip is typically attached to a blue film (i.e., dicing tape). When using plasma dicing, due to the need for over-etching during the etching process to ensure complete chip cutting, some of the blue film surface will inevitably be etched. This causes organic matter within the blue film to be released under plasma bombardment, generating gas, which in turn causes displacement of the blue film, resulting in a change in chip position and thus affecting dicing accuracy.

[0028] Furthermore, during plasma dicing, a certain space exists between the annular region and the wafer. This portion of the blue film is exposed to plasma bombardment, and prolonged exposure causes it to continuously release gas, thus affecting the plasma environment and leading to etching anomalies. In this process, the blue film with a larger exposed area will adversely affect the dicing process. Figure 1 shows the structural relationship between the wafer, the blue tape (also known as the blue film), and the ring frame. Figures 2 and 3 show actual photographs and the mechanism of gas release and bubble formation by the blue tape / blue film under plasma bombardment.

[0029] After plasma cutting, Asher ashing and Wet Strip cleaning processes are required. First, the Asher process, essentially plasma etching in an oxygen atmosphere, will also etch the exposed film layers, leading to blue film deformation, chip displacement, and gas release issues. Second, the solutions typically used in the Wet Strip cleaning process (such as SC1, SC2, HF, H2SO4, H2O2, etc.) react with organic matter in the blue film, potentially causing blue film damage or reduced adhesion to the chip, leading to chip detachment. Furthermore, if the reaction byproducts are not completely removed, they may adhere to the chip surface, affecting the final bonding effect.

[0030] In the subsequent pre-bonding process, a surface solution cleaning is first performed to remove the oxide film, surface particles, and other contaminants from the Cu Pad surface. Next, the chip surface undergoes plasma activation, typically using gases such as Ar, N2, and O2 to bombard the surface with plasma, making it hydrophilic. Following this, a water spin-coating process is applied to the chip surface, again preparing for subsequent hydrophilic bonding. These processes also suffer from the aforementioned incompatibility between the blue film and wafer manufacturing processes, resulting in additional contamination and affecting the final bonding effect.

[0031] Besides the drawbacks of the blue film mentioned above, there's also the issue that bonding the wafer to the blue film results in less flatness after bonding due to the film's flexibility. This leads to a decrease in the precision of subsequent photoresist coating, development, and exposure. Consequently, the subsequent plasma etching and die cutting process will also be affected.

[0032] Besides the blue film, the outer ring surrounding it is also a risk factor. Similar problems can arise, such as corrosion in pickling solutions, leading to damage. Furthermore, corrosion can generate contaminants, which can also affect the existing process. Because the ring structure is not a common structure in wafer front-end processes, it also presents its own risks.

[0033] Figure 4 illustrates the process steps that may be affected by the Blue Tape / Frame material during wafer-to-chip plasma etching and chip-to-wafer hybrid bonding processes.

[0034] Because we adopted the Blue Tape+Frame structure, which is 380mm in size, it is incompatible with the existing 12-inch silicon-based 300mm chuck. Therefore, structures such as the EFEM and chamber cannot be shared. This means that many processes (such as plasma pretreatment before bonding and hydrophilic water spin coating) must be equipped with separate EFEMs and chambers, making it impossible to share with mature wafer-to-wafer fusion / hybrid bonding processes, which has become a disadvantage.

[0035] In summary, the commonly used blue film materials / rings are incompatible with the advanced packaging front-end wafer manufacturing processes used in advanced packaging, leading to a series of problems. The optimization goal of this patent is precisely to solve this problem, thereby improving the final realization effect of chip-to-wafer advanced packaging.

[0036] The most common chip-to-wafer fusion bonding / hybrid bonding process flow currently involves dicing the wafer into chips using plasma etching on a blue film on the frame (including Litho, ETCH, Asher, Wet Stripe, etc.). Then, film expansion is performed, creating gaps between the individual chips, forming separate chips. The frame ring then supports these separate chips, and subsequent bonding preparation processes, mainly cleaning, plasma activation, and spin-coating with water, are performed. The aforementioned wafer-to-chip plasma etching and dicing processes, as well as the chip-to-wafer bonding pre-processes, all rely on frames with blue films to support the wafers or chips. However, as mentioned above, the incompatibility of the blue film / ring material with the front-end wafer manufacturing processes for advanced packaging applications leads to a series of blue film / ring decomposition and breakage issues. This decomposition then causes contamination problems.

[0037] The current common approach is to collaboratively optimize the blue film / ring material and the process recipes involved in the aforementioned processes. However, this involves optimizing the blue film / ring and modifying the process recipes, resulting in a huge workload. When the blue film / ring material cannot meet the process recipe requirements, adjustments to the process recipe are necessary. This requires modifying an already mature and effective process recipe, necessitating extensive validation work. It is highly likely that the adjusted process recipe will not achieve the original results.

[0038] The advantage of this invention lies in replacing the original blue film / ring material with an inorganic film material commonly used in wafer manufacturing through process optimization. This allows subsequent processes such as wafer-to-chip plasma dicing and chip-to-wafer bonding to utilize existing, mature front-end wafer manufacturing processes, resulting in the lowest cost. Furthermore, these process recipes have undergone large-scale process verification, demonstrating better and more mature process implementation. Moreover, all carriers and EFEMs following this invention can utilize existing conventional 12-inch 300mm wafer systems, whereas the original blue film / ring was 380mm in size, requiring corresponding carrier modifications for processing. Therefore, existing 12-inch wafer systems have better compatibility with this invention. In summary, using this invention ultimately achieves the best results in advanced chip-to-wafer fusion / hybrid bonding packaging.

[0039] Figure 5 shows a schematic diagram of the optimized chip-to-wafer advanced packaging process of the present invention.

[0040] The detailed process flow is as follows: It mainly consists of four parts, which are described in detail below: 1. Melt bonding between the wafer to be diced and the carrier wafer: Prepare the carrier wafer, deposit a dielectric film layer of a certain thickness on its surface using CVD technology, and then perform CMP to planarize its surface. At this time, the back side of the wafer to be diced, which is to be bonded to it, already has a SiO2 film layer of a certain thickness due to natural oxidation, and is also CMP planarized. After the two wafers are prepared, perform the plasma activation required for melt bonding, followed by a hydrophilic spin-coating process, and then melt bond the two wafers together.

[0041] 2. Wafer Plasma Etching and Dicing: This process is more similar to the front-end wafer manufacturing process, except that the substrate is not a frame but a carrier wafer. It's a single unit consisting of the E-Chuck carrier wafer and the wafer to be diced, commonly found in wafer foundries. Therefore, it's almost identical to the wafers processed by typical wafer foundries, requiring minimal modification and achieving better results. The process begins with photoresist coating, followed by exposure and development. Then, plasma etching is performed to ashing residual photoresist, and acid washing is used to clean the modified photoresist and etching byproducts. This completes the plasma etching and dicing of the wafer core. These steps involve materials commonly found in wafer foundries, such as silicon and dielectric films, thus avoiding additional contamination or introducing other variables.

[0042] 3. Hybrid Bonding Chip Pretreatment: Here, we employ conventional pre-hybrid bonding plasma activation and surface spin-coating with water for hydrophilication, preparing for subsequent chip-to-wafer hybrid bonding and advanced packaging. Similar to step two, the materials involved are common silicon and dielectric films, thus introducing other variables such as contamination.

[0043] 4. Chip and carrier wafer debonding: Because gaps exist between the chips after dicing, a solution that can only dissolve the dielectric film is dripped into these gaps (and onto the edges of the chip and carrier wafer). This dissolves the dielectric film, thus debonding the chip and carrier wafer. We then obtain an independent chip. Subsequently, we can directly perform co-bonding with a wafer or another chip for advanced packaging.

[0044] Furthermore, it's important to clarify the first step of fusion bonding. We can deposit a layer of SiO2 on the surface of the carrier wafer, or deposit a layer of SiO2 followed by a layer of SiN / SiCN (since SiN / SiCN has higher stress, SiO2 needs to be deposited first as a buffer layer), and then perform CMP to planarize the surface. The wafer to be diced, which is being bonded to, does not require an additional dielectric film layer because in a conventional fab environment, a SiO2 film tens of nanometers thick is formed on the back side of the silicon. Therefore, we can directly perform CMP to planarize it. After preparing this pair of wafers, we can then perform plasma activation, hydrophilic treatment, and other processes for fusion bonding. A schematic diagram of the film structure of the wafer to be diced and the carrier wafer is shown in Figure 6.

[0045] In the second step of wafer plasma etching and dicing, and the third step of hybrid bonding chip pre-processing, we use the foundry's front-end processes. After optimization with this solution, all processes still involve silicon, dielectric films, and other materials. Therefore, unlike Blue Tape and Frame, it does not introduce other variables, nor does it cause additional contamination or alter the process environment. The overall process consistency is higher, and minimal process adjustments are required. Existing mature processes require almost no modification and can be used directly.

[0046] In the fourth step of the chip-carrier wafer debonding process, we need to select a solvent that has a very fast etching rate for SiO2 but a very slow etching rate for Si, SiN, and SiCN materials.

[0047] The first type is Buffered Oxide Etch (BOE), also called BHF (Buffered HF). A typical formulation is NH4F + HF + H2O (common ratios are 6:1 or 7:1, etc.). Etching rates are: SiO2 (thermal silicon oxide): hundreds to thousands of Å / min (depending on concentration and temperature); PECVD SiO2 (TEOS or Silane-based): 1200~3500 Å / min (usually 1.5~4 times faster than thermal oxidation, depending on deposition conditions; low-temperature TEOS can reach over 4000 Å / min); SiN (LPCVD Si3N4): <1 Å / min (almost no etching); Single-crystal silicon Si: almost no etching (selectivity >1000:1). The second type is Diluted Hydrofluoric Acid (DHF). The most common formulation is 49% HF diluted with DIW (ultrapure water) at a ratio of 1:50 (HF ≈ 1). Etching rates (at room temperature 23~25°C, typical measured values): Thermally oxidized SiO2 (dense): 1:100 → 12~18 Å / min; 1:200 → 6~9 Å / min; 1:500 → 2~4 Å / min; PECVD SiO2 (TEOS or Silane-based, common dielectric layer): 1:100 → 80~300 Å / min (typically 6~20 times faster than thermal oxidation); 1:200 → 40~150 Å / min (the specific rate depends on the deposition temperature, density, and hydrogen content; low-temperature PECVD TEOS can reach up to 400 Å / min). Native oxide (1.5~3 nm thick) at a selectivity ratio of 1:100 is approximately 30~50 Å / min. LPCVD Si3N4 (high-temperature silicon nitride) <0.1 Å / min (almost no etching). PECVD SiN 0.2~1.5 Å / min (still extremely slow). Single-crystal silicon (bare silicon) <0.05 Å / min (selectivity ratio >10,000:1, considered completely no etching). Polycrystalline silicon (Poly-Si) <0.2 Å / min (also considered no etching). The interface state before hybrid bonding on the chip surface has been formed, and we need to maintain its state. Since there are gaps between chips, we add the solution through these gaps (and at the edge between the chip and the carrier wafer). The thickness of the added solution cannot exceed the thickness of Si in the chip to avoid damaging the dielectric film layer on the Si in the chip.Once the added solution has etched the SiO2 onto the chip, there is no longer any bonding force between the chip and the carrier wafer. We can then use a chip bonding machine to directly pick up the chip for subsequent hybrid bonding and advanced packaging.

[0048] After the chip is debonded to the carrier wafer in the fourth step and all the chip is removed, if the carrier wafer has a SiO2 film layer, much of it has been lost due to the solution. In this case, a new SiO2 film layer can be deposited using CVD, followed by CMP planarization. This allows the wafer to be reused as a carrier wafer. If the carrier wafer has a SiCN / SiN film structure, the solution loss is minimal, so it can be directly planarized using CMP and reused. If the loss is considered significant, a SiCN / SiN layer (or SiO2) can be deposited using CVD, followed by CMP planarization. This allows it to be reused as a carrier wafer. Compared to the single-use, non-reusable nature of frames, this method is more advantageous.

[0049] The original blue tape / ring structure was 380mm in size, instead of the common 300mm size used in front-end wafer manufacturing processes, necessitating hardware modifications to the equipment. This involved modifications to the EFEM, cavity, and many other hardware structures. However, with this invention, all dimensions are standard 12-inch 300mm wafers. Therefore, the EFEM and process cavities for the wafer-to-chip plasma etching and dicing series of equipment (photolithography, etching, ashing, cleaning, etc.) and the chip bonding pretreatment equipment (brushing, plasma activation, surface hydrophilic treatment) can be directly used, meaning it is fully compatible with existing 12-inch 300mm wafers. The wafer-to-chip plasma dicing series of equipment can utilize equipment used in TSV fabrication. The chip bonding pretreatment equipment can use a cavity for wafer-to-wafer hybrid bonding plasma activation and hydrophilic treatment; however, the bonding module within it needs to use a chip-to-wafer bonding machine. This is because current chip-to-wafer hybrid bonding mostly uses separate equipment, with one machine being the chip bonding machine and the other being a separate plasma activation and hydrophilic treatment unit. This eliminates the need to purchase a dedicated plasma activation and hydrophilic treatment machine; the existing wafer-to-wafer hybrid bonding machine can suffice. Only a chip-to-wafer hybrid bonding machine needs to be purchased. In summary, the wafer-to-chip plasma etching and dicing and chip bonding pretreatment machines described above can utilize existing equipment and mature recipes, significantly reducing workload and costs, while ultimately achieving better process results.

[0050] Traditional temporary bonding with blue adhesive tape can lead to poor surface flatness due to the elasticity of the tape surface, which can cause deformation. In this invention, fusion bonding is used to bond the wafer to be diced onto a silicon carrier wafer for dicing and subsequent pre-bonding processes. The use of CMP and fusion bonding processes results in a high degree of surface flatness after bonding. Therefore, the high-flatness chip surface morphology achieved by this invention significantly improves the accuracy of subsequent photolithography and etching processes, thus enhancing the precision of wafer-to-chip plasma etching and dicing. Similarly, the precision of subsequent pre-bonding cleaning, plasma activation, and hydrophilic water spin coating processes is also improved, ultimately achieving the advanced chip-to-wafer fusion / hybrid bonding packaging effect.

[0051] The temporary bonding and debonding methods described above utilize melt bonding. Alternatively, temporary bonding adhesive can be used. Specifically, the first step involves uniformly spin-coating temporary bonding adhesive onto the bonding interface between the wafer to be diced and the carrier wafer to achieve temporary bonding. The second step, wafer plasma dicing, and the third step, hybrid bonding chip pretreatment remain unchanged. The fourth step, the debonding process from the carrier wafer, uses UV or other methods to debond the chip, thus separating it from the carrier wafer. After separation, residual temporary bonding adhesive on the carrier wafer can be removed using wet acid washing, allowing the carrier wafer to be reused. Subsequently, temporary bonding adhesive can be spin-coated again, repeating the temporary bonding process from the first step. This enables the reuse of the carrier wafer.

[0052] Figure 5 illustrates the chip-to-wafer advanced packaging process in a preferred embodiment of the present invention. Figure 6 illustrates the film structure of the wafer to be diced and the carrier wafer in a preferred embodiment of the present invention.

[0053] This solution relates to an improvement in the chip-to-wafer fusion / hybrid bonding advanced packaging process. The main improvement involves replacing the traditional method of temporary bonding between the blue film / ring and the chip wafer with a fusion bonding method between the silicon carrier and the wafer to be diced. This is followed by chip plasma etching and pre-bonding processes. Finally, a solution to dissolve the dielectric film is dripped into the gaps between the chips to achieve debonding between the chip and the silicon carrier wafer. The chip-to-wafer fusion / hybrid bonding advanced packaging process is then performed.

[0054] The main advantage lies in reducing the impact of introducing blue tape / frame on existing mature front-end wafer manufacturing processes. The key advantages are: all substrates are silicon carrier wafers, making the process fully compatible with existing front-end wafer manufacturing equipment and hardware. Hardware modifications to the equipment for blue tape / frame are unnecessary, and there's no concern about byproducts from blue tape / frame affecting the process. This maximizes compatibility with existing production lines, resulting in the lowest cost and best process performance; furthermore, the chip-carrier wafer debonding is stress-free, and the carrier wafer can be reused after a simple rework.

[0055] The points requiring protection are as described in claim 1. The chip wafer to be cut and the silicon carrier wafer are bonded together using a fusion bonding method. A schematic diagram of the film structure is shown in Figure 6. The bonding interface consists of SiO2, SiCN, and SiN.

[0056] The point requiring protection, as described in claim 1, involves a solvent used during debonding that exhibits a high etching rate for SiO2 but a very slow etching rate for Si, SiCN, and SiN. This etching solvent possesses an extremely high selectivity ratio for SiO2 to Si / SiCN / SiN. As mentioned above, BOE (Buffered Oxide Etch), also known as BHF (Buffered HF) or DHF (Diluted Hydrofluoric Acid), is available; detailed formulation descriptions are provided in Part III Supplementary Notes.

[0057] As described in claim 1, the points requiring protection involve dripping etching solvent into the gap between the chips during debonding. Furthermore, the thickness of the solvent dripped in must be less than the thickness of the silicon in the chip, with a thickness difference of at least 10 μm. This ensures that the dielectric film layer on the chip itself is not damaged, as illustrated in Figure 7.

[0058] In this invention, the first step of bonding the wafer to be diced to the carrier wafer uses a temporary bonding process. Previously mentioned was the fusion bonding process for temporary bonding and subsequent debonding. Alternatively, we can use a method of uniformly applying temporary bonding adhesive to the surfaces of both the wafer to be diced and the carrier wafer to temporarily bond them. Subsequent wafer plasma etching and chip pretreatment are the same as described above. During subsequent debonding, methods such as UV bonding can be used, at which point the chip separates from the carrier wafer. In this method, the temporary bonding adhesive on the carrier wafer can be completely removed by wet acid washing. The carrier wafer can then be reused. Subsequently, temporary bonding adhesive can be spin-coated again, repeating the temporary bonding process from the first step. This allows for the reuse of the carrier wafer.

[0059] The points requiring protection are as described in claim 1. This solution can be applied to advanced packaging applications requiring high cleanliness and precision, such as fusion bonding and hybrid bonding, from chip to wafer / chip to chip.

[0060] Figure 7 shows the droplet position and thickness of the etching solution in a preferred embodiment of the present invention.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0064] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A chip-to-wafer advanced packaging method, characterized in that, Includes the following steps: A carrier wafer and a wafer to be diced are provided, wherein the wafer to be diced has multiple predefined chip units; The back side of the wafer to be cut is bonded to the front side of the carrier wafer through a temporary bonding process to form a bonded whole; the carrier wafer is used as the process carrier substrate, and the bonded whole is subjected to a plasma etching and cutting process to divide the wafer to be cut into individual chips. The chip after dicing undergoes a pre-bonding process; the carrier wafer and the chip are then debonded to separate the individual chips.

2. The chip-to-wafer advanced packaging method according to claim 1, characterized in that, The temporary bonding process, specifically fusion bonding, includes: forming a dielectric material layer on the front side of the carrier wafer and / or the back side of the wafer to be cut; planarizing the surface of the dielectric material layer; plasma-activating and hydrophilicating the surface of the dielectric material layer; and bonding the back side of the wafer to be cut to the front side of the carrier wafer through the dielectric material layer.

3. The chip-to-wafer advanced packaging method according to claim 2, characterized in that, The dielectric material layer includes at least one of SiO2, SiN, and SiCN.

4. The chip-to-wafer advanced packaging method according to claim 2, characterized in that, The debonding process includes: introducing an etching solution into the gap between adjacent chips, wherein the etching solution has a higher etching selectivity for the material constituting the dielectric material layer than for other material layers, so as to dissolve the dielectric material layer between the chip and the carrier wafer, thereby achieving debonding.

5. The chip-to-wafer advanced packaging method according to claim 4, characterized in that, The etching solution is a buffered oxide etching solution or a diluted hydrofluoric acid solution.

6. The chip-to-wafer advanced packaging method according to claim 4, characterized in that, The thickness of the etch solution layer is less than the thickness of the semiconductor material layer in the chip.

7. The chip-to-wafer advanced packaging method according to claim 1, characterized in that, The temporary bonding process involves using temporary bonding adhesive for bonding, and the debonding process includes using ultraviolet light irradiation or heat baking to make the temporary bonding adhesive lose its adhesiveness, thereby achieving debonding.

8. The chip-to-wafer advanced packaging method according to claim 7, characterized in that, The method further includes cleaning the carrier wafer after debonding to remove residual temporary bonding adhesive, and recoating the surface of the carrier wafer with adhesive for reuse.

9. The chip-to-wafer advanced packaging method according to any one of claims 1 to 8, characterized in that, When using the carrier wafer as the process carrier substrate for plasma etching and / or bonding pretreatment processes, process equipment and process formulations adapted to standard-sized wafers are used.

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