Data transmission method, electronic equipment and computer readable storage medium

Abstract

The invention relates to the field of terminals, in particular to a data transmission method, electronic equipment and a computer readable storage medium. In the data transmission method provided by the invention, a period of time is reserved as time for packaging and unified transmission of the instruction data before the display screen refreshes the image, so that the instruction data received in one frame can be issued in time, and the situations of frame loss and lagging caused by unsuccessful issuing of the instruction data are reduced.

Description

Data transmission methods, electronic devices and computer-readable storage media Technical Field

[0001] This application relates to the field of terminals, and more particularly to a data transmission method, electronic device, and computer-readable storage medium. Background Technology

[0002] On the system side (application processor side) of an electronic device, data can be exchanged with the display driver integrated circuit (DDIC) on the screen side through the display path of the Mobile Industry Processor Interface (MIPI). For example, the system side sends command data and image data to the DDIC through the MIPI display path, and the DDIC refreshes the image data onto the display panel according to the command data. The image data and command data share the display path in a time-division multiplexing manner. In some cases, if the command data in a frame fails to be sent successfully, this will cause frame drops and stuttering, thus affecting the display effect.

[0003] Summary of the Invention

[0004] This application provides a data transmission method, an electronic device, and a computer-readable storage medium, which can effectively reduce frame drops and stuttering, thereby improving the display effect.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a data transmission method is provided, applied to an electronic device, the electronic device including an application processor and a display screen, the method comprising:

[0007] At the first moment, the display screen generates a first TE signal;

[0008] In response to the first TE signal, the application processor transmits first image data to the display screen;

[0009] If one or more first instruction data are received between the first time and the second time, then between the second time and the third time, the application processor packages the one or more first instruction data to obtain a first instruction packet and sends the first instruction packet to the display screen, wherein the second time is after the first time and the third time is after the second time.

[0010] In this embodiment, before the screen refreshes the image, the AP reserves a period of time (between the second and third moments) for the packaging and unified transmission of instruction data. This enables the timely delivery of multiple instruction data received within a frame, thereby reducing frame drops and stuttering caused by unsuccessful delivery of instruction data.

[0011] In some cases, if only one first instruction is received between the first and second time points, the application processor does not need to package the received first instruction and send it to the display screen between the second and third time points.

[0012] In one implementation, the time period for packaging and issuing instructions (such as the time period between the second and third moments) can be preset and set based on empirical values ​​of the time required for the system to package and issue instructions. As shown in Figures 7 to 9, T2 is the time period for packaging and issuing instructions, and T2 can be set to 0.2ms.

[0013] As one implementation of the first aspect, the method further includes:

[0014] Between the first time point and the second time point, each time a first instruction data is received, the first instruction data is cached.

[0015] Optionally, between the second and third time points, the application processor counts the number of cached first instruction data; if the count is 1, the application processor sends the one first instruction data to the display screen; if the count is greater than 1, the application processor packages multiple first instruction data into a first instruction packet and sends the first instruction packet to the display screen.

[0016] In this embodiment, by caching instruction data, it is equivalent to receiving instruction data centrally between the first and second moments without sending it out, and then packaging and sending the instructions uniformly between the second and third moments. In this way, the instruction data received within a frame can be sent out in a timely manner, thereby reducing frame loss and stuttering caused by the failure to send instruction data successfully.

[0017] As one implementation of the first aspect, the method further includes:

[0018] At the fourth moment, the display screen generates a second TE signal, wherein the second TE signal is the next TE signal after the first TE signal;

[0019] In response to the second TE signal, the application processor transmits second image data to the display screen, wherein the second image data is the next frame of image data of the first image data.

[0020] As one implementation of the first aspect, the third time point is after the fourth time point.

[0021] As shown in Figures 8(b) and 9(b) and (c), T1 is the time period for receiving instruction data, and T2 is the time period for packaging and sending instructions. The moment when the TE0 signal is generated is the first moment, and the moment when the TE1 signal is generated is the fourth moment. The end time of T1 between the TE0 and TE1 signals is the second moment, the start time of T2 is the second moment, and the end time of T2 is the third moment, which is after the fourth moment.

[0022] In this embodiment, since the third time point is after the fourth time point, the time period for instruction packaging and distribution (the time period between the second and third time points) can be further delayed, thereby extending the instruction reception time period (the time period between the first and second time points) to a certain extent, which can effectively reduce frame drops and stuttering caused by failure to receive instruction data.

[0023] As one implementation of the first aspect, the third moment is the start moment of the hardware Vsync signal generated by the display screen after the fourth moment.

[0024] For example, as shown in Figures 8(b) and (c), the end time of T2 is recorded as the third time, and the time when the TE1 signal is generated is the fourth time. The third time is the start time of the hardware Vsync signal HW-Vsync1 after the fourth time.

[0025] In this embodiment, the instruction is packaged and sent before the start of the hardware Vsync signal. This reduces the failure of instruction data sending and enables the instructions to take effect in a timely manner, thereby effectively reducing frame drops and stuttering.

[0026] As one implementation of the first aspect, the method further includes:

[0027] The first instruction data will be received starting at the fifth moment;

[0028] At the second moment, stop receiving the first instruction data;

[0029] The fifth moment is the start time of the hardware Vsync signal generated by the display screen after the first moment.

[0030] For example, as shown in Figure 8(c), T1 is the time period for receiving instruction data, and the start time of T1 after the TE0 signal is the start time of the hardware Vsync signal HW-Vysnc0 after the first time.

[0031] In this embodiment, the time period for receiving instruction data coincides with the transmission time of image data, which is equivalent to allowing instruction data to be received during the transmission time, thus extending the time for receiving instruction data and effectively reducing frame drops and stuttering caused by failure to receive instruction data.

[0032] As one implementation of the first aspect, the third time point is prior to the sixth time point, which is the start time of the hardware Vsync signal generated by the display screen after the fourth time point.

[0033] For example, as shown in Figures 9(b) and (c), T2 is the time period for instruction packaging and issuance. The end time of T2 between TE0 and TE1 is the third time point. The time when the TE1 signal is generated is the fourth time point. The sixth time point is the start time of the hardware Vsync signal HW-Vysnc1 after the fourth time point. The third time point is after the sixth time point.

[0034] In this embodiment, advancing the third moment reduces the overlap between the time period for instruction packaging and issuance and the time period for transmitting the second image data, thereby reducing the mutual influence between instruction issuance and image data transmission.

[0035] As one implementation of the first aspect, the method further includes:

[0036] The first instruction data will be received starting at the seventh moment;

[0037] At the second moment, stop receiving the first instruction data;

[0038] Wherein, the first interval is the same as the second interval, the first interval is the time interval between the first time and the seventh time, the seventh time being after the first time; the second interval is the time interval between the fourth time and the third time.

[0039] For example, as shown in Figure 9(c), T1 is the time period for receiving instruction data, the moment when the TE0 signal is generated is the first moment, and the moment when the TE1 signal is generated is the fourth moment. The time interval (first interval) between the start time of T1 and the first moment is T. offset The time interval (second interval) between the cutoff time of T2 (the third time) and the fourth time is also T. offset .

[0040] In another implementation, the seventh time is the start time of the hardware Vsync signal after the first time (as shown in (c) of Figure 9, the start time of HW-Vsync0).

[0041] In this embodiment, the time period for receiving instruction data coincides with the transmission time of image data, which is equivalent to allowing instruction data to be received during the transmission time, thus extending the time for receiving instruction data and effectively reducing frame drops and stuttering caused by failure to receive instruction data.

[0042] As one implementation of the first aspect, the third time point and the fourth time point are the same time point.

[0043] For example, as shown in Figures 7(b) and (c), T2 is the time when the instruction data is packaged and sent, the time when the TE0 signal is generated is the first time, and the time when the TE1 signal is generated is the fourth time. The cutoff time of T2 between the TE0 and TE1 signals is the third time. The third time and the fourth time are the same time.

[0044] In this embodiment of the application, when the time period for packaging and sending frame instruction data does not coincide with the transmission time of the next frame image data, the mutual influence between the transmission processes of instruction and image data can be reduced.

[0045] As one implementation of the first aspect, the method further includes:

[0046] The first instruction data will be received starting at the sixth moment;

[0047] At the second moment, stop receiving the first instruction data;

[0048] The sixth time point is the start time of the hardware Vsync signal HW-Vysnc0 generated between the first time point and the fourth time point.

[0049] For example, as shown in Figure 7(c), the moment when the TE0 signal is generated is the first moment, and the starting moment of the hardware Vsync signal HW-Vysnc0 is the sixth moment.

[0050] As one implementation of the first aspect, the method further includes:

[0051] Between the first time point and the second time point, each time a first instruction data is received, the first instruction data is cached.

[0052] In this embodiment, by caching instruction data, it is equivalent to receiving instruction data centrally during the time period between the first and second time points without issuing it, and then issuing the instruction uniformly during the time period between the second and third time points. In this way, the instruction data received within a frame can be issued in a timely manner, thereby reducing frame loss and stuttering caused by the failure to issue instruction data.

[0053] As one implementation of the first aspect, the method further includes:

[0054] If no first instruction data is received between the first time and the second time, the preset flag is set to the first preset value.

[0055] In this embodiment of the application, by setting a flag bit, it is possible to clearly indicate whether instruction data has been received, which facilitates subsequent processing of the instruction.

[0056] As one implementation of the first aspect, between the second and third time points, the application processor packages the plurality of first instruction data to obtain a first instruction packet, including:

[0057] Between the second time point and the third time point, if the preset flag bit is not the first preset value, the application processor packages the plurality of first instruction data to obtain the first instruction packet;

[0058] Between the second time point and the third time point, if the preset flag is the first preset value, the application processor monitors the next TE signal.

[0059] In this embodiment, during the instruction packaging time period, a preset flag is used to determine whether instruction data has been received within the instruction receiving time period; if no instruction data is received, there is no need to package and send it, thereby reducing processing time.

[0060] Secondly, a data transmission method is provided, applied to an electronic device, the electronic device including an application processor and a display screen, the method comprising:

[0061] At the first moment, the display screen generates a first TE signal;

[0062] In response to the first TE signal, the application processor transmits first image data to the display screen;

[0063] If multiple first instruction data are received between the eighth and ninth times, the application processor packages the multiple first instruction data into a first instruction packet between the ninth and tenth times, and sends the first instruction packet to the display screen; wherein the ninth time is the end time of the application processor transmitting the first image data, and the tenth time is after the ninth time.

[0064] In this embodiment, before the screen refreshes the image, the AP reserves a period of time (between the second and third moments) for the packaging and unified transmission of instruction data. This enables the timely delivery of multiple instruction data received within a frame, thereby reducing frame drops and stuttering caused by unsuccessful delivery of instruction data.

[0065] As one implementation of the second aspect, the method further includes:

[0066] At the fourth moment, the display screen generates a second TE signal, wherein the second TE signal is the next TE signal after the first TE signal;

[0067] In response to the second TE signal, the application processor transmits second image data to the display screen, wherein the second image data is the next frame of image data of the first image data.

[0068] As one implementation of the second aspect, the tenth time is after the fourth time.

[0069] As shown in Figure 8(a) and Figure 9(a), T1 is the time period for receiving instruction data, and T2 is the time period for packaging and sending instructions. The moment when the TE0 signal is generated is the first moment, and the moment when the TE1 signal is generated is the fourth moment. The end time of T2 between the TE0 and TE1 signals is the tenth moment, which is after the fourth moment.

[0070] In this embodiment, since the tenth time is after the fourth time, the time period for instruction packaging and distribution (the time period between the ninth and tenth times) can be later, thereby extending the instruction reception time period (the time period between the eighth and ninth times) to a certain extent, which can effectively reduce frame loss and stuttering caused by failure to receive instruction data.

[0071] As one implementation of the second aspect, the tenth moment is the start moment of the hardware Vsync signal generated by the display screen after the fourth moment.

[0072] As shown in Figure 8(a), T1 is the time period for receiving instruction data, and T2 is the time period for packaging and sending instructions. The moment when the TE0 signal is generated is the first moment, and the moment when the TE1 signal is generated is the fourth moment. The end time of T2 between the first moment and the fourth moment is the tenth moment. The tenth moment is the start time of the hardware Vsync signal HW-Vsync1 after the fourth moment.

[0073] In this embodiment, since the tenth time is after the fourth time, the time period for instruction packaging and distribution (the time period between the ninth and tenth times) can be later, thereby extending the instruction reception time period (the time period between the eighth and ninth times) to a certain extent, which can effectively reduce frame loss and stuttering caused by failure to receive instruction data.

[0074] As one implementation of the second aspect, the tenth moment is prior to the sixth moment; wherein the sixth moment is the start moment of the hardware Vsync signal generated by the display screen after the fourth moment.

[0075] As shown in Figure 9(a), the time interval between the tenth time and the fourth time is T. offset The time interval is T. offset Less than the time interval between TE1 (fourth time point) and the hardware Vsync signal HW-Vsync1 after the fourth time point.

[0076] In this embodiment, advancing the third moment reduces the overlap between the time period for instruction packaging and issuance and the time period for transmitting the second image data, thereby reducing the mutual influence between instruction issuance and image data transmission.

[0077] As one implementation of the second aspect, the tenth moment and the fourth moment are the same moment.

[0078] As shown in Figure 7(a), the cutoff time of T2 is the rising edge of the TE signal.

[0079] As one implementation of the second aspect, the method further includes:

[0080] Between the eighth and ninth time points, each time a first instruction data is received, the first instruction data is cached.

[0081] In this embodiment, by caching instruction data, it is equivalent to receiving instruction data centrally during the time period between the first and second time points without issuing it, and then issuing the instruction uniformly during the time period between the second and third time points. In this way, the instruction data received within a frame can be issued in a timely manner, thereby reducing frame loss and stuttering caused by the failure to issue instruction data.

[0082] As one implementation of the second aspect, the method further includes:

[0083] If no first instruction data is received between the eighth and ninth time points, the preset flag is set to the first preset value.

[0084] In this embodiment of the application, by setting a flag bit, it is possible to clearly indicate whether instruction data has been received, which facilitates subsequent processing of the instruction.

[0085] As one implementation of the second aspect, between the ninth and tenth time points, the application processor packages the plurality of first instruction data to obtain a first instruction packet, including:

[0086] Between the ninth and tenth time points, if the preset flag is not the first preset value, the application processor packages the plurality of first instruction data to obtain the first instruction packet.

[0087] Between the ninth and tenth time points, if the preset flag is the first preset value, the application processor monitors the next TE signal.

[0088] In this embodiment, during the instruction packaging time period, a preset flag is used to determine whether instruction data has been received within the instruction receiving time period; if no instruction data is received, there is no need to package and send it, thereby reducing processing time.

[0089] Thirdly, an electronic device is provided, including a processor for running a computer program stored in a memory to implement the method of any one of the first aspects of this application or the method of any one of the second aspects of this application.

[0090] Fourthly, a chip system is provided, including a processor coupled to a memory, wherein the processor executes a computer program stored in the memory to implement the method of any one of the first aspects of this application or the method of any one of the second aspects of this application.

[0091] Fifthly, a computer-readable storage medium is provided, which stores a computer program that, when executed by one or more processors, implements the method of any one of the first aspects of this application or the method of any one of the second aspects of this application.

[0092] Sixthly, embodiments of this application provide a computer program product that, when run on a device, causes the device to execute any of the methods in the first aspect or implement any of the methods in the second aspect of this application.

[0093] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0094] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0095] Figure 2 is a structural block diagram of the display system of the electronic device 100 according to an embodiment of this application;

[0096] Figure 3 is a schematic diagram of the image transmission and display timing on the system side provided in an embodiment of this application;

[0097] Figure 4 is a timing diagram of instruction data issuance provided in an embodiment of this application;

[0098] Figure 5 is a timing diagram of instruction data issuance provided in another embodiment of this application;

[0099] Figure 6 is a timing diagram of instruction data issuance provided in another embodiment of this application;

[0100] Figure 7 is a timing diagram of instruction data issuance provided in another embodiment of this application;

[0101] Figure 8 is a timing diagram of instruction data issuance provided in another embodiment of this application;

[0102] Figure 9 is a timing diagram of instruction data issuance provided in another embodiment of this application;

[0103] Figure 10 is a schematic diagram of the information transmission process provided in an embodiment of this application;

[0104] Figure 11 is a schematic diagram of the information transmission process provided in another embodiment of this application. Detailed Implementation

[0105] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limiting purposes, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details.

[0106] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0107] It should also be understood that in the embodiments of this application, "one or more" refers to one, two, or more; "and / or" describes the relationship between the associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0108] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," "fourth," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0109] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0110] The data transmission method provided in this application can be applied to electronic devices with screens and camera functions. Electronic devices include terminal devices, which can also be called terminals, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. Terminal devices can be mobile phones, smart TVs, wearable devices, tablets, smart screens, computers with wireless transceiver capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and so on. The embodiments of this application do not limit the specific technologies or device forms used in the electronic devices.

[0111] Referring to Figure 1, it is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a touch sensor 180K, an ambient light sensor 180L, etc.

[0112] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0113] Processor 110 may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. For example, processor 110 is used to execute the data transmission method in the embodiments of this application.

[0114] The controller can be the nerve center and command center of the electronic device 100. The controller can generate operation control signals according to the instruction opcode and timing signals to complete the control of fetching and executing instructions.

[0115] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0116] External memory 120 generally refers to external storage. In the embodiments of this application, external storage refers to storage other than the memory of electronic devices and the cache of processors. This storage is generally non-volatile memory.

[0117] Internal memory 121, also known as "RAM," can be used to store executable program code for a computer, including instructions. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a given function (such as sound playback, image playback, etc.).

[0118] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a minimized display, a microLED, a micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1. In some embodiments, electronic device 100 displays a user interface through the displays 194.

[0119] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0120] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0121] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0122] Electronic device 100 also includes various sensors that can convert different physical signals into electrical signals. For example, pressure sensor 180A is used to sense pressure signals and convert them into electrical signals. Gyroscope sensor 180B can be used to determine the motion posture of electronic device 100. Barometric pressure sensor 180C is used to measure air pressure. Magnetic sensor 180D includes a Hall sensor. Accelerometer sensor 180E can detect the magnitude of acceleration of electronic device 100 in various directions (generally three axes). Distance sensor 180F is used to measure distance. Electronic device 100 can measure distance using infrared or laser. Proximity sensor 180G may include, for example, a light-emitting diode (LED) and a photodetector, such as a photodiode. Ambient light sensor 180L is used to sense ambient light brightness. Electronic device 100 can adaptively adjust the brightness of display screen 194 according to the sensed ambient light brightness. Fingerprint sensor 180H is used to collect fingerprints. Electronic device 100 can use the collected fingerprint characteristics to achieve fingerprint unlocking, access application lock, fingerprint photography, fingerprint answering of calls, etc. Temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 uses the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. The bone conduction sensor 180M can acquire vibration signals.

[0123] Touch sensor 180K, also known as a "touch panel," can be located on display screen 194. The touch sensor 180K and display screen 194 together form a touchscreen, also known as a "touch screen." Touch sensor 180K detects touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 194. In other embodiments, touch sensor 180K may also be located on the surface of electronic device 100, in a different position than display screen 194.

[0124] For example, in this embodiment of the application, the touch sensor 180K can detect the user's click operation on the application icon, and pass the detected click operation to the application processor to determine that the click operation is used to start or run the application, and then execute the application's running operation.

[0125] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0126] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0127] The above is a detailed description of the embodiments of this application using electronic device 100 as an example. It should be understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on electronic device 100. Electronic device 100 may have more or fewer components than shown in the figures, may combine two or more components, or may have different component configurations. The various components shown in the figures can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0128] In addition, an operating system runs on top of the aforementioned components. Examples include iOS, Android (an open-source operating system), and Windows. Applications can be installed and run on this operating system.

[0129] Figure 2 is a structural block diagram of the display system of an electronic device 100 according to an embodiment of this application. By way of example and not limitation, as shown in Figure 2, the display system of the electronic device 100 may include an application processor (AP) and a display screen, wherein the AP runs an operating system. The display screen includes a display driver integrated circuit (DDIC) and a display panel.

[0130] The operating system can also be referred to as a System on Chip (SOC). The operating system of the electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment takes the layered architecture Android system as an example to illustrate the software structure of the electronic device 100.

[0131] A layered architecture divides software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: Application Layer, Application Framework Layer, Hardware Abstraction Layer (HAL), and Kernel Layer.

[0132] The application layer can include a series of application packages. These application packages can be simply referred to as applications. As shown in Figure 2, the application layer can include camera applications, gallery applications, navigation applications, e-book applications, video applications, and game applications, etc.

[0133] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0134] As shown in Figure 2, the application framework layer may include the SurfaceFlinger module, which is used to set the refresh rate and render and composite the layers drawn by the application.

[0135] The hardware abstraction layer can include a hardware composer (HWC). The HWC is used to set refresh rates and perform image layer compositing. The HWC works in conjunction with SurfaceFlinger and the display screen to complete image display.

[0136] The kernel layer is the layer between hardware and software. At a minimum, the kernel layer contains a display driver, which drives the display screen in the hardware layer.

[0137] In some application scenarios, after the SurfaceFlinger module sets the refresh rate, it sends the latest refresh rate to the display driver in the kernel layer via HWC. Then, the display driver sends it to the Display Driver Integrated Circuit (DDIC) so that the DDIC controls the display panel to refresh and display the image at the latest refresh rate.

[0138] In other application scenarios, as shown in Figure 2, the display driver may include a first display engine driver and a second display engine driver. The first display engine driver may be the native Android system display engine driver (DE Driver), while the second display engine driver may be a self-developed display engine driver. In this embodiment, the first display engine driver interacts with the HWC and the display driver integrated circuit (DDIC) in the hardware layer to drive the DDIC to control the display panel to complete the display processing and implementation. The second display engine driver is used to execute customized screen processing logic.

[0139] For example, as shown in Figure 2, the first display engine driver may include a window calculation module and an instruction control module. The window calculation module is used to obtain or calculate the window time T1 described in the embodiments of Figures 7 to 11. The instruction control module is used for timing the window time T1 and the reserved time T2, caching instruction data, and setting flag bits.

[0140] The second display engine driver may include an instruction packaging and distribution module for packaging and distributing instruction data.

[0141] In this embodiment, the instruction data refers to display-related instructions sent by the system to the DDIC. For example, the instruction data may include backlight instructions for adjusting screen brightness, frame-switching instructions for adjusting frame rate, ROI instructions for controlling the display screen to refresh the Region of Interest (ROI), frequency-hopping instructions (such as TEI instructions) for hopping TE signals, and TE mask instructions (such as TEMASK instructions) for masking TE signals.

[0142] In some application scenarios, HWC sends frequency hopping instructions and TE mask instructions to the second display engine driver. The second display engine driver then packages the frequency hopping instructions and TE mask instructions and sends them to the first display engine driver, which in turn sends the instruction package to DDIC.

[0143] In other application scenarios, HWC sends backlight instructions, frame cutting instructions, and ROI instructions to the first display engine driver. The first display engine driver then sends the backlight instructions, frame cutting instructions, and ROI instructions to the second display engine driver. The second display engine driver then packages the backlight instructions, frame cutting instructions, and ROI instructions and sends them to the first display engine driver, which then sends the instruction package to DDIC.

[0144] The DDIC is one of the main control components of a display screen. The DDIC sends drive signals and image data to the display panel via electrical signals, thereby controlling the screen's brightness and color, enabling image information to be displayed on the display panel.

[0145] The DDIC includes graphics random access memory (GRAM), which is used to store image data sent from the system side.

[0146] The system side and DDIC can exchange data via the Mobile Industry Processor Interface (MIPI). For example, the display driver on the system side stores image data in the DDIC's GRAM via MIPI. When the display generates a hardware Vsync signal, the DDIC refreshes the image data in the GRAM onto the display panel.

[0147] To facilitate a clear description of the technical solutions in the embodiments of this application, some terms and related technologies involved in the embodiments of this application are introduced below.

[0148] (1) Hardware Vertical Synchronization (Vsync) Signal

[0149] The hardware Vsync signal is a periodic signal generated by the display screen, serving as the screen's reference signal. Its period depends on the display screen's hardware performance parameters. For example, at a refresh rate of 60Hz, the hardware Vsync signal period is approximately 16.7ms; at a refresh rate of 90Hz, the period is approximately 11.1ms; and at a refresh rate of 120Hz, the period is approximately 8.3ms.

[0150] For example, referring to the display system architecture shown in Figure 2, the display system of an electronic device may include a system side (AP side) and a screen side (DDIC and display panel). The process of refreshing the image on the display screen includes:

[0151] On the system side, the application layer draws image frames based on the display parameters of the screen to be displayed (such as the width, height, position, and color of the interface to be displayed). The Surfaceflinger module in the application framework layer renders and merges the image frames drawn by the application to obtain layers, and sends the layers to the HWC in the hardware abstraction layer. The HWC performs layer compositing based on the received layers to obtain image data, and sends the image data to the hardware frame buffer of the display driver in the kernel layer. When the TE signal generated by the display screen is received, the display driver in the kernel layer sends the latest frame image data in the hardware frame buffer to the GRAM of the screen DDIC.

[0152] On the screen side, when the display generates a hardware Vsync signal, the DDIC is responsible for presenting the image data in the current GRAM to the display panel.

[0153] (2) Refresh rate

[0154] Refresh rate refers to the number of times a display screen shows images per second. The unit is Hertz (Hz). For example, a refresh rate of 60Hz means the screen displays 60 frames per second. A refresh rate of 120Hz means the screen displays 120 frames per second.

[0155] (3) Screen tearing

[0156] Screen tearing refers to the tearing effect that occurs when image data on a screen comes from two different frames.

[0157] (4) Tearing effect (TE) signal

[0158] The TE signal is a signal output by the display driver chip (DDIC) to the system side to prevent screen tearing during image refresh. For example, the system side sends the next frame of image data to the DDIC after detecting the rising edge of the TE signal or when the TE signal is high.

[0159] The period of the TE signal is based on the hardware Vsync signal, and the timing relationship between the hardware Vsync signal and the TE signal can be adjusted. However, to avoid screen flickering, the hardware Vsync signal is usually adjusted to follow the TE signal, that is, the display is sent for a period of time before refreshing.

[0160] It should be noted that although the TE signal and the hardware Vsync signal have a timing relationship, the system side calculates the period based on the time interval between two adjacent TE signals, while the screen side calculates the period based on the time interval between two adjacent hardware Vsync signals. In this embodiment, when described from the system side perspective, the time when the system side receives the rising edge of the TE signal is taken as the start time of the period, as shown in Figures 3 to 9.

[0161] For example, referring to Figure 3, is a schematic diagram of the image display timing on the system side provided in an embodiment of this application. As shown in Figure 3(a), when the DDIC generates a TE0 signal, the system side, upon hearing the rising edge of a TE0 signal, sequentially draws and renders image frame 1 (the rectangle labeled 1 in Figure 3). When the DDIC generates a TE1 signal again, the system side, upon hearing the rising edge of a TE1 signal, synthesizes image frame 1 and sequentially draws and renders image frame 2 (the rectangle labeled 2 in Figure 3). When the DDIC generates a TE2 signal again, the system side, upon hearing the rising edge of a TE2 signal, synthesizes image frame 2, sends the image data of image frame 1 to the GRAM of the DDIC, and sequentially draws and renders image frame 3 (the rectangle labeled 3 in Figure 3). And so on.

[0162] Figure 3(b) shows the timing diagram of the hardware Vsync signal cycle. The starting point shown in Figure 3(b) is the start of a hardware Vsync cycle. The short high-level period after the starting point is called the Vertical Back Porch (VBP). After the VBP, the Vsync signal waveform experiences a falling edge, followed by a low level (Vactive). The rising edge after the low level is the TE signal. Immediately following the TE signal is a short high-level period called the Vertical Front Porch (VFP). The VFP, plus the compensation time (i.e., the VFP extension region), constitutes a complete frame of the hardware Vsync signal. The length of the VFP extension region varies for different refresh rates. As shown in Figure 3(b), the length of the VFP extension region differs between a 120Hz refresh rate and a 90Hz refresh rate. The end of the compensation time marks the end of a hardware Vsync cycle.

[0163] In other words, as shown in Figure 3(a), a complete hardware Vsync cycle starts from the starting point shown in Figure 3(a), passes through the vertical trailing edge VBP, low level Vactive, TE signal, vertical leading edge VFP, VFP extension region and then reaches the ending point.

[0164] It should be noted that for a hardware Vsync cycle, instruction data can only take effect in that hardware Vsync cycle if it is sent to DDIC before VBP in that hardware Vsync cycle.

[0165] The display path between the system side and the screen side DDIC (as shown in Figure 2) can transmit not only image data but also command data. Image data and command data are time-division multiplexed within the display path. As shown in Figure 4, the system side sends display command data within one frame, during the time period between detecting the rising edge of a TE0 signal and detecting the rising edge of the next TE1 signal. When the rising edge of the TE1 signal is detected, the system-side display driver (Display) sends image frame 1 to the DDIC (the rectangle labeled 1 in Figure 4). Similarly, the system side sends command data during the time period between detecting the rising edge of the TE1 signal and detecting the rising edge of the TE2 signal. When the rising edge of the TE2 signal is detected, the system-side display driver (Display) sends image frame 2 to the DDIC (the rectangle labeled 2 in Figure 4), and so on.

[0166] As shown in Figure 4, the delivery time of command data and image data is sequential. Since the screen refreshes based on the hardware Vsync signal, the command data needs to be delivered before the next hardware Vsync signal (HW-Vsync as shown in Figure 4) to ensure that the screen refreshes the image data according to the command data in the next frame. If the command data is not successfully delivered before the next hardware Vsync signal, it may cause abnormal image data display in the next frame. For example, in the application scenario of partial refresh, the command data is the Region of Interest (ROI) command. The ROI command can include parameters for partial refresh, such as screen coordinates. Suppose that the ROI command of the current frame indicates to refresh image data in the range of screen coordinates 0-100, and the ROI command of the previous frame indicates to refresh image data in the range of screen coordinates 100-200. If the ROI instruction for the current frame is successfully issued, the image data in the next frame will be refreshed according to the ROI instruction of the current frame, that is, the image data within the screen coordinate range of 0-100 will be refreshed. If the ROI instruction for the current frame is not successfully issued, the image data in the next frame will still be refreshed according to the ROI instruction of the previous frame, that is, the image data within the screen coordinate range of 100-200 will be refreshed. This will affect the display effect.

[0167] The delivery of instruction data includes two methods: serial and parallel delivery.

[0168] In the serial transmission method, a blocking mechanism is used to ensure the timing of instruction data and image data transmission. In the blocking mechanism, if instruction data is not successfully transmitted within a certain frame, the transmission of the next frame of image data is blocked.

[0169] One scenario where instruction data fails to be sent is that instruction data occupies the display path for an extended period within a certain frame. For example, see Figure 5, a timing diagram illustrating instruction data sending according to an embodiment of this application. As an example, not a limitation, as shown in Figure 5, if the instruction data for image frame 1, sent after the rising edge of the TE0 signal is detected, occupies the display path for an extended period, and the instruction data for image frame 1 has not yet been sent when the display generates the hardware Vsync signal HW-Vsync1, then the display of image frame 1 is blocked. When the rising edge of the TE2 signal is detected, the instruction data for image frame 1 has been successfully sent, and the system sends image frame 1 to the DDIC. In other words, within a frame after the rising edge of the TE1 signal is detected, the screen still refreshes according to image frame 0; within a frame after the rising edge of the TE2 signal is detected, the screen refreshes according to image frame 1. Image frame 1 is "lost" within the frame between the TE1 and TE2 signals, resulting in display stuttering. As can be seen from the example in Figure 5, if the instruction data in a certain frame occupies the display path for a long time, it will block the sending of the next frame of image data, making it impossible for the screen to obtain the latest image data, thus causing frame drops and stuttering.

[0170] Another scenario where instruction data fails to be sent is when multiple instructions are sent. Due to limited MIPI resources, multiple instructions need to compete for MIPI resources. If an instruction is sent late or fails to compete for MIPI resources due to conflicts with other instructions, it may fail to be sent within a certain frame. For example, see Figure 6, which is a timing diagram of instruction data sending according to another embodiment of this application. As an example and not a limitation, as shown in Figure 6, backlight instructions, frame cutting instructions, and ROI instructions are successfully sent within the time period after the rising edge of the TE0 signal and before the rising edge of the TE1 signal. When the rising edge of the TE1 signal is detected, the system sends image frame 1 to the DDIC. Backlight instructions and frame cutting instructions are successfully sent within the time period after the rising edge of the TE1 signal and before the rising edge of the TE2 signal. However, due to the late sending of the ROI instruction or failure to compete for MIPI resources, the ROI instruction fails to be sent. When the rising edge of the TE2 signal is detected, image frame 2 is blocked from being displayed. The ROI command is successfully issued within the time period between the rising edge of the TE2 signal and the rising edge of the TE3 signal. When the rising edge of the TE3 signal is detected, the system sends image frame 2 to the DDIC. As shown in the example in Figure 6, in the case of multiple command issuance, if the command data in a certain frame fails to be issued successfully, it will block the display of the next frame of image data, resulting in frame drops and stuttering.

[0171] In parallel data delivery, while the failure to send a command data packet does not block the display of image data, the inability to send frame command data may still affect the display quality of the next frame or system power consumption. For example, if the backlight command fails to send a frame, the screen brightness in the next frame may not match the image, resulting in a poor display quality. Furthermore, if the frequency hopping command or TE mask command fails to send, it will affect the adaptive refresh rate adjustment, thus impacting system power consumption.

[0172] In view of this, this application provides a data transmission method in which the AP side reserves a period of time for packaging and unified transmission of instruction data before refreshing the image on the screen side. This enables the timely transmission of instruction data received within a frame, thereby reducing frame loss and stuttering caused by unsuccessful transmission of instruction data.

[0173] The technical solutions provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0174] In this embodiment, the time it takes for the system to send image data to the DDIC within each frame (i.e., the time it takes to send and display the data) is recorded as the transfer time, and the time within each frame excluding the transfer time is recorded as the idle time. The time interval between the rising edges of two adjacent TE signals detected by the system is recorded as one frame.

[0175] As one embodiment of setting a reservation time, a preset time is reserved before the rising edge of the TE signal is detected. In this embodiment, within each frame, the system receives instruction data for a period of time before the reservation time, and then packages the received instruction data and sends it to the DDIC within the reservation time.

[0176] For example, referring to Figure 7, is a timing diagram of the instruction data delivery provided in an embodiment of this application. As shown in Figure 7, T2 is the reserved time before the rising edge of the TE signal, that is, the cutoff time of T2 is at or before the time corresponding to the rising edge of the TE signal. When the rising edge of the TE0 signal is detected, the system side sends the image data of image frame 0 (the rectangle labeled 0 in Figure 7) to the DDIC. Correspondingly, the system side receives instruction data within the time period T1 of the frame corresponding to TE0 (the time interval between the rising edge of TE0 and the rising edge of TE1), and packages and sends the instruction data received in the frame corresponding to TE0 to the DDIC within the time period T2 of the frame corresponding to TE0. When the rising edge of the TE1 signal is detected, the system side sends the image data of image frame 1 (the rectangle labeled 1 in Figure 7) to the DDIC. Correspondingly, the system receives instruction data within time period T1 of the frame corresponding to TE1 (the time interval between the rising edge of TE1 and the rising edge of TE2). Within time period T2 of the frame corresponding to TE1, it packages the instruction data received in the frame corresponding to TE1 and sends it to DDIC. And so on.

[0177] As another embodiment of setting a reservation time, a preset time is reserved before the hardware Vsync signal. In this embodiment, within each transmission cycle, the system side receives instruction data for a period of time before the reserved time, and then packages the received instruction data and sends it to DDIC uniformly within the reserved time. Here, a transmission cycle is the sum of the time of one frame and a preset time threshold.

[0178] For example, referring to Figure 8, is a timing diagram of instruction data delivery provided in another embodiment of this application. As shown in Figure 8, T2 is the reserved time before the hardware Vsync signal, that is, the end time of T2 is the time corresponding to the hardware Vsync signal. The time interval between the time when the rising edge of the TE0 signal is detected and the time when the HW-Vsync1 signal is detected is one transmission cycle, the time interval between the time when the rising edge of the TE1 signal is detected and the time when the HW-Vsync2 signal is detected is one transmission cycle, and the time interval between the time when the rising edge of the TE2 signal is detected and the time when the HW-Vsync3 signal is detected is one transmission cycle. When the rising edge of the TE0 signal is detected, the system side sends the image data of image frame 0 (the rectangle labeled 0 in Figure 8) to the DDIC. Correspondingly, the system side receives instruction data during the time period T1 between the rising edge of TE0 and HW-Vsync1, and packages and sends the instruction data received during the time period T1 between the rising edge of TE0 and HW-Vsync1 to the DDIC during the time period T2 between the rising edge of TE0 and HW-Vsync1. When the rising edge of the TE1 signal is detected, the system sends the image data of image frame 1 (the rectangle labeled 1 in Figure 8) to the DDIC. Correspondingly, the system receives command data during the time period T1 between the rising edge of TE1 and HW-Vsync2, and during the time period T2 between the rising edge of TE1 and HW-Vsync2, packages the command data received during the time period T1 between TE1 and HW-Vsync2 and sends it to the DDIC. This process continues in sequence.

[0179] T in Figure 8 offset This is a preset time threshold. As shown in Figure 8, the time threshold T... offset This is equal to the second time interval, which is the time interval between the time when the rising edge of the TE signal is detected and the time when the hardware Vsync signal is detected within a frame. As shown in Figure 8, the second time interval is the time interval between the time when the rising edge of TE0 is detected and the time when HW-Vsync0 is detected, and also the time interval between the time when the rising edge of TE1 is detected and the time when HW-Vsync1 is detected.

[0180] As can be seen from Figure 8, the time threshold T offset If the second time interval is equal, it may result in T2 not ending when the next hardware Vsync signal is detected. That is, the instruction data is not packaged and transmitted within one transmission cycle, and the instruction data delivery fails. This will block the next frame of image data from being sent for display, resulting in frame drops and stuttering.

[0181] In addition, as can be seen from Figure 8, since the deadline of the reserved time T2 is at the time corresponding to the hardware Vsync signal, the reserved time T2 overlaps with the display time. In other words, there may be a situation where the instruction issuance time and the display time simultaneously compete for MIPI resources, which may affect the display of the next frame of image data.

[0182] To avoid the above situation, the time threshold can be adjusted to reduce frame drops and stuttering, as well as the impact of command issuance on image data transmission and display. Optionally, T can be set. offset Less than the second time interval. As shown in Figure 9, the cutoff time of T2 is before the moment the hardware Vsync signal is detected. In some methods, by setting T... offset The interval between the cutoff time of T2 and the hardware Vsync signal can be set to 0.05 to 0.1 ms to reduce frame drops and stuttering, as well as to reduce the impact of command issuance on image data display.

[0183] As shown in Figures 7 to 9, there is a window time T1 before the reserved time T2, during which the system receives instruction data. The window time T1 can be set in several ways.

[0184] The first setting method is shown in Figure 7(a), where T1 = T idle -T2,T idle =T m -T transfer Where T2 is the reserved time, which can be preset. transfer The transmission time, T, can be calculated based on the refresh rate and the MIPI transmission rate. idle This is for free time. (T) m The time interval corresponding to one frame is the time interval between the rising edges of two adjacent TE signals, which is determined according to the refresh rate.

[0185] For example, T2 can be set to 0.2ms. When the refresh rate is 120Hz, T... m Approximately 8.3ms, T transfer If T1 is approximately 7ms and T2 is 0.2ms, then T1 is approximately 1.1ms. When the refresh rate is 60Hz, T... m It takes approximately 16.7ms.

[0186] In one case, T transfer If T1 is approximately 7ms and T2 is 0.2ms, then T1 is approximately 9.5ms.

[0187] In another case, T transfer If T1 is approximately 14ms and T2 is 0.2ms, then T1 is approximately 2.5ms. When the refresh rate is 90Hz, T...m Approximately 11.1 ms, T transfer If T1 is approximately 9ms and T2 is 0.2ms, then T1 is approximately 1.9ms.

[0188] As can be seen from the above example, when the reserved time is determined, the transmission time and idle time are different for different refresh rates, so the corresponding time T1 for receiving instructions is also different.

[0189] This configuration separates the transmission time, the instruction data reception time, and the instruction packaging time, ensuring they do not interfere with each other and improving the accuracy of information transmission.

[0190] The second setting is shown in Figure 8(a) and Figure 9(a), where T1 = T idle -T2+T offset T idle =T m -T transfer Among them, T offset This is a preset time threshold.

[0191] Compared to the first setting method, the second setting method, due to the addition of a time threshold, allows the reserved time T2 to be further back, which can extend the window time T1 to a certain extent. This is equivalent to extending the time for receiving instruction data, which can effectively reduce frame drops and stuttering caused by not receiving instruction data.

[0192] The third setting is shown in Figure 8(b) and Figure 9(b), where T1 = T m +T offset -T2.

[0193] Compared to the second setting, the third setting allows receiving instruction data during the transmission time, further extending the window time T1, which can effectively reduce frame drops and stuttering caused by not receiving instruction data.

[0194] The fourth setting is shown in Figure 7(b), Figure 8(c), and Figure 9(c), where T1 = T m -T2.

[0195] Compared to the third setting method, the fourth setting method takes into account the problem of the window time T1 and the reserved time T2 coinciding. This is equivalent to separating the time period for receiving instruction data and the time period for packaging instructions, so that the two time periods do not overlap. This can effectively reduce the conflict between the system-side receiving task and packaging task, which is conducive to improving the reliability of instruction data transmission, thereby reducing frame loss and stuttering.

[0196] The fifth setting is shown in Figure 7(c), where T1 = Tm -T2-T n Among them, T n The time interval between the rising edge of the TE signal and the hardware Vsync signal being detected within a frame.

[0197] Compared to the third setting method, the fourth setting method takes into account the problem of the window time T1 and the reserved time T2 coinciding. This is equivalent to separating the time period for receiving instruction data and the time period for packaging instructions, so that the two time periods do not overlap. This can effectively reduce the conflict between the system-side receiving task and packaging task, which is conducive to improving the reliability of instruction data transmission, thereby reducing frame loss and stuttering.

[0198] Understandably, the first and second settings separate the transmission time and the window time T1, ensuring they do not overlap and interfere with each other, thus improving the accuracy of information transmission. The third, fourth, and fifth settings allow the reception of command data within the transmission time, further extending the window time T1 and effectively reducing frame drops and stuttering caused by missing command data.

[0199] Based on the different calculation methods of the window time T1 mentioned above, different information transmission processes can be designed.

[0200] For the first and second settings of window time T1, which separate the transmission time from the window time T1, the corresponding information transmission flow is shown in Figure 10. As an example and not a limitation, as shown in Figure 10, the information transmission flow on the system side may include the following steps:

[0201] S1001, system-side display startup.

[0202] When the DDIC generates a TE signal, the system side detects the rising edge of the TE signal and initiates display sending, that is, sends the image data of the latest image frame to the DDIC.

[0203] S1002, the system side calculates the idle time.

[0204] As mentioned above, the system side can determine the refresh rate and formula T based on the current refresh rate. idle =T m -T transfer Calculate idle time.

[0205] S1003, system-side calculation window time T1.

[0206] It is understandable that, for the first setting of window time T1, the method used in S1002-S1003 to calculate window time T1 is the formula T1 = Tidle -T2. For the second setting method of window time T1, S802-S803 calculates window time T1 using the formula T1=T idle -T2+T offset .

[0207] As shown in steps S1002-S1003, in one implementation, the system side can calculate the window time T1 based on the current refresh rate within each frame.

[0208] In another implementation, the system can pre-calculate and store the window time T1 corresponding to each of the various refresh rates supported by the electronic device. Then, after the display is initiated in S1001, the system retrieves the window time T1 corresponding to the current refresh rate from the stored window times T1. Compared with the previous implementation, since T1 is pre-calculated in this implementation, the system can obtain the time of T1 within each frame. This not only reduces the computational burden on the system but also effectively reduces the possibility of not obtaining T1 by the end of the transmission time due to the time spent calculating T1, thereby improving the reliability of information transmission.

[0209] S1004, display finished, timer starts.

[0210] In one implementation, the system can set a timer to T1 and start the timer when the display ends. Correspondingly, when the timer reaches 0, it indicates that T1 has ended.

[0211] In another implementation, the system can set the timer to 0 and start the timer when the display ends. Correspondingly, when the timer reaches T1, it indicates the end of T1.

[0212] Among them, the end of display refers to T transfer Finish.

[0213] S1005, the system side determines whether T1 has ended.

[0214] If T1 has not ended, execute S1006; if T1 has ended, execute S1009.

[0215] S1006, T1 not yet finished, the system side determines whether instruction data has been received.

[0216] S1007, No instruction data received, set preset flag.

[0217] In one implementation, the preset flag can be set to a first preset value by default. When instruction data is received, the preset flag is set to empty or a second preset value.

[0218] In another implementation, the preset flag can be set to empty or the second preset value by default. If no instruction data is received by the end of the display process, the preset flag is set to the first preset value.

[0219] S1008, received instruction data, buffer the received instruction data.

[0220] S1009, T1 ends, check if the flag bit is set.

[0221] If the preset flag is set, the next frame will continue to be displayed. Specifically, when the rising edge of the next TE signal is detected, S1001 is executed.

[0222] In step S1009, it can be determined whether the preset flag bit is the first preset value. As described in step S1007, if the preset flag bit is the first preset value by default, it means that the preset flag bit is not set; if the preset flag bit is not the first preset value, it means that the preset flag bit is set. If the preset flag bit is empty or the second preset value by default, if the preset flag bit is the first preset value, it means that the preset flag bit is set; if the preset flag bit is not the first preset value, it means that the preset flag bit is not set.

[0223] S1010 If the preset flag is not set, the system side packages the cached instruction data to obtain the instruction packet and transmits the instruction packet to DDIC.

[0224] In some implementations, the calculation steps S1002-S1003 can be executed by the window calculation module driven by the first display engine in Figure 2. S1004-S1009 can be executed by the instruction control module driven by the first display engine in Figure 2. The window calculation module driven by the first display engine sends the calculated window time T1 to the instruction control module, so that the instruction control module executes S1004-S1009 according to the window time T1. S1010 can be executed by the instruction packaging and distribution module driven by the second display engine in Figure 2.

[0225] In some implementations, if the window time T1 is pre-calculated, the pre-calculated window time T1 corresponding to each refresh rate can be stored in the second display engine driver. When S1001 is sent to start the display, the first display engine driver obtains the pre-calculated window time T1 matching the current refresh rate from the second display engine driver and sends it to the instruction control module so that the instruction control module executes S1004-S1009 at window time T1.

[0226] Optionally, the pre-set reservation time T2 can be stored in the first display engine driver or the second display engine driver.

[0227] For example, in the above implementation where T1 is not pre-calculated, the reserved time T2 can be stored in the window calculation module of the first display engine driver. The window calculation module of the first display engine driver calculates T1 based on the stored T2, and then sends the calculated T1 to the instruction control module of the first display engine driver.

[0228] For example, in the above implementation of pre-calculating T1, the reserved time T2 can be stored in the second display engine driver. The window calculation module of the first display engine driver obtains T2 from the second display engine driver, calculates T1 corresponding to each of the multiple refresh rates supported by the electronic device based on T2, and stores the calculated T1 in the second display engine driver.

[0229] For the third, fourth, and fifth settings of window time T1, i.e., when the transmission time and window time T1 coincide, the corresponding information transmission process is shown in Figure 11. As an example, and not a limitation, as shown in Figure 11, the information transmission process on the system side may include the following steps:

[0230] S1101, system-side calculation window time T1.

[0231] It is understandable that for the third way of setting the window time T1, the formula for the window time T1 is T1 = T m +T offset -T2. For the fourth setting of window time T1, the formula for window time T1 is T1 = T... m -T2. For the fifth setting of window time T1, the formula for window time T1 is T1 = T m -T2-T n .

[0232] In one implementation, the system can calculate T based on the current refresh rate within each frame. m Then according to T m Calculate the window time T1.

[0233] In another implementation, the system can pre-calculate and store the window time T1 corresponding to each of the various refresh rates supported by the electronic device. Then, after the display is initiated in S1001, the system retrieves the window time T1 corresponding to the current refresh rate from the stored window times T1. Compared with the previous implementation, since T1 is pre-calculated in this implementation, the system can obtain the time of T1 within each frame. This not only reduces the computational burden on the system but also effectively reduces the possibility of not obtaining T1 by the end of the transmission time due to the time spent calculating T1, thereby improving the reliability of information transmission.

[0234] S1102, the system side calculates the timing.

[0235] In this embodiment of the application, the timing time is used to indicate the moment when receiving instruction data begins.

[0236] As shown in Figure 7(b), Figure 8(b), and Figure 9(b), after the display is started, instruction data is received. In this case, the timing point is the moment when the rising edge of TE is detected.

[0237] As shown in Figure 8(c) and Figure 9(c), after the display is started, the interval T offset When command data reception begins, the timing is the moment the rising edge of the TE signal is detected + T. offset .

[0238] In one implementation, S1101-S1102 can be executed after the display sending starts. Because computation is time-consuming, in this method, the computation task may occupy window time T1, i.e., the time required to receive instruction data. However, in the embodiment of this application, S1101-S1102 are executed before the display sending starts, so that the computation task does not occupy window time T1, which is beneficial for receiving instruction data.

[0239] S1103, system-side display startup.

[0240] When the DDIC generates a TE signal, the system side detects the rising edge of the TE signal and initiates display sending, that is, sends the image data of the latest image frame to the DDIC.

[0241] S1104, the system side determines whether the timing time has been reached.

[0242] In one implementation, the time interval between the display start time (i.e. the time when the rising edge of TE is detected) and the time when instruction data reception begins can be calculated, and a timer can be set according to this time interval; when the timer reaches the preset value, it is determined that the timing time has been reached.

[0243] If the timing has not been reached, the system continues to display data and monitor whether the timing has been reached. If the timing has been reached, the system executes step S1105.

[0244] S1105, the system side starts timing T1.

[0245] In one implementation, the system can set a timer to T1 and start the timer when the timer reaches its set point. Correspondingly, when the timer reaches 0, it indicates the end of time T1.

[0246] In another implementation, the system can set the timer to 0 and start it when the timer reaches its set point. Correspondingly, when the timer reaches T1, it indicates the end of time T1.

[0247] S1106, the system side determines whether T1 has ended.

[0248] If T1 has not ended, execute S1107; if T1 has ended, execute S1110.

[0249] S1107, T1 not finished, the system side determines whether instruction data has been received.

[0250] S1108, No instruction data received, set the flag bit.

[0251] S1109, received instruction data, buffer the received instruction data.

[0252] S1110, T1 ends, check if the flag bit is set.

[0253] If the flag is set, then continue with S1101.

[0254] S1111 If the flag bit is not set, the system side packs the cached instruction data to obtain the instruction packet and transmits the instruction packet to DDIC.

[0255] Steps S1106-S1111 are the same as steps S1005-S1010 above, and can be found in the description in the embodiment of Figure 10, which will not be repeated here.

[0256] By using the data transmission method in the above embodiments of this application, a period of time is reserved before the screen refreshes the image for the packaging and unified transmission of instruction data. This enables the timely delivery of instruction data received within a frame. This method effectively reduces the situation where instruction delivery fails due to instruction data occupying the display path for an extended period, as shown in Figure 5. It also effectively reduces the situation where instruction delivery fails in multi-instruction scenarios, as shown in Figure 6, due to a single instruction failing to preempt the delivery opportunity. This reduces frame drops and stuttering caused by unsuccessful instruction data delivery.

[0257] The data transmission method in the above embodiments of this application can also be applied to application scenarios where multiple instructions take effect within the same frame.

[0258] For example, in one application scenario, commands to switch gamma values ​​and backlight are issued. If the commands to switch gamma values ​​and backlight do not take effect in the same frame, the backlight will not have a corresponding gamma value in the next frame, resulting in full-screen flashing.

[0259] To solve the screen flickering problem, the instructions for switching gamma values ​​and backlighting need to be applied in the same frame.

[0260] The data transmission method in this application embodiment receives and caches instruction data in a concentrated manner within a time period, and then packages multiple instruction data within a reserved time and sends them out uniformly. This enables multiple instruction data to be responded to in a single frame, thereby improving the display effect.

[0261] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0262] This application also provides a computer-readable storage medium storing a computer program that, when run on an electronic device, can implement the steps in the above-described method embodiments.

[0263] This application also provides a computer program product that, when run on an electronic device or a wireless router, enables the electronic device to perform the steps described in the various method embodiments above.

[0264] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to the first device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0265] This application also provides a chip, which includes a processor coupled to a memory. The processor calls a computer program stored in the memory to implement the steps of any method embodiment of this application. The chip can be a single chip or a chip module composed of multiple chips.

[0266] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0267] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0268] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data transmission method, characterized in that, Applied to an electronic device, the electronic device including an application processor and a display screen, the method includes: At the first moment, the display screen generates a first TE signal; In response to the first TE signal, the application processor transmits first image data to the display screen; If multiple first instruction data are received between the first time and the second time, the application processor packages the multiple first instruction data into a first instruction packet between the second time and the third time, and sends the first instruction packet to the display screen, wherein the second time is after the first time and the third time is after the second time.

2. The data transmission method according to claim 1, characterized in that, The method further includes: At the fourth moment, the display screen generates a second TE signal, wherein the second TE signal is the next TE signal after the first TE signal; In response to the second TE signal, the application processor transmits second image data to the display screen, wherein the second image data is the next frame of image data of the first image data.

3. The data transmission method according to claim 2, characterized in that, The third time point is after the fourth time point.

4. The data transmission method according to claim 3, characterized in that, The third moment is the start time of the hardware Vsync signal generated by the display screen after the fourth moment.

5. The data transmission method according to claim 4, characterized in that, The method further includes: The first instruction data will be received starting at the fifth moment; At the second moment, stop receiving the first instruction data; The fifth moment is the start time of the hardware Vsync signal generated by the display screen after the first moment.

6. The data transmission method according to claim 3, characterized in that, The third time point is before the sixth time point, which is the start time of the hardware Vsync signal generated by the display screen after the fourth time point.

7. The data transmission method according to claim 6, characterized in that, The method further includes: The first instruction data will be received starting at the seventh moment; At the second moment, stop receiving the first instruction data; Wherein, the first interval is the same as the second interval, the first interval is the time interval between the first time and the seventh time, the seventh time being after the first time; the second interval is the time interval between the fourth time and the third time.

8. The data transmission method according to claim 2, characterized in that, The third time point and the fourth time point are the same time point.

9. The data transmission method according to claim 8, characterized in that, The method further includes: The first instruction data will be received starting at the fifth moment; At the second moment, stop receiving the first instruction data; The fifth moment is the start time of the hardware Vsync signal generated by the display screen after the first moment.

10. The data transmission method according to any one of claims 1 to 9, characterized in that, The method further includes: Between the first time point and the second time point, each time a first instruction data is received, the first instruction data is cached.

11. The data transmission method according to any one of claims 1 to 9, characterized in that, The method further includes: If no first instruction data is received between the first time and the second time, the preset flag is set to the first preset value.

12. The data transmission method as described in claim 11, characterized in that, Between the second and third time points, the application processor packages the plurality of first instruction data to obtain a first instruction packet, including: Between the second time point and the third time point, if the preset flag bit is not the first preset value, the application processor packages the plurality of first instruction data to obtain the first instruction packet; Between the second time point and the third time point, if the preset flag is the first preset value, the application processor monitors the next TE signal.

13. A data transmission method, characterized in that, Applied to an electronic device, the electronic device including an application processor and a display screen, the method includes: At the first moment, the display screen generates a first TE signal; In response to the first TE signal, the application processor transmits first image data to the display screen; If multiple first instruction data are received between the eighth and ninth times, the application processor packages the multiple first instruction data into a first instruction packet between the ninth and tenth times, and sends the first instruction packet to the display screen; wherein the ninth time is the end time of the application processor transmitting the first image data, and the tenth time is after the ninth time.

14. The data transmission method according to claim 13, characterized in that, The method further includes: At the fourth moment, the display screen generates a second TE signal, wherein the second TE signal is the next TE signal after the first TE signal; In response to the second TE signal, the application processor transmits second image data to the display screen, wherein the second image data is the next frame of image data of the first image data.

15. The data transmission method according to claim 14, characterized in that, The tenth moment is after the fourth moment.

16. The data transmission method according to claim 15, characterized in that, The tenth moment is the start time of the hardware Vsync signal generated by the display screen after the fourth moment.

17. The data transmission method according to claim 15, characterized in that, The tenth moment is before the sixth moment; wherein the sixth moment is the start time of the hardware Vsync signal generated by the display screen after the fourth moment.

18. The data transmission method according to claim 14, characterized in that, The tenth moment and the fourth moment are the same moment.

19. The data transmission method according to any one of claims 13 to 18, characterized in that, The method further includes: Between the eighth and ninth time points, each time a first instruction data is received, the first instruction data is cached.

20. The data transmission method according to any one of claims 13 to 18, characterized in that, The method further includes: If no first instruction data is received between the eighth and ninth time points, the preset flag is set to the first preset value.

21. The data transmission method as described in claim 20, characterized in that, Between the ninth and tenth time points, the application processor packages the plurality of first instruction data to obtain a first instruction packet, including: Between the ninth and tenth time points, if the preset flag is not the first preset value, the application processor packages the plurality of first instruction data to obtain the first instruction packet. Between the ninth and tenth time points, if the preset flag is the first preset value, the application processor monitors the next TE signal.

22. An electronic device, characterized in that, The electronic device includes a processor for running a computer program stored in a memory to implement the method as claimed in any one of claims 1 to 12 or the method as claimed in any one of claims 13 to 21.

23. A chip system, characterized in that, The chip system includes a processor coupled to a memory, the processor being configured to run a computer program stored in the memory to implement the method as claimed in any one of claims 1 to 12 or to implement the method as claimed in any one of claims 13 to 21.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by one or more processors, implements the method as claimed in any one of claims 1 to 12 or the method as claimed in any one of claims 13 to 21.

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