Actual activation range limitation for neural network quantization

Abstract

A processor-implemented method determines an actual domain of a following function in a following layer of an artificial neural network. The artificial neural network includes a guiding function in a guiding layer and a following function in a following layer, the following layer being a subsequent contiguous layer of the artificial neural network. The method also sets a first quantization range of output activation of the steering function based on the actual domain.

Description

Actual activation range limitation for neural network quantization

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 544,169, filed December 18, 2023, entitled “PRACTICAL ACTIVATION RANGE RESTRICTION FOR NEURAL NETWORK QUANTIZATION,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 589,898, filed October 12, 2023, entitled “PRACTICAL ACTIVATION RANGE RESTRICTION FOR NEURAL NETWORK QUANTIZATION,” the disclosures of which are expressly incorporated herein by reference in their entirety. Technical Field

[0003] All aspects of this disclosure relate to artificial neural networks in general, and more specifically to the practical activation range limitations used for neural network quantization. Background Technology

[0004] Artificial neural networks can comprise interconnected groups of artificial neurons (e.g., neuron models). An artificial neural network (ANN) can be a computing device or represented as a method to be performed by a computing device. A convolutional neural network (CNN) is a type of feedforward ANN. A CNN can comprise an ensemble of neurons, where each neuron has a receptive field and collectively constructs the input space. CNNs such as deep convolutional neural networks (DCNs) have numerous applications. Specifically, these neural network architectures are used in a variety of technologies, such as image recognition, speech recognition, acoustic scene classification, keyword retrieval, autonomous driving, and other classification tasks.

[0005] Edge devices, such as smartphones, are widely used. Given the many useful applications of neural networks, the demand for edge devices and personalized services for such devices is constantly increasing. However, edge devices have limited computing resources, while generalized models can utilize more complex networks and computing resources.

[0006] Transformer-based architectures have become the de facto standard model for various natural language processing tasks. However, their memory footprint and high latency hinder efficient deployment and inference on resource-constrained devices.

[0007] The aim is to improve quantization techniques used in neural network architectures. Summary of the Invention

[0008] Various aspects of this disclosure relate to an apparatus. The apparatus includes one or more memories and one or more processors coupled to the one or more memories. The processors are configured to determine the actual domain of a follower function in a follower layer of an artificial neural network. The artificial neural network includes a leader function in a leader layer and follower functions in a follower layer, which is a subsequent successive layer of the artificial neural network. The processors are also configured to set a first quantization range of the output activation of the leader function based on the actual domain.

[0009] In other aspects of this disclosure, a processor-implemented method includes determining the actual domain of a follower function in a follower layer of an artificial neural network. The artificial neural network includes a guide function in a guide layer and follower functions in a follower layer, the follower layer being subsequent successive layers of the artificial neural network. The method further includes setting a first quantization range of the output activation of the guide function based on the actual domain.

[0010] In other aspects of this disclosure, a non-transitory computer-readable medium having program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for determining the actual domain of a follower function in a follower layer of an artificial neural network. The artificial neural network includes a leader function in a leader layer and follower functions in a follower layer, which is a subsequent successive layer of the artificial neural network. The program code also includes program code for setting a first quantization range of the output activation of the leader function based on the actual domain.

[0011] Other aspects of this disclosure relate to an apparatus. The apparatus includes components for determining the actual domain of a follower function in a follower layer of an artificial neural network. The artificial neural network includes a leader function in a leader layer and a follower function in a follower layer, the follower layer being a subsequent successive layer of the artificial neural network. The apparatus also includes components for setting a first quantization range of the output activation of the leader function based on the actual domain.

[0012] Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for implementing the same purposes as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0013] The features, substance, and advantages of this disclosure will become more apparent when understood in conjunction with the accompanying drawings, in which the same reference numerals are always used to identify the parts of the drawings.

[0014] Figure 1 illustrates an example implementation of a neural network using a system-on-a-chip (SoC) (including a general-purpose processor) according to certain aspects of this disclosure.

[0015] Figures 2A, 2B and 2C are illustrations of neural networks according to various aspects of the present disclosure.

[0016] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to various aspects of this disclosure.

[0017] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to various aspects of this disclosure.

[0018] Figure 4 is a block diagram illustrating an exemplary software architecture that enables modularization of artificial intelligence (AI) functions according to various aspects of this disclosure.

[0019] Figure 5 is a graph illustrating the functions of the rectified linear unit (ReLU) and the sigmoid linear unit (SiLU).

[0020] Figure 6 is a graph illustrating an sigmoid function.

[0021] Figure 7 is a graph illustrating examples of improved quantization ranges selected according to various aspects of this disclosure.

[0022] Figures 8 through 10 are graphs illustrating more details of the improved quantization ranges selected according to various aspects of this disclosure.

[0023] Figure 11 is a block diagram illustrating backpropagation of the actual domain through multiple layers according to various aspects of this disclosure.

[0024] Figure 12 is a block diagram illustrating a portion of a large language model according to various aspects of this disclosure.

[0025] Figure 13 is a flowchart illustrating examples of processes for setting a quantization range according to various aspects of this disclosure. Detailed Implementation

[0026] The detailed description that follows, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only configurations in which the described concepts can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0027] Based on the teachings, those skilled in the art will recognize that the scope of this disclosure is intended to cover any aspect of this disclosure, whether implemented independently of or in combination with any other aspect of this disclosure. For example, an apparatus or method may be implemented using any number of the aspects described. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using other structures, functionalities, or structures and functionalities that complement or differ from the various aspects of this disclosure described. It should be understood that any aspect of this disclosure may be embodied by one or more elements of the claims.

[0028] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” need not be interpreted as superior to or better than other aspects.

[0029] While specific aspects have been described, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or purpose. Rather, aspects of this disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0030] Recently, transformer architectures have demonstrated improvements in language modeling and natural language processing (NLP) tasks. Based on conventional transformer architectures, language models can be pre-trained from large corpora of unlabeled text. Therefore, such transformer architectures have become common building blocks in conventional NLP pipelines as well as in other fields such as computer vision and audio processing.

[0031] While offering performance improvements in many applications, pre-trained converter-based models can be extremely large, sometimes exceeding billions of parameters. Therefore, efficiently deploying such converter-based models on resource-constrained embedded systems, including mobile devices (e.g., smartphones) and Internet of Things (IoT) devices, as well as some systems in data centers, is challenging due to increased latency, energy consumption, and excessive memory footprint.

[0032] One effective approach to addressing this problem is neural network quantization. Neural network quantization reduces memory consumption by using low-bit precision for the weights and activation tensors. Furthermore, it reduces inference time and improves energy efficiency by employing low-bit fixed-point arithmetic instead of floating-point arithmetic.

[0033] However, quantization can introduce additional noise into neural networks, which can lead to decreased model accuracy and increased computational complexity. For example, transformer models may have numerous outliers in their activations. These activation outliers can cause large quantization errors.

[0034] Some conventional methods attempt to address large quantization errors by applying quantization-aware training (QAT). QAT involves a fine-tuning process based on the same training dataset and training pipeline as the original model. However, the QAT process can overfit because it alters the parameters of the pre-trained model when adapting to unfamiliar distributions or domains. Furthermore, many pre-trained language models may not allow access to the training dataset and pipeline, forcing users to rely on arbitrary datasets and training pipelines for fine-tuning, which can also lead to the model overfitting to the fine-tuned data.

[0035] Other conventional methods determine the activation quantization range based on the statistics of the distribution of the activated outputs. For example, when setting the quantization range, maximum, minimum, average, variance, etc., may be considered. Due to outliers, the activation quantization range at layers of artificial neural networks can be very wide. For any given wide range, a wide quantization range leads to lower resolution and therefore larger quantization errors. To address these and other issues, aspects of this disclosure relate to improving quantization in neural network models.

[0036] Artificial neural networks can comprise multiple consecutive layers. In a simplified example for illustrative purposes, the neural network comprises two consecutive layers: a guiding layer and a follower layer. The guiding layer includes a guiding function. The output from the guiding function is received as the input to the follower function in the follower layer of the network.

[0037] When a follower function has a many-to-one mapping, the portion of the range of the previous function that maps to the same or very close values ​​in the follower function is wasted. Aspects of this disclosure restrict the domain of the follower function to the actual domain that transforms the function into a practically one-to-one mapping. This domain restriction narrows the quantization range, resulting in higher quantization resolution for the corresponding activation.

[0038] Various aspects of this disclosure maximize quantization resolution or equivalently minimize quantization error by determining the activation quantization range based on the actual domain of the follower function, thus taking into account inter-layer dependencies. By looking at the next layer, the output of previous layers may be constrained, resulting in a narrower quantization range. In other words, inter-layer dependencies are considered to improve quantization.

[0039] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described quantization techniques reduce quantization errors.

[0040] Figure 1 illustrates an example implementation of a System-on-Chip (SOC) 100, which may include a Central Processing Unit (CPU) 102 or a multi-core CPU configured for quantization based on actual activation range limitations. Variables (e.g., neural signals and synaptic weights), system parameters associated with the computing device (e.g., a weighted neural network), latency, frequency window (bin) information, and task information may be stored in a memory block associated with a Neural Processing Unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a Graphics Processing Unit (GPU) 104, a memory block associated with a Digital Signal Processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from the program memory associated with the CPU 102 or from memory block 118.

[0041] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth-generation (5G) connectivity, fourth-generation LTE (4G) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 capable of, for example, detecting and recognizing gestures. In one specific implementation, an NPU 108 is implemented within a CPU 102, a DSP 106, and / or a GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0042] The SOC 100 may be based on the ARM instruction set. In various aspects of this disclosure, instructions loaded into the general-purpose processor 102 may include code for determining the actual domain of a follower function in a follower layer of an artificial neural network. The artificial neural network includes a bootstrap function in a bootstrap layer and follower functions in a follower layer, which is a subsequent, consecutive layer of the artificial neural network. The general-purpose processor 102 may also include code for setting a first quantization range of the output activation of the bootstrap function based on the actual domain.

[0043] Deep learning architectures perform object recognition tasks by learning to represent inputs at progressively higher levels of abstraction in each layer, thereby constructing useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Before deep learning, machine learning methods for object recognition problems often relied heavily on human-designed features, possibly in conjunction with shallow classifiers. Shallow classifiers could be two-class linear classifiers, where a weighted sum of feature vector components is compared to a threshold to predict which class the input belongs to. Human-designed features could be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, this requires training. Furthermore, deep networks can learn to represent and recognize novel types of features that humans might not have considered.

[0044] Deep learning architectures can learn hierarchical structures of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power at specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0045] Deep learning architectures perform particularly well when applied to problems with a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to identify features such as wheels, windshields, and others. These features can then be combined in different ways at higher levels to identify cars, trucks, and airplanes.

[0046] Neural networks can be designed to have multiple connectivity patterns. In feedforward networks, information is passed from lower layers to higher layers, where each neuron in a given layer communicates with neurons in higher layers. As described above, hierarchical representations can be built in successive layers of a feedforward network. Neural networks can also have recurrent or feedback (also known as top-down) connections. In recurrent connections, the output from a neuron in a given layer can be passed to another neuron in the same layer. Recurrent architectures can help identify patterns across more than one block of input data that is sequentially delivered to the neural network. Connections from neurons in a given layer to neurons in lower layers are called feedback (or top-down) connections. Networks with many feedback connections can be helpful when the recognition of higher-level concepts can aid in discerning specific lower-level features of the input.

[0047] The connections between layers in a neural network can be fully connected or locally connected. Figure 2A illustrates an example of a fully connected neural network 202. In a fully connected neural network 202, neurons in the first layer can transmit their outputs to each neuron in the second layer, such that each neuron in the second layer receives input from each neuron in the first layer. Figure 2B illustrates an example of a locally connected neural network 204. In a locally connected neural network 204, neurons in the first layer can connect to a limited number of neurons in the second layer. More generally, the locally connected layers of a locally connected neural network 204 can be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strength can have different values ​​(e.g., 210, 212, 214, and 216). The connectivity pattern of locally connected layers can produce spatially different receptive fields in higher layers because neurons in higher layers in a given region can receive inputs that are tuned to the characteristics of a restricted portion of the total input to the network through training.

[0048] An example of a locally connected neural network is a convolutional neural network. Figure 2C illustrates an example of a convolutional neural network 206. Convolutional neural network 206 can be configured such that the connection strength associated with the input for each neuron in the second layer is shared (e.g., 208). Convolutional neural networks may be well-suited for problems where the spatial location of the input is meaningful.

[0049] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D illustrates a detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as an in-vehicle camera). The DCN 200 in the current example can be trained to identify traffic signs and the numbers provided on them. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0050] Supervised learning can be used to train the DCN 200. During training, an image (such as image 226 of a speed limit sign) can be presented to the DCN 200, and forward passes can then be computed to produce output 222. The DCN 200 may include a feature extraction part and a classification part. Upon receiving image 226, convolutional layer 232 may apply a convolutional kernel (not shown) to image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel used for convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In this example, since four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to image 226 at convolutional layer 232. Convolutional kernels may also be referred to as filters or convolutional filters.

[0051] The first set of feature maps 218 can be subsampled by a max-pooling layer (not shown) to generate a second set of feature maps 220. The max-pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (e.g., 14×14) is smaller than the size of the first set of feature maps 218 (e.g., 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0052] In the example of Figure 2D, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of image 226, such as "sign", "60", and "100". A softmax function (not shown) converts the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of DCN 200 can be the probability that image 226 includes one or more features.

[0053] In this example, the probabilities for "sign" and "60" in output 222 are higher than the probabilities for other numbers in output 222 (such as "30", "40", "50", "70", "80", "90", and "100"). Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the baseline ground truth (e.g., "sign" and "60") of image 226. The weights of DCN 200 can then be adjusted so that output 222 of DCN 200 is more closely aligned with the target output.

[0054] To adjust the weights, the learning algorithm computes the gradient vector of the weights. The gradient indicates by how much the error will increase or decrease as the weights are adjusted. At the top layers, the gradient corresponds directly to the values ​​of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient depends on the values ​​of the weights and the error gradient computed in the higher layers. The weights can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves "passing backward" through the neural network.

[0055] In practice, the error gradient of the weights can be calculated using a small number of examples to make the calculated gradient approximate the true error gradient. This approximation method is called stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, a new image (e.g., a speed limit sign in image 226) can be presented to DCN 200, and output 222 can be generated through the forward pass of DCN 200. This output can be considered as an inference or prediction of DCN 200.

[0056] Deep Belief Networks (DBNs) are probabilistic models that include multiple layers of hidden nodes. DBNs can be used to extract hierarchical representations of training datasets. DBNs are obtained by stacking layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that learns a probability distribution from a set of inputs. Because RBMs can learn a probability distribution without information about the class each input should be classified into, they are often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained unsupervised and used as a feature extractor, while the top RBM can be trained supervisedly (on the joint distribution of inputs from the previous layer and the target class) and used as a classifier.

[0057] DCN is a network of convolutional networks configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many paradigms and are used to modify the network's weights using gradient descent.

[0058] DCNs can be feedforward networks. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational cost of a DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0059] The processing at each layer of a convolutional network can be thought of as a spatially invariant template or base projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then a convolutional network trained on that input can be thought of as three-dimensional, with two spatial dimensions along the image's axes and a third dimension capturing color information. The output of the convolutional connections can be thought of as forming a feature map in the next layer, where each element in the feature map (e.g., 220) receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed using non-linear methods (e.g., rectified, max(0,x)). Values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and provides additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied through lateral inhibition between neurons in the feature map.

[0060] Figure 3 is a block diagram illustrating DCN 350. DCN 350 may include multiple layers of different types based on connectivity and weight sharing. As shown in Figure 3, DCN 350 includes convolutional blocks 354A and 354B. Each convolutional block in convolutional blocks 354A and 354B may be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

[0061] Although only two convolutional blocks 354A and 354B are shown, this disclosure is not limited thereto, and any number of convolutional blocks 354A and 354B may be included in the DCN 350 according to design preferences.

[0062] Convolutional layer 356 may include one or more convolutional filters that can be applied to the input data to generate feature maps. Normalization layer 358 may normalize the output of the convolutional filters. For example, normalization layer 358 may provide whitening or lateral suppression. Max pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0063] Parallel filter banks of deep convolutional networks can be loaded onto the CPU 102 or GPU 104 of the SOC 100 (e.g., Figure 1) to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter banks can be loaded onto the DSP 106 or ISP 116 of the SOC 100. Furthermore, the DCN 350 can access other processing blocks that may exist on the SOC 100, such as sensor processor 114 and navigation module 120, respectively dedicated to sensors and navigation.

[0064] The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may also include logistic regression (LR) layers 364. Weights (not shown) to be updated are located between each of the layers 356, 358, 360, 362, and 364 of the DCN 350. The output of each layer (e.g., 356, 358, 360, 362, and 364) can be used as input to the next layer in the DCN 350 (e.g., 356, 358, 360, 362, and 364) to learn hierarchical feature representations from the input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block in convolutional block 354A. The output of the DCN 350 is a classification score 366 of the input data 352. The classification score 366 may be a set of probabilities, where each probability is a probability of the input data, which includes features from a feature set.

[0065] Figure 4 is a block diagram illustrating an exemplary software architecture 400 for modular artificial intelligence (AI) functionality. Using architecture 400, applications can be designed that enable various processing blocks of an SOC 420 (which may be similar to SOC 100 of Figure 1) (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) to support quantization based on actual activation range limitations for AI applications 402 according to various aspects of this disclosure. Architecture 400 can, for example, be included in a computing device such as a smartphone.

[0066] AI application 402 can be configured to invoke functions defined in user space 404, which may, for example, provide the detection and recognition of a scene indicating the current location of the computing device (including architecture 400). For example, AI application 402 may configure microphones and cameras differently depending on whether the recognized scene is an office, lecture hall, restaurant, or outdoor environment (such as a lake). AI application 402 may make requests to compiled program code associated with libraries defined in AI Function Application Programming Interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide inferred responses based on, for example, video and location data.

[0067] Runtime engine 408 (which may be compiled code of a runtime framework) may be further accessible to AI application 402. AI application 402 may cause runtime engine 408 to request inference, for example, at specific time intervals or when triggered by events detected by the user interface of AI application 402. Upon causing runtime engine 408 to provide an inference response, the runtime engine may then signal to the operating system (OS) space 410 running on SOC 420, such as kernel 412. In some examples, kernel 412 may be a LINUX kernel. The operating system may then enable quantization to be performed on CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed via drivers such as drivers 414, 416, or 418 for DSP 424, GPU 426, or NPU 428, respectively. In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422, DSP 424 and GPU 426, or on NPU 428.

[0068] Recently, transformer architectures have demonstrated improvements in language modeling and natural language processing (NLP) tasks. Based on conventional transformer architectures, language models can be pre-trained from large corpora of unlabeled text. Therefore, such transformer architectures have become common building blocks in conventional NLP pipelines as well as in other fields such as computer vision and audio processing.

[0069] While offering performance improvements in many applications, pre-trained converter-based models can be extremely large, sometimes exceeding billions of parameters. Therefore, efficiently deploying such converter-based models on resource-constrained embedded systems, including mobile devices (e.g., smartphones) and Internet of Things (IoT) devices, as well as some systems in data centers, is challenging due to increased latency, energy consumption, and excessive memory footprint.

[0070] One effective approach to addressing this problem is neural network quantization. Neural network quantization reduces memory consumption by using low-bit precision for the weights and activation tensors. Furthermore, it reduces inference time and improves energy efficiency by employing low-bit fixed-point arithmetic instead of floating-point arithmetic.

[0071] However, quantization can introduce additional noise into neural networks, which can lead to decreased model accuracy and increased computational complexity. For example, transformer models may have numerous outliers in their activations. These activation outliers can cause large quantization errors.

[0072] Some conventional methods attempt to address large quantization errors by applying quantization-aware training (QAT). QAT involves a fine-tuning process based on the same training dataset and training pipeline as the original model. However, the QAT process can overfit because it alters the parameters of the pre-trained model when adapting to unfamiliar distributions or domains. Furthermore, many pre-trained language models may not allow access to the training dataset and pipeline, forcing users to rely on arbitrary datasets and training pipelines for fine-tuning, which can also lead to the model overfitting to the fine-tuned data.

[0073] Other conventional methods determine the activation quantization range based on the statistics of the distribution of the activated outputs. For example, when setting the quantization range, maximum, minimum, average, variance, etc., may be considered. Due to outliers, the activation quantization range at layers of artificial neural networks can be very wide. For any given wide range, a wide quantization range leads to lower resolution and therefore larger quantization errors. To address these and other issues, aspects of this disclosure relate to improving quantization in neural network models.

[0074] Nonlinear layers (or activation functions) are used in neural networks. Some of these activation functions have a many-to-one mapping. For example, the Rectified Linear Unit (ReLU) function has a domain. and range .

[0075] Artificial neural networks can comprise multiple consecutive layers. In a simplified example for illustrative purposes, the neural network comprises two consecutive layers: a guiding layer and a follower layer. The guiding layer includes a guiding function. The output from the guiding function is received as the input to the follower function in the follower layer of the network.

[0076] When the follower function has a many-to-one mapping, the portion of the range of the preceding function that maps to the same or very close values ​​in the follower function is wasted. Aspects of this disclosure limit the domain of the follower function to the actual domain that transforms the function into a practically one-to-one mapping. For example, as seen in Figure 5, the actual domain of ReLU is... ,because The actual domain of SiLU (S-shaped linear unit) is [-7.5, ], SiLU=x σ(x), where σ(x) is a logical sigmoid. As shown in Figure 6, the practical domain of the sigmoid function is approximately... ,because as well as The restriction domain narrows the quantization range, resulting in a higher quantization resolution for the corresponding activation.

[0077] Various aspects of this disclosure maximize quantization resolution or equivalently minimize quantization error by determining the activation quantization range based on the actual domain of the follower function, thus taking into account inter-layer dependencies. By looking at the next layer, the output of previous layers may be constrained, resulting in a narrower quantization range. In other words, inter-layer dependencies are considered to improve quantization.

[0078] Figure 7 is a graph illustrating examples of improved quantization ranges selected according to various aspects of this disclosure. To determine the improved quantization range, let... and For the first in a neural network Layer and first Two continuous functions at the layer, where and They represent the first The domain and range at the layer, where l represents the lower limit and u represents the upper limit. Let... For the first The actual domain at the layer, and assume For the first time using the predetermined quantization method The quantization range of the output activation at the layer.

[0079] Assuming these definitions, the actual domain It can be determined as ,in , , and This represents the tolerance (or margin) of the actual range and upper bound of the domain. Both the tolerance and margin are positive real numbers. The new quantization range for the output activation at the layer can be set to: .

[0080] Figures 8 through 10 are graphs illustrating more details of the improved quantization ranges selected according to various aspects of this disclosure. In the example of Figure 8, the function is first identified. 802 Next, determine the inverse function for the actual range. and The inverse function in the actual range is a slightly smaller version in the one-to-one mapping region.

[0081] As shown in Figure 9, The actual domain 902 is configured with margin: .

[0082] As shown in Figure 10, the new activation quantization range of 1002 is set at the [missing value]. At the layer: .

[0083] The technology disclosed herein can be extended to more than two layers via backpropagation through the actual domain. Figure 11 is a block diagram illustrating backpropagation through multiple layers of the actual domain according to various aspects of this disclosure. As seen in the example of Figure 11, four layers... , +1、 +2 and +3 exists in the neural network. According to various aspects of this disclosure, the actual domain is sequentially backpropagated. For example, The actual range of the layer Set to the defined quantization range . The actual range of the layer Used to determine The actual domain in the layer And therefore Quantization range in the layer Wait: More generally expressed as .

[0084] Figure 12 is a block diagram illustrating a portion of a large language model according to various aspects of this disclosure. In the example of Figure 12, the output of the first linear layer 1202 (GateProjection) is fed to a sigmoid function 1204. In the first multiplier 1206, the sigmoid output is multiplied element-wise by the GateProjection output. At the second multiplier 1210, the output of the first multiplier 1206 is multiplied element-wise by the output of the second linear layer 1208 (UpProjection) to generate the input of the third linear layer 1212 (DownProjection).

[0085] As shown in Figure 6, the practical domain of the sigmoid function is approximately [-6, 6] or [-7.5, 7.5] with a margin. Therefore, the practical domain (or quantization range) of the linear layer 1202 can be set such that the output of the linear layer 1202 is capped at [-7.5, 7.5]. This improves the network performance. If the sigmoid linear unit (SiLU) function is used, the practical domain of the SiLU function is [-7.5, 6]. In this case, the upper limit can be determined based on experience.

[0086] This disclosure presents various quantization techniques that can be used to improve quantization resolution for a given localization budget. These techniques can be applied to virtually every neural network quantization. These techniques are particularly useful for neural networks with large outliers, such as those with transformers (e.g., Large Language Models (LLMs) and Visual Transformers (ViTs)) that have strongly nonlinear activations, such as the Rectified Linear Unit (ReLU) function, ReLU6, sigmoid function, hyperbolic tangent (Tanh) function, sigmoid linear unit (SiLU) function, etc., which are popular choices in neural network design.

[0087] Figure 13 illustrates a process 1300 for quantizing a neural network based on actual activation range constraints according to various aspects of this disclosure. As shown in Figure 13, in some aspects, process 1300 may include determining the actual domain of a follower function in a follower layer of the artificial neural network. The artificial neural network includes a guide function in a guide layer and a follower function in a follower layer, which is a subsequent successive layer of the artificial neural network (box 1302). For example, process 1300 may include computing the actual domain based on the inverse function of the follower function and multiple tolerances for lower and upper bounds. The follower function may be an activation function with a many-to-one mapping.

[0088] In some aspects, process 1300 may include setting a first quantization range for the output activation of the bootstrap function based on the actual domain (box 1304). For example, process 1300 sets the first quantization range based on the maximum value and the minimum value of a predetermined quantization range.

[0089] Example

[0090] Aspect 1: An apparatus comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor being configured to: determine an actual domain of a follower function in a follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and set a first quantization range of the output activation of the guide function based on the actual domain.

[0091] Aspect 2: The apparatus according to aspect 1, wherein the at least one processor is further configured to compute the actual domain based on the inverse function of the follower function and a plurality of tolerances.

[0092] Aspect 3: The apparatus according to aspect 1 or 2, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

[0093] Aspect 4: The apparatus according to any one of the preceding aspects, wherein the at least one processor is further configured to set the first quantization range based on the maximum value of the predetermined quantization range and the minimum value of the predetermined quantization range.

[0094] Aspect 5: The apparatus according to any one of the preceding aspects, wherein the at least one processor is further configured to: set the actual range of the bootstrap function in the bootstrap layer based on the first quantization range; determine the actual domain of the bootstrap function in the bootstrap layer based on the actual range of the bootstrap function; and set a second quantization range of a previous function of a previous layer immediately preceding the bootstrap layer based on the actual domain of the bootstrap function.

[0095] Aspect 6: The apparatus according to any one of the preceding aspects, wherein the follow function includes an activation function having a many-to-one mapping.

[0096] Aspect 7: The apparatus according to any one of the preceding aspects, wherein the activation function includes a nonlinear activation function.

[0097] Aspect 8: A processor-implemented method comprising: determining an actual domain of a follower function in a follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and setting a first quantization range for the output activation of the guide function based on the actual domain.

[0098] Aspect 9: The processor-implemented method according to aspect 8 further includes calculating the actual domain based on the inverse function of the follower function and multiple tolerances.

[0099] Aspect 10: A processor-implemented method according to aspect 8 or 9, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

[0100] Aspect 11: The processor-implemented method according to any one of Aspects 8 to 10, the processor-implemented method further comprising setting the first quantization range based on a maximum value of a predetermined quantization range and a minimum value of the predetermined quantization range.

[0101] Aspect 12: A processor-implemented method according to any one of Aspects 8 to 11, the processor-implemented method further comprising: setting an actual range of the bootstrap function in the bootstrap layer based on a first quantization range; determining an actual domain of the bootstrap function in the bootstrap layer based on the actual range of the bootstrap function; and setting a second quantization range of a previous function of a previous layer immediately preceding the bootstrap layer based on the actual domain of the bootstrap function.

[0102] Aspect 13: A method implemented by a processor according to any one of Aspects 8 to 12, wherein the follower function includes an activation function having a many-to-one mapping.

[0103] Aspect 14: A method implemented by a processor according to any one of Aspects 8 to 13, wherein the activation function includes a non-linear activation function.

[0104] Aspect 15: An apparatus comprising: means for determining an actual domain of a follower function in a follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and means for setting a first quantization range of the output activation of the guide function based on the actual domain.

[0105] Aspect 16: The apparatus according to aspect 15 further includes components for calculating the actual domain based on the inverse function of the follower function and a plurality of tolerances.

[0106] Aspect 17: The apparatus according to aspects 15 to 16, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

[0107] Aspect 18: The apparatus according to any one of aspects 15 to 17, the apparatus further comprising a component for setting the first quantization range based on a maximum value of a predetermined quantization range and a minimum value of the predetermined quantization range.

[0108] Aspect 19: The apparatus according to any one of Aspects 15 to 18, the apparatus further comprising: means for setting an actual range of the bootstrap function in the bootstrap layer based on a first quantization range; means for determining an actual domain of the bootstrap function of the bootstrap layer based on the actual range of the bootstrap function; and means for setting a second quantization range of a previous function of a previous layer immediately preceding the bootstrap layer based on the actual domain of the bootstrap function.

[0109] Aspect 20: The apparatus according to any one of aspects 15 to 19, wherein the follow function includes an activation function having a many-to-one mapping.

[0110] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the cases where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components with similar numbering plus functional components.

[0111] As used, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, computation, processing, derivation, research, searching (e.g., looking in a table, database, or other data structure), assertion, etc. Additionally, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Furthermore, "determine" can include parsing, selecting, choosing, building, etc.

[0112] As used, the phrase "at least one of the items in the list" refers to any combination of these items, including a single member. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0113] The various exemplary logic blocks, modules, and circuits described in this disclosure can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic component, discrete hardware component, or any combination thereof designed to perform the described functions. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0114] The steps or algorithms of the methods described in this disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of both. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction or multiple instructions and may be distributed across several different code segments, across different programs, and across multiple storage media. The storage medium may be coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor.

[0115] The disclosed method includes one or more steps or actions for implementing the described method. The steps and / or actions of the method may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0116] The described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system within the device. This processing system may utilize a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnect buses and bridges. The bus can link various circuits together, including processors, machine-readable media, and bus interfaces. The bus interface can be used to connect network adapters, etc., to the processing system via the bus. The network adapter can be used to implement signal processing functions. In some respects, user interfaces (e.g., keypads, displays, mice, joysticks, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0117] A processor may be responsible for managing the bus and general-purpose processing, including executing software stored on a machine-readable medium. A processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software should be interpreted broadly as instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. By way of example, a machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, disks, optical disks, hard disks, or any other suitable storage medium, or any combination thereof. A machine-readable medium may be embodied as a computer program product. A computer program product may include packaging material.

[0118] In a hardware implementation, machine-readable media can be part of a processing system separate from the processor. However, as those skilled in the art will readily understand, machine-readable media, or any portion thereof, can be external to the processing system. By way of example, machine-readable media may include transmit lines, carrier waves modulated by data, and / or computer components separate from the device, all accessible to the processor via a bus interface. Alternatively or additionally, machine-readable media, or any portion thereof, may be integrated into the processor, such as in the case of a cache and / or a general-purpose register file. Although the various components discussed may be described as having a specific location, such as local components, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[0119] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of machine-readable medium, all of which are linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron and nervous system models. As another alternative, the processing system may be implemented using an application-specific integrated circuit (ASIC) having a processor, bus interface, user interface, supporting circuitry, and at least a portion of machine-readable medium integrated on a single chip, or using one or more field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic components, discrete hardware components, or any other suitable circuitry, or any combination of circuitry capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depends on the specific application and the overall design constraints imposed on the system as a whole.

[0120] Machine-readable media may include multiple software modules. These software modules include instructions that, when executed by a processor, cause the processing system to perform various functions. Software modules may include send and receive modules. Each software module may reside in a single storage device or be distributed across multiple storage devices. For example, when a triggering event occurs, a software module may be loaded from a hard disk drive into RAM. During the execution of a software module, the processor may load some of the instructions into a cache to improve access speed. One or more cache lines may then be loaded into a general-purpose register file for processor execution. When the functionality of a software module is referred to below, it will be understood that such functionality is implemented by the processor when executing the instructions from that software module. Furthermore, it should be understood that aspects of this disclosure result in improvements to the functionality of a processor, computer, machine, or other system implementing such aspects.

[0121] If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. A storage medium can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Additionally, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then such coaxial cable, optical fiber, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. The disks and optical discs used include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, and optical discs reproduce data optically using lasers. Therefore, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Furthermore, in other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0122] Therefore, certain aspects may include a computer program product for performing the presented operations. For example, such a computer program product may include a computer-readable medium on which instructions are stored (and / or encoded) that can be executed by one or more processors to perform the described operations. In some aspects, the computer program product may include packaging material.

[0123] Furthermore, it should be understood that modules and / or other suitable components for performing the described methods and techniques may be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such devices can be coupled to a server to facilitate the delivery of components for performing the described methods. Alternatively, the various methods described can be provided via storage components (e.g., RAM, ROM, physical storage media such as CDs or floppy disks) so that the user terminal and / or base station can obtain the various methods once the storage component is coupled to or provided to the device. In addition, any other suitable techniques suitable for providing the described methods and techniques to the device may be utilized.

[0124] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus, the apparatus comprising: At least one memory; and at least one processor coupled to at least one memory, the at least one processor being configured to: determine the actual domain of a follower function in a follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and set a first quantization range for the output activation of the guide function based on the actual domain.

2. The apparatus of claim 1, wherein the at least one processor is further configured to compute the actual domain based on the inverse function of the follower function and a plurality of tolerances.

3. The apparatus of claim 2, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

4. The apparatus of claim 1, wherein the at least one processor is further configured to set the first quantization range based on a maximum value of a predetermined quantization range and a minimum value of the predetermined quantization range.

5. The apparatus of claim 1, wherein the at least one processor is further configured to: set the actual range of the bootstrap function in the bootstrap layer based on the first quantization range; determine the actual domain of the bootstrap function in the bootstrap layer based on the actual range of the bootstrap function; and set a second quantization range of a previous function of a previous layer immediately preceding the bootstrap layer based on the actual domain of the bootstrap function.

6. The apparatus of claim 1, wherein the follow function comprises an activation function having a many-to-one mapping.

7. The apparatus of claim 6, wherein the activation function comprises a nonlinear activation function.

8. A processor-implemented method, the processor-implemented method comprising: Determine the actual domain of the follower function in the follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and set a first quantization range for the output activation of the guide function based on the actual domain.

9. The processor-implemented method according to claim 8, further comprising calculating the actual domain based on the inverse function of the follower function and multiple tolerances.

10. The processor-implemented method of claim 9, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

11. The processor-implemented method according to claim 8, further comprising setting the first quantization range based on a maximum value of a predetermined quantization range and a minimum value of the predetermined quantization range.

12. The processor-implemented method according to claim 8, further comprising: The actual range of the bootstrap function in the bootstrap layer is set based on the first quantization range. The actual domain of the bootstrap function of the bootstrap layer is determined based on the actual range of the bootstrap function. And based on the actual domain of the bootstrap function, set a second quantization range for the previous function of the previous layer immediately preceding the bootstrap layer.

13. The processor-implemented method of claim 8, wherein the follow function comprises an activation function having a many-to-one mapping.

14. The processor-implemented method of claim 13, wherein the activation function includes a non-linear activation function.

15. An apparatus comprising: A component for determining the actual domain of a follower function in a follower layer of an artificial neural network, the artificial neural network including a guide function in a guide layer and the follower function in the follower layer, the follower layer being a subsequent successive layer of the artificial neural network; and a component for setting a first quantization range of the output activation of the guide function based on the actual domain.

16. The apparatus of claim 15, further comprising a component for calculating the actual domain based on the inverse function of the follower function and a plurality of tolerances.

17. The apparatus of claim 16, wherein the plurality of tolerances includes a first tolerance for a lower bound of the range of the follower function, a second tolerance for an upper bound of the range of the follower function, a third tolerance for a lower bound of the determined actual domain of the follower function, and a fourth tolerance for an upper bound of the determined actual domain of the follower function.

18. The apparatus of claim 15, further comprising a component for setting the first quantization range based on a maximum value of a predetermined quantization range and a minimum value of the predetermined quantization range.

19. The apparatus of claim 15, further comprising: A component for setting the actual range of the bootstrap function in the bootstrap layer based on the first quantization range; A component for determining the actual domain of the bootstrap function of the bootstrap layer based on the actual range of the bootstrap function; And a component for setting a second quantization range of a previous function of a previous layer immediately preceding the bootstrap layer, based on the actual domain of the bootstrap function.

20. The apparatus of claim 15, wherein the follow function comprises an activation function having a many-to-one mapping.

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