Chip and test method thereof, computer equipment and storage medium
By using a mode switching module and time-division multiplexing technology, the problem of limited PIN count after chip packaging was solved, improving testing efficiency and accuracy, and enabling precise logic fault diagnosis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ARTMEM TECHNOLOGY CO LTD
- Filing Date
- 2025-12-02
- Publication Date
- 2026-05-05
AI Technical Summary
In existing technologies, the limited number of pins after chip packaging leads to complex compression and decompression logic for high compression ratios, reducing fault diagnosis accuracy and causing coverage loss.
By employing a mode switching module, an input decompression module, and an output compression module, and using time-division multiplexing and a tripled clock, the scanning chain test mode switching and data restoration are realized, thereby improving test efficiency and accuracy.
It improves the efficiency and accuracy of chip testing, reduces the complexity and cost of fault diagnosis, and enables accurate judgment of logic faults.
Smart Images
Figure CN121978501A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a chip and its testing method, computer equipment and storage medium. Background Technology
[0002] In related technologies, the number of pins after chip packaging is limited. Conventional designs improve the compression ratio by integrating high-compression-ratio compressor and decompressor modules inside the chip. However, high compression ratios require more complex compression and decompression logic, leading to decreased fault diagnosis accuracy and a loss of coverage. Summary of the Invention
[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip and its testing method, a computer device, and a storage medium, aiming to improve the efficiency and accuracy of testing.
[0004] In a first aspect, embodiments of this application provide a chip, the chip including a mode switching module, an input decompression module, and an output compression module, comprising: The output compression module is equipped with a triple clock, which is used to output the compressed final scan chain test pins in multiple compressed clock cycles through time-division multiplexing of the response signal output by the scan chain inside the chip in the final scan chain test mode. The mode switching module is equipped with control pins, a multiplexer, and multiplexed wafer scan chain test pins. The control signal output from the control pins drives the multiplexer to switch test modes. The input decompression module includes multi-level registers and combinational logic.
[0005] According to some embodiments of this application, the test mode includes a wafer scan chain test mode and a final scan chain test mode, and the multiplexed wafer scan chain test pins serve as input pins and output pins in the final scan chain test mode.
[0006] According to some embodiments of this application, the input decompression module is used to receive multi-phase compressed data input in the final scan chain test mode according to a preset compression specification, latch and splice it in the multi-level registers in a periodic manner, restore it to the test vector in the wafer scan chain test mode, and input it to the internal scan chain of the chip.
[0007] According to some embodiments of this application, in the wafer scan chain test mode, the mode switching module includes: The multiplexer enables the scan chain input signal and scan chain output signal in the wafer scan chain test mode to be directly connected to the internal scan chain of the chip, while the input decompression module and the output compression module are in an idle state.
[0008] Secondly, embodiments of this application provide a chip testing method, applied to a chip, the chip including a mode switching module, an input decompression module, and an output compression module, comprising: Obtain the compression specifications of the input decompression module and the time-division multiplexing rules of the output compression module; According to the compression specification and the time-division multiplexing rule, the scan chain test vector of the wafer scan chain test mode is converted into the scan chain test vector of the final scan chain test mode, wherein the scan chain test vector of the final scan chain test mode includes the compressed final scan chain test input vector and the corresponding expected final scan chain test output response; The ATE machine loads the scan chain test vector of the final scan chain test mode onto the chip, sets the control pin to the final scan chain test mode level, restores the test vector of the original wafer scan chain test mode through the input decompression module and inputs it into the internal scan chain of the chip, and outputs the final scan chain test response signal through the output compression module. The final scan chain test response signal is compared with the expected final scan chain test output response signal to obtain the comparison result; Based on the comparison results, the chip logic fault judgment result is obtained.
[0009] According to some embodiments of this application, it also includes: The target total number of wafer scan chain test response signals output by the internal scan chain of the chip are output sequentially according to the preset period of the triple clock, wherein the target number of response data is output in each preset period. According to some embodiments of this application, the step of restoring the test vector to the original wafer scan chain test mode through the input decompression module includes: During the first preset period of the tripled clock, the first compressed data is received by the input decompression module and latched into the low target bit register. During the second preset cycle of the tripled clock, the second compressed data is received by the input decompression module and latched into the high target digital register. During the third preset cycle of the tripled clock, the third compressed data is received through the input decompression module and concatenated with the data latched in the low target bit register and the high target bit register to restore the wafer scan chain test vector with a target total number of bits.
[0010] According to some embodiments of this application, obtaining the chip logic fault judgment result based on the comparison result includes: When the comparison result indicates that the final scan chain test response signal is completely consistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has no logic fault. When the comparison result indicates that the final scan chain test response signal is inconsistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has a logic fault and the fault location is located.
[0011] Thirdly, embodiments of this application provide a computer device, including: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the chip testing method described in the second aspect above.
[0012] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the chip testing method described in the second aspect above.
[0013] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: The chip testing method of this application is applied to a chip, the chip including a mode switching module, an input decompression module, and an output compression module, including: acquiring the compression specification of the input decompression module and the time-division multiplexing rule of the output compression module; converting the scan chain test vector of the wafer scan chain test mode into the scan chain test vector of the final scan chain test mode according to the compression specification and the time-division multiplexing rule, wherein the scan chain test vector of the final scan chain test mode includes the compressed final scan chain test input vector and the corresponding expected final scan chain test output response; loading the scan chain test vector of the final scan chain test mode onto the chip through an ATE machine, setting the control pin to the final scan chain test mode level, so that the chip restores the original wafer scan chain test vector through the input decompression module and inputs it into the internal scan chain of the chip, and outputs the final scan chain test response signal through the output compression module; comparing the final scan chain test response signal with the expected final scan chain test output response to obtain a comparison result; and obtaining a chip logic fault judgment result based on the comparison result. This application can improve the efficiency and accuracy of testing. Attached Figure Description
[0014] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0015] Figure 1 This is a schematic diagram of the structure of a chip provided in one embodiment of this application; Figure 2 This is a schematic flowchart of a chip testing method provided in one embodiment of this application; Figure 3 This is a schematic flowchart of a chip testing method provided in another embodiment of this application; Figure 4 This is a schematic diagram of an FT Scan PIN compression and decompression principle provided in one embodiment of this application; Figure 5 This is a timing diagram for FT Scan output PIN compression provided in one embodiment of this application; Figure 6 This is a timing diagram for decompressing an FT Scan input PIN according to an embodiment of this application; Figure 7 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Detailed Implementation
[0016] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0017] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0018] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0019] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.
[0020] First, let's analyze some of the terms used in this application: FT (Final Test): Final test. This is the last testing stage after chip packaging is completed, used to ensure the chip's performance and reliability in real-world applications.
[0021] Scan (chain): Scan testing is a key technology in integrated circuit testing, primarily used to detect structural faults in the internal logic circuits of a chip. Its core principle is to connect flip-flops within the chip in series to form a scan chain, enabling the loading, execution, and comparison of test vectors, thereby quickly identifying physical damage or logical errors.
[0022] PIN: pin.
[0023] FT scan PIN: Final scan chain test pin.
[0024] CP (Chip Probing): Wafer testing. CP testing occurs between wafer fabrication and packaging in the entire chip manufacturing process. The testing targets each die in the entire wafer, aiming to ensure that the function, electrical parameters, etc., of each die in the entire wafer meet the design requirements, thereby eliminating defective products and reducing subsequent packaging costs.
[0025] CP Scan: Wafer scan chain test mode.
[0026] FT Scan: Final scan chain test mode.
[0027] scan_di: Input signal for the scan chain in CP test mode.
[0028] scan_do: Output signal of the scan chain in CP test mode.
[0029] scan chain: a chain of scanned data.
[0030] scan_di_ft: Input signal for the scan chain in FT test mode; scan_do_ft: FT test mode scan chain output signal; Scan pattern: Scan chain test vector. The ATPG pattern mentioned in the text is equivalent to scan pattern. ATPG (Automatic Test Pattern Generation) is an automatic test vector generation tool. EDA tools automatically generate vectors for ATE (Automatic Test Equipment) testing based on a specific algorithm, inputting them through the scan in pin and outputting the results through the scan out pin.
[0031] CP scan pattern: ATPG pattern during the CP scan test phase.
[0032] FT scan pattern: ATPG pattern during the FT scan test phase.
[0033] The chip testing method provided in this application is specifically illustrated through the following embodiments.
[0034] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.
[0035] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.
[0036] The chip testing method provided in this application relates to the field of chip technology. The chip testing method provided in this application can be applied to a terminal or a server, and can also be software running on either the terminal or the server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application implementing the chip testing method, etc., but is not limited to the above forms.
[0037] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.
[0038] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the normal operation of the embodiments of this application be obtained.
[0039] The various embodiments of the chip of this application will be further described below with reference to the accompanying drawings.
[0040] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a chip provided in one embodiment of this application.
[0041] In one embodiment, the chip 100 includes a mode switching module 110, an input decompression module 120, and an output compression module 130, comprising: The output compression module 130 is equipped with a triple clock, which is used to output the response signal output by the internal scan chain of the chip in the final scan chain test mode through time division multiplexing in multiple compressed clock cycles to output the compressed final scan chain test pin. The mode switching module 110 is equipped with control pins, a multiplexer, and multiplexed wafer scan chain test pins. The control signal output from the control pins drives the multiplexer to switch test modes. The input decompression module 120 includes multi-level registers and combinational logic.
[0042] In one embodiment, the test modes include a wafer scan chain test mode and a final scan chain test mode, with the multiplexed wafer scan chain test pins serving as input and output pins in the final scan chain test mode.
[0043] In one embodiment, the input decompression module 120 is used to receive multi-shot compressed data input in the final scan chain test mode according to a preset compression specification, latch and splice it in a multi-level register in a periodic manner, restore it to the test vector in the wafer scan chain test mode, and input it to the internal scan chain of the chip.
[0044] In one embodiment, in wafer scan chain test mode, the mode switching module 110 includes: The multiplexer enables the scan chain input signal and scan chain output signal in the wafer scan chain test mode to be directly connected to the internal scan chain of the chip, while the input decompression module 120 and the output compression module 130 are in an idle state.
[0045] Please see Figure 2 , Figure 2 This is a schematic flowchart of a chip testing method provided in one embodiment of this application; the chip testing method provided in this embodiment includes, but is not limited to, steps S210 to S250, which will be described in turn below. Step S210: Obtain the compression specifications of the input decompression module and the time-division multiplexing rules of the output compression module; Step S220: According to the compression specification and time-division multiplexing rules, the scan chain test vector of the wafer scan chain test mode is converted into the scan chain test vector of the final scan chain test mode. The scan chain test vector of the final scan chain test mode includes the compressed final scan chain test input vector and the corresponding expected final scan chain test output response. Step S230: Load the scan chain test vector of the final scan chain test mode into the chip through the ATE machine, set the control pin to the final scan chain test mode level, restore the test vector of the original wafer scan chain test mode through the input decompression module and input it into the internal scan chain of the chip, and output the final scan chain test response signal through the output compression module. Step S240: Compare the final scan chain test response signal with the expected final scan chain test output response signal to obtain the comparison result; Step S250: Based on the comparison results, obtain the chip logic fault judgment results.
[0046] It should be noted that the acquisition of compression specifications includes the following: during the chip front-end design stage, the compression specifications of the input decompression module are clearly written into the Design Specification (DS) and Test Plan Document (TPS), and are directly extracted from these documents before test execution; reading the chip's built-in registers: the compression specification parameters are stored in the built-in configuration registers before the chip leaves the factory. The ATE equipment sends a read command through the chip's JTAG interface or dedicated test interface to obtain real-time and valid compression specification data from the registers, avoiding the problem of inconsistency between the document and the actual chip parameters.
[0047] In one embodiment, the output compression module is a hardware module inside the chip used to compress the test output responses of the internal scan chains and output them in a time-division multiplexing manner. Its time-division multiplexing rules determine how the output responses of multiple internal scan chains are transmitted to the ATE equipment through a limited number of output pins. Specifically, it includes: the number of multiplexing channels: that is, the number of physical output pins of the output compression module (e.g., 8 or 16), which is much less than the total number of scan chains inside the chip; the mapping relationship between scan chains and channels: clarifying which multiplexing channel the output response of each internal scan chain is assigned to (e.g., scan chains 1-8 correspond to channel 1, scan chains 9-16 correspond to channel 2, etc.); time-division multiplexing timing: including the response output clock cycle of each channel, the timing switching rules between different channels (e.g., the time-division multiplexing frame length is 32 clock cycles, and each channel occupies 4 clock cycles); response compression format: such as whether the output response has undergone XOR compression, CRC check processing, and the bit arrangement order of the compressed data (e.g., high-order bits first, low-order bits first).
[0048] In one embodiment, the original test vector is complete test data designed for all scan chains within the chip, comprising two parts: the original scan chain test input vector, used to input into the internal scan chains of the chip to activate the chip's logic functions, containing shift and capture data of all scan chains, and its bit length is equal to the total length of all scan chains (for example, if the chip contains 100 scan chains, each scan chain is 1024 bits long, then the original input vector length is 100 × 1024 = 102400 bits); and the original scan chain test output response, which is the correct response data that the internal scan chains should output under the action of the original input vector (the ideal output when there is no fault), and its bit length is consistent with the bit length of the original input vector, used as a benchmark for subsequent fault judgment.
[0049] In one embodiment, the compressed final scan chain test input vector is generated by dividing the original scan chain test input vector into several independent data blocks according to the data block partitioning rules in the compression specification (for example, according to the compression specification, each 256 bits is divided into one data block, so the 102400-bit original input vector is divided into 400 data blocks); each data block is compressed using the compression algorithm specified in the compression specification (for example, using the LFSR compression algorithm to compress each 256-bit data block into 32 bits, with a compression ratio of 8:1); the compressed data blocks are arranged according to the format required by the compression specification, including adding a decompression synchronization header (such as a 32-bit synchronization code for synchronizing the decompression module) and adjusting the data block order (to ensure that the restoration order during decompression is consistent with the original input vector), finally forming the compressed final scan chain test input vector.
[0050] It should be noted that the above conversion process is implemented using a dedicated test vector conversion tool (such as a script tool developed based on Python or C++). This tool has a built-in compression algorithm library and a time-division multiplexing timing simulator, supporting the import of original test vectors, compression specifications, and time-division multiplexing rule parameters, and automatically completes the conversion. After conversion, verification is required. This involves simulating the operation of the input decompression module to restore the compressed input vector to the original input vector, checking whether the restored vector matches the original input vector; simultaneously, simulating the operation of the output compression module to convert the original output response into the expected final output response, ensuring the accuracy of the conversion result.
[0051] It is worth noting that the compression processing of the input decompression module significantly reduces the amount of data in the test input vector, thereby reducing the storage pressure and data transmission time of the ATE equipment and improving test efficiency. Test channel utilization is also improved: the time-division multiplexing rule of the output compression module allows responses from multiple scan chains to be transmitted through a limited number of output pins, eliminating the need for independent output pins for each scan chain and reducing chip testing costs. Fault diagnosis is more accurate: by comparing the final response bit-by-bit with the expected response, combined with the reverse derivation of the time-division multiplexing rule, accurate fault location can be achieved, providing a basis for chip failure analysis and design optimization.
[0052] In one embodiment, firstly, during the chip design phase, the compression and decompression logic from CP scan to FT scan is implemented according to the established compression and decompression rules; then, a script is designed to convert the CP ATPG Pattern into an FT Pattern according to the same rules, wherein the scan input and output in the Pattern are compressed according to the same specifications; in the FT phase, the FT Pattern test stimulus is loaded through an ATE machine, and the expected output results are compared to check for logic faults.
[0053] In one embodiment, the target total number of bits wafer scan chain test response signals output by the chip's internal scan chain are output sequentially according to a preset period of a triple clock, wherein the target number of bits response data is output in each preset period.
[0054] Please see Figure 3 , Figure 3 This is a schematic flowchart of a chip testing method provided in another embodiment of this application; regarding the above step S230, which restores the test vector of the original wafer scan chain test mode by inputting the decompression module, including but not limited to steps S310 to S330, each step will be described in turn below. Step S310: In the first preset period of the triple clock, the first compressed data is received through the input decompression module and latched into the low target bit register; Step S320: During the second preset cycle of the tripled clock, the second compressed data is received through the input decompression module and latched into the high target digital register; Step S330: In the third preset cycle of the tripled clock, the third compressed data is received through the input decompression module and spliced with the data latched in the low target bit register and the high target bit register to restore the test vector of the wafer scan chain test mode with a target total number of bits.
[0055] In one embodiment, the chip logic fault determination result is obtained based on the comparison result, including: When the comparison result indicates that the final scan chain test response signal is completely consistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has no logic fault. When the comparison results indicate that the final scan chain test response signal is inconsistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has a logic fault and the fault location is located.
[0056] See Figures 4 to 6 , Figure 4 This is a schematic diagram of an FT Scan PIN compression and decompression principle provided in one embodiment of this application; Figure 5 This is a timing diagram for FT Scan output PIN compression provided in one embodiment of this application; Figure 6 This is a timing diagram for decompressing an FT Scan input PIN provided in one embodiment of this application.
[0057] In one embodiment, FT scan PIN compression / decompression logic is inserted during the chip design phase, as shown in Figure 2. Compared to CP Scan mode, FT Scan mode adds an ft_mode pin and a compressed clock (Figures 3 and 4 illustrate a tripled clock scan_clk_cmps). The ft_mode pin enables switching between CPScan and FT Scan modes, and a multiplexer (MUX) is used in hardware to switch the signal path.
[0058] Specifically, the chip incorporates a design schematic for the compression and decompression logic of the SCAN PIN required for FT testing. The diagram shows that the ft_mode PIN is used to select between FT Scan mode and CP Scan mode, scan_di / scan_do are the PINs used in the CP Scan stage, and scan_di_ft / scan_do_ft are the CP Scan PINs used in the FT Scan stage. It can be seen that scan_di_ft / scan_do_ft reuses a small number of scan_di / scan_dout PINs, significantly reducing PIN usage in the FT stage. The CP Scan PINs not reused in the FT stage do not need to be encapsulated.
[0059] Specifically, in CP Scan mode, the scan input scan_di and scan output scan_do are directly connected to the internal ScanChain. In FT mode, scan_di_ft and scan_do_ft reuse some CP Scan pins (as shown in Figures 3 and 4, scan_di[3:0] and scan_do[3:0] are reused as scan_di_ft[3:0] and scan_do_ft[3:0]). The compressed FT scan test vector is restored to the CP scan test vector through decompression logic; the Scan chain output response signal is compressed into the FT scan output response through compression logic. This achieves the same test content as CPScan with fewer pins in FT Scan.
[0060] Specifically, the FT Scan input decompression logic consists of multi-level registers and combinational logic, with scan_clk_cmps and scan_clk synchronized and in a triplet relationship. The CP scan pattern is converted into the FT scan pattern according to the compression specification, as shown in Figure 4, in three cycles (cycle0-2). Cycle 0 receives the first compressed data scan_di_ft[3:0] and latches it into the lower 4 bits of the register. Cycle 1 receives the second compressed data scan_di_ft[3:0] and latches it into the higher 4 bits of the register. Finally, it is concatenated with the third compressed data scan_di_ft[3:0] input from cycle 2 to restore the complete 12-bit CP scan input vector. This serves as the 12-bit input stimulus for the internal scan chain, restoring the CP Scan test vector.
[0061] In one embodiment, see Figure 6 The ATPG pattern, converted from CP to FT, has its scan input test vector compressed three times, reducing the number of scan pins from 12 to 4. The scan_di[11:0] input in one cycle of the CP stage is input in three scan_clk_cmps cycles cycle0 / cycle1 / cycle2. After simple decompression logic inside the chip, it is restored to 12 scan input vectors.
[0062] For details, see Figure 5 The FT Scan output compression logic divides the 12-bit scan output signal of one scan_clk cycle into three scan_clk_cmps cycles (cycles 0-2) and outputs them sequentially to four scan_out_ft[3:0] pins. An external ATE machine compares the expected response after CP scan pattern compression with the chip's output response to check if the pattern passes. The internal scan output of the chip is compressed three times during the FT stage, where scan_clk_cmps is a three-fold harmonic of scan_clk. It occupies 12 output pins during the CP stage, but only four scan_out_ft[3:0] pins are needed during the FT stage. The scan output signal of one scan_clk cycle is output through three scan_clk_cmps cycles (cycles 0 / 1 / 2).
[0063] This application also provides a computer device comprising: at least one memory, at least one processor, and at least one computer program. The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the chip testing method of any of the above embodiments. This computer device can be any smart terminal, including tablet computers, in-vehicle computers, etc.
[0064] See Figure 7 , Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. The computer device includes: The processor 710 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 720 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 720 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 720 and is called by the processor 710 to execute the chip testing method of the embodiments of this application. The input / output interface 730 is used to implement information input and output; The communication interface 740 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 750 transmits information between various components of the device (e.g., processor 710, memory 720, input / output interface 730, and communication interface 740); The processor 710, memory 720, input / output interface 730 and communication interface 740 are connected to each other within the device via bus 750.
[0065] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the testing method for the aforementioned chip.
[0066] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0067] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0068] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.
[0069] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0070] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0071] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0072] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0073] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0074] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0075] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0076] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0077] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A chip, characterized in that, The chip includes a mode switching module, an input decompression module, and an output compression module, comprising: The output compression module is equipped with a triple clock, which is used to output the compressed final scan chain test pins in multiple compressed clock cycles through time-division multiplexing of the response signal output by the scan chain inside the chip in the final scan chain test mode. The mode switching module is equipped with control pins, a multiplexer, and multiplexed wafer scan chain test pins. The control signal output from the control pins drives the multiplexer to switch test modes. The input decompression module includes multi-level registers and combinational logic.
2. The chip according to claim 1, characterized in that, The test modes include wafer scan chain test mode and final scan chain test mode, and the multiplexed wafer scan chain test pins serve as input pins and output pins in the final scan chain test mode.
3. The chip according to claim 1, characterized in that, The input decompression module is used to receive multi-phase compressed data input in the final scan chain test mode according to a preset compression specification, latch and splice it in the multi-level registers in a periodic manner, restore it to the test vector in the wafer scan chain test mode, and input it to the internal scan chain of the chip.
4. The chip according to claim 2, characterized in that, In the wafer scan chain test mode, the mode switching module includes: The multiplexer enables the scan chain input signal and scan chain output signal in the wafer scan chain test mode to be directly connected to the internal scan chain of the chip, while the input decompression module and the output compression module are in an idle state.
5. A method for testing a chip, characterized in that, Applied to a chip, the chip includes a mode switching module, an input decompression module, and an output compression module, comprising: Obtain the compression specifications of the input decompression module and the time-division multiplexing rules of the output compression module; According to the compression specification and the time-division multiplexing rule, the scan chain test vector of the wafer scan chain test mode is converted into the scan chain test vector of the final scan chain test mode, wherein the scan chain test vector of the final scan chain test mode includes the compressed final scan chain test input vector and the corresponding expected final scan chain test output response; The ATE machine loads the scan chain test vector of the final scan chain test mode onto the chip, sets the control pin to the final scan chain test mode level, restores the test vector of the original wafer scan chain test mode through the input decompression module and inputs it into the internal scan chain of the chip, and outputs the final scan chain test response signal through the output compression module. The final scan chain test response signal is compared with the expected final scan chain test output response signal to obtain the comparison result; Based on the comparison results, the chip logic fault judgment result is obtained.
6. The method according to claim 5, characterized in that, Also includes: The target total number of wafer scan chain test response signals output by the internal scan chain of the chip are output sequentially according to the preset period of the triple clock, wherein the target number of response data is output in each preset period.
7. The method according to claim 6, characterized in that, The test vector, which is restored to the original wafer scan chain test mode by the input decompression module, includes: During the first preset period of the tripled clock, the first compressed data is received by the input decompression module and latched into the low target bit register. During the second preset cycle of the tripled clock, the second compressed data is received by the input decompression module and latched into the high target digital register. During the third preset cycle of the tripled clock, the third compressed data is received through the input decompression module and concatenated with the data latched in the low target bit register and the high target bit register to restore the test vector of the wafer scan chain test mode with a target total number of bits.
8. The method according to claim 5, characterized in that, The step of obtaining the chip logic fault judgment result based on the comparison result includes: When the comparison result indicates that the final scan chain test response signal is completely consistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has no logic fault. When the comparison result indicates that the final scan chain test response signal is inconsistent with the expected final scan chain test output response, the chip logic fault judgment result is that the chip has a logic fault and the fault location is located.
9. A computer device, characterized in that, include: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method as described in any one of claims 5 to 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing a computer to perform the method as described in any one of claims 5 to 8.